net/iavf: count continuous DD bits for Arm in flex Rx

On Arm platforms, reading of descriptors may be re-ordered causing the
status of DD bits to be discontinuous. Add logic to only process
continuous descriptors by checking DD bits.

Fixes: b8b4c54ef9b0 ("net/iavf: support flexible Rx descriptor in normal path")
Cc: stable@dpdk.org
Signed-off-by: Kathleen Capella <kathleen.capella@arm.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
Reviewed-by: Qi Zhang <qi.z.zhang@intel.com>

diff --git a/drivers/net/iavf/iavf_rxtx.c b/drivers/net/iavf/iavf_rxtx.c
index f07d886821908a28b8fa2fb98dd17e003d76a824..41244055e51bcd582f9e338b3e0cc3a557efa338 100644 (file)
--- a/drivers/net/iavf/iavf_rxtx.c
+++ b/drivers/net/iavf/iavf_rxtx.c
@@ -1818,7 +1818,7 @@ iavf_rx_scan_hw_ring_flex_rxd(struct iavf_rx_queue *rxq)
        struct rte_mbuf *mb;
        uint16_t stat_err0;
        uint16_t pkt_len;
-       int32_t s[IAVF_LOOK_AHEAD], nb_dd;
+       int32_t s[IAVF_LOOK_AHEAD], var, nb_dd;
        int32_t i, j, nb_rx = 0;
        uint64_t pkt_flags;
        const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
@@ -1843,9 +1843,27 @@ iavf_rx_scan_hw_ring_flex_rxd(struct iavf_rx_queue *rxq)
 
                rte_smp_rmb();
 
-               /* Compute how many status bits were set */
-               for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++)
-                       nb_dd += s[j] & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S);
+               /* Compute how many contiguous DD bits were set */
+               for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++) {
+                       var = s[j] & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S);
+#ifdef RTE_ARCH_ARM
+                       /* For Arm platforms, count only contiguous descriptors
+                        * whose DD bit is set to 1. On Arm platforms, reads of
+                        * descriptors can be reordered. Since the CPU may
+                        * be reading the descriptors as the NIC updates them
+                        * in memory, it is possbile that the DD bit for a
+                        * descriptor earlier in the queue is read as not set
+                        * while the DD bit for a descriptor later in the queue
+                        * is read as set.
+                        */
+                       if (var)
+                               nb_dd += 1;
+                       else
+                               break;
+#else
+                       nb_dd += var;
+#endif
+               }
 
                nb_rx += nb_dd;