switch (enp->en_family) {
 #if EFSYS_OPT_RIVERHEAD
        case EFX_FAMILY_RIVERHEAD:
-               EFX_BAR_WRITED(enp, ER_GZ_MC_DB_HWRD_REG, &dword, B_FALSE);
+               EFX_BAR_FCW_WRITED(enp, ER_GZ_MC_DB_HWRD_REG, &dword);
                break;
 #endif /* EFSYS_OPT_RIVERHEAD */
        default:
        switch (enp->en_family) {
 #if EFSYS_OPT_RIVERHEAD
        case EFX_FAMILY_RIVERHEAD:
-               EFX_BAR_WRITED(enp, ER_GZ_MC_DB_LWRD_REG, &dword, B_FALSE);
+               EFX_BAR_FCW_WRITED(enp, ER_GZ_MC_DB_LWRD_REG, &dword);
                break;
 #endif /* EFSYS_OPT_RIVERHEAD */
        default:
        switch (enp->en_family) {
 #if EFSYS_OPT_RIVERHEAD
        case EFX_FAMILY_RIVERHEAD:
-               EFX_BAR_WRITED(enp, ER_GZ_MC_DB_HWRD_REG, &dword, B_FALSE);
+               EFX_BAR_FCW_WRITED(enp, ER_GZ_MC_DB_HWRD_REG, &dword);
                break;
 #endif /* EFSYS_OPT_RIVERHEAD */
        default:
 
        old_status = emip->emi_mc_reboot_status;
 
-       EFX_STATIC_ASSERT(ER_DZ_BIU_MC_SFT_STATUS_REG_OFST ==
-           ER_GZ_MC_SFT_STATUS_OFST);
-
        /* Update MC reboot status word */
-       EFX_BAR_TBL_READD(enp, ER_DZ_BIU_MC_SFT_STATUS_REG, 0, &dword, B_FALSE);
+       switch (enp->en_family) {
+#if EFSYS_OPT_RIVERHEAD
+       case EFX_FAMILY_RIVERHEAD:
+               EFX_BAR_FCW_READD(enp, ER_GZ_MC_SFT_STATUS, &dword);
+               break;
+#endif /* EFSYS_OPT_RIVERHEAD */
+       default:
+               EFX_BAR_READD(enp, ER_DZ_BIU_MC_SFT_STATUS_REG,
+                             &dword, B_FALSE);
+               break;
+       }
        new_status = dword.ed_u32[0];
 
        /* MC has rebooted if the value has changed */
 
        __in            efx_family_t family,
        __in            efsys_identifier_t *esip,
        __in            efsys_bar_t *esbp,
+       __in            uint32_t fcw_offset,
        __in            efsys_lock_t *eslp,
        __deref_out     efx_nic_t **enpp);
 
 
                        int                     ena_vi_base;
                        int                     ena_vi_count;
                        int                     ena_vi_shift;
+                       uint32_t                ena_fcw_base;
 #if EFSYS_OPT_VPD
                        caddr_t                 ena_svpd;
                        size_t                  ena_svpd_length;
  * Code used on EF10 *must* use EFX_BAR_VI_*() macros for per-VI registers,
  * to ensure the correct runtime VI window size is used on Medford2.
  *
+ * Code used on EF100 *must* use EFX_BAR_FCW_* macros for function control
+ * window registers, to ensure the correct starting offset is used.
+ *
  * Siena-only code may continue using EFX_BAR_TBL_*() macros for VI registers.
  */
 
        _NOTE(CONSTANTCONDITION)                                        \
        } while (B_FALSE)
 
+/*
+ * Accessors for memory BAR function control window registers.
+ *
+ * The function control window is located at an offset which can be
+ * non-zero in case of Riverhead.
+ */
+
+#if EFSYS_OPT_RIVERHEAD
+
+#define        EFX_BAR_FCW_READD(_enp, _reg, _edp)                             \
+       do {                                                            \
+               EFX_CHECK_REG((_enp), (_reg));                          \
+               EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST +        \
+                   (_enp)->en_arch.ef10.ena_fcw_base,                  \
+                   (_edp), B_FALSE);                                   \
+               EFSYS_PROBE3(efx_bar_fcw_readd, const char *, #_reg,    \
+                   uint32_t, _reg ## _OFST,                            \
+                   uint32_t, (_edp)->ed_u32[0]);                       \
+       _NOTE(CONSTANTCONDITION)                                        \
+       } while (B_FALSE)
+
+#define        EFX_BAR_FCW_WRITED(_enp, _reg, _edp)                            \
+       do {                                                            \
+               EFX_CHECK_REG((_enp), (_reg));                          \
+               EFSYS_PROBE3(efx_bar_fcw_writed, const char *, #_reg,   \
+                   uint32_t, _reg ## _OFST,                            \
+                   uint32_t, (_edp)->ed_u32[0]);                       \
+               EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST +       \
+                   (_enp)->en_arch.ef10.ena_fcw_base,                  \
+                   (_edp), B_FALSE);                                   \
+       _NOTE(CONSTANTCONDITION)                                        \
+       } while (B_FALSE)
+
+#endif /* EFSYS_OPT_RIVERHEAD */
+
 /*
  * Accessors for memory BAR per-VI registers.
  *
 
        __in            efx_family_t family,
        __in            efsys_identifier_t *esip,
        __in            efsys_bar_t *esbp,
+       __in            uint32_t fcw_offset,
        __in            efsys_lock_t *eslp,
        __deref_out     efx_nic_t **enpp)
 {
                    EFX_FEATURE_MCDI |
                    EFX_FEATURE_MAC_HEADER_FILTERS |
                    EFX_FEATURE_MCDI_DMA;
+               enp->en_arch.ef10.ena_fcw_base = fcw_offset;
                break;
 #endif /* EFSYS_OPT_RIVERHEAD */
 
                goto fail2;
        }
 
+       if ((family != EFX_FAMILY_RIVERHEAD) && (fcw_offset != 0)) {
+               rc = EINVAL;
+               goto fail3;
+       }
+
        enp->en_family = family;
        enp->en_esip = esip;
        enp->en_esbp = esbp;
 
        return (0);
 
+fail3:
+       EFSYS_PROBE(fail3);
 fail2:
        EFSYS_PROBE(fail2);
 
 
        EFX_POPULATE_DWORD_2(dword, ERF_GZ_EVQ_ID, eep->ee_index,
            ERF_GZ_IDX, rptr);
        /* EVQ_INT_PRIME lives function control window only on Riverhead */
-       EFX_BAR_WRITED(enp, ER_GZ_EVQ_INT_PRIME, &dword, B_FALSE);
+       EFX_BAR_FCW_WRITED(enp, ER_GZ_EVQ_INT_PRIME, &dword);
 
        return (0);
 }
 
        if (enp->en_reset_flags & EFX_RESET_HW_UNAVAIL)
                return (B_TRUE);
 
-       EFX_BAR_READD(enp, ER_GZ_MC_SFT_STATUS, &dword, B_FALSE);
+       EFX_BAR_FCW_READD(enp, ER_GZ_MC_SFT_STATUS, &dword);
        if (EFX_DWORD_FIELD(dword, EFX_DWORD_0) == 0xffffffff)
                goto unavail;
 
 
        sfc_log_init(sa, "create nic");
        rte_spinlock_init(&sa->nic_lock);
        rc = efx_nic_create(sa->family, (efsys_identifier_t *)sa,
-                           &sa->mem_bar, &sa->nic_lock, &enp);
+                           &sa->mem_bar, 0,
+                           &sa->nic_lock, &enp);
        if (rc != 0)
                goto fail_nic_create;
        sa->nic = enp;