{
char pool_name[25];
int ret;
+ uint8_t tim_ring_id;
uint64_t nb_timers;
struct rte_event_timer_adapter_conf *rcfg = &adptr->data->conf;
struct timvf_ring *timr;
- struct timvf_info tinfo;
const char *mempool_ops;
unsigned int mp_flags = 0;
- if (timvf_info(&tinfo) < 0)
- return -ENODEV;
-
- if (adptr->data->id >= tinfo.total_timvfs)
+ tim_ring_id = timvf_get_ring();
+ if (tim_ring_id == UINT8_MAX)
return -ENODEV;
timr = rte_zmalloc("octeontx_timvf_priv",
}
timr->clk_src = (int) rcfg->clk_src;
- timr->tim_ring_id = adptr->data->id;
+ timr->tim_ring_id = tim_ring_id;
timr->tck_nsec = RTE_ALIGN_MUL_CEIL(rcfg->timer_tick_ns, 10);
timr->max_tout = rcfg->max_tmo_ns;
timr->nb_bkts = (timr->max_tout / timr->tck_nsec);
timvf_ring_free(struct rte_event_timer_adapter *adptr)
{
struct timvf_ring *timr = adptr->data->adapter_priv;
+
rte_mempool_free(timr->chunk_pool);
rte_free(timr->bkt);
+ timvf_release_ring(timr->tim_ring_id);
rte_free(adptr->data->adapter_priv);
return 0;
}
extern int otx_logtype_timvf;
static const uint16_t nb_chunk_slots = (TIM_CHUNK_SIZE / 16) - 1;
-struct timvf_info {
- uint16_t domain; /* Domain id */
- uint8_t total_timvfs; /* Total timvf available in domain */
-};
-
enum timvf_clk_src {
TIM_CLK_SRC_SCLK = RTE_EVENT_TIMER_ADAPTER_CPU_CLK,
TIM_CLK_SRC_GPIO = RTE_EVENT_TIMER_ADAPTER_EXT_CLK0,
return rel_bkt & (nb_bkts - 1);
}
-int timvf_info(struct timvf_info *tinfo);
+uint8_t timvf_get_ring(void);
+void timvf_release_ring(uint8_t vfid);
void *timvf_bar(uint8_t id, uint8_t bar);
int timvf_timer_adapter_caps_get(const struct rte_eventdev *dev, uint64_t flags,
uint32_t *caps, const struct rte_event_timer_adapter_ops **ops,
#define TIM_MAX_RINGS (64)
struct timvf_res {
+ uint8_t in_use;
uint16_t domain;
uint16_t vfid;
void *bar0;
static struct timdev tdev;
-int
-timvf_info(struct timvf_info *tinfo)
+uint8_t
+timvf_get_ring(void)
{
+ uint16_t global_domain = octeontx_get_global_domain();
int i;
- struct ssovf_info info;
- if (tinfo == NULL)
- return -EINVAL;
+ for (i = 0; i < tdev.total_timvfs; i++) {
+ if (tdev.rings[i].domain != global_domain)
+ continue;
+ if (tdev.rings[i].in_use)
+ continue;
- if (!tdev.total_timvfs)
- return -ENODEV;
+ tdev.rings[i].in_use = true;
+ return tdev.rings[i].vfid;
+ }
- if (ssovf_info(&info) < 0)
- return -EINVAL;
+ return UINT8_MAX;
+}
+
+void
+timvf_release_ring(uint8_t tim_ring_id)
+{
+ uint16_t global_domain = octeontx_get_global_domain();
+ int i;
for (i = 0; i < tdev.total_timvfs; i++) {
- if (info.domain != tdev.rings[i].domain) {
- timvf_log_err("GRP error, vfid=%d/%d domain=%d/%d %p",
- i, tdev.rings[i].vfid,
- info.domain, tdev.rings[i].domain,
- tdev.rings[i].bar0);
- return -EINVAL;
- }
+ if (tdev.rings[i].domain != global_domain)
+ continue;
+ if (tdev.rings[i].vfid == tim_ring_id)
+ tdev.rings[i].in_use = false;
}
-
- tinfo->total_timvfs = tdev.total_timvfs;
- tinfo->domain = info.domain;
- return 0;
}
void*
-timvf_bar(uint8_t id, uint8_t bar)
+timvf_bar(uint8_t vfid, uint8_t bar)
{
+ uint16_t global_domain = octeontx_get_global_domain();
+ struct timvf_res *res = NULL;
+ int i;
+
if (rte_eal_process_type() != RTE_PROC_PRIMARY)
return NULL;
- if (id > tdev.total_timvfs)
+ for (i = 0; i < tdev.total_timvfs; i++) {
+ if (tdev.rings[i].domain != global_domain)
+ continue;
+ if (tdev.rings[i].vfid == vfid)
+ res = &tdev.rings[i];
+
+ }
+
+ if (res == NULL)
return NULL;
switch (bar) {
case 0:
- return tdev.rings[id].bar0;
+ return res->bar0;
case 4:
- return tdev.rings[id].bar4;
+ return res->bar4;
default:
return NULL;
}
res->bar2 = pci_dev->mem_resource[2].addr;
res->bar4 = pci_dev->mem_resource[4].addr;
res->domain = (val >> 7) & 0xffff;
+ res->in_use = false;
tdev.total_timvfs++;
rte_wmb();