goto error;
}
}
+ if (attr->eswitch_manager) {
+ hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
+ MLX5_SET_HCA_CAP_OP_MOD_ESW |
+ MLX5_HCA_CAP_OPMOD_GET_CUR);
+ if (!hcattr)
+ return rc;
+ attr->esw_mgr_vport_id_valid =
+ MLX5_GET(esw_cap, hcattr,
+ esw_manager_vport_number_valid);
+ attr->esw_mgr_vport_id =
+ MLX5_GET(esw_cap, hcattr, esw_manager_vport_number);
+ }
return 0;
error:
rc = (rc > 0) ? -rc : rc;
uint32_t umr_modify_entity_size_disabled:1;
uint32_t umr_indirect_mkey_disabled:1;
uint32_t log_min_stride_wqe_sz:5;
+ uint32_t esw_mgr_vport_id_valid:1; /* E-Switch Mgr vport ID is valid. */
+ uint16_t esw_mgr_vport_id; /* E-Switch Mgr vport ID . */
uint16_t max_wqe_sz_sq;
};
MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1,
MLX5_GET_HCA_CAP_OP_MOD_ROCE = 0x4 << 1,
MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE = 0x7 << 1,
+ MLX5_SET_HCA_CAP_OP_MOD_ESW = 0x9 << 1,
MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1,
MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP = 0x1C << 1,
MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 = 0x20 << 1,
u8 reserved_at_100[0x700];
};
+struct mlx5_ifc_esw_cap_bits {
+ u8 reserved_at_0[0x60];
+
+ u8 esw_manager_vport_number_valid[0x1];
+ u8 reserved_at_61[0xf];
+ u8 esw_manager_vport_number[0x10];
+
+ u8 reserved_at_80[0x780];
+};
+
union mlx5_ifc_hca_cap_union_bits {
struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
struct mlx5_ifc_qos_cap_bits qos_cap;
struct mlx5_ifc_virtio_emulation_cap_bits vdpa_caps;
struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
+ struct mlx5_ifc_esw_cap_bits esw_cap;
struct mlx5_ifc_roce_caps_bits roce_caps;
u8 reserved_at_0[0x8000];
};
flow_dv_get_esw_manager_vport_id(struct rte_eth_dev *dev)
{
struct mlx5_priv *priv = dev->data->dev_private;
+ struct mlx5_common_device *cdev = priv->sh->cdev;
+
+ if (cdev->config.hca_attr.esw_mgr_vport_id_valid)
+ return (int16_t)cdev->config.hca_attr.esw_mgr_vport_id;
if (priv->pci_dev == NULL)
return 0;