net/sfc/base: decode Medford2 FEC stats if available
authorAndy Moreton <amoreton@solarflare.com>
Tue, 20 Feb 2018 07:34:00 +0000 (07:34 +0000)
committerFerruh Yigit <ferruh.yigit@intel.com>
Fri, 30 Mar 2018 12:08:42 +0000 (14:08 +0200)
Decode Medford2 FEC stats if available in MAC stats DMA buffer.

Signed-off-by: Andy Moreton <amoreton@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
drivers/net/sfc/base/ef10_mac.c
drivers/net/sfc/base/ef10_nic.c
drivers/net/sfc/base/efx.h

index b1534a8..f5e6e41 100644 (file)
@@ -523,8 +523,20 @@ ef10_mac_stats_get_mask(
                        goto fail6;
        }
 
+       if (encp->enc_fec_counters) {
+               const struct efx_mac_stats_range ef10_fec[] = {
+                       { EFX_MAC_FEC_UNCORRECTED_ERRORS,
+                           MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE3 },
+               };
+               if ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size,
+                   ef10_fec, EFX_ARRAY_SIZE(ef10_fec))) != 0)
+                       goto fail7;
+       }
+
        return (0);
 
+fail7:
+       EFSYS_PROBE(fail7);
 fail6:
        EFSYS_PROBE(fail6);
 fail5:
@@ -880,6 +892,38 @@ ef10_mac_stats_update(
        EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_OVERFLOW, &value);
        EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_OVERFLOW]), &value);
 
+
+       if (encp->enc_mac_stats_nstats < MC_CMD_MAC_NSTATS_V2)
+               goto done;
+
+       /* FEC */
+       EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_FEC_UNCORRECTED_ERRORS, &value);
+       EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_FEC_UNCORRECTED_ERRORS]), &value);
+
+       EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_FEC_CORRECTED_ERRORS, &value);
+       EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_FEC_CORRECTED_ERRORS]), &value);
+
+       EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE0,
+           &value);
+       EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0]),
+           &value);
+
+       EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE1,
+           &value);
+       EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1]),
+           &value);
+
+       EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE2,
+           &value);
+       EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2]),
+           &value);
+
+       EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE3,
+           &value);
+       EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3]),
+           &value);
+
+done:
        /* Read START generation counter */
        EFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, EFSYS_MEM_SIZE(esmp));
        EFSYS_MEM_READ_BARRIER();
index a23cf63..b06c73e 100644 (file)
@@ -1185,6 +1185,11 @@ ef10_get_datapath_caps(
                encp->enc_mac_stats_nstats = MC_CMD_MAC_NSTATS;
        }
 
+       if (encp->enc_mac_stats_nstats >= MC_CMD_MAC_NSTATS_V2)
+               encp->enc_fec_counters = B_TRUE;
+       else
+               encp->enc_fec_counters = B_FALSE;
+
 #undef CAP_FLAGS1
 #undef CAP_FLAGS2
 
index ba1f76d..09926ba 100644 (file)
@@ -1240,6 +1240,7 @@ typedef struct efx_nic_cfg_s {
        uint32_t                enc_nvram_update_verify_result_supported;
        /* Firmware support for extended MAC_STATS buffer */
        uint32_t                enc_mac_stats_nstats;
+       boolean_t               enc_fec_counters;
 } efx_nic_cfg_t;
 
 #define        EFX_PCI_FUNCTION_IS_PF(_encp)   ((_encp)->enc_vf == 0xffff)