]> git.droids-corp.org - dpdk.git/commitdiff
common/mlx5: fix umem buffer alignment
authorDekel Peled <dekelp@mellanox.com>
Mon, 11 May 2020 10:02:45 +0000 (13:02 +0300)
committerFerruh Yigit <ferruh.yigit@intel.com>
Mon, 18 May 2020 18:35:56 +0000 (20:35 +0200)
The value MLX5_WQE_BUF_ALIGNMENT is defined as 512.
In some cases this alignment size is not adequate, which results in
memory registration that is not accepted by FW.
The result error can be "page_offset is not aligned to page_size/64,
bad umem_offset" (syndrome 0x357275).

This patch updates the definition to match the running system.

Fixes: 18a68e046b51 ("net/mlx5: fix DevX Rx queue memory alignment")
Cc: stable@dpdk.org
Signed-off-by: Dekel Peled <dekelp@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
drivers/common/mlx5/mlx5_prm.h

index 4ab1c7593016a415c4f6ab89fb63b0dcb068926a..b39a141d740b6165dc5039b71e383d118f742ff3 100644 (file)
@@ -16,6 +16,8 @@
 #pragma GCC diagnostic error "-Wpedantic"
 #endif
 
+#include <unistd.h>
+
 #include <rte_vect.h>
 #include <rte_byteorder.h>
 
 #define MLX5_MAX_LOG_RQ_SEGS 5u
 
 /* The alignment needed for WQ buffer. */
-#define MLX5_WQE_BUF_ALIGNMENT 512
+#define MLX5_WQE_BUF_ALIGNMENT sysconf(_SC_PAGESIZE)
 
 /* Completion mode. */
 enum mlx5_completion_mode {