hw_vlan_strip : 1, /**< VLAN strip enable. */
hw_vlan_extend : 1, /**< Extended VLAN enable. */
jumbo_frame : 1, /**< Jumbo Frame Receipt enable. */
- hw_strip_crc : 1; /**< Enable CRC stripping by hardware. */
+ hw_strip_crc : 1, /**< Enable CRC stripping by hardware. */
+ enable_scatter : 1; /**< Enable scatter packets rx handler */
};
/**
}
}
+ if (dev->data->dev_conf.rxmode.enable_scatter) {
+ dev->rx_pkt_burst = eth_em_recv_scattered_pkts;
+ dev->data->scattered_rx = 1;
+ }
+
/*
* Setup the Checksum Register.
* Receive Full-Packet Checksum Offload is mutually exclusive with RSS.
E1000_WRITE_REG(hw, E1000_RXDCTL(rxq->reg_idx), rxdctl);
}
+ if (dev->data->dev_conf.rxmode.enable_scatter) {
+ dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
+ dev->data->scattered_rx = 1;
+ }
+
/*
* Setup BSIZE field of RCTL register, if needed.
* Buffer sizes >= 1024 are not [supposed to be] setup in the RCTL
E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
}
+ if (dev->data->dev_conf.rxmode.enable_scatter) {
+ dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
+ dev->data->scattered_rx = 1;
+ }
+
/*
* Setup the HW Rx Head and Tail Descriptor Pointers.
* This needs to be done after enable.
}
}
+ if (dev->data->dev_conf.rxmode.enable_scatter) {
+ dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
+ dev->data->scattered_rx = 1;
+ }
+
/*
* Device configured with multiple RX queues.
*/
}
}
+ if (dev->data->dev_conf.rxmode.enable_scatter) {
+ dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
+ dev->data->scattered_rx = 1;
+ }
+
return 0;
}