examples/pipeline: add l2fwd with MAC swap example

Add L2 Forwarding example with MAC destination and source address swap
to the SWX pipeline application. Example command line:
./build/pipeline -l0-1 -- -s ./examples/l2fwd_macswp.cli

Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>

diff --git a/examples/pipeline/examples/l2fwd_macswp.cli b/examples/pipeline/examples/l2fwd_macswp.cli
new file mode 100644 (file)
index 0000000..0f2a89a
--- /dev/null
+++ b/examples/pipeline/examples/l2fwd_macswp.cli
@@ -0,0 +1,25 @@
+; SPDX-License-Identifier: BSD-3-Clause
+; Copyright(c) 2020 Intel Corporation
+
+mempool MEMPOOL0 buffer 2304 pool 32K cache 256 cpu 0
+
+link LINK0 dev 0000:18:00.0 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on
+link LINK1 dev 0000:18:00.1 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on
+link LINK2 dev 0000:3b:00.0 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on
+link LINK3 dev 0000:3b:00.1 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on
+
+pipeline PIPELINE0 create 0
+
+pipeline PIPELINE0 port in 0 link LINK0 rxq 0 bsz 32
+pipeline PIPELINE0 port in 1 link LINK1 rxq 0 bsz 32
+pipeline PIPELINE0 port in 2 link LINK2 rxq 0 bsz 32
+pipeline PIPELINE0 port in 3 link LINK3 rxq 0 bsz 32
+
+pipeline PIPELINE0 port out 0 link LINK0 txq 0 bsz 32
+pipeline PIPELINE0 port out 1 link LINK1 txq 0 bsz 32
+pipeline PIPELINE0 port out 2 link LINK2 txq 0 bsz 32
+pipeline PIPELINE0 port out 3 link LINK3 txq 0 bsz 32
+
+pipeline PIPELINE0 build ./examples/pipeline/examples/l2fwd_macswp.spec
+
+thread 1 pipeline PIPELINE0 enable

diff --git a/examples/pipeline/examples/l2fwd_macswp.spec b/examples/pipeline/examples/l2fwd_macswp.spec
new file mode 100644 (file)
index 0000000..e81f206
--- /dev/null
+++ b/examples/pipeline/examples/l2fwd_macswp.spec
@@ -0,0 +1,59 @@
+; SPDX-License-Identifier: BSD-3-Clause
+; Copyright(c) 2020 Intel Corporation
+
+//
+// Packet headers.
+//
+struct ethernet_h {
+       bit<48> dst_addr
+       bit<48> src_addr
+       bit<16> ether_type
+}
+
+header ethernet instanceof ethernet_h
+
+//
+// Packet meta-data.
+//
+struct metadata_t {
+       bit<32> port
+       bit<48> addr
+}
+
+metadata instanceof metadata_t
+
+//
+// Actions.
+//
+action macswp args none {
+       mov m.addr h.ethernet.dst_addr
+       mov h.ethernet.dst_addr h.ethernet.src_addr
+       mov h.ethernet.src_addr m.addr
+       return
+}
+
+//
+// Tables.
+//
+table stub {
+       key {
+       }
+
+       actions {
+               macswp
+       }
+
+       default_action macswp args none const
+}
+
+//
+// Pipeline.
+//
+apply {
+       rx m.port
+       extract h.ethernet
+       table stub
+       xor m.port 1
+       emit h.ethernet
+       tx m.port
+}

diff --git a/examples/pipeline/examples/l2fwd_macswp_pcap.cli b/examples/pipeline/examples/l2fwd_macswp_pcap.cli
new file mode 100644 (file)
index 0000000..043379c
--- /dev/null
+++ b/examples/pipeline/examples/l2fwd_macswp_pcap.cli
@@ -0,0 +1,20 @@
+; SPDX-License-Identifier: BSD-3-Clause
+; Copyright(c) 2020 Intel Corporation
+
+mempool MEMPOOL0 buffer 2304 pool 32K cache 256 cpu 0
+
+pipeline PIPELINE0 create 0
+
+pipeline PIPELINE0 port in 0 source MEMPOOL0 ./examples/packet.pcap
+pipeline PIPELINE0 port in 1 source MEMPOOL0 ./examples/packet.pcap
+pipeline PIPELINE0 port in 2 source MEMPOOL0 ./examples/packet.pcap
+pipeline PIPELINE0 port in 3 source MEMPOOL0 ./examples/packet.pcap
+
+pipeline PIPELINE0 port out 0 sink none
+pipeline PIPELINE0 port out 1 sink none
+pipeline PIPELINE0 port out 2 sink none
+pipeline PIPELINE0 port out 3 sink none
+
+pipeline PIPELINE0 build ./examples/l2fwd_macswp.spec
+
+thread 1 pipeline PIPELINE0 enable