net/hns3: get device capability from firmware
authorWei Hu (Xavier) <xavier.huwei@huawei.com>
Tue, 25 Aug 2020 11:52:55 +0000 (19:52 +0800)
committerFerruh Yigit <ferruh.yigit@intel.com>
Fri, 18 Sep 2020 16:55:07 +0000 (18:55 +0200)
This patch adds getting device capabilities from firmware, so driver can
supply different capabilities and specifications to upper level
applications base on different versions of hardware network engine.

Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com>
drivers/net/hns3/hns3_cmd.c
drivers/net/hns3/hns3_cmd.h
drivers/net/hns3/hns3_ethdev.c
drivers/net/hns3/hns3_ethdev.h

index cbb0988..0299072 100644 (file)
@@ -426,8 +426,29 @@ hns3_cmd_send(struct hns3_hw *hw, struct hns3_cmd_desc *desc, int num)
        return retval;
 }
 
+static void hns3_parse_capability(struct hns3_hw *hw,
+                                 struct hns3_query_version_cmd *cmd)
+{
+       uint32_t caps = rte_le_to_cpu_32(cmd->caps[0]);
+
+       if (hns3_get_bit(caps, HNS3_CAPS_UDP_GSO_B))
+               hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_UDP_GSO_B, 1);
+       if (hns3_get_bit(caps, HNS3_CAPS_ADQ_B))
+               hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_ADQ_B, 1);
+       if (hns3_get_bit(caps, HNS3_CAPS_PTP_B))
+               hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_PTP_B, 1);
+       if (hns3_get_bit(caps, HNS3_CAPS_TX_PUSH_B))
+               hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_TX_PUSH_B, 1);
+       if (hns3_get_bit(caps, HNS3_CAPS_PHY_IMP_B))
+               hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_COPPER_B, 1);
+       if (hns3_get_bit(caps, HNS3_CAPS_TQP_TXRX_INDEP_B))
+               hns3_set_bit(hw->capability, HNS3_CAPS_TQP_TXRX_INDEP_B, 1);
+       if (hns3_get_bit(caps, HNS3_CAPS_STASH_B))
+               hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_STASH_B, 1);
+}
+
 static enum hns3_cmd_status
-hns3_cmd_query_firmware_version(struct hns3_hw *hw, uint32_t *version)
+hns3_cmd_query_firmware_version_and_capability(struct hns3_hw *hw)
 {
        struct hns3_query_version_cmd *resp;
        struct hns3_cmd_desc desc;
@@ -438,10 +459,13 @@ hns3_cmd_query_firmware_version(struct hns3_hw *hw, uint32_t *version)
 
        /* Initialize the cmd function */
        ret = hns3_cmd_send(hw, &desc, 1);
-       if (ret == 0)
-               *version = rte_le_to_cpu_32(resp->firmware);
+       if (ret)
+               return ret;
 
-       return ret;
+       hw->fw_version = rte_le_to_cpu_32(resp->firmware);
+       hns3_parse_capability(hw, resp);
+
+       return 0;
 }
 
 int
@@ -519,13 +543,13 @@ hns3_cmd_init(struct hns3_hw *hw)
        }
        rte_atomic16_clear(&hw->reset.disable_cmd);
 
-       ret = hns3_cmd_query_firmware_version(hw, &version);
+       ret = hns3_cmd_query_firmware_version_and_capability(hw);
        if (ret) {
                PMD_INIT_LOG(ERR, "firmware version query failed %d", ret);
                goto err_cmd_init;
        }
 
-       hw->fw_version = version;
+       version = hw->fw_version;
        PMD_INIT_LOG(INFO, "The firmware version is %lu.%lu.%lu.%lu",
                     hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
                                    HNS3_FW_VERSION_BYTE3_S),
index d70f42e..a13b799 100644 (file)
@@ -264,9 +264,26 @@ struct hns3_rx_priv_buff_cmd {
 #define HNS3_FW_VERSION_BYTE1_M                GENMASK(15, 8)
 #define HNS3_FW_VERSION_BYTE0_S                0
 #define HNS3_FW_VERSION_BYTE0_M                GENMASK(7, 0)
+
+enum HNS3_CAPS_BITS {
+       HNS3_CAPS_UDP_GSO_B,
+       HNS3_CAPS_ATR_B,
+       HNS3_CAPS_ADQ_B,
+       HNS3_CAPS_PTP_B,
+       HNS3_CAPS_INT_QL_B,
+       HNS3_CAPS_SIMPLE_BD_B,
+       HNS3_CAPS_TX_PUSH_B,
+       HNS3_CAPS_PHY_IMP_B,
+       HNS3_CAPS_TQP_TXRX_INDEP_B,
+       HNS3_CAPS_HW_PAD_B,
+       HNS3_CAPS_STASH_B,
+};
+#define HNS3_QUERY_CAP_LENGTH          3
 struct hns3_query_version_cmd {
        uint32_t firmware;
-       uint32_t firmware_rsv[5];
+       uint32_t hardware;
+       uint32_t rsv;
+       uint32_t caps[HNS3_QUERY_CAP_LENGTH]; /* capabilities of device */
 };
 
 #define HNS3_RX_PRIV_EN_B      15
index fab1914..44fd69f 100644 (file)
@@ -2837,9 +2837,6 @@ hns3_get_capability(struct hns3_hw *hw)
        }
        hw->revision = revision;
 
-       if (revision >= PCI_REVISION_ID_HIP09_A)
-               hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_COPPER_B, 1);
-
        return 0;
 }
 
index 0e665e5..1914e58 100644 (file)
@@ -535,13 +535,42 @@ struct hns3_adapter {
 
 #define HNS3_DEV_SUPPORT_DCB_B                 0x0
 #define HNS3_DEV_SUPPORT_COPPER_B              0x1
+#define HNS3_DEV_SUPPORT_UDP_GSO_B             0x2
+#define HNS3_DEV_SUPPORT_ADQ_B                 0x3
+#define HNS3_DEV_SUPPORT_PTP_B                 0x4
+#define HNS3_DEV_SUPPORT_TX_PUSH_B             0x5
+#define HNS3_DEV_SUPPORT_INDEP_TXRX_B          0x6
+#define HNS3_DEV_SUPPORT_STASH_B               0x7
 
 #define hns3_dev_dcb_supported(hw) \
        hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_DCB_B)
 
+/* Support copper media type */
 #define hns3_dev_copper_supported(hw) \
        hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_COPPER_B)
 
+/* Support UDP GSO offload */
+#define hns3_dev_udp_gso_supported(hw) \
+       hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_UDP_GSO_B)
+
+/* Support Application Device Queue */
+#define hns3_dev_adq_supported(hw) \
+       hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_ADQ_B)
+
+/* Support PTP timestamp offload */
+#define hns3_dev_ptp_supported(hw) \
+       hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_PTP_B)
+
+#define hns3_dev_tx_push_supported(hw) \
+       hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_TX_PUSH_B)
+
+/* Support to Independently enable/disable/reset Tx or Rx queues */
+#define hns3_dev_indep_txrx_supported(hw) \
+       hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_INDEP_TXRX_B)
+
+#define hns3_dev_stash_supported(hw) \
+       hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_STASH_B)
+
 #define HNS3_DEV_PRIVATE_TO_HW(adapter) \
        (&((struct hns3_adapter *)adapter)->hw)
 #define HNS3_DEV_PRIVATE_TO_ADAPTER(adapter) \