common/mlx5: add virtio queue protection domain

Starting from FW version 22.27.4002, it is required to
configure protection domain (PD) for each virtq created by
DevX.

Add PD requirement in virtq DevX APIs.

Cc: stable@dpdk.org
Signed-off-by: Matan Azrad <matan@mellanox.com>
Signed-off-by: Xueming Li <xuemingl@mellanox.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>

diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c
index c5dba299e853ce12578bb01a93df4627a2fc6f77..ec92eb60e51f21be167e4caf97e4ed0109c608d0 100644 (file)
--- a/drivers/common/mlx5/mlx5_devx_cmds.c
+++ b/drivers/common/mlx5/mlx5_devx_cmds.c
@@ -1269,6 +1269,7 @@ mlx5_devx_cmd_create_virtq(void *ctx,
        MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size);
        MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset);
        MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id);
+       MLX5_SET(virtio_q, virtctx, pd, attr->pd);
        MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id);
        virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
                                                    sizeof(out));

diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h
index 59a70a0e047be4c5624724d5a28edc254748ba48..3ce44c353ec07e74f294c56e12c7920dfc9dc800 100644 (file)
--- a/drivers/common/mlx5/mlx5_devx_cmds.h
+++ b/drivers/common/mlx5/mlx5_devx_cmds.h
@@ -259,6 +259,7 @@ struct mlx5_devx_virtq_attr {
        uint16_t hw_available_index;
        uint16_t hw_used_index;
        uint16_t q_size;
+       uint32_t pd:24;
        uint32_t virtio_version_1_0:1;
        uint32_t tso_ipv4:1;
        uint32_t tso_ipv6:1;

diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 5fc10d688a0556d382d362b43020c7ddcdaf1e39..c63795fc84c5cc542287a84d77223fe4cc82c4a9 100644 (file)
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -2088,7 +2088,9 @@ struct mlx5_ifc_virtio_q_bits {
        u8 umem_3_size[0x20];
        u8 umem_3_offset[0x40];
        u8 counter_set_id[0x20];
-       u8 reserved_at_320[0xe0];
+       u8 reserved_at_320[0x8];
+       u8 pd[0x18];
+       u8 reserved_at_340[0xc0];
 };
 
 struct mlx5_ifc_virtio_net_q_bits {