net/mlx5: remove CQE padding device argument

The data-path code doesn't take care on 'rxq_cqe_pad_en' and use padded
CQE for any case when the system cache-line size is 128B.

This makes the argument redundant.

Remove it.

Fixes: bc91e8db12cd ("net/mlx5: add 128B padding of Rx completion entry")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index 3bda0f84176dffd335f54f022b7e9724c0d5d04a..6950cc1188e89f2b3f40fa098c20f8cdf23c9ec6 100644 (file)
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -448,24 +448,6 @@ Driver options
   - POWER9 and ARMv8 with ConnectX-4 Lx, ConnectX-5, ConnectX-6, ConnectX-6 Dx,
     ConnectX-6 Lx, BlueField and BlueField-2.
 
-- ``rxq_cqe_pad_en`` parameter [int]
-
-  A nonzero value enables 128B padding of CQE on RX side. The size of CQE
-  is aligned with the size of a cacheline of the core. If cacheline size is
-  128B, the CQE size is configured to be 128B even though the device writes
-  only 64B data on the cacheline. This is to avoid unnecessary cache
-  invalidation by device's two consecutive writes on to one cacheline.
-  However in some architecture, it is more beneficial to update entire
-  cacheline with padding the rest 64B rather than striding because
-  read-modify-write could drop performance a lot. On the other hand,
-  writing extra data will consume more PCIe bandwidth and could also drop
-  the maximum throughput. It is recommended to empirically set this
-  parameter. Disabled by default.
-
-  Supported on:
-
-  - CPU having 128B cacheline with ConnectX-5 and BlueField.
-
 - ``rxq_pkt_pad_en`` parameter [int]
 
   A nonzero value enables padding Rx packet to the size of cacheline on PCI

diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c
index 6812a1f2152a6093b8950ccf09901d255732b40d..9ac1d46b1b88275d8512ac795d1d3fb0b8ecb13d 100644 (file)
--- a/drivers/net/mlx5/linux/mlx5_os.c
+++ b/drivers/net/mlx5/linux/mlx5_os.c
@@ -677,7 +677,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
        unsigned int hw_padding = 0;
        unsigned int mps;
        unsigned int cqe_comp;
-       unsigned int cqe_pad = 0;
        unsigned int tunnel_en = 0;
        unsigned int mpls_en = 0;
        unsigned int swp = 0;
@@ -875,11 +874,6 @@ err_secondary:
        else
                cqe_comp = 1;
        config->cqe_comp = cqe_comp;
-#ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
-       /* Whether device supports 128B Rx CQE padding. */
-       cqe_pad = RTE_CACHE_LINE_SIZE == 128 &&
-                 (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD);
-#endif
 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
        if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
                tunnel_en = ((dv_attr.tunnel_offloads_caps &
@@ -1116,12 +1110,6 @@ err_secondary:
                DRV_LOG(WARNING, "Rx CQE compression isn't supported");
                config->cqe_comp = 0;
        }
-       if (config->cqe_pad && !cqe_pad) {
-               DRV_LOG(WARNING, "Rx CQE padding isn't supported");
-               config->cqe_pad = 0;
-       } else if (config->cqe_pad) {
-               DRV_LOG(INFO, "Rx CQE padding is enabled");
-       }
        if (config->devx) {
                err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config->hca_attr);
                if (err) {

diff --git a/drivers/net/mlx5/linux/mlx5_verbs.c b/drivers/net/mlx5/linux/mlx5_verbs.c
index b52ae2e6c110548a0ed8f1d3b4c47dc9efe2d3de..318e39b1dfd9f5b598e2735a70a91efc0df645f4 100644 (file)
--- a/drivers/net/mlx5/linux/mlx5_verbs.c
+++ b/drivers/net/mlx5/linux/mlx5_verbs.c
@@ -234,7 +234,7 @@ mlx5_rxq_ibv_cq_create(struct rte_eth_dev *dev, uint16_t idx)
                        dev->data->port_id);
        }
 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
-       if (priv->config.cqe_pad) {
+       if (RTE_CACHE_LINE_SIZE == 128) {
                cq_attr.mlx5.comp_mask |= MLX5DV_CQ_INIT_ATTR_MASK_FLAGS;
                cq_attr.mlx5.flags |= MLX5DV_CQ_INIT_ATTR_FLAGS_CQE_PAD;
        }

diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c
index e47ad6bd42d9e7abb35bc7afca351972047541c4..1afad046b55e3027ca9df4cbb1ad9e61cb7bd016 100644 (file)
--- a/drivers/net/mlx5/mlx5.c
+++ b/drivers/net/mlx5/mlx5.c
@@ -44,9 +44,6 @@
 /* Device parameter to enable RX completion queue compression. */
 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
 
-/* Device parameter to enable RX completion entry padding to 128B. */
-#define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
-
 /* Device parameter to enable padding Rx packet to cacheline size. */
 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
 
@@ -1633,8 +1630,6 @@ mlx5_args_check(const char *key, const char *val, void *opaque)
                }
                config->cqe_comp = !!tmp;
                config->cqe_comp_fmt = tmp;
-       } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
-               config->cqe_pad = !!tmp;
        } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
                config->hw_padding = !!tmp;
        } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
@@ -1763,7 +1758,6 @@ mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
 {
        const char **params = (const char *[]){
                MLX5_RXQ_CQE_COMP_EN,
-               MLX5_RXQ_CQE_PAD_EN,
                MLX5_RXQ_PKT_PAD_EN,
                MLX5_RX_MPRQ_EN,
                MLX5_RX_MPRQ_LOG_STRIDE_NUM,

diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index 41034f5d197b931b3da9f27f056982bb117ee5a1..92a5d042257eb4f10cfcdbff5ababb4115f02857 100644 (file)
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -212,7 +212,6 @@ struct mlx5_dev_config {
        unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
        unsigned int cqe_comp:1; /* CQE compression is enabled. */
        unsigned int cqe_comp_fmt:3; /* CQE compression format. */
-       unsigned int cqe_pad:1; /* CQE padding is enabled. */
        unsigned int tso:1; /* Whether TSO is supported. */
        unsigned int rx_vec_en:1; /* Rx vector is enabled. */
        unsigned int mr_ext_memseg_en:1;

diff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c
index fdd69fd3c193416c8aebe3cb1a486633a9d5bbb9..b036432937d503ad0fe35ecaa157c6aeabb48486 100644 (file)
--- a/drivers/net/mlx5/windows/mlx5_os.c
+++ b/drivers/net/mlx5/windows/mlx5_os.c
@@ -313,7 +313,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
        struct mlx5_priv *priv = NULL;
        int err = 0;
        unsigned int cqe_comp;
-       unsigned int cqe_pad = 0;
        struct rte_ether_addr mac;
        char name[RTE_ETH_NAME_MAX_LEN];
        int own_domain_id = 0;
@@ -461,12 +460,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
                DRV_LOG(WARNING, "Rx CQE compression isn't supported.");
                config->cqe_comp = 0;
        }
-       if (config->cqe_pad && !cqe_pad) {
-               DRV_LOG(WARNING, "Rx CQE padding isn't supported.");
-               config->cqe_pad = 0;
-       } else if (config->cqe_pad) {
-               DRV_LOG(INFO, "Rx CQE padding is enabled.");
-       }
        if (config->devx) {
                err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config->hca_attr);
                if (err) {