ixgbe/base: iosf sideband read/write

Signed-off-by: Changchun Ouyang <changchun.ouyang@intel.com>
[Thomas: split patch]

diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.c
index 5cbd055..88137cf 100644 (file)
--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.c
+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.c
@@ -1122,6 +1122,38 @@ void ixgbe_set_ethertype_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
                hw->mac.ops.set_ethertype_anti_spoofing(hw, enable, vf);
 }
 
+/**
+ *  ixgbe_read_iosf_sb_reg - Read 32 bit PHY register
+ *  @hw: pointer to hardware structure
+ *  @reg_addr: 32 bit address of PHY register to read
+ *  @device_type: type of device you want to communicate with
+ *  @phy_data: Pointer to read data from PHY register
+ *
+ *  Reads a value from a specified PHY register
+ **/
+s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,
+                          u32 device_type, u32 *phy_data)
+{
+       return ixgbe_call_func(hw, hw->mac.ops.read_iosf_sb_reg, (hw, reg_addr,
+                              device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_write_iosf_sb_reg - Write 32 bit register through IOSF Sideband
+ *  @hw: pointer to hardware structure
+ *  @reg_addr: 32 bit PHY register to write
+ *  @device_type: type of device you want to communicate with
+ *  @phy_data: Data to write to the PHY register
+ *
+ *  Writes a value to specified PHY register
+ **/
+s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,
+                           u32 device_type, u32 phy_data)
+{
+       return ixgbe_call_func(hw, hw->mac.ops.write_iosf_sb_reg, (hw, reg_addr,
+                              device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
+}
+
 /**
  *  ixgbe_read_analog_reg8 - Reads 8 bit analog register
  *  @hw: pointer to hardware structure

diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.h b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.h
index 5c88278..7c2cffb 100644 (file)
--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.h
+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.h
@@ -187,6 +187,10 @@ void ixgbe_set_source_address_pruning(struct ixgbe_hw *hw, bool enable,
                                      unsigned int vf);
 void ixgbe_set_ethertype_anti_spoofing(struct ixgbe_hw *hw, bool enable,
                                       int vf);
+s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,
+                       u32 device_type, u32 *phy_data);
+s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,
+                       u32 device_type, u32 phy_data);
 void ixgbe_disable_rx(struct ixgbe_hw *hw);
 void ixgbe_enable_rx(struct ixgbe_hw *hw);
 

diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h
index bc230e0..dfb1477 100644 (file)
--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h
+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h
@@ -3259,6 +3259,8 @@ struct ixgbe_mac_operations {
                                           unsigned int);
        void (*disable_rx)(struct ixgbe_hw *hw);
        void (*enable_rx)(struct ixgbe_hw *hw);
+       s32 (*read_iosf_sb_reg)(struct ixgbe_hw *, u32, u32, u32 *);
+       s32 (*write_iosf_sb_reg)(struct ixgbe_hw *, u32, u32, u32);
 };
 
 struct ixgbe_phy_operations {
@@ -3447,8 +3449,23 @@ struct ixgbe_hw {
 #define IXGBE_NOT_IMPLEMENTED                  0x7FFFFFFF
 
 
-#ifdef IXGBE_OSDEP2
-#include "ixgbe_osdep2.h"
+#define IXGBE_SB_IOSF_INDIRECT_CTRL    0x00011144
+#define IXGBE_SB_IOSF_INDIRECT_DATA    0x00011148
+
+#define IXGBE_SB_IOSF_CTRL_ADDR_SHIFT          0
+#define IXGBE_SB_IOSF_CTRL_ADDR_MASK           0xFF
+#define IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT     18
+#define IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK      \
+                               (0x3 << IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT)
+#define IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT      20
+#define IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK       \
+                               (0xFF << IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT)
+#define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT 28
+#define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_MASK  0x7
+#define IXGBE_SB_IOSF_CTRL_BUSY_SHIFT          31
+#define IXGBE_SB_IOSF_CTRL_BUSY                (1 << IXGBE_SB_IOSF_CTRL_BUSY_SHIFT)
+#define IXGBE_SB_IOSF_TARGET_KR_PHY    0
+#define IXGBE_SB_IOSF_TARGET_KX4_PHY   1
+#define IXGBE_SB_IOSF_TARGET_KX4_PCS   2
 
-#endif /* IXGBE_OSDEP2 */
 #endif /* _IXGBE_TYPE_H_ */