evdev_dlb2_default_info.max_event_ports =
dlb2->hw_rsrc_query_results.num_ldb_ports;
- evdev_dlb2_default_info.max_num_events =
- dlb2->hw_rsrc_query_results.num_ldb_credits;
-
+ if (dlb2->version == DLB2_HW_V2_5) {
+ evdev_dlb2_default_info.max_num_events =
+ dlb2->hw_rsrc_query_results.num_credits;
+ } else {
+ evdev_dlb2_default_info.max_num_events =
+ dlb2->hw_rsrc_query_results.num_ldb_credits;
+ }
/* Save off values used when creating the scheduling domain. */
handle->info.num_sched_domains =
dlb2->hw_rsrc_query_results.num_sched_domains;
- handle->info.hw_rsrc_max.nb_events_limit =
- dlb2->hw_rsrc_query_results.num_ldb_credits;
-
+ if (dlb2->version == DLB2_HW_V2_5) {
+ handle->info.hw_rsrc_max.nb_events_limit =
+ dlb2->hw_rsrc_query_results.num_credits;
+ } else {
+ handle->info.hw_rsrc_max.nb_events_limit =
+ dlb2->hw_rsrc_query_results.num_ldb_credits;
+ }
handle->info.hw_rsrc_max.num_queues =
dlb2->hw_rsrc_query_results.num_ldb_queues +
dlb2->hw_rsrc_query_results.num_dir_ports;
* contiguous range of history list entries.
* - num_ldb_credits: Amount of available load-balanced QE storage.
* - num_dir_credits: Amount of available directed QE storage.
+ * - response.status: Detailed error code. In certain cases, such as if the
+ * ioctl request arg is invalid, the driver won't set status.
*/
struct dlb2_get_num_resources_args {
/* Output parameters */
+ struct dlb2_cmd_response response;
__u32 num_sched_domains;
__u32 num_ldb_queues;
__u32 num_ldb_ports;
__u32 num_atomic_inflights;
__u32 num_hist_list_entries;
__u32 max_contiguous_hist_list_entries;
- __u32 num_ldb_credits;
- __u32 num_dir_credits;
+ union {
+ struct {
+ __u32 num_ldb_credits;
+ __u32 num_dir_credits;
+ };
+ struct {
+ __u32 num_credits;
+ };
+ };
};
/*
DLB2_CSR_WR(hw, DLB2_CHP_CFG_CHP_CSR_CTRL, r0.val);
}
-int dlb2_hw_get_num_resources(struct dlb2_hw *hw,
- struct dlb2_get_num_resources_args *arg,
- bool vdev_req,
- unsigned int vdev_id)
-{
- struct dlb2_function_resources *rsrcs;
- struct dlb2_bitmap *map;
- int i;
-
- if (vdev_req && vdev_id >= DLB2_MAX_NUM_VDEVS)
- return -EINVAL;
-
- if (vdev_req)
- rsrcs = &hw->vdev[vdev_id];
- else
- rsrcs = &hw->pf;
-
- arg->num_sched_domains = rsrcs->num_avail_domains;
-
- arg->num_ldb_queues = rsrcs->num_avail_ldb_queues;
-
- arg->num_ldb_ports = 0;
- for (i = 0; i < DLB2_NUM_COS_DOMAINS; i++)
- arg->num_ldb_ports += rsrcs->num_avail_ldb_ports[i];
-
- arg->num_cos_ldb_ports[0] = rsrcs->num_avail_ldb_ports[0];
- arg->num_cos_ldb_ports[1] = rsrcs->num_avail_ldb_ports[1];
- arg->num_cos_ldb_ports[2] = rsrcs->num_avail_ldb_ports[2];
- arg->num_cos_ldb_ports[3] = rsrcs->num_avail_ldb_ports[3];
-
- arg->num_dir_ports = rsrcs->num_avail_dir_pq_pairs;
-
- arg->num_atomic_inflights = rsrcs->num_avail_aqed_entries;
-
- map = rsrcs->avail_hist_list_entries;
-
- arg->num_hist_list_entries = dlb2_bitmap_count(map);
-
- arg->max_contiguous_hist_list_entries =
- dlb2_bitmap_longest_set_range(map);
-
- arg->num_ldb_credits = rsrcs->num_avail_qed_entries;
-
- arg->num_dir_credits = rsrcs->num_avail_dqed_entries;
-
- return 0;
-}
-
void dlb2_hw_enable_sparse_ldb_cq_mode(struct dlb2_hw *hw)
{
union dlb2_chp_cfg_chp_csr_ctrl r0;
DLB2_CSR_WR(hw, DLB2_CM_CFG_PM_PMCSR_DISABLE(ver), pmcsr_dis);
}
+/**
+ * dlb2_hw_get_num_resources() - query the PCI function's available resources
+ * @hw: dlb2_hw handle for a particular device.
+ * @arg: pointer to resource counts.
+ * @vdev_req: indicates whether this request came from a vdev.
+ * @vdev_id: If vdev_req is true, this contains the vdev's ID.
+ *
+ * This function returns the number of available resources for the PF or for a
+ * VF.
+ *
+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual
+ * device.
+ *
+ * Return:
+ * Returns 0 upon success, -EINVAL if vdev_req is true and vdev_id is
+ * invalid.
+ */
+int dlb2_hw_get_num_resources(struct dlb2_hw *hw,
+ struct dlb2_get_num_resources_args *arg,
+ bool vdev_req,
+ unsigned int vdev_id)
+{
+ struct dlb2_function_resources *rsrcs;
+ struct dlb2_bitmap *map;
+ int i;
+
+ if (vdev_req && vdev_id >= DLB2_MAX_NUM_VDEVS)
+ return -EINVAL;
+
+ if (vdev_req)
+ rsrcs = &hw->vdev[vdev_id];
+ else
+ rsrcs = &hw->pf;
+
+ arg->num_sched_domains = rsrcs->num_avail_domains;
+
+ arg->num_ldb_queues = rsrcs->num_avail_ldb_queues;
+
+ arg->num_ldb_ports = 0;
+ for (i = 0; i < DLB2_NUM_COS_DOMAINS; i++)
+ arg->num_ldb_ports += rsrcs->num_avail_ldb_ports[i];
+
+ arg->num_cos_ldb_ports[0] = rsrcs->num_avail_ldb_ports[0];
+ arg->num_cos_ldb_ports[1] = rsrcs->num_avail_ldb_ports[1];
+ arg->num_cos_ldb_ports[2] = rsrcs->num_avail_ldb_ports[2];
+ arg->num_cos_ldb_ports[3] = rsrcs->num_avail_ldb_ports[3];
+
+ arg->num_dir_ports = rsrcs->num_avail_dir_pq_pairs;
+
+ arg->num_atomic_inflights = rsrcs->num_avail_aqed_entries;
+
+ map = rsrcs->avail_hist_list_entries;
+
+ arg->num_hist_list_entries = dlb2_bitmap_count(map);
+
+ arg->max_contiguous_hist_list_entries =
+ dlb2_bitmap_longest_set_range(map);
+
+ if (hw->ver == DLB2_HW_V2) {
+ arg->num_ldb_credits = rsrcs->num_avail_qed_entries;
+ arg->num_dir_credits = rsrcs->num_avail_dqed_entries;
+ } else {
+ arg->num_credits = rsrcs->num_avail_entries;
+ }
+ return 0;
+}