net/mlx5: replace I/O memory barrier with coherent version

Signed-off-by: Yongseok Koh <yskoh@mellanox.com>

diff --git a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c
index 3b8f71c281422a2a8f387584d8dd53ba389751f7..7a24d671db38de73e64185d1849a583ae001e88f 100644 (file)
--- a/drivers/net/mlx5/mlx5_rxtx.c
+++ b/drivers/net/mlx5/mlx5_rxtx.c
@@ -1898,9 +1898,9 @@ skip:
                return 0;
        /* Update the consumer index. */
        rxq->rq_ci = rq_ci >> sges_n;
-       rte_io_wmb();
+       rte_cio_wmb();
        *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
-       rte_io_wmb();
+       rte_cio_wmb();
        *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
 #ifdef MLX5_PMD_SOFT_COUNTERS
        /* Increment packets counter. */

diff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h
index 2eb2f0506354a17097c96bb6d532a6bcf33b84c6..9d984436539b629d720ec8c1bec91ea98eb6f9de 100644 (file)
--- a/drivers/net/mlx5/mlx5_rxtx.h
+++ b/drivers/net/mlx5/mlx5_rxtx.h
@@ -598,7 +598,7 @@ mlx5_tx_dbrec_cond_wmb(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe,
        uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
        volatile uint64_t *src = ((volatile uint64_t *)wqe);
 
-       rte_io_wmb();
+       rte_cio_wmb();
        *txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci);
        /* Ensure ordering between DB record and BF copy. */
        rte_wmb();

diff --git a/drivers/net/mlx5/mlx5_rxtx_vec.h b/drivers/net/mlx5/mlx5_rxtx_vec.h
index 7d7f016f16eb754f9035b3cd0aa9e210f8877713..be133a48110eb352fc1fa8d13a60da36d295d9a9 100644 (file)
--- a/drivers/net/mlx5/mlx5_rxtx_vec.h
+++ b/drivers/net/mlx5/mlx5_rxtx_vec.h
@@ -135,7 +135,7 @@ mlx5_rx_replenish_bulk_mbuf(struct mlx5_rxq_data *rxq, uint16_t n)
        elts_idx = rxq->rq_ci & q_mask;
        for (i = 0; i < MLX5_VPMD_DESCS_PER_LOOP; ++i)
                (*rxq->elts)[elts_idx + i] = &rxq->fake_mbuf;
-       rte_io_wmb();
+       rte_cio_wmb();
        *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
 }