eal: add cache line demotion API

rte_cldemote is similar to a prefetch hint - in reverse.
On x86, cldemote(addr) enables software to hint to hardware that line is
likely to be shared. This is quite useful in core-to-core communications
where cache-line is likely to be shared.
ARM and PPC implementation is provided with NOP and can be added if any
equivalent instructions could be used for implementation on those
architectures.

Signed-off-by: Omkar Maslekar <omkar.maslekar@intel.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: David Christensen <drc@linux.vnet.ibm.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>

diff --git a/app/test/test_prefetch.c b/app/test/test_prefetch.c
index 32e08f8afe29154f45e420b2d92c9c1de6d3af82..5489885b518f680ed30268530af17dfc0fac255b 100644 (file)
--- a/app/test/test_prefetch.c
+++ b/app/test/test_prefetch.c
@@ -30,6 +30,8 @@ test_prefetch(void)
        rte_prefetch1_write(&a);
        rte_prefetch2_write(&a);
 
+       rte_cldemote(&a);
+
        return 0;
 }
 

diff --git a/doc/guides/rel_notes/release_20_11.rst b/doc/guides/rel_notes/release_20_11.rst
index cda5b2f5b25d2399dc5f1dd2ecfd3a8ad2e34686..48717ee5368b63119e962b35aa7232ddca9721d0 100644 (file)
--- a/doc/guides/rel_notes/release_20_11.rst
+++ b/doc/guides/rel_notes/release_20_11.rst
@@ -68,6 +68,15 @@ New Features
   which allow the programmer to prefetch a cache line and also indicate
   the intention to write.
 
+* **Added the rte_cldemote API.**
+
+  Added a hardware hint CLDEMOTE, which is similar to prefetch in reverse.
+  CLDEMOTE moves the cache line to the more remote cache, where it expects
+  sharing to be efficient. Moving the cache line to a level more distant from
+  the processor helps to accelerate core-to-core communication.
+  This API is specific to x86 and implemented as a stub for other
+  architectures.
+
 * **Updated CRC modules of the net library.**
 
   * Added runtime selection of the optimal architecture-specific CRC path.

diff --git a/lib/librte_eal/arm/include/rte_prefetch_32.h b/lib/librte_eal/arm/include/rte_prefetch_32.h
index e53420a0ba870c35614ab6fa5cfb23753ba995e7..303caaa78026178197fc5c1dcf2c91bdc0ba9a51 100644 (file)
--- a/lib/librte_eal/arm/include/rte_prefetch_32.h
+++ b/lib/librte_eal/arm/include/rte_prefetch_32.h
@@ -33,6 +33,13 @@ static inline void rte_prefetch_non_temporal(const volatile void *p)
        rte_prefetch0(p);
 }
 
+__rte_experimental
+static inline void
+rte_cldemote(const volatile void *p)
+{
+       RTE_SET_USED(p);
+}
+
 #ifdef __cplusplus
 }
 #endif

diff --git a/lib/librte_eal/arm/include/rte_prefetch_64.h b/lib/librte_eal/arm/include/rte_prefetch_64.h
index fc2b391aa88f17757e2b8833c12fcd402dec2255..e28b66fee0bc1b902e9fb74581004a0e360ba94f 100644 (file)
--- a/lib/librte_eal/arm/include/rte_prefetch_64.h
+++ b/lib/librte_eal/arm/include/rte_prefetch_64.h
@@ -32,6 +32,13 @@ static inline void rte_prefetch_non_temporal(const volatile void *p)
        asm volatile ("PRFM PLDL1STRM, [%0]" : : "r" (p));
 }
 
+__rte_experimental
+static inline void
+rte_cldemote(const volatile void *p)
+{
+       RTE_SET_USED(p);
+}
+
 #ifdef __cplusplus
 }
 #endif

diff --git a/lib/librte_eal/include/generic/rte_prefetch.h b/lib/librte_eal/include/generic/rte_prefetch.h
index df9764e0bc6e4329210ea3eff97da6031bfab6ff..f9fab5e359297dea174e2f64fced5a43c05db330 100644 (file)
--- a/lib/librte_eal/include/generic/rte_prefetch.h
+++ b/lib/librte_eal/include/generic/rte_prefetch.h
@@ -116,4 +116,22 @@ rte_prefetch2_write(const void *p)
        __builtin_prefetch(p, 1, 1);
 }
 
+/**
+ * @warning
+ * @b EXPERIMENTAL: this API may change, or be removed, without prior notice
+ *
+ * Demote a cache line to a more distant level of cache from the processor.
+ * CLDEMOTE hints to hardware to move (demote) a cache line from the closest to
+ * the processor to a level more distant from the processor. It is a hint and
+ * not guaranteed. rte_cldemote is intended to move the cache line to the more
+ * remote cache, where it expects sharing to be efficient and to indicate that
+ * a line may be accessed by a different core in the future.
+ *
+ * @param p
+ *   Address to demote
+ */
+__rte_experimental
+static inline void
+rte_cldemote(const volatile void *p);
+
 #endif /* _RTE_PREFETCH_H_ */

diff --git a/lib/librte_eal/ppc/include/rte_prefetch.h b/lib/librte_eal/ppc/include/rte_prefetch.h
index 9ba07c815d6d1e643e51436d8e3535c5781296ac..6df8087e41ac36cb9eea0545fd6d5a15a2612906 100644 (file)
--- a/lib/librte_eal/ppc/include/rte_prefetch.h
+++ b/lib/librte_eal/ppc/include/rte_prefetch.h
@@ -34,6 +34,13 @@ static inline void rte_prefetch_non_temporal(const volatile void *p)
        rte_prefetch0(p);
 }
 
+__rte_experimental
+static inline void
+rte_cldemote(const volatile void *p)
+{
+       RTE_SET_USED(p);
+}
+
 #ifdef __cplusplus
 }
 #endif

diff --git a/lib/librte_eal/x86/include/rte_prefetch.h b/lib/librte_eal/x86/include/rte_prefetch.h
index 384c6b3ef2d3fdbe829f415af0dc516de52c4a9b..53404989dd905cd396d3a3dc4cf9397f13233bdc 100644 (file)
--- a/lib/librte_eal/x86/include/rte_prefetch.h
+++ b/lib/librte_eal/x86/include/rte_prefetch.h
@@ -32,6 +32,17 @@ static inline void rte_prefetch_non_temporal(const volatile void *p)
        asm volatile ("prefetchnta %[p]" : : [p] "m" (*(const volatile char *)p));
 }
 
+/*
+ * We use raw byte codes for now as only the newest compiler
+ * versions support this instruction natively.
+ */
+__rte_experimental
+static inline void
+rte_cldemote(const volatile void *p)
+{
+       asm volatile(".byte 0x0f, 0x1c, 0x06" :: "S" (p));
+}
+
 #ifdef __cplusplus
 }
 #endif