uint8_t *val = NULL;
uint64_t regval;
uint32_t val_size = 0, field_size = 0;
+ uint64_t act_bit;
+ uint8_t act_val;
switch (fld->result_opcode) {
case BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT:
return -EINVAL;
}
break;
+ case BNXT_ULP_RESULT_OPC_SET_TO_ACT_BIT:
+ if (!ulp_operand_read(fld->result_operand,
+ (uint8_t *)&act_bit, sizeof(uint64_t))) {
+ BNXT_TF_DBG(ERR, "%s operand read failed\n", name);
+ return -EINVAL;
+ }
+ act_bit = tfp_be_to_cpu_64(act_bit);
+ act_val = ULP_BITMAP_ISSET(parms->act_bitmap->bits, act_bit);
+ if (fld->field_bit_size > ULP_BYTE_2_BITS(sizeof(act_val))) {
+ BNXT_TF_DBG(ERR, "%s field size is incorrect\n", name);
+ return -EINVAL;
+ }
+ if (!ulp_blob_push(blob, &act_val, fld->field_bit_size)) {
+ BNXT_TF_DBG(ERR, "%s push field failed\n", name);
+ return -EINVAL;
+ }
+ val = &act_val;
+ break;
case BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ:
if (!ulp_operand_read(fld->result_operand,
(uint8_t *)&idx, sizeof(uint16_t))) {
const struct rte_flow_action *action_item = actions;
struct bnxt_ulp_rte_act_info *hdr_info;
+ if (params->dir == ULP_DIR_EGRESS)
+ ULP_BITMAP_SET(params->act_bitmap.bits,
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR);
+
/* Parse all the items in the pattern */
while (action_item && action_item->type != RTE_FLOW_ACTION_TYPE_END) {
/* get the header information from the flow_hdr_info table */
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_BIT,
+ .result_operand = {
+ ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 2,
BNXT_ULP_ACTION_BIT_VPORT = 0x0000000000000040,
BNXT_ULP_ACTION_BIT_VXLAN_DECAP = 0x0000000000000080,
BNXT_ULP_ACTION_BIT_NVGRE_DECAP = 0x0000000000000100,
- BNXT_ULP_ACTION_BIT_OF_POP_MPLS = 0x0000000000000200,
- BNXT_ULP_ACTION_BIT_OF_PUSH_MPLS = 0x0000000000000400,
+ BNXT_ULP_ACTION_BIT_POP_MPLS = 0x0000000000000200,
+ BNXT_ULP_ACTION_BIT_PUSH_MPLS = 0x0000000000000400,
BNXT_ULP_ACTION_BIT_MAC_SWAP = 0x0000000000000800,
BNXT_ULP_ACTION_BIT_SET_MAC_SRC = 0x0000000000001000,
BNXT_ULP_ACTION_BIT_SET_MAC_DST = 0x0000000000002000,
- BNXT_ULP_ACTION_BIT_OF_POP_VLAN = 0x0000000000004000,
- BNXT_ULP_ACTION_BIT_OF_PUSH_VLAN = 0x0000000000008000,
- BNXT_ULP_ACTION_BIT_OF_SET_VLAN_PCP = 0x0000000000010000,
- BNXT_ULP_ACTION_BIT_OF_SET_VLAN_VID = 0x0000000000020000,
+ BNXT_ULP_ACTION_BIT_POP_VLAN = 0x0000000000004000,
+ BNXT_ULP_ACTION_BIT_PUSH_VLAN = 0x0000000000008000,
+ BNXT_ULP_ACTION_BIT_SET_VLAN_PCP = 0x0000000000010000,
+ BNXT_ULP_ACTION_BIT_SET_VLAN_VID = 0x0000000000020000,
BNXT_ULP_ACTION_BIT_SET_IPV4_SRC = 0x0000000000040000,
BNXT_ULP_ACTION_BIT_SET_IPV4_DST = 0x0000000000080000,
BNXT_ULP_ACTION_BIT_SET_IPV6_SRC = 0x0000000000100000,
enum bnxt_ulp_result_opc {
BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT = 0,
BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP = 1,
- BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ = 2,
- BNXT_ULP_RESULT_OPC_SET_TO_REGFILE = 3,
- BNXT_ULP_RESULT_OPC_SET_TO_GLB_REGFILE = 4,
- BNXT_ULP_RESULT_OPC_SET_TO_COMP_FIELD = 5,
- BNXT_ULP_RESULT_OPC_LAST = 6
+ BNXT_ULP_RESULT_OPC_SET_TO_ACT_BIT = 2,
+ BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ = 3,
+ BNXT_ULP_RESULT_OPC_SET_TO_REGFILE = 4,
+ BNXT_ULP_RESULT_OPC_SET_TO_GLB_REGFILE = 5,
+ BNXT_ULP_RESULT_OPC_SET_TO_COMP_FIELD = 6,
+ BNXT_ULP_RESULT_OPC_LAST = 7
};
enum bnxt_ulp_search_before_alloc {