+++ /dev/null
-/*\r
- LUFA Library\r
- Copyright (C) Dean Camera, 2011.\r
-\r
- dean [at] fourwalledcubicle [dot] com\r
- www.lufa-lib.org\r
-*/\r
-\r
-/*\r
- Copyright 2011 Dean Camera (dean [at] fourwalledcubicle [dot] com)\r
-\r
- Permission to use, copy, modify, distribute, and sell this\r
- software and its documentation for any purpose is hereby granted\r
- without fee, provided that the above copyright notice appear in\r
- all copies and that both that the copyright notice and this\r
- permission notice and warranty disclaimer appear in supporting\r
- documentation, and that the name of the author not be used in\r
- advertising or publicity pertaining to distribution of the\r
- software without specific, written prior permission.\r
-\r
- The author disclaim all warranties with regard to this\r
- software, including all implied warranties of merchantability\r
- and fitness. In no event shall the author be liable for any\r
- special, indirect or consequential damages or any damages\r
- whatsoever resulting from loss of use, data or profits, whether\r
- in an action of contract, negligence or other tortious action,\r
- arising out of or in connection with the use or performance of\r
- this software.\r
-*/\r
-\r
-/** \file\r
- *\r
- * USB Device Descriptors, for library use when in USB device mode. Descriptors are special\r
- * computer-readable structures which the host requests upon device enumeration, to determine\r
- * the device's capabilities and functions.\r
- */\r
-\r
-#include "Descriptors.h"\r
-\r
-/* On some devices, there is a factory set internal serial number which can be automatically sent to the host as\r
- * the device's serial number when the Device Descriptor's .SerialNumStrIndex entry is set to USE_INTERNAL_SERIAL.\r
- * This allows the host to track a device across insertions on different ports, allowing them to retain allocated\r
- * resources like COM port numbers and drivers. On demos using this feature, give a warning on unsupported devices\r
- * so that the user can supply their own serial number descriptor instead or remove the USE_INTERNAL_SERIAL value\r
- * from the Device Descriptor (forcing the host to generate a serial number for each device from the VID, PID and\r
- * port location).\r
- */\r
-#if (USE_INTERNAL_SERIAL == NO_DESCRIPTOR)\r
- #warning USE_INTERNAL_SERIAL is not available on this AVR - please manually construct a device serial descriptor.\r
-#endif\r
-\r
-/** Device descriptor structure. This descriptor, located in FLASH memory, describes the overall\r
- * device characteristics, including the supported USB version, control endpoint size and the\r
- * number of device configurations. The descriptor is read out by the USB host when the enumeration\r
- * process begins.\r
- */\r
-const USB_Descriptor_Device_t PROGMEM DeviceDescriptor =\r
-{\r
- .Header = {.Size = sizeof(USB_Descriptor_Device_t), .Type = DTYPE_Device},\r
-\r
- .USBSpecification = VERSION_BCD(01.10),\r
- .Class = USB_CSCP_IADDeviceClass,\r
- .SubClass = USB_CSCP_IADDeviceSubclass,\r
- .Protocol = USB_CSCP_IADDeviceProtocol,\r
-\r
- .Endpoint0Size = FIXED_CONTROL_ENDPOINT_SIZE,\r
-\r
- .VendorID = 0x03EB,\r
- .ProductID = 0x204E,\r
- .ReleaseNumber = VERSION_BCD(00.01),\r
-\r
- .ManufacturerStrIndex = 0x01,\r
- .ProductStrIndex = 0x02,\r
- .SerialNumStrIndex = USE_INTERNAL_SERIAL,\r
-\r
- .NumberOfConfigurations = FIXED_NUM_CONFIGURATIONS\r
-};\r
-\r
-/** Configuration descriptor structure. This descriptor, located in FLASH memory, describes the usage\r
- * of the device in one of its supported configurations, including information about any device interfaces\r
- * and endpoints. The descriptor is read out by the USB host during the enumeration process when selecting\r
- * a configuration so that the host may correctly communicate with the USB device.\r
- */\r
-const USB_Descriptor_Configuration_t PROGMEM ConfigurationDescriptor =\r
-{\r
- .Config =\r
- {\r
- .Header = {.Size = sizeof(USB_Descriptor_Configuration_Header_t), .Type = DTYPE_Configuration},\r
-\r
- .TotalConfigurationSize = sizeof(USB_Descriptor_Configuration_t),\r
- .TotalInterfaces = 4,\r
-\r
- .ConfigurationNumber = 1,\r
- .ConfigurationStrIndex = NO_DESCRIPTOR,\r
-\r
- .ConfigAttributes = (USB_CONFIG_ATTR_BUSPOWERED | USB_CONFIG_ATTR_SELFPOWERED),\r
-\r
- .MaxPowerConsumption = USB_CONFIG_POWER_MA(100)\r
- },\r
-\r
- .CDC1_IAD =\r
- {\r
- .Header = {.Size = sizeof(USB_Descriptor_Interface_Association_t), .Type = DTYPE_InterfaceAssociation},\r
-\r
- .FirstInterfaceIndex = 0,\r
- .TotalInterfaces = 2,\r
-\r
- .Class = CDC_CSCP_CDCClass,\r
- .SubClass = CDC_CSCP_ACMSubclass,\r
- .Protocol = CDC_CSCP_ATCommandProtocol,\r
-\r
- .IADStrIndex = NO_DESCRIPTOR\r
- },\r
-\r
- .CDC1_CCI_Interface =\r
- {\r
- .Header = {.Size = sizeof(USB_Descriptor_Interface_t), .Type = DTYPE_Interface},\r
-\r
- .InterfaceNumber = 0,\r
- .AlternateSetting = 0,\r
-\r
- .TotalEndpoints = 1,\r
-\r
- .Class = CDC_CSCP_CDCClass,\r
- .SubClass = CDC_CSCP_ACMSubclass,\r
- .Protocol = CDC_CSCP_ATCommandProtocol,\r
-\r
- .InterfaceStrIndex = NO_DESCRIPTOR\r
- },\r
-\r
- .CDC1_Functional_Header =\r
- {\r
- .Header = {.Size = sizeof(USB_CDC_Descriptor_FunctionalHeader_t), .Type = DTYPE_CSInterface},\r
- .Subtype = CDC_DSUBTYPE_CSInterface_Header,\r
-\r
- .CDCSpecification = VERSION_BCD(01.10),\r
- },\r
-\r
- .CDC1_Functional_ACM =\r
- {\r
- .Header = {.Size = sizeof(USB_CDC_Descriptor_FunctionalACM_t), .Type = DTYPE_CSInterface},\r
- .Subtype = CDC_DSUBTYPE_CSInterface_ACM,\r
-\r
- .Capabilities = 0x06,\r
- },\r
-\r
- .CDC1_Functional_Union =\r
- {\r
- .Header = {.Size = sizeof(USB_CDC_Descriptor_FunctionalUnion_t), .Type = DTYPE_CSInterface},\r
- .Subtype = CDC_DSUBTYPE_CSInterface_Union,\r
-\r
- .MasterInterfaceNumber = 0,\r
- .SlaveInterfaceNumber = 1,\r
- },\r
-\r
- .CDC1_ManagementEndpoint =\r
- {\r
- .Header = {.Size = sizeof(USB_Descriptor_Endpoint_t), .Type = DTYPE_Endpoint},\r
-\r
- .EndpointAddress = (ENDPOINT_DIR_IN | CDC1_NOTIFICATION_EPNUM),\r
- .Attributes = (EP_TYPE_INTERRUPT | ENDPOINT_ATTR_NO_SYNC | ENDPOINT_USAGE_DATA),\r
- .EndpointSize = CDC_NOTIFICATION_EPSIZE,\r
- .PollingIntervalMS = 0xFF\r
- },\r
-\r
- .CDC1_DCI_Interface =\r
- {\r
- .Header = {.Size = sizeof(USB_Descriptor_Interface_t), .Type = DTYPE_Interface},\r
-\r
- .InterfaceNumber = 1,\r
- .AlternateSetting = 0,\r
-\r
- .TotalEndpoints = 2,\r
-\r
- .Class = CDC_CSCP_CDCDataClass,\r
- .SubClass = CDC_CSCP_NoDataSubclass,\r
- .Protocol = CDC_CSCP_NoDataProtocol,\r
-\r
- .InterfaceStrIndex = NO_DESCRIPTOR\r
- },\r
-\r
- .CDC1_DataOutEndpoint =\r
- {\r
- .Header = {.Size = sizeof(USB_Descriptor_Endpoint_t), .Type = DTYPE_Endpoint},\r
-\r
- .EndpointAddress = (ENDPOINT_DIR_OUT | CDC1_RX_EPNUM),\r
- .Attributes = (EP_TYPE_BULK | ENDPOINT_ATTR_NO_SYNC | ENDPOINT_USAGE_DATA),\r
- .EndpointSize = CDC_TXRX_EPSIZE,\r
- .PollingIntervalMS = 0x01\r
- },\r
-\r
- .CDC1_DataInEndpoint =\r
- {\r
- .Header = {.Size = sizeof(USB_Descriptor_Endpoint_t), .Type = DTYPE_Endpoint},\r
-\r
- .EndpointAddress = (ENDPOINT_DIR_IN | CDC1_TX_EPNUM),\r
- .Attributes = (EP_TYPE_BULK | ENDPOINT_ATTR_NO_SYNC | ENDPOINT_USAGE_DATA),\r
- .EndpointSize = CDC_TXRX_EPSIZE,\r
- .PollingIntervalMS = 0x01\r
- },\r
-\r
- .CDC2_IAD =\r
- {\r
- .Header = {.Size = sizeof(USB_Descriptor_Interface_Association_t), .Type = DTYPE_InterfaceAssociation},\r
-\r
- .FirstInterfaceIndex = 2,\r
- .TotalInterfaces = 2,\r
-\r
- .Class = CDC_CSCP_CDCClass,\r
- .SubClass = CDC_CSCP_ACMSubclass,\r
- .Protocol = CDC_CSCP_ATCommandProtocol,\r
-\r
- .IADStrIndex = NO_DESCRIPTOR\r
- },\r
-\r
- .CDC2_CCI_Interface =\r
- {\r
- .Header = {.Size = sizeof(USB_Descriptor_Interface_t), .Type = DTYPE_Interface},\r
-\r
- .InterfaceNumber = 2,\r
- .AlternateSetting = 0,\r
-\r
- .TotalEndpoints = 1,\r
-\r
- .Class = CDC_CSCP_CDCClass,\r
- .SubClass = CDC_CSCP_ACMSubclass,\r
- .Protocol = CDC_CSCP_ATCommandProtocol,\r
-\r
- .InterfaceStrIndex = NO_DESCRIPTOR\r
- },\r
-\r
- .CDC2_Functional_Header =\r
- {\r
- .Header = {.Size = sizeof(USB_CDC_Descriptor_FunctionalHeader_t), .Type = DTYPE_CSInterface},\r
- .Subtype = CDC_DSUBTYPE_CSInterface_Header,\r
-\r
- .CDCSpecification = VERSION_BCD(01.10),\r
- },\r
-\r
- .CDC2_Functional_ACM =\r
- {\r
- .Header = {.Size = sizeof(USB_CDC_Descriptor_FunctionalACM_t), .Type = DTYPE_CSInterface},\r
- .Subtype = CDC_DSUBTYPE_CSInterface_ACM,\r
-\r
- .Capabilities = 0x06,\r
- },\r
-\r
- .CDC2_Functional_Union =\r
- {\r
- .Header = {.Size = sizeof(USB_CDC_Descriptor_FunctionalUnion_t), .Type = DTYPE_CSInterface},\r
- .Subtype = CDC_DSUBTYPE_CSInterface_Union,\r
-\r
- .MasterInterfaceNumber = 2,\r
- .SlaveInterfaceNumber = 3,\r
- },\r
-\r
- .CDC2_ManagementEndpoint =\r
- {\r
- .Header = {.Size = sizeof(USB_Descriptor_Endpoint_t), .Type = DTYPE_Endpoint},\r
-\r
- .EndpointAddress = (ENDPOINT_DIR_IN | CDC2_NOTIFICATION_EPNUM),\r
- .Attributes = (EP_TYPE_INTERRUPT | ENDPOINT_ATTR_NO_SYNC | ENDPOINT_USAGE_DATA),\r
- .EndpointSize = CDC_NOTIFICATION_EPSIZE,\r
- .PollingIntervalMS = 0xFF\r
- },\r
-\r
- .CDC2_DCI_Interface =\r
- {\r
- .Header = {.Size = sizeof(USB_Descriptor_Interface_t), .Type = DTYPE_Interface},\r
-\r
- .InterfaceNumber = 3,\r
- .AlternateSetting = 0,\r
-\r
- .TotalEndpoints = 2,\r
-\r
- .Class = CDC_CSCP_CDCDataClass,\r
- .SubClass = CDC_CSCP_NoDataSubclass,\r
- .Protocol = CDC_CSCP_NoDataProtocol,\r
-\r
- .InterfaceStrIndex = NO_DESCRIPTOR\r
- },\r
-\r
- .CDC2_DataOutEndpoint =\r
- {\r
- .Header = {.Size = sizeof(USB_Descriptor_Endpoint_t), .Type = DTYPE_Endpoint},\r
-\r
- .EndpointAddress = (ENDPOINT_DIR_OUT | CDC2_RX_EPNUM),\r
- .Attributes = (EP_TYPE_BULK | ENDPOINT_ATTR_NO_SYNC | ENDPOINT_USAGE_DATA),\r
- .EndpointSize = CDC_TXRX_EPSIZE,\r
- .PollingIntervalMS = 0x01\r
- },\r
-\r
- .CDC2_DataInEndpoint =\r
- {\r
- .Header = {.Size = sizeof(USB_Descriptor_Endpoint_t), .Type = DTYPE_Endpoint},\r
-\r
- .EndpointAddress = (ENDPOINT_DIR_IN | CDC2_TX_EPNUM),\r
- .Attributes = (EP_TYPE_BULK | ENDPOINT_ATTR_NO_SYNC | ENDPOINT_USAGE_DATA),\r
- .EndpointSize = CDC_TXRX_EPSIZE,\r
- .PollingIntervalMS = 0x01\r
- }\r
-};\r
-\r
-/** Language descriptor structure. This descriptor, located in FLASH memory, is returned when the host requests\r
- * the string descriptor with index 0 (the first index). It is actually an array of 16-bit integers, which indicate\r
- * via the language ID table available at USB.org what languages the device supports for its string descriptors.\r
- */\r
-const USB_Descriptor_String_t PROGMEM LanguageString =\r
-{\r
- .Header = {.Size = USB_STRING_LEN(1), .Type = DTYPE_String},\r
-\r
- .UnicodeString = {LANGUAGE_ID_ENG}\r
-};\r
-\r
-/** Manufacturer descriptor string. This is a Unicode string containing the manufacturer's details in human readable\r
- * form, and is read out upon request by the host when the appropriate string ID is requested, listed in the Device\r
- * Descriptor.\r
- */\r
-const USB_Descriptor_String_t PROGMEM ManufacturerString =\r
-{\r
- .Header = {.Size = USB_STRING_LEN(11), .Type = DTYPE_String},\r
-\r
- .UnicodeString = L"Dean Camera"\r
-};\r
-\r
-/** Product descriptor string. This is a Unicode string containing the product's details in human readable form,\r
- * and is read out upon request by the host when the appropriate string ID is requested, listed in the Device\r
- * Descriptor.\r
- */\r
-const USB_Descriptor_String_t PROGMEM ProductString =\r
-{\r
- .Header = {.Size = USB_STRING_LEN(13), .Type = DTYPE_String},\r
-\r
- .UnicodeString = L"LUFA Dual CDC Demo"\r
-};\r
-\r
-/** This function is called by the library when in device mode, and must be overridden (see library "USB Descriptors"\r
- * documentation) by the application code so that the address and size of a requested descriptor can be given\r
- * to the USB library. When the device receives a Get Descriptor request on the control endpoint, this function\r
- * is called so that the descriptor details can be passed back and the appropriate descriptor sent back to the\r
- * USB host.\r
- */\r
-uint16_t CALLBACK_USB_GetDescriptor(const uint16_t wValue,\r
- const uint8_t wIndex,\r
- const void** const DescriptorAddress)\r
-{\r
- const uint8_t DescriptorType = (wValue >> 8);\r
- const uint8_t DescriptorNumber = (wValue & 0xFF);\r
-\r
- const void* Address = NULL;\r
- uint16_t Size = NO_DESCRIPTOR;\r
-\r
- switch (DescriptorType)\r
- {\r
- case DTYPE_Device:\r
- Address = &DeviceDescriptor;\r
- Size = sizeof(USB_Descriptor_Device_t);\r
- break;\r
- case DTYPE_Configuration:\r
- Address = &ConfigurationDescriptor;\r
- Size = sizeof(USB_Descriptor_Configuration_t);\r
- break;\r
- case DTYPE_String:\r
- switch (DescriptorNumber)\r
- {\r
- case 0x00:\r
- Address = &LanguageString;\r
- Size = pgm_read_byte(&LanguageString.Header.Size);\r
- break;\r
- case 0x01:\r
- Address = &ManufacturerString;\r
- Size = pgm_read_byte(&ManufacturerString.Header.Size);\r
- break;\r
- case 0x02:\r
- Address = &ProductString;\r
- Size = pgm_read_byte(&ProductString.Header.Size);\r
- break;\r
- }\r
-\r
- break;\r
- }\r
-\r
- *DescriptorAddress = Address;\r
- return Size;\r
-}\r
-\r
+++ /dev/null
-/*\r
- LUFA Library\r
- Copyright (C) Dean Camera, 2011.\r
-\r
- dean [at] fourwalledcubicle [dot] com\r
- www.lufa-lib.org\r
-*/\r
-\r
-/*\r
- Copyright 2011 Dean Camera (dean [at] fourwalledcubicle [dot] com)\r
-\r
- Permission to use, copy, modify, distribute, and sell this\r
- software and its documentation for any purpose is hereby granted\r
- without fee, provided that the above copyright notice appear in\r
- all copies and that both that the copyright notice and this\r
- permission notice and warranty disclaimer appear in supporting\r
- documentation, and that the name of the author not be used in\r
- advertising or publicity pertaining to distribution of the\r
- software without specific, written prior permission.\r
-\r
- The author disclaim all warranties with regard to this\r
- software, including all implied warranties of merchantability\r
- and fitness. In no event shall the author be liable for any\r
- special, indirect or consequential damages or any damages\r
- whatsoever resulting from loss of use, data or profits, whether\r
- in an action of contract, negligence or other tortious action,\r
- arising out of or in connection with the use or performance of\r
- this software.\r
-*/\r
-\r
-/** \file\r
- *\r
- * Header file for Descriptors.c.\r
- */\r
-\r
-#ifndef _DESCRIPTORS_H_\r
-#define _DESCRIPTORS_H_\r
-\r
- /* Includes: */\r
- #include <avr/pgmspace.h>\r
-\r
- #include <LUFA/Drivers/USB/USB.h>\r
-\r
- /* Macros: */\r
- /** Endpoint number of the first CDC interface's device-to-host data IN endpoint. */\r
- #define CDC1_TX_EPNUM 1\r
-\r
- /** Endpoint number of the first CDC interface's host-to-device data OUT endpoint. */\r
- #define CDC1_RX_EPNUM 2\r
-\r
- /** Endpoint number of the first CDC interface's device-to-host notification IN endpoint. */\r
- #define CDC1_NOTIFICATION_EPNUM 3\r
-\r
- /** Endpoint number of the second CDC interface's device-to-host data IN endpoint. */\r
- #define CDC2_TX_EPNUM 4\r
-\r
- /** Endpoint number of the second CDC interface's host-to-device data OUT endpoint. */\r
- #define CDC2_RX_EPNUM 5\r
-\r
- /** Endpoint number of the second CDC interface's device-to-host notification IN endpoint. */\r
- #define CDC2_NOTIFICATION_EPNUM 6\r
-\r
- /** Size in bytes of the CDC device-to-host notification IN endpoints. */\r
- #define CDC_NOTIFICATION_EPSIZE 8\r
-\r
- /** Size in bytes of the CDC data IN and OUT endpoints. */\r
- #define CDC_TXRX_EPSIZE 16\r
-\r
- /* Type Defines: */\r
- /** Type define for the device configuration descriptor structure. This must be defined in the\r
- * application code, as the configuration descriptor contains several sub-descriptors which\r
- * vary between devices, and which describe the device's usage to the host.\r
- */\r
- typedef struct\r
- {\r
- USB_Descriptor_Configuration_Header_t Config;\r
-\r
- // First CDC Control Interface\r
- USB_Descriptor_Interface_Association_t CDC1_IAD;\r
- USB_Descriptor_Interface_t CDC1_CCI_Interface;\r
- USB_CDC_Descriptor_FunctionalHeader_t CDC1_Functional_Header;\r
- USB_CDC_Descriptor_FunctionalACM_t CDC1_Functional_ACM;\r
- USB_CDC_Descriptor_FunctionalUnion_t CDC1_Functional_Union;\r
- USB_Descriptor_Endpoint_t CDC1_ManagementEndpoint;\r
-\r
- // First CDC Data Interface\r
- USB_Descriptor_Interface_t CDC1_DCI_Interface;\r
- USB_Descriptor_Endpoint_t CDC1_DataOutEndpoint;\r
- USB_Descriptor_Endpoint_t CDC1_DataInEndpoint;\r
-\r
- // Second CDC Control Interface\r
- USB_Descriptor_Interface_Association_t CDC2_IAD;\r
- USB_Descriptor_Interface_t CDC2_CCI_Interface;\r
- USB_CDC_Descriptor_FunctionalHeader_t CDC2_Functional_Header;\r
- USB_CDC_Descriptor_FunctionalACM_t CDC2_Functional_ACM;\r
- USB_CDC_Descriptor_FunctionalUnion_t CDC2_Functional_Union;\r
- USB_Descriptor_Endpoint_t CDC2_ManagementEndpoint;\r
-\r
- // Second CDC Data Interface\r
- USB_Descriptor_Interface_t CDC2_DCI_Interface;\r
- USB_Descriptor_Endpoint_t CDC2_DataOutEndpoint;\r
- USB_Descriptor_Endpoint_t CDC2_DataInEndpoint;\r
- } USB_Descriptor_Configuration_t;\r
-\r
- /* Function Prototypes: */\r
- uint16_t CALLBACK_USB_GetDescriptor(const uint16_t wValue,\r
- const uint8_t wIndex,\r
- const void** const DescriptorAddress)\r
- ATTR_WARN_UNUSED_RESULT ATTR_NON_NULL_PTR_ARG(3);\r
-\r
-#endif\r
+++ /dev/null
-# Doxyfile 1.6.2\r
-\r
-# This file describes the settings to be used by the documentation system\r
-# doxygen (www.doxygen.org) for a project\r
-#\r
-# All text after a hash (#) is considered a comment and will be ignored\r
-# The format is:\r
-# TAG = value [value, ...]\r
-# For lists items can also be appended using:\r
-# TAG += value [value, ...]\r
-# Values that contain spaces should be placed between quotes (" ")\r
-\r
-#---------------------------------------------------------------------------\r
-# Project related configuration options\r
-#---------------------------------------------------------------------------\r
-\r
-# This tag specifies the encoding used for all characters in the config file\r
-# that follow. The default is UTF-8 which is also the encoding used for all\r
-# text before the first occurrence of this tag. Doxygen uses libiconv (or the\r
-# iconv built into libc) for the transcoding. See\r
-# http://www.gnu.org/software/libiconv for the list of possible encodings.\r
-\r
-DOXYFILE_ENCODING = UTF-8\r
-\r
-# The PROJECT_NAME tag is a single word (or a sequence of words surrounded\r
-# by quotes) that should identify the project.\r
-\r
-PROJECT_NAME = "LUFA Library - Dual Virtual Serial Device Demo"\r
-\r
-# The PROJECT_NUMBER tag can be used to enter a project or revision number.\r
-# This could be handy for archiving the generated documentation or\r
-# if some version control system is used.\r
-\r
-PROJECT_NUMBER = 0.0.0\r
-\r
-# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute)\r
-# base path where the generated documentation will be put.\r
-# If a relative path is entered, it will be relative to the location\r
-# where doxygen was started. If left blank the current directory will be used.\r
-\r
-OUTPUT_DIRECTORY = ./Documentation/\r
-\r
-# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create\r
-# 4096 sub-directories (in 2 levels) under the output directory of each output\r
-# format and will distribute the generated files over these directories.\r
-# Enabling this option can be useful when feeding doxygen a huge amount of\r
-# source files, where putting all generated files in the same directory would\r
-# otherwise cause performance problems for the file system.\r
-\r
-CREATE_SUBDIRS = NO\r
-\r
-# The OUTPUT_LANGUAGE tag is used to specify the language in which all\r
-# documentation generated by doxygen is written. Doxygen will use this\r
-# information to generate all constant output in the proper language.\r
-# The default language is English, other supported languages are:\r
-# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional,\r
-# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German,\r
-# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English\r
-# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian,\r
-# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak,\r
-# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese.\r
-\r
-OUTPUT_LANGUAGE = English\r
-\r
-# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will\r
-# include brief member descriptions after the members that are listed in\r
-# the file and class documentation (similar to JavaDoc).\r
-# Set to NO to disable this.\r
-\r
-BRIEF_MEMBER_DESC = YES\r
-\r
-# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend\r
-# the brief description of a member or function before the detailed description.\r
-# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the\r
-# brief descriptions will be completely suppressed.\r
-\r
-REPEAT_BRIEF = YES\r
-\r
-# This tag implements a quasi-intelligent brief description abbreviator\r
-# that is used to form the text in various listings. Each string\r
-# in this list, if found as the leading text of the brief description, will be\r
-# stripped from the text and the result after processing the whole list, is\r
-# used as the annotated text. Otherwise, the brief description is used as-is.\r
-# If left blank, the following values are used ("$name" is automatically\r
-# replaced with the name of the entity): "The $name class" "The $name widget"\r
-# "The $name file" "is" "provides" "specifies" "contains"\r
-# "represents" "a" "an" "the"\r
-\r
-ABBREVIATE_BRIEF = "The $name class" \\r
- "The $name widget" \\r
- "The $name file" \\r
- is \\r
- provides \\r
- specifies \\r
- contains \\r
- represents \\r
- a \\r
- an \\r
- the\r
-\r
-# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then\r
-# Doxygen will generate a detailed section even if there is only a brief\r
-# description.\r
-\r
-ALWAYS_DETAILED_SEC = NO\r
-\r
-# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all\r
-# inherited members of a class in the documentation of that class as if those\r
-# members were ordinary class members. Constructors, destructors and assignment\r
-# operators of the base classes will not be shown.\r
-\r
-INLINE_INHERITED_MEMB = NO\r
-\r
-# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full\r
-# path before files name in the file list and in the header files. If set\r
-# to NO the shortest path that makes the file name unique will be used.\r
-\r
-FULL_PATH_NAMES = YES\r
-\r
-# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag\r
-# can be used to strip a user-defined part of the path. Stripping is\r
-# only done if one of the specified strings matches the left-hand part of\r
-# the path. The tag can be used to show relative paths in the file list.\r
-# If left blank the directory from which doxygen is run is used as the\r
-# path to strip.\r
-\r
-STRIP_FROM_PATH =\r
-\r
-# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of\r
-# the path mentioned in the documentation of a class, which tells\r
-# the reader which header file to include in order to use a class.\r
-# If left blank only the name of the header file containing the class\r
-# definition is used. Otherwise one should specify the include paths that\r
-# are normally passed to the compiler using the -I flag.\r
-\r
-STRIP_FROM_INC_PATH =\r
-\r
-# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter\r
-# (but less readable) file names. This can be useful is your file systems\r
-# doesn't support long names like on DOS, Mac, or CD-ROM.\r
-\r
-SHORT_NAMES = YES\r
-\r
-# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen\r
-# will interpret the first line (until the first dot) of a JavaDoc-style\r
-# comment as the brief description. If set to NO, the JavaDoc\r
-# comments will behave just like regular Qt-style comments\r
-# (thus requiring an explicit @brief command for a brief description.)\r
-\r
-JAVADOC_AUTOBRIEF = NO\r
-\r
-# If the QT_AUTOBRIEF tag is set to YES then Doxygen will\r
-# interpret the first line (until the first dot) of a Qt-style\r
-# comment as the brief description. If set to NO, the comments\r
-# will behave just like regular Qt-style comments (thus requiring\r
-# an explicit \brief command for a brief description.)\r
-\r
-QT_AUTOBRIEF = NO\r
-\r
-# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen\r
-# treat a multi-line C++ special comment block (i.e. a block of //! or ///\r
-# comments) as a brief description. This used to be the default behaviour.\r
-# The new default is to treat a multi-line C++ comment block as a detailed\r
-# description. Set this tag to YES if you prefer the old behaviour instead.\r
-\r
-MULTILINE_CPP_IS_BRIEF = NO\r
-\r
-# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented\r
-# member inherits the documentation from any documented member that it\r
-# re-implements.\r
-\r
-INHERIT_DOCS = YES\r
-\r
-# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce\r
-# a new page for each member. If set to NO, the documentation of a member will\r
-# be part of the file/class/namespace that contains it.\r
-\r
-SEPARATE_MEMBER_PAGES = NO\r
-\r
-# The TAB_SIZE tag can be used to set the number of spaces in a tab.\r
-# Doxygen uses this value to replace tabs by spaces in code fragments.\r
-\r
-TAB_SIZE = 4\r
-\r
-# This tag can be used to specify a number of aliases that acts\r
-# as commands in the documentation. An alias has the form "name=value".\r
-# For example adding "sideeffect=\par Side Effects:\n" will allow you to\r
-# put the command \sideeffect (or @sideeffect) in the documentation, which\r
-# will result in a user-defined paragraph with heading "Side Effects:".\r
-# You can put \n's in the value part of an alias to insert newlines.\r
-\r
-ALIASES =\r
-\r
-# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C\r
-# sources only. Doxygen will then generate output that is more tailored for C.\r
-# For instance, some of the names that are used will be different. The list\r
-# of all members will be omitted, etc.\r
-\r
-OPTIMIZE_OUTPUT_FOR_C = YES\r
-\r
-# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java\r
-# sources only. Doxygen will then generate output that is more tailored for\r
-# Java. For instance, namespaces will be presented as packages, qualified\r
-# scopes will look different, etc.\r
-\r
-OPTIMIZE_OUTPUT_JAVA = NO\r
-\r
-# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran\r
-# sources only. Doxygen will then generate output that is more tailored for\r
-# Fortran.\r
-\r
-OPTIMIZE_FOR_FORTRAN = NO\r
-\r
-# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL\r
-# sources. Doxygen will then generate output that is tailored for\r
-# VHDL.\r
-\r
-OPTIMIZE_OUTPUT_VHDL = NO\r
-\r
-# Doxygen selects the parser to use depending on the extension of the files it parses.\r
-# With this tag you can assign which parser to use for a given extension.\r
-# Doxygen has a built-in mapping, but you can override or extend it using this tag.\r
-# The format is ext=language, where ext is a file extension, and language is one of\r
-# the parsers supported by doxygen: IDL, Java, Javascript, C#, C, C++, D, PHP,\r
-# Objective-C, Python, Fortran, VHDL, C, C++. For instance to make doxygen treat\r
-# .inc files as Fortran files (default is PHP), and .f files as C (default is Fortran),\r
-# use: inc=Fortran f=C. Note that for custom extensions you also need to set FILE_PATTERNS otherwise the files are not read by doxygen.\r
-\r
-EXTENSION_MAPPING =\r
-\r
-# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want\r
-# to include (a tag file for) the STL sources as input, then you should\r
-# set this tag to YES in order to let doxygen match functions declarations and\r
-# definitions whose arguments contain STL classes (e.g. func(std::string); v.s.\r
-# func(std::string) {}). This also make the inheritance and collaboration\r
-# diagrams that involve STL classes more complete and accurate.\r
-\r
-BUILTIN_STL_SUPPORT = NO\r
-\r
-# If you use Microsoft's C++/CLI language, you should set this option to YES to\r
-# enable parsing support.\r
-\r
-CPP_CLI_SUPPORT = NO\r
-\r
-# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only.\r
-# Doxygen will parse them like normal C++ but will assume all classes use public\r
-# instead of private inheritance when no explicit protection keyword is present.\r
-\r
-SIP_SUPPORT = NO\r
-\r
-# For Microsoft's IDL there are propget and propput attributes to indicate getter\r
-# and setter methods for a property. Setting this option to YES (the default)\r
-# will make doxygen to replace the get and set methods by a property in the\r
-# documentation. This will only work if the methods are indeed getting or\r
-# setting a simple type. If this is not the case, or you want to show the\r
-# methods anyway, you should set this option to NO.\r
-\r
-IDL_PROPERTY_SUPPORT = YES\r
-\r
-# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC\r
-# tag is set to YES, then doxygen will reuse the documentation of the first\r
-# member in the group (if any) for the other members of the group. By default\r
-# all members of a group must be documented explicitly.\r
-\r
-DISTRIBUTE_GROUP_DOC = NO\r
-\r
-# Set the SUBGROUPING tag to YES (the default) to allow class member groups of\r
-# the same type (for instance a group of public functions) to be put as a\r
-# subgroup of that type (e.g. under the Public Functions section). Set it to\r
-# NO to prevent subgrouping. Alternatively, this can be done per class using\r
-# the \nosubgrouping command.\r
-\r
-SUBGROUPING = YES\r
-\r
-# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum\r
-# is documented as struct, union, or enum with the name of the typedef. So\r
-# typedef struct TypeS {} TypeT, will appear in the documentation as a struct\r
-# with name TypeT. When disabled the typedef will appear as a member of a file,\r
-# namespace, or class. And the struct will be named TypeS. This can typically\r
-# be useful for C code in case the coding convention dictates that all compound\r
-# types are typedef'ed and only the typedef is referenced, never the tag name.\r
-\r
-TYPEDEF_HIDES_STRUCT = NO\r
-\r
-# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to\r
-# determine which symbols to keep in memory and which to flush to disk.\r
-# When the cache is full, less often used symbols will be written to disk.\r
-# For small to medium size projects (<1000 input files) the default value is\r
-# probably good enough. For larger projects a too small cache size can cause\r
-# doxygen to be busy swapping symbols to and from disk most of the time\r
-# causing a significant performance penality.\r
-# If the system has enough physical memory increasing the cache will improve the\r
-# performance by keeping more symbols in memory. Note that the value works on\r
-# a logarithmic scale so increasing the size by one will rougly double the\r
-# memory usage. The cache size is given by this formula:\r
-# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0,\r
-# corresponding to a cache size of 2^16 = 65536 symbols\r
-\r
-SYMBOL_CACHE_SIZE = 0\r
-\r
-#---------------------------------------------------------------------------\r
-# Build related configuration options\r
-#---------------------------------------------------------------------------\r
-\r
-# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in\r
-# documentation are documented, even if no documentation was available.\r
-# Private class members and static file members will be hidden unless\r
-# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES\r
-\r
-EXTRACT_ALL = YES\r
-\r
-# If the EXTRACT_PRIVATE tag is set to YES all private members of a class\r
-# will be included in the documentation.\r
-\r
-EXTRACT_PRIVATE = YES\r
-\r
-# If the EXTRACT_STATIC tag is set to YES all static members of a file\r
-# will be included in the documentation.\r
-\r
-EXTRACT_STATIC = YES\r
-\r
-# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs)\r
-# defined locally in source files will be included in the documentation.\r
-# If set to NO only classes defined in header files are included.\r
-\r
-EXTRACT_LOCAL_CLASSES = YES\r
-\r
-# This flag is only useful for Objective-C code. When set to YES local\r
-# methods, which are defined in the implementation section but not in\r
-# the interface are included in the documentation.\r
-# If set to NO (the default) only methods in the interface are included.\r
-\r
-EXTRACT_LOCAL_METHODS = NO\r
-\r
-# If this flag is set to YES, the members of anonymous namespaces will be\r
-# extracted and appear in the documentation as a namespace called\r
-# 'anonymous_namespace{file}', where file will be replaced with the base\r
-# name of the file that contains the anonymous namespace. By default\r
-# anonymous namespace are hidden.\r
-\r
-EXTRACT_ANON_NSPACES = NO\r
-\r
-# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all\r
-# undocumented members of documented classes, files or namespaces.\r
-# If set to NO (the default) these members will be included in the\r
-# various overviews, but no documentation section is generated.\r
-# This option has no effect if EXTRACT_ALL is enabled.\r
-\r
-HIDE_UNDOC_MEMBERS = NO\r
-\r
-# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all\r
-# undocumented classes that are normally visible in the class hierarchy.\r
-# If set to NO (the default) these classes will be included in the various\r
-# overviews. This option has no effect if EXTRACT_ALL is enabled.\r
-\r
-HIDE_UNDOC_CLASSES = NO\r
-\r
-# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all\r
-# friend (class|struct|union) declarations.\r
-# If set to NO (the default) these declarations will be included in the\r
-# documentation.\r
-\r
-HIDE_FRIEND_COMPOUNDS = NO\r
-\r
-# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any\r
-# documentation blocks found inside the body of a function.\r
-# If set to NO (the default) these blocks will be appended to the\r
-# function's detailed documentation block.\r
-\r
-HIDE_IN_BODY_DOCS = NO\r
-\r
-# The INTERNAL_DOCS tag determines if documentation\r
-# that is typed after a \internal command is included. If the tag is set\r
-# to NO (the default) then the documentation will be excluded.\r
-# Set it to YES to include the internal documentation.\r
-\r
-INTERNAL_DOCS = NO\r
-\r
-# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate\r
-# file names in lower-case letters. If set to YES upper-case letters are also\r
-# allowed. This is useful if you have classes or files whose names only differ\r
-# in case and if your file system supports case sensitive file names. Windows\r
-# and Mac users are advised to set this option to NO.\r
-\r
-CASE_SENSE_NAMES = NO\r
-\r
-# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen\r
-# will show members with their full class and namespace scopes in the\r
-# documentation. If set to YES the scope will be hidden.\r
-\r
-HIDE_SCOPE_NAMES = NO\r
-\r
-# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen\r
-# will put a list of the files that are included by a file in the documentation\r
-# of that file.\r
-\r
-SHOW_INCLUDE_FILES = YES\r
-\r
-# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen\r
-# will list include files with double quotes in the documentation\r
-# rather than with sharp brackets.\r
-\r
-FORCE_LOCAL_INCLUDES = NO\r
-\r
-# If the INLINE_INFO tag is set to YES (the default) then a tag [inline]\r
-# is inserted in the documentation for inline members.\r
-\r
-INLINE_INFO = YES\r
-\r
-# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen\r
-# will sort the (detailed) documentation of file and class members\r
-# alphabetically by member name. If set to NO the members will appear in\r
-# declaration order.\r
-\r
-SORT_MEMBER_DOCS = YES\r
-\r
-# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the\r
-# brief documentation of file, namespace and class members alphabetically\r
-# by member name. If set to NO (the default) the members will appear in\r
-# declaration order.\r
-\r
-SORT_BRIEF_DOCS = NO\r
-\r
-# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen will sort the (brief and detailed) documentation of class members so that constructors and destructors are listed first. If set to NO (the default) the constructors will appear in the respective orders defined by SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO.\r
-\r
-SORT_MEMBERS_CTORS_1ST = NO\r
-\r
-# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the\r
-# hierarchy of group names into alphabetical order. If set to NO (the default)\r
-# the group names will appear in their defined order.\r
-\r
-SORT_GROUP_NAMES = NO\r
-\r
-# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be\r
-# sorted by fully-qualified names, including namespaces. If set to\r
-# NO (the default), the class list will be sorted only by class name,\r
-# not including the namespace part.\r
-# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES.\r
-# Note: This option applies only to the class list, not to the\r
-# alphabetical list.\r
-\r
-SORT_BY_SCOPE_NAME = NO\r
-\r
-# The GENERATE_TODOLIST tag can be used to enable (YES) or\r
-# disable (NO) the todo list. This list is created by putting \todo\r
-# commands in the documentation.\r
-\r
-GENERATE_TODOLIST = NO\r
-\r
-# The GENERATE_TESTLIST tag can be used to enable (YES) or\r
-# disable (NO) the test list. This list is created by putting \test\r
-# commands in the documentation.\r
-\r
-GENERATE_TESTLIST = NO\r
-\r
-# The GENERATE_BUGLIST tag can be used to enable (YES) or\r
-# disable (NO) the bug list. This list is created by putting \bug\r
-# commands in the documentation.\r
-\r
-GENERATE_BUGLIST = NO\r
-\r
-# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or\r
-# disable (NO) the deprecated list. This list is created by putting\r
-# \deprecated commands in the documentation.\r
-\r
-GENERATE_DEPRECATEDLIST= YES\r
-\r
-# The ENABLED_SECTIONS tag can be used to enable conditional\r
-# documentation sections, marked by \if sectionname ... \endif.\r
-\r
-ENABLED_SECTIONS =\r
-\r
-# The MAX_INITIALIZER_LINES tag determines the maximum number of lines\r
-# the initial value of a variable or define consists of for it to appear in\r
-# the documentation. If the initializer consists of more lines than specified\r
-# here it will be hidden. Use a value of 0 to hide initializers completely.\r
-# The appearance of the initializer of individual variables and defines in the\r
-# documentation can be controlled using \showinitializer or \hideinitializer\r
-# command in the documentation regardless of this setting.\r
-\r
-MAX_INITIALIZER_LINES = 30\r
-\r
-# Set the SHOW_USED_FILES tag to NO to disable the list of files generated\r
-# at the bottom of the documentation of classes and structs. If set to YES the\r
-# list will mention the files that were used to generate the documentation.\r
-\r
-SHOW_USED_FILES = YES\r
-\r
-# If the sources in your project are distributed over multiple directories\r
-# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy\r
-# in the documentation. The default is NO.\r
-\r
-SHOW_DIRECTORIES = YES\r
-\r
-# Set the SHOW_FILES tag to NO to disable the generation of the Files page.\r
-# This will remove the Files entry from the Quick Index and from the\r
-# Folder Tree View (if specified). The default is YES.\r
-\r
-SHOW_FILES = YES\r
-\r
-# Set the SHOW_NAMESPACES tag to NO to disable the generation of the\r
-# Namespaces page.\r
-# This will remove the Namespaces entry from the Quick Index\r
-# and from the Folder Tree View (if specified). The default is YES.\r
-\r
-SHOW_NAMESPACES = YES\r
-\r
-# The FILE_VERSION_FILTER tag can be used to specify a program or script that\r
-# doxygen should invoke to get the current version for each file (typically from\r
-# the version control system). Doxygen will invoke the program by executing (via\r
-# popen()) the command <command> <input-file>, where <command> is the value of\r
-# the FILE_VERSION_FILTER tag, and <input-file> is the name of an input file\r
-# provided by doxygen. Whatever the program writes to standard output\r
-# is used as the file version. See the manual for examples.\r
-\r
-FILE_VERSION_FILTER =\r
-\r
-# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed by\r
-# doxygen. The layout file controls the global structure of the generated output files\r
-# in an output format independent way. The create the layout file that represents\r
-# doxygen's defaults, run doxygen with the -l option. You can optionally specify a\r
-# file name after the option, if omitted DoxygenLayout.xml will be used as the name\r
-# of the layout file.\r
-\r
-LAYOUT_FILE =\r
-\r
-#---------------------------------------------------------------------------\r
-# configuration options related to warning and progress messages\r
-#---------------------------------------------------------------------------\r
-\r
-# The QUIET tag can be used to turn on/off the messages that are generated\r
-# by doxygen. Possible values are YES and NO. If left blank NO is used.\r
-\r
-QUIET = YES\r
-\r
-# The WARNINGS tag can be used to turn on/off the warning messages that are\r
-# generated by doxygen. Possible values are YES and NO. If left blank\r
-# NO is used.\r
-\r
-WARNINGS = YES\r
-\r
-# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings\r
-# for undocumented members. If EXTRACT_ALL is set to YES then this flag will\r
-# automatically be disabled.\r
-\r
-WARN_IF_UNDOCUMENTED = YES\r
-\r
-# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for\r
-# potential errors in the documentation, such as not documenting some\r
-# parameters in a documented function, or documenting parameters that\r
-# don't exist or using markup commands wrongly.\r
-\r
-WARN_IF_DOC_ERROR = YES\r
-\r
-# This WARN_NO_PARAMDOC option can be abled to get warnings for\r
-# functions that are documented, but have no documentation for their parameters\r
-# or return value. If set to NO (the default) doxygen will only warn about\r
-# wrong or incomplete parameter documentation, but not about the absence of\r
-# documentation.\r
-\r
-WARN_NO_PARAMDOC = YES\r
-\r
-# The WARN_FORMAT tag determines the format of the warning messages that\r
-# doxygen can produce. The string should contain the $file, $line, and $text\r
-# tags, which will be replaced by the file and line number from which the\r
-# warning originated and the warning text. Optionally the format may contain\r
-# $version, which will be replaced by the version of the file (if it could\r
-# be obtained via FILE_VERSION_FILTER)\r
-\r
-WARN_FORMAT = "$file:$line: $text"\r
-\r
-# The WARN_LOGFILE tag can be used to specify a file to which warning\r
-# and error messages should be written. If left blank the output is written\r
-# to stderr.\r
-\r
-WARN_LOGFILE =\r
-\r
-#---------------------------------------------------------------------------\r
-# configuration options related to the input files\r
-#---------------------------------------------------------------------------\r
-\r
-# The INPUT tag can be used to specify the files and/or directories that contain\r
-# documented source files. You may enter file names like "myfile.cpp" or\r
-# directories like "/usr/src/myproject". Separate the files or directories\r
-# with spaces.\r
-\r
-INPUT = ./\r
-\r
-# This tag can be used to specify the character encoding of the source files\r
-# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is\r
-# also the default input encoding. Doxygen uses libiconv (or the iconv built\r
-# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for\r
-# the list of possible encodings.\r
-\r
-INPUT_ENCODING = UTF-8\r
-\r
-# If the value of the INPUT tag contains directories, you can use the\r
-# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp\r
-# and *.h) to filter out the source-files in the directories. If left\r
-# blank the following patterns are tested:\r
-# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx\r
-# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90\r
-\r
-FILE_PATTERNS = *.h \\r
- *.c \\r
- *.txt\r
-\r
-# The RECURSIVE tag can be used to turn specify whether or not subdirectories\r
-# should be searched for input files as well. Possible values are YES and NO.\r
-# If left blank NO is used.\r
-\r
-RECURSIVE = YES\r
-\r
-# The EXCLUDE tag can be used to specify files and/or directories that should\r
-# excluded from the INPUT source files. This way you can easily exclude a\r
-# subdirectory from a directory tree whose root is specified with the INPUT tag.\r
-\r
-EXCLUDE = Documentation/\r
-\r
-# The EXCLUDE_SYMLINKS tag can be used select whether or not files or\r
-# directories that are symbolic links (a Unix filesystem feature) are excluded\r
-# from the input.\r
-\r
-EXCLUDE_SYMLINKS = NO\r
-\r
-# If the value of the INPUT tag contains directories, you can use the\r
-# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude\r
-# certain files from those directories. Note that the wildcards are matched\r
-# against the file with absolute path, so to exclude all test directories\r
-# for example use the pattern */test/*\r
-\r
-EXCLUDE_PATTERNS = \r
-\r
-# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names\r
-# (namespaces, classes, functions, etc.) that should be excluded from the\r
-# output. The symbol name can be a fully qualified name, a word, or if the\r
-# wildcard * is used, a substring. Examples: ANamespace, AClass,\r
-# AClass::ANamespace, ANamespace::*Test\r
-\r
-EXCLUDE_SYMBOLS = __* \\r
- INCLUDE_FROM_*\r
-\r
-# The EXAMPLE_PATH tag can be used to specify one or more files or\r
-# directories that contain example code fragments that are included (see\r
-# the \include command).\r
-\r
-EXAMPLE_PATH =\r
-\r
-# If the value of the EXAMPLE_PATH tag contains directories, you can use the\r
-# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp\r
-# and *.h) to filter out the source-files in the directories. If left\r
-# blank all files are included.\r
-\r
-EXAMPLE_PATTERNS = *\r
-\r
-# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be\r
-# searched for input files to be used with the \include or \dontinclude\r
-# commands irrespective of the value of the RECURSIVE tag.\r
-# Possible values are YES and NO. If left blank NO is used.\r
-\r
-EXAMPLE_RECURSIVE = NO\r
-\r
-# The IMAGE_PATH tag can be used to specify one or more files or\r
-# directories that contain image that are included in the documentation (see\r
-# the \image command).\r
-\r
-IMAGE_PATH =\r
-\r
-# The INPUT_FILTER tag can be used to specify a program that doxygen should\r
-# invoke to filter for each input file. Doxygen will invoke the filter program\r
-# by executing (via popen()) the command <filter> <input-file>, where <filter>\r
-# is the value of the INPUT_FILTER tag, and <input-file> is the name of an\r
-# input file. Doxygen will then use the output that the filter program writes\r
-# to standard output.\r
-# If FILTER_PATTERNS is specified, this tag will be\r
-# ignored.\r
-\r
-INPUT_FILTER =\r
-\r
-# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern\r
-# basis.\r
-# Doxygen will compare the file name with each pattern and apply the\r
-# filter if there is a match.\r
-# The filters are a list of the form:\r
-# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further\r
-# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER\r
-# is applied to all files.\r
-\r
-FILTER_PATTERNS =\r
-\r
-# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using\r
-# INPUT_FILTER) will be used to filter the input files when producing source\r
-# files to browse (i.e. when SOURCE_BROWSER is set to YES).\r
-\r
-FILTER_SOURCE_FILES = NO\r
-\r
-#---------------------------------------------------------------------------\r
-# configuration options related to source browsing\r
-#---------------------------------------------------------------------------\r
-\r
-# If the SOURCE_BROWSER tag is set to YES then a list of source files will\r
-# be generated. Documented entities will be cross-referenced with these sources.\r
-# Note: To get rid of all source code in the generated output, make sure also\r
-# VERBATIM_HEADERS is set to NO.\r
-\r
-SOURCE_BROWSER = NO\r
-\r
-# Setting the INLINE_SOURCES tag to YES will include the body\r
-# of functions and classes directly in the documentation.\r
-\r
-INLINE_SOURCES = NO\r
-\r
-# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct\r
-# doxygen to hide any special comment blocks from generated source code\r
-# fragments. Normal C and C++ comments will always remain visible.\r
-\r
-STRIP_CODE_COMMENTS = YES\r
-\r
-# If the REFERENCED_BY_RELATION tag is set to YES\r
-# then for each documented function all documented\r
-# functions referencing it will be listed.\r
-\r
-REFERENCED_BY_RELATION = NO\r
-\r
-# If the REFERENCES_RELATION tag is set to YES\r
-# then for each documented function all documented entities\r
-# called/used by that function will be listed.\r
-\r
-REFERENCES_RELATION = NO\r
-\r
-# If the REFERENCES_LINK_SOURCE tag is set to YES (the default)\r
-# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from\r
-# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will\r
-# link to the source code.\r
-# Otherwise they will link to the documentation.\r
-\r
-REFERENCES_LINK_SOURCE = NO\r
-\r
-# If the USE_HTAGS tag is set to YES then the references to source code\r
-# will point to the HTML generated by the htags(1) tool instead of doxygen\r
-# built-in source browser. The htags tool is part of GNU's global source\r
-# tagging system (see http://www.gnu.org/software/global/global.html). You\r
-# will need version 4.8.6 or higher.\r
-\r
-USE_HTAGS = NO\r
-\r
-# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen\r
-# will generate a verbatim copy of the header file for each class for\r
-# which an include is specified. Set to NO to disable this.\r
-\r
-VERBATIM_HEADERS = NO\r
-\r
-#---------------------------------------------------------------------------\r
-# configuration options related to the alphabetical class index\r
-#---------------------------------------------------------------------------\r
-\r
-# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index\r
-# of all compounds will be generated. Enable this if the project\r
-# contains a lot of classes, structs, unions or interfaces.\r
-\r
-ALPHABETICAL_INDEX = YES\r
-\r
-# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then\r
-# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns\r
-# in which this list will be split (can be a number in the range [1..20])\r
-\r
-COLS_IN_ALPHA_INDEX = 5\r
-\r
-# In case all classes in a project start with a common prefix, all\r
-# classes will be put under the same header in the alphabetical index.\r
-# The IGNORE_PREFIX tag can be used to specify one or more prefixes that\r
-# should be ignored while generating the index headers.\r
-\r
-IGNORE_PREFIX =\r
-\r
-#---------------------------------------------------------------------------\r
-# configuration options related to the HTML output\r
-#---------------------------------------------------------------------------\r
-\r
-# If the GENERATE_HTML tag is set to YES (the default) Doxygen will\r
-# generate HTML output.\r
-\r
-GENERATE_HTML = YES\r
-\r
-# The HTML_OUTPUT tag is used to specify where the HTML docs will be put.\r
-# If a relative path is entered the value of OUTPUT_DIRECTORY will be\r
-# put in front of it. If left blank `html' will be used as the default path.\r
-\r
-HTML_OUTPUT = html\r
-\r
-# The HTML_FILE_EXTENSION tag can be used to specify the file extension for\r
-# each generated HTML page (for example: .htm,.php,.asp). If it is left blank\r
-# doxygen will generate files with .html extension.\r
-\r
-HTML_FILE_EXTENSION = .html\r
-\r
-# The HTML_HEADER tag can be used to specify a personal HTML header for\r
-# each generated HTML page. If it is left blank doxygen will generate a\r
-# standard header.\r
-\r
-HTML_HEADER =\r
-\r
-# The HTML_FOOTER tag can be used to specify a personal HTML footer for\r
-# each generated HTML page. If it is left blank doxygen will generate a\r
-# standard footer.\r
-\r
-HTML_FOOTER =\r
-\r
-# The HTML_STYLESHEET tag can be used to specify a user-defined cascading\r
-# style sheet that is used by each HTML page. It can be used to\r
-# fine-tune the look of the HTML output. If the tag is left blank doxygen\r
-# will generate a default style sheet. Note that doxygen will try to copy\r
-# the style sheet file to the HTML output directory, so don't put your own\r
-# stylesheet in the HTML output directory as well, or it will be erased!\r
-\r
-HTML_STYLESHEET =\r
-\r
-# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML\r
-# page will contain the date and time when the page was generated. Setting\r
-# this to NO can help when comparing the output of multiple runs.\r
-\r
-HTML_TIMESTAMP = NO\r
-\r
-# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes,\r
-# files or namespaces will be aligned in HTML using tables. If set to\r
-# NO a bullet list will be used.\r
-\r
-HTML_ALIGN_MEMBERS = YES\r
-\r
-# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML\r
-# documentation will contain sections that can be hidden and shown after the\r
-# page has loaded. For this to work a browser that supports\r
-# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox\r
-# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari).\r
-\r
-HTML_DYNAMIC_SECTIONS = YES\r
-\r
-# If the GENERATE_DOCSET tag is set to YES, additional index files\r
-# will be generated that can be used as input for Apple's Xcode 3\r
-# integrated development environment, introduced with OSX 10.5 (Leopard).\r
-# To create a documentation set, doxygen will generate a Makefile in the\r
-# HTML output directory. Running make will produce the docset in that\r
-# directory and running "make install" will install the docset in\r
-# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find\r
-# it at startup.\r
-# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html for more information.\r
-\r
-GENERATE_DOCSET = NO\r
-\r
-# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the\r
-# feed. A documentation feed provides an umbrella under which multiple\r
-# documentation sets from a single provider (such as a company or product suite)\r
-# can be grouped.\r
-\r
-DOCSET_FEEDNAME = "Doxygen generated docs"\r
-\r
-# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that\r
-# should uniquely identify the documentation set bundle. This should be a\r
-# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen\r
-# will append .docset to the name.\r
-\r
-DOCSET_BUNDLE_ID = org.doxygen.Project\r
-\r
-# If the GENERATE_HTMLHELP tag is set to YES, additional index files\r
-# will be generated that can be used as input for tools like the\r
-# Microsoft HTML help workshop to generate a compiled HTML help file (.chm)\r
-# of the generated HTML documentation.\r
-\r
-GENERATE_HTMLHELP = NO\r
-\r
-# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can\r
-# be used to specify the file name of the resulting .chm file. You\r
-# can add a path in front of the file if the result should not be\r
-# written to the html output directory.\r
-\r
-CHM_FILE =\r
-\r
-# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can\r
-# be used to specify the location (absolute path including file name) of\r
-# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run\r
-# the HTML help compiler on the generated index.hhp.\r
-\r
-HHC_LOCATION =\r
-\r
-# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag\r
-# controls if a separate .chi index file is generated (YES) or that\r
-# it should be included in the master .chm file (NO).\r
-\r
-GENERATE_CHI = NO\r
-\r
-# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING\r
-# is used to encode HtmlHelp index (hhk), content (hhc) and project file\r
-# content.\r
-\r
-CHM_INDEX_ENCODING =\r
-\r
-# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag\r
-# controls whether a binary table of contents is generated (YES) or a\r
-# normal table of contents (NO) in the .chm file.\r
-\r
-BINARY_TOC = NO\r
-\r
-# The TOC_EXPAND flag can be set to YES to add extra items for group members\r
-# to the contents of the HTML help documentation and to the tree view.\r
-\r
-TOC_EXPAND = YES\r
-\r
-# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and QHP_VIRTUAL_FOLDER\r
-# are set, an additional index file will be generated that can be used as input for\r
-# Qt's qhelpgenerator to generate a Qt Compressed Help (.qch) of the generated\r
-# HTML documentation.\r
-\r
-GENERATE_QHP = NO\r
-\r
-# If the QHG_LOCATION tag is specified, the QCH_FILE tag can\r
-# be used to specify the file name of the resulting .qch file.\r
-# The path specified is relative to the HTML output folder.\r
-\r
-QCH_FILE =\r
-\r
-# The QHP_NAMESPACE tag specifies the namespace to use when generating\r
-# Qt Help Project output. For more information please see\r
-# http://doc.trolltech.com/qthelpproject.html#namespace\r
-\r
-QHP_NAMESPACE = org.doxygen.Project\r
-\r
-# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating\r
-# Qt Help Project output. For more information please see\r
-# http://doc.trolltech.com/qthelpproject.html#virtual-folders\r
-\r
-QHP_VIRTUAL_FOLDER = doc\r
-\r
-# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to add.\r
-# For more information please see\r
-# http://doc.trolltech.com/qthelpproject.html#custom-filters\r
-\r
-QHP_CUST_FILTER_NAME =\r
-\r
-# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the custom filter to add.For more information please see\r
-# <a href="http://doc.trolltech.com/qthelpproject.html#custom-filters">Qt Help Project / Custom Filters</a>.\r
-\r
-QHP_CUST_FILTER_ATTRS =\r
-\r
-# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this project's\r
-# filter section matches.\r
-# <a href="http://doc.trolltech.com/qthelpproject.html#filter-attributes">Qt Help Project / Filter Attributes</a>.\r
-\r
-QHP_SECT_FILTER_ATTRS =\r
-\r
-# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can\r
-# be used to specify the location of Qt's qhelpgenerator.\r
-# If non-empty doxygen will try to run qhelpgenerator on the generated\r
-# .qhp file.\r
-\r
-QHG_LOCATION =\r
-\r
-# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files\r
-# will be generated, which together with the HTML files, form an Eclipse help\r
-# plugin. To install this plugin and make it available under the help contents\r
-# menu in Eclipse, the contents of the directory containing the HTML and XML\r
-# files needs to be copied into the plugins directory of eclipse. The name of\r
-# the directory within the plugins directory should be the same as\r
-# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before the help appears.\r
-\r
-GENERATE_ECLIPSEHELP = NO\r
-\r
-# A unique identifier for the eclipse help plugin. When installing the plugin\r
-# the directory name containing the HTML and XML files should also have\r
-# this name.\r
-\r
-ECLIPSE_DOC_ID = org.doxygen.Project\r
-\r
-# The DISABLE_INDEX tag can be used to turn on/off the condensed index at\r
-# top of each HTML page. The value NO (the default) enables the index and\r
-# the value YES disables it.\r
-\r
-DISABLE_INDEX = NO\r
-\r
-# This tag can be used to set the number of enum values (range [1..20])\r
-# that doxygen will group on one line in the generated HTML documentation.\r
-\r
-ENUM_VALUES_PER_LINE = 1\r
-\r
-# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index\r
-# structure should be generated to display hierarchical information.\r
-# If the tag value is set to YES, a side panel will be generated\r
-# containing a tree-like index structure (just like the one that\r
-# is generated for HTML Help). For this to work a browser that supports\r
-# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser).\r
-# Windows users are probably better off using the HTML help feature.\r
-\r
-GENERATE_TREEVIEW = YES\r
-\r
-# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories,\r
-# and Class Hierarchy pages using a tree view instead of an ordered list.\r
-\r
-USE_INLINE_TREES = NO\r
-\r
-# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be\r
-# used to set the initial width (in pixels) of the frame in which the tree\r
-# is shown.\r
-\r
-TREEVIEW_WIDTH = 250\r
-\r
-# Use this tag to change the font size of Latex formulas included\r
-# as images in the HTML documentation. The default is 10. Note that\r
-# when you change the font size after a successful doxygen run you need\r
-# to manually remove any form_*.png images from the HTML output directory\r
-# to force them to be regenerated.\r
-\r
-FORMULA_FONTSIZE = 10\r
-\r
-# When the SEARCHENGINE tag is enabled doxygen will generate a search box for the HTML output. The underlying search engine uses javascript\r
-# and DHTML and should work on any modern browser. Note that when using HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets (GENERATE_DOCSET) there is already a search function so this one should\r
-# typically be disabled. For large projects the javascript based search engine\r
-# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution.\r
-\r
-SEARCHENGINE = NO\r
-\r
-# When the SERVER_BASED_SEARCH tag is enabled the search engine will be implemented using a PHP enabled web server instead of at the web client using Javascript. Doxygen will generate the search PHP script and index\r
-# file to put on the web server. The advantage of the server based approach is that it scales better to large projects and allows full text search. The disadvances is that it is more difficult to setup\r
-# and does not have live searching capabilities.\r
-\r
-SERVER_BASED_SEARCH = NO\r
-\r
-#---------------------------------------------------------------------------\r
-# configuration options related to the LaTeX output\r
-#---------------------------------------------------------------------------\r
-\r
-# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will\r
-# generate Latex output.\r
-\r
-GENERATE_LATEX = NO\r
-\r
-# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put.\r
-# If a relative path is entered the value of OUTPUT_DIRECTORY will be\r
-# put in front of it. If left blank `latex' will be used as the default path.\r
-\r
-LATEX_OUTPUT = latex\r
-\r
-# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be\r
-# invoked. If left blank `latex' will be used as the default command name.\r
-# Note that when enabling USE_PDFLATEX this option is only used for\r
-# generating bitmaps for formulas in the HTML output, but not in the\r
-# Makefile that is written to the output directory.\r
-\r
-LATEX_CMD_NAME = latex\r
-\r
-# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to\r
-# generate index for LaTeX. If left blank `makeindex' will be used as the\r
-# default command name.\r
-\r
-MAKEINDEX_CMD_NAME = makeindex\r
-\r
-# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact\r
-# LaTeX documents. This may be useful for small projects and may help to\r
-# save some trees in general.\r
-\r
-COMPACT_LATEX = NO\r
-\r
-# The PAPER_TYPE tag can be used to set the paper type that is used\r
-# by the printer. Possible values are: a4, a4wide, letter, legal and\r
-# executive. If left blank a4wide will be used.\r
-\r
-PAPER_TYPE = a4wide\r
-\r
-# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX\r
-# packages that should be included in the LaTeX output.\r
-\r
-EXTRA_PACKAGES =\r
-\r
-# The LATEX_HEADER tag can be used to specify a personal LaTeX header for\r
-# the generated latex document. The header should contain everything until\r
-# the first chapter. If it is left blank doxygen will generate a\r
-# standard header. Notice: only use this tag if you know what you are doing!\r
-\r
-LATEX_HEADER =\r
-\r
-# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated\r
-# is prepared for conversion to pdf (using ps2pdf). The pdf file will\r
-# contain links (just like the HTML output) instead of page references\r
-# This makes the output suitable for online browsing using a pdf viewer.\r
-\r
-PDF_HYPERLINKS = YES\r
-\r
-# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of\r
-# plain latex in the generated Makefile. Set this option to YES to get a\r
-# higher quality PDF documentation.\r
-\r
-USE_PDFLATEX = YES\r
-\r
-# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode.\r
-# command to the generated LaTeX files. This will instruct LaTeX to keep\r
-# running if errors occur, instead of asking the user for help.\r
-# This option is also used when generating formulas in HTML.\r
-\r
-LATEX_BATCHMODE = NO\r
-\r
-# If LATEX_HIDE_INDICES is set to YES then doxygen will not\r
-# include the index chapters (such as File Index, Compound Index, etc.)\r
-# in the output.\r
-\r
-LATEX_HIDE_INDICES = NO\r
-\r
-# If LATEX_SOURCE_CODE is set to YES then doxygen will include source code with syntax highlighting in the LaTeX output. Note that which sources are shown also depends on other settings such as SOURCE_BROWSER.\r
-\r
-LATEX_SOURCE_CODE = NO\r
-\r
-#---------------------------------------------------------------------------\r
-# configuration options related to the RTF output\r
-#---------------------------------------------------------------------------\r
-\r
-# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output\r
-# The RTF output is optimized for Word 97 and may not look very pretty with\r
-# other RTF readers or editors.\r
-\r
-GENERATE_RTF = NO\r
-\r
-# The RTF_OUTPUT tag is used to specify where the RTF docs will be put.\r
-# If a relative path is entered the value of OUTPUT_DIRECTORY will be\r
-# put in front of it. If left blank `rtf' will be used as the default path.\r
-\r
-RTF_OUTPUT = rtf\r
-\r
-# If the COMPACT_RTF tag is set to YES Doxygen generates more compact\r
-# RTF documents. This may be useful for small projects and may help to\r
-# save some trees in general.\r
-\r
-COMPACT_RTF = NO\r
-\r
-# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated\r
-# will contain hyperlink fields. The RTF file will\r
-# contain links (just like the HTML output) instead of page references.\r
-# This makes the output suitable for online browsing using WORD or other\r
-# programs which support those fields.\r
-# Note: wordpad (write) and others do not support links.\r
-\r
-RTF_HYPERLINKS = NO\r
-\r
-# Load stylesheet definitions from file. Syntax is similar to doxygen's\r
-# config file, i.e. a series of assignments. You only have to provide\r
-# replacements, missing definitions are set to their default value.\r
-\r
-RTF_STYLESHEET_FILE =\r
-\r
-# Set optional variables used in the generation of an rtf document.\r
-# Syntax is similar to doxygen's config file.\r
-\r
-RTF_EXTENSIONS_FILE =\r
-\r
-#---------------------------------------------------------------------------\r
-# configuration options related to the man page output\r
-#---------------------------------------------------------------------------\r
-\r
-# If the GENERATE_MAN tag is set to YES (the default) Doxygen will\r
-# generate man pages\r
-\r
-GENERATE_MAN = NO\r
-\r
-# The MAN_OUTPUT tag is used to specify where the man pages will be put.\r
-# If a relative path is entered the value of OUTPUT_DIRECTORY will be\r
-# put in front of it. If left blank `man' will be used as the default path.\r
-\r
-MAN_OUTPUT = man\r
-\r
-# The MAN_EXTENSION tag determines the extension that is added to\r
-# the generated man pages (default is the subroutine's section .3)\r
-\r
-MAN_EXTENSION = .3\r
-\r
-# If the MAN_LINKS tag is set to YES and Doxygen generates man output,\r
-# then it will generate one additional man file for each entity\r
-# documented in the real man page(s). These additional files\r
-# only source the real man page, but without them the man command\r
-# would be unable to find the correct page. The default is NO.\r
-\r
-MAN_LINKS = NO\r
-\r
-#---------------------------------------------------------------------------\r
-# configuration options related to the XML output\r
-#---------------------------------------------------------------------------\r
-\r
-# If the GENERATE_XML tag is set to YES Doxygen will\r
-# generate an XML file that captures the structure of\r
-# the code including all documentation.\r
-\r
-GENERATE_XML = NO\r
-\r
-# The XML_OUTPUT tag is used to specify where the XML pages will be put.\r
-# If a relative path is entered the value of OUTPUT_DIRECTORY will be\r
-# put in front of it. If left blank `xml' will be used as the default path.\r
-\r
-XML_OUTPUT = xml\r
-\r
-# The XML_SCHEMA tag can be used to specify an XML schema,\r
-# which can be used by a validating XML parser to check the\r
-# syntax of the XML files.\r
-\r
-XML_SCHEMA =\r
-\r
-# The XML_DTD tag can be used to specify an XML DTD,\r
-# which can be used by a validating XML parser to check the\r
-# syntax of the XML files.\r
-\r
-XML_DTD =\r
-\r
-# If the XML_PROGRAMLISTING tag is set to YES Doxygen will\r
-# dump the program listings (including syntax highlighting\r
-# and cross-referencing information) to the XML output. Note that\r
-# enabling this will significantly increase the size of the XML output.\r
-\r
-XML_PROGRAMLISTING = YES\r
-\r
-#---------------------------------------------------------------------------\r
-# configuration options for the AutoGen Definitions output\r
-#---------------------------------------------------------------------------\r
-\r
-# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will\r
-# generate an AutoGen Definitions (see autogen.sf.net) file\r
-# that captures the structure of the code including all\r
-# documentation. Note that this feature is still experimental\r
-# and incomplete at the moment.\r
-\r
-GENERATE_AUTOGEN_DEF = NO\r
-\r
-#---------------------------------------------------------------------------\r
-# configuration options related to the Perl module output\r
-#---------------------------------------------------------------------------\r
-\r
-# If the GENERATE_PERLMOD tag is set to YES Doxygen will\r
-# generate a Perl module file that captures the structure of\r
-# the code including all documentation. Note that this\r
-# feature is still experimental and incomplete at the\r
-# moment.\r
-\r
-GENERATE_PERLMOD = NO\r
-\r
-# If the PERLMOD_LATEX tag is set to YES Doxygen will generate\r
-# the necessary Makefile rules, Perl scripts and LaTeX code to be able\r
-# to generate PDF and DVI output from the Perl module output.\r
-\r
-PERLMOD_LATEX = NO\r
-\r
-# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be\r
-# nicely formatted so it can be parsed by a human reader.\r
-# This is useful\r
-# if you want to understand what is going on.\r
-# On the other hand, if this\r
-# tag is set to NO the size of the Perl module output will be much smaller\r
-# and Perl will parse it just the same.\r
-\r
-PERLMOD_PRETTY = YES\r
-\r
-# The names of the make variables in the generated doxyrules.make file\r
-# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX.\r
-# This is useful so different doxyrules.make files included by the same\r
-# Makefile don't overwrite each other's variables.\r
-\r
-PERLMOD_MAKEVAR_PREFIX =\r
-\r
-#---------------------------------------------------------------------------\r
-# Configuration options related to the preprocessor\r
-#---------------------------------------------------------------------------\r
-\r
-# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will\r
-# evaluate all C-preprocessor directives found in the sources and include\r
-# files.\r
-\r
-ENABLE_PREPROCESSING = YES\r
-\r
-# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro\r
-# names in the source code. If set to NO (the default) only conditional\r
-# compilation will be performed. Macro expansion can be done in a controlled\r
-# way by setting EXPAND_ONLY_PREDEF to YES.\r
-\r
-MACRO_EXPANSION = YES\r
-\r
-# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES\r
-# then the macro expansion is limited to the macros specified with the\r
-# PREDEFINED and EXPAND_AS_DEFINED tags.\r
-\r
-EXPAND_ONLY_PREDEF = YES\r
-\r
-# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files\r
-# in the INCLUDE_PATH (see below) will be search if a #include is found.\r
-\r
-SEARCH_INCLUDES = YES\r
-\r
-# The INCLUDE_PATH tag can be used to specify one or more directories that\r
-# contain include files that are not input files but should be processed by\r
-# the preprocessor.\r
-\r
-INCLUDE_PATH =\r
-\r
-# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard\r
-# patterns (like *.h and *.hpp) to filter out the header-files in the\r
-# directories. If left blank, the patterns specified with FILE_PATTERNS will\r
-# be used.\r
-\r
-INCLUDE_FILE_PATTERNS =\r
-\r
-# The PREDEFINED tag can be used to specify one or more macro names that\r
-# are defined before the preprocessor is started (similar to the -D option of\r
-# gcc). The argument of the tag is a list of macros of the form: name\r
-# or name=definition (no spaces). If the definition and the = are\r
-# omitted =1 is assumed. To prevent a macro definition from being\r
-# undefined via #undef or recursively expanded use the := operator\r
-# instead of the = operator.\r
-\r
-PREDEFINED = __DOXYGEN__ \\r
- PROGMEM\r
-\r
-# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then\r
-# this tag can be used to specify a list of macro names that should be expanded.\r
-# The macro definition that is found in the sources will be used.\r
-# Use the PREDEFINED tag if you want to use a different macro definition.\r
-\r
-EXPAND_AS_DEFINED = \r
-\r
-# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then\r
-# doxygen's preprocessor will remove all function-like macros that are alone\r
-# on a line, have an all uppercase name, and do not end with a semicolon. Such\r
-# function macros are typically used for boiler-plate code, and will confuse\r
-# the parser if not removed.\r
-\r
-SKIP_FUNCTION_MACROS = YES\r
-\r
-#---------------------------------------------------------------------------\r
-# Configuration::additions related to external references\r
-#---------------------------------------------------------------------------\r
-\r
-# The TAGFILES option can be used to specify one or more tagfiles.\r
-# Optionally an initial location of the external documentation\r
-# can be added for each tagfile. The format of a tag file without\r
-# this location is as follows:\r
-#\r
-# TAGFILES = file1 file2 ...\r
-# Adding location for the tag files is done as follows:\r
-#\r
-# TAGFILES = file1=loc1 "file2 = loc2" ...\r
-# where "loc1" and "loc2" can be relative or absolute paths or\r
-# URLs. If a location is present for each tag, the installdox tool\r
-# does not have to be run to correct the links.\r
-# Note that each tag file must have a unique name\r
-# (where the name does NOT include the path)\r
-# If a tag file is not located in the directory in which doxygen\r
-# is run, you must also specify the path to the tagfile here.\r
-\r
-TAGFILES =\r
-\r
-# When a file name is specified after GENERATE_TAGFILE, doxygen will create\r
-# a tag file that is based on the input files it reads.\r
-\r
-GENERATE_TAGFILE =\r
-\r
-# If the ALLEXTERNALS tag is set to YES all external classes will be listed\r
-# in the class index. If set to NO only the inherited external classes\r
-# will be listed.\r
-\r
-ALLEXTERNALS = NO\r
-\r
-# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed\r
-# in the modules index. If set to NO, only the current project's groups will\r
-# be listed.\r
-\r
-EXTERNAL_GROUPS = YES\r
-\r
-# The PERL_PATH should be the absolute path and name of the perl script\r
-# interpreter (i.e. the result of `which perl').\r
-\r
-PERL_PATH = /usr/bin/perl\r
-\r
-#---------------------------------------------------------------------------\r
-# Configuration options related to the dot tool\r
-#---------------------------------------------------------------------------\r
-\r
-# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will\r
-# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base\r
-# or super classes. Setting the tag to NO turns the diagrams off. Note that\r
-# this option is superseded by the HAVE_DOT option below. This is only a\r
-# fallback. It is recommended to install and use dot, since it yields more\r
-# powerful graphs.\r
-\r
-CLASS_DIAGRAMS = NO\r
-\r
-# You can define message sequence charts within doxygen comments using the \msc\r
-# command. Doxygen will then run the mscgen tool (see\r
-# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the\r
-# documentation. The MSCGEN_PATH tag allows you to specify the directory where\r
-# the mscgen tool resides. If left empty the tool is assumed to be found in the\r
-# default search path.\r
-\r
-MSCGEN_PATH =\r
-\r
-# If set to YES, the inheritance and collaboration graphs will hide\r
-# inheritance and usage relations if the target is undocumented\r
-# or is not a class.\r
-\r
-HIDE_UNDOC_RELATIONS = YES\r
-\r
-# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is\r
-# available from the path. This tool is part of Graphviz, a graph visualization\r
-# toolkit from AT&T and Lucent Bell Labs. The other options in this section\r
-# have no effect if this option is set to NO (the default)\r
-\r
-HAVE_DOT = NO\r
-\r
-# By default doxygen will write a font called FreeSans.ttf to the output\r
-# directory and reference it in all dot files that doxygen generates. This\r
-# font does not include all possible unicode characters however, so when you need\r
-# these (or just want a differently looking font) you can specify the font name\r
-# using DOT_FONTNAME. You need need to make sure dot is able to find the font,\r
-# which can be done by putting it in a standard location or by setting the\r
-# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory\r
-# containing the font.\r
-\r
-DOT_FONTNAME = FreeSans\r
-\r
-# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs.\r
-# The default size is 10pt.\r
-\r
-DOT_FONTSIZE = 10\r
-\r
-# By default doxygen will tell dot to use the output directory to look for the\r
-# FreeSans.ttf font (which doxygen will put there itself). If you specify a\r
-# different font using DOT_FONTNAME you can set the path where dot\r
-# can find it using this tag.\r
-\r
-DOT_FONTPATH =\r
-\r
-# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen\r
-# will generate a graph for each documented class showing the direct and\r
-# indirect inheritance relations. Setting this tag to YES will force the\r
-# the CLASS_DIAGRAMS tag to NO.\r
-\r
-CLASS_GRAPH = NO\r
-\r
-# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen\r
-# will generate a graph for each documented class showing the direct and\r
-# indirect implementation dependencies (inheritance, containment, and\r
-# class references variables) of the class with other documented classes.\r
-\r
-COLLABORATION_GRAPH = NO\r
-\r
-# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen\r
-# will generate a graph for groups, showing the direct groups dependencies\r
-\r
-GROUP_GRAPHS = NO\r
-\r
-# If the UML_LOOK tag is set to YES doxygen will generate inheritance and\r
-# collaboration diagrams in a style similar to the OMG's Unified Modeling\r
-# Language.\r
-\r
-UML_LOOK = NO\r
-\r
-# If set to YES, the inheritance and collaboration graphs will show the\r
-# relations between templates and their instances.\r
-\r
-TEMPLATE_RELATIONS = NO\r
-\r
-# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT\r
-# tags are set to YES then doxygen will generate a graph for each documented\r
-# file showing the direct and indirect include dependencies of the file with\r
-# other documented files.\r
-\r
-INCLUDE_GRAPH = NO\r
-\r
-# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and\r
-# HAVE_DOT tags are set to YES then doxygen will generate a graph for each\r
-# documented header file showing the documented files that directly or\r
-# indirectly include this file.\r
-\r
-INCLUDED_BY_GRAPH = NO\r
-\r
-# If the CALL_GRAPH and HAVE_DOT options are set to YES then\r
-# doxygen will generate a call dependency graph for every global function\r
-# or class method. Note that enabling this option will significantly increase\r
-# the time of a run. So in most cases it will be better to enable call graphs\r
-# for selected functions only using the \callgraph command.\r
-\r
-CALL_GRAPH = NO\r
-\r
-# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then\r
-# doxygen will generate a caller dependency graph for every global function\r
-# or class method. Note that enabling this option will significantly increase\r
-# the time of a run. So in most cases it will be better to enable caller\r
-# graphs for selected functions only using the \callergraph command.\r
-\r
-CALLER_GRAPH = NO\r
-\r
-# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen\r
-# will graphical hierarchy of all classes instead of a textual one.\r
-\r
-GRAPHICAL_HIERARCHY = NO\r
-\r
-# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES\r
-# then doxygen will show the dependencies a directory has on other directories\r
-# in a graphical way. The dependency relations are determined by the #include\r
-# relations between the files in the directories.\r
-\r
-DIRECTORY_GRAPH = NO\r
-\r
-# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images\r
-# generated by dot. Possible values are png, jpg, or gif\r
-# If left blank png will be used.\r
-\r
-DOT_IMAGE_FORMAT = png\r
-\r
-# The tag DOT_PATH can be used to specify the path where the dot tool can be\r
-# found. If left blank, it is assumed the dot tool can be found in the path.\r
-\r
-DOT_PATH =\r
-\r
-# The DOTFILE_DIRS tag can be used to specify one or more directories that\r
-# contain dot files that are included in the documentation (see the\r
-# \dotfile command).\r
-\r
-DOTFILE_DIRS =\r
-\r
-# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of\r
-# nodes that will be shown in the graph. If the number of nodes in a graph\r
-# becomes larger than this value, doxygen will truncate the graph, which is\r
-# visualized by representing a node as a red box. Note that doxygen if the\r
-# number of direct children of the root node in a graph is already larger than\r
-# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note\r
-# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH.\r
-\r
-DOT_GRAPH_MAX_NODES = 15\r
-\r
-# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the\r
-# graphs generated by dot. A depth value of 3 means that only nodes reachable\r
-# from the root by following a path via at most 3 edges will be shown. Nodes\r
-# that lay further from the root node will be omitted. Note that setting this\r
-# option to 1 or 2 may greatly reduce the computation time needed for large\r
-# code bases. Also note that the size of a graph can be further restricted by\r
-# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction.\r
-\r
-MAX_DOT_GRAPH_DEPTH = 2\r
-\r
-# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent\r
-# background. This is disabled by default, because dot on Windows does not\r
-# seem to support this out of the box. Warning: Depending on the platform used,\r
-# enabling this option may lead to badly anti-aliased labels on the edges of\r
-# a graph (i.e. they become hard to read).\r
-\r
-DOT_TRANSPARENT = YES\r
-\r
-# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output\r
-# files in one run (i.e. multiple -o and -T options on the command line). This\r
-# makes dot run faster, but since only newer versions of dot (>1.8.10)\r
-# support this, this feature is disabled by default.\r
-\r
-DOT_MULTI_TARGETS = NO\r
-\r
-# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will\r
-# generate a legend page explaining the meaning of the various boxes and\r
-# arrows in the dot generated graphs.\r
-\r
-GENERATE_LEGEND = YES\r
-\r
-# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will\r
-# remove the intermediate dot files that are used to generate\r
-# the various graphs.\r
-\r
-DOT_CLEANUP = YES\r
+++ /dev/null
-<AVRStudio><MANAGEMENT><ProjectName>DualVirtualSerial</ProjectName><Created>13-Jul-2010 15:24:20</Created><LastEdit>13-Jul-2010 15:25:07</LastEdit><ICON>241</ICON><ProjectType>0</ProjectType><Created>13-Jul-2010 15:24:20</Created><Version>4</Version><Build>4, 18, 0, 685</Build><ProjectTypeName>AVR GCC</ProjectTypeName></MANAGEMENT><CODE_CREATION><ObjectFile></ObjectFile><EntryFile></EntryFile><SaveFolder>C:\Users\Dean\Documents\Electronics\Projects\WORK\LUFAWORK\Demos\Device\ClassDriver\DualVirtualSerial\</SaveFolder></CODE_CREATION><DEBUG_TARGET><CURRENT_TARGET>AVR ONE!</CURRENT_TARGET><CURRENT_PART></CURRENT_PART><BREAKPOINTS></BREAKPOINTS><IO_EXPAND><HIDE>false</HIDE></IO_EXPAND><REGISTERNAMES><Register>R00</Register><Register>R01</Register><Register>R02</Register><Register>R03</Register><Register>R04</Register><Register>R05</Register><Register>R06</Register><Register>R07</Register><Register>R08</Register><Register>R09</Register><Register>R10</Register><Register>R11</Register><Register>R12</Register><Register>R13</Register><Register>R14</Register><Register>R15</Register><Register>R16</Register><Register>R17</Register><Register>R18</Register><Register>R19</Register><Register>R20</Register><Register>R21</Register><Register>R22</Register><Register>R23</Register><Register>R24</Register><Register>R25</Register><Register>R26</Register><Register>R27</Register><Register>R28</Register><Register>R29</Register><Register>R30</Register><Register>R31</Register></REGISTERNAMES><COM>Auto</COM><COMType>0</COMType><WATCHNUM>0</WATCHNUM><WATCHNAMES><Pane0></Pane0><Pane1></Pane1><Pane2></Pane2><Pane3></Pane3></WATCHNAMES><BreakOnTrcaeFull>0</BreakOnTrcaeFull></DEBUG_TARGET><Debugger><Triggers></Triggers></Debugger><AVRGCCPLUGIN><FILES><SOURCEFILE>Descriptors.c</SOURCEFILE><SOURCEFILE>DualVirtualSerial.c</SOURCEFILE><HEADERFILE>Descriptors.h</HEADERFILE><HEADERFILE>DualVirtualSerial.h</HEADERFILE><OTHERFILE>makefile</OTHERFILE></FILES><CONFIGS><CONFIG><NAME>default</NAME><USESEXTERNALMAKEFILE>YES</USESEXTERNALMAKEFILE><EXTERNALMAKEFILE>makefile</EXTERNALMAKEFILE><PART>atmega128</PART><HEX>1</HEX><LIST>1</LIST><MAP>1</MAP><OUTPUTFILENAME>DualVirtualSerial.elf</OUTPUTFILENAME><OUTPUTDIR>default\</OUTPUTDIR><ISDIRTY>1</ISDIRTY><OPTIONS/><INCDIRS/><LIBDIRS/><LIBS/><LINKOBJECTS/><OPTIONSFORALL>-Wall -gdwarf-2 -std=gnu99 -Os -funsigned-char -funsigned-bitfields -fpack-struct -fshort-enums</OPTIONSFORALL><LINKEROPTIONS></LINKEROPTIONS><SEGMENTS/></CONFIG></CONFIGS><LASTCONFIG>default</LASTCONFIG><USES_WINAVR>1</USES_WINAVR><GCC_LOC>C:\WinAVR-20100110\bin\avr-gcc.exe</GCC_LOC><MAKE_LOC>C:\WinAVR-20100110\utils\bin\make.exe</MAKE_LOC></AVRGCCPLUGIN><IOView><usergroups/><sort sorted="0" column="0" ordername="0" orderaddress="0" ordergroup="0"/></IOView><Files></Files><Events><Bookmarks></Bookmarks></Events><Trace><Filters></Filters></Trace></AVRStudio>\r
+++ /dev/null
-/*\r
- LUFA Library\r
- Copyright (C) Dean Camera, 2011.\r
-\r
- dean [at] fourwalledcubicle [dot] com\r
- www.lufa-lib.org\r
-*/\r
-\r
-/*\r
- Copyright 2011 Dean Camera (dean [at] fourwalledcubicle [dot] com)\r
-\r
- Permission to use, copy, modify, distribute, and sell this\r
- software and its documentation for any purpose is hereby granted\r
- without fee, provided that the above copyright notice appear in\r
- all copies and that both that the copyright notice and this\r
- permission notice and warranty disclaimer appear in supporting\r
- documentation, and that the name of the author not be used in\r
- advertising or publicity pertaining to distribution of the\r
- software without specific, written prior permission.\r
-\r
- The author disclaim all warranties with regard to this\r
- software, including all implied warranties of merchantability\r
- and fitness. In no event shall the author be liable for any\r
- special, indirect or consequential damages or any damages\r
- whatsoever resulting from loss of use, data or profits, whether\r
- in an action of contract, negligence or other tortious action,\r
- arising out of or in connection with the use or performance of\r
- this software.\r
-*/\r
-\r
-/** \file\r
- *\r
- * Main source file for the DualVirtualSerial demo. This file contains the main tasks of\r
- * the demo and is responsible for the initial application hardware configuration.\r
- */\r
-\r
-#include "DualVirtualSerial.h"\r
-\r
-\r
-#include <aversive.h>\r
-#include <aversive/error.h>\r
-#include <aversive/queue.h>\r
-\r
-#include <scheduler.h>\r
-#include <clock_time.h>\r
-#include <parse.h>\r
-#include <rdline.h>\r
-#include <timer.h>\r
-\r
-#include "xbee_neighbor.h"\r
-#include "xbee_atcmd.h"\r
-#include "xbee_stats.h"\r
-#include "xbee_buf.h"\r
-#include "xbee_proto.h"\r
-#include "xbee.h"\r
-\r
-#include "callout.h"\r
-#include "main.h"\r
-#include "cmdline.h"\r
-\r
-/** LUFA CDC Class driver interface configuration and state information. This structure is\r
- * passed to all CDC Class driver functions, so that multiple instances of the same class\r
- * within a device can be differentiated from one another. This is for the first CDC interface,\r
- * which sends strings to the host for each joystick movement.\r
- */\r
-USB_ClassInfo_CDC_Device_t VirtualSerial1_CDC_Interface =\r
- {\r
- .Config =\r
- {\r
- .ControlInterfaceNumber = 0,\r
-\r
- .DataINEndpointNumber = CDC1_TX_EPNUM,\r
- .DataINEndpointSize = CDC_TXRX_EPSIZE,\r
- .DataINEndpointDoubleBank = false,\r
-\r
- .DataOUTEndpointNumber = CDC1_RX_EPNUM,\r
- .DataOUTEndpointSize = CDC_TXRX_EPSIZE,\r
- .DataOUTEndpointDoubleBank = false,\r
-\r
- .NotificationEndpointNumber = CDC1_NOTIFICATION_EPNUM,\r
- .NotificationEndpointSize = CDC_NOTIFICATION_EPSIZE,\r
- .NotificationEndpointDoubleBank = false,\r
- },\r
- };\r
-\r
-/** LUFA CDC Class driver interface configuration and state information. This structure is\r
- * passed to all CDC Class driver functions, so that multiple instances of the same class\r
- * within a device can be differentiated from one another. This is for the second CDC interface,\r
- * which echos back all received data from the host.\r
- */\r
-USB_ClassInfo_CDC_Device_t VirtualSerial2_CDC_Interface =\r
- {\r
- .Config =\r
- {\r
- .ControlInterfaceNumber = 2,\r
-\r
- .DataINEndpointNumber = CDC2_TX_EPNUM,\r
- .DataINEndpointSize = CDC_TXRX_EPSIZE,\r
- .DataINEndpointDoubleBank = false,\r
-\r
- .DataOUTEndpointNumber = CDC2_RX_EPNUM,\r
- .DataOUTEndpointSize = CDC_TXRX_EPSIZE,\r
- .DataOUTEndpointDoubleBank = false,\r
-\r
- .NotificationEndpointNumber = CDC2_NOTIFICATION_EPNUM,\r
- .NotificationEndpointSize = CDC_NOTIFICATION_EPSIZE,\r
- .NotificationEndpointDoubleBank = false,\r
- },\r
- };\r
-\r
-\r
-/** Configures the board hardware and chip peripherals for the demo's functionality. */\r
-void SetupHardware(void)\r
-{\r
- /* Disable watchdog if enabled by bootloader/fuses */\r
- MCUSR &= ~(1 << WDRF);\r
- wdt_disable();\r
-\r
- /* Disable clock division */\r
- clock_prescale_set(clock_div_1);\r
-\r
- /* Hardware Initialization */\r
- Joystick_Init();\r
- LEDs_Init();\r
- USB_Init();\r
-}\r
-\r
-/** Checks for changes in the position of the board joystick, sending strings to the host upon each change\r
- * through the first of the CDC interfaces.\r
- */\r
-void CheckJoystickMovement(void)\r
-{\r
- uint8_t JoyStatus_LCL = Joystick_GetStatus();\r
- char* ReportString = NULL;\r
- static bool ActionSent = false;\r
-\r
- if (JoyStatus_LCL & JOY_UP)\r
- ReportString = "Joystick Up\r\n";\r
- else if (JoyStatus_LCL & JOY_DOWN)\r
- ReportString = "Joystick Down\r\n";\r
- else if (JoyStatus_LCL & JOY_LEFT)\r
- ReportString = "Joystick Left\r\n";\r
- else if (JoyStatus_LCL & JOY_RIGHT)\r
- ReportString = "Joystick Right\r\n";\r
- else if (JoyStatus_LCL & JOY_PRESS)\r
- ReportString = "Joystick Pressed\r\n";\r
- else\r
- ActionSent = false;\r
-\r
- if ((ReportString != NULL) && (ActionSent == false))\r
- {\r
- ActionSent = true;\r
-\r
- CDC_Device_SendString(&VirtualSerial1_CDC_Interface, ReportString);\r
- }\r
-}\r
-\r
-/** Event handler for the library USB Connection event. */\r
-void EVENT_USB_Device_Connect(void)\r
-{\r
- LEDs_SetAllLEDs(LEDMASK_USB_ENUMERATING);\r
-}\r
-\r
-/** Event handler for the library USB Disconnection event. */\r
-void EVENT_USB_Device_Disconnect(void)\r
-{\r
- LEDs_SetAllLEDs(LEDMASK_USB_NOTREADY);\r
-}\r
-\r
-/** Event handler for the library USB Configuration Changed event. */\r
-void EVENT_USB_Device_ConfigurationChanged(void)\r
-{\r
- bool ConfigSuccess = true;\r
-\r
- ConfigSuccess &= CDC_Device_ConfigureEndpoints(&VirtualSerial1_CDC_Interface);\r
- ConfigSuccess &= CDC_Device_ConfigureEndpoints(&VirtualSerial2_CDC_Interface);\r
-\r
- LEDs_SetAllLEDs(ConfigSuccess ? LEDMASK_USB_READY : LEDMASK_USB_ERROR);\r
-\r
- rdline_newline(&xbeeboard.rdl, xbeeboard.prompt);\r
-}\r
-\r
-/** Event handler for the library USB Control Request reception event. */\r
-void EVENT_USB_Device_ControlRequest(void)\r
-{\r
- CDC_Device_ProcessControlRequest(&VirtualSerial1_CDC_Interface);\r
- CDC_Device_ProcessControlRequest(&VirtualSerial2_CDC_Interface);\r
-}\r
-\r
+++ /dev/null
-/*\r
- LUFA Library\r
- Copyright (C) Dean Camera, 2011.\r
-\r
- dean [at] fourwalledcubicle [dot] com\r
- www.lufa-lib.org\r
-*/\r
-\r
-/*\r
- Copyright 2011 Dean Camera (dean [at] fourwalledcubicle [dot] com)\r
-\r
- Permission to use, copy, modify, distribute, and sell this\r
- software and its documentation for any purpose is hereby granted\r
- without fee, provided that the above copyright notice appear in\r
- all copies and that both that the copyright notice and this\r
- permission notice and warranty disclaimer appear in supporting\r
- documentation, and that the name of the author not be used in\r
- advertising or publicity pertaining to distribution of the\r
- software without specific, written prior permission.\r
-\r
- The author disclaim all warranties with regard to this\r
- software, including all implied warranties of merchantability\r
- and fitness. In no event shall the author be liable for any\r
- special, indirect or consequential damages or any damages\r
- whatsoever resulting from loss of use, data or profits, whether\r
- in an action of contract, negligence or other tortious action,\r
- arising out of or in connection with the use or performance of\r
- this software.\r
-*/\r
-\r
-/** \file\r
- *\r
- * Header file for DualVirtualSerial.c.\r
- */\r
-\r
-#ifndef _DUAL_VIRTUALSERIAL_H_\r
-#define _DUAL_VIRTUALSERIAL_H_\r
-\r
- /* Includes: */\r
- #include <avr/io.h>\r
- #include <avr/wdt.h>\r
- #include <avr/power.h>\r
- #include <avr/interrupt.h>\r
- #include <string.h>\r
-\r
- #include "Descriptors.h"\r
-\r
- #include <LUFA/Version.h>\r
- #include <LUFA/Drivers/Board/LEDs.h>\r
- #include <LUFA/Drivers/Board/Joystick.h>\r
- #include <LUFA/Drivers/USB/USB.h>\r
-\r
- /* Macros: */\r
- /** LED mask for the library LED driver, to indicate that the USB interface is not ready. */\r
- #define LEDMASK_USB_NOTREADY LEDS_LED1\r
-\r
- /** LED mask for the library LED driver, to indicate that the USB interface is enumerating. */\r
- #define LEDMASK_USB_ENUMERATING (LEDS_LED2 | LEDS_LED3)\r
-\r
- /** LED mask for the library LED driver, to indicate that the USB interface is ready. */\r
- #define LEDMASK_USB_READY (LEDS_LED2 | LEDS_LED4)\r
-\r
- /** LED mask for the library LED driver, to indicate that an error has occurred in the USB interface. */\r
- #define LEDMASK_USB_ERROR (LEDS_LED1 | LEDS_LED3)\r
-\r
- /* Function Prototypes: */\r
- void SetupHardware(void);\r
- void CheckJoystickMovement(void);\r
-\r
- void EVENT_USB_Device_Connect(void);\r
- void EVENT_USB_Device_Disconnect(void);\r
- void EVENT_USB_Device_ConfigurationChanged(void);\r
- void EVENT_USB_Device_ControlRequest(void);\r
-\r
-extern USB_ClassInfo_CDC_Device_t VirtualSerial1_CDC_Interface;\r
-extern USB_ClassInfo_CDC_Device_t VirtualSerial2_CDC_Interface;\r
-\r
-#endif\r
-\r
+++ /dev/null
-;************************************************************\r
-; Windows USB CDC ACM Setup File\r
-; Copyright (c) 2000 Microsoft Corporation\r
-\r
-\r
-[Version]\r
-Signature="$Windows NT$"\r
-Class=Ports\r
-ClassGuid={4D36E978-E325-11CE-BFC1-08002BE10318}\r
-Provider=%MFGNAME%\r
-LayoutFile=layout.inf\r
-CatalogFile=%MFGFILENAME%.cat\r
-DriverVer=11/15/2007,5.1.2600.0\r
-\r
-[Manufacturer]\r
-%MFGNAME%=DeviceList, NTamd64\r
-\r
-[DestinationDirs]\r
-DefaultDestDir=12\r
-\r
-\r
-;------------------------------------------------------------------------------\r
-; Windows 2000/XP/Vista-32bit Sections\r
-;------------------------------------------------------------------------------\r
-\r
-[DriverInstall.nt]\r
-include=mdmcpq.inf\r
-CopyFiles=DriverCopyFiles.nt\r
-AddReg=DriverInstall.nt.AddReg\r
-\r
-[DriverCopyFiles.nt]\r
-usbser.sys,,,0x20\r
-\r
-[DriverInstall.nt.AddReg]\r
-HKR,,DevLoader,,*ntkern\r
-HKR,,NTMPDriver,,%DRIVERFILENAME%.sys\r
-HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider"\r
-\r
-[DriverInstall.nt.Services]\r
-AddService=usbser, 0x00000002, DriverService.nt\r
-\r
-[DriverService.nt]\r
-DisplayName=%SERVICE%\r
-ServiceType=1\r
-StartType=3\r
-ErrorControl=1\r
-ServiceBinary=%12%\%DRIVERFILENAME%.sys\r
-\r
-;------------------------------------------------------------------------------\r
-; Vista-64bit Sections\r
-;------------------------------------------------------------------------------\r
-\r
-[DriverInstall.NTamd64]\r
-include=mdmcpq.inf\r
-CopyFiles=DriverCopyFiles.NTamd64\r
-AddReg=DriverInstall.NTamd64.AddReg\r
-\r
-[DriverCopyFiles.NTamd64]\r
-%DRIVERFILENAME%.sys,,,0x20\r
-\r
-[DriverInstall.NTamd64.AddReg]\r
-HKR,,DevLoader,,*ntkern\r
-HKR,,NTMPDriver,,%DRIVERFILENAME%.sys\r
-HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider"\r
-\r
-[DriverInstall.NTamd64.Services]\r
-AddService=usbser, 0x00000002, DriverService.NTamd64\r
-\r
-[DriverService.NTamd64]\r
-DisplayName=%SERVICE%\r
-ServiceType=1\r
-StartType=3\r
-ErrorControl=1\r
-ServiceBinary=%12%\%DRIVERFILENAME%.sys\r
-\r
-\r
-;------------------------------------------------------------------------------\r
-; Vendor and Product ID Definitions\r
-;------------------------------------------------------------------------------\r
-; When developing your USB device, the VID and PID used in the PC side\r
-; application program and the firmware on the microcontroller must match.\r
-; Modify the below line to use your VID and PID. Use the format as shown below.\r
-; Note: One INF file can be used for multiple devices with different VID and PIDs.\r
-; For each supported device, append ",USB\VID_xxxx&PID_yyyy" to the end of the line.\r
-;------------------------------------------------------------------------------\r
-[SourceDisksFiles]\r
-[SourceDisksNames]\r
-[DeviceList]\r
-%DESCRIPTION%=DriverInstall, USB\VID_03EB&PID_204E&MI_00, USB\VID_03EB&PID_204E&MI_02\r
-\r
-[DeviceList.NTamd64]\r
-%DESCRIPTION%=DriverInstall, USB\VID_03EB&PID_204E&MI_00, USB\VID_03EB&PID_204E&MI_02\r
-\r
-\r
-;------------------------------------------------------------------------------\r
-; String Definitions\r
-;------------------------------------------------------------------------------\r
-;Modify these strings to customize your device\r
-;------------------------------------------------------------------------------\r
-[Strings]\r
-MFGFILENAME="CDC_vista"\r
-DRIVERFILENAME ="usbser"\r
-MFGNAME="http://www.lufa-lib.org"\r
-INSTDISK="LUFA Dual CDC Driver Installer"\r
-DESCRIPTION="Communications Port"\r
-SERVICE="USB RS-232 Emulation Driver"
\ No newline at end of file
--- /dev/null
+TARGET = main
+
+AVERSIVE_DIR ?= ../..
+
+# List C source files here. (C dependencies are automatically generated.)
+SRC = $(TARGET).c
+SRC += spi_servo.c
+SRC += commands.c
+SRC += commands_gen.c
+SRC += rc_proto.c
+SRC += xbee_atcmd.c
+SRC += xbee.c
+SRC += xbee_neighbor.c
+SRC += xbee_proto.c
+SRC += xbee_stats.c
+SRC += callout.c
+SRC += parse_neighbor.c
+SRC += parse_atcmd.c
+SRC += parse_monitor.c
+SRC += cmdline.c
+
+CFLAGS += -W -Wall -Werror
+
+########################################
+
+-include .aversive_conf
+include $(AVERSIVE_DIR)/mk/aversive_project.mk
+++ /dev/null
-/*
- * Automatically generated by make menuconfig: don't edit
- */
-#define AUTOCONF_INCLUDED
-
-/*
- * Hardware
- */
-#undef CONFIG_MCU_AT90S2313
-#undef CONFIG_MCU_AT90S2323
-#undef CONFIG_MCU_AT90S3333
-#undef CONFIG_MCU_AT90S2343
-#undef CONFIG_MCU_ATTINY22
-#undef CONFIG_MCU_ATTINY26
-#undef CONFIG_MCU_AT90S4414
-#undef CONFIG_MCU_AT90S4433
-#undef CONFIG_MCU_AT90S4434
-#undef CONFIG_MCU_AT90S8515
-#undef CONFIG_MCU_AT90S8534
-#undef CONFIG_MCU_AT90S8535
-#undef CONFIG_MCU_AT86RF401
-#undef CONFIG_MCU_ATMEGA103
-#undef CONFIG_MCU_ATMEGA603
-#undef CONFIG_MCU_AT43USB320
-#undef CONFIG_MCU_AT43USB355
-#undef CONFIG_MCU_AT76C711
-#undef CONFIG_MCU_ATMEGA8
-#undef CONFIG_MCU_ATMEGA48
-#undef CONFIG_MCU_ATMEGA88
-#undef CONFIG_MCU_ATMEGA8515
-#undef CONFIG_MCU_ATMEGA8535
-#undef CONFIG_MCU_ATTINY13
-#undef CONFIG_MCU_ATTINY2313
-#undef CONFIG_MCU_ATMEGA16
-#undef CONFIG_MCU_ATMEGA161
-#undef CONFIG_MCU_ATMEGA162
-#undef CONFIG_MCU_ATMEGA163
-#undef CONFIG_MCU_ATMEGA165
-#undef CONFIG_MCU_ATMEGA168
-#undef CONFIG_MCU_ATMEGA169
-#undef CONFIG_MCU_ATMEGA32
-#undef CONFIG_MCU_ATMEGA323
-#undef CONFIG_MCU_ATMEGA325
-#undef CONFIG_MCU_ATMEGA3250
-#undef CONFIG_MCU_ATMEGA64
-#undef CONFIG_MCU_ATMEGA645
-#undef CONFIG_MCU_ATMEGA6450
-#undef CONFIG_MCU_ATMEGA128
-#undef CONFIG_MCU_ATMEGA1281
-#undef CONFIG_MCU_AT90CAN128
-#undef CONFIG_MCU_AT94K
-#undef CONFIG_MCU_AT90S1200
-#undef CONFIG_MCU_ATMEGA2560
-#undef CONFIG_MCU_ATMEGA256
-#define CONFIG_MCU_ATMEGAUSB1287
-#define CONFIG_QUARTZ (8000000)
-
-/*
- * Generation options
- */
-#undef CONFIG_OPTM_0
-#undef CONFIG_OPTM_1
-#undef CONFIG_OPTM_2
-#undef CONFIG_OPTM_3
-#define CONFIG_OPTM_S 1
-#define CONFIG_MATH_LIB 1
-#undef CONFIG_FDEVOPEN_COMPAT
-#undef CONFIG_NO_PRINTF
-#undef CONFIG_MINIMAL_PRINTF
-#undef CONFIG_STANDARD_PRINTF
-#define CONFIG_ADVANCED_PRINTF 1
-#undef CONFIG_FORMAT_IHEX
-#undef CONFIG_FORMAT_SREC
-#define CONFIG_FORMAT_BINARY 1
-
-/*
- * Base modules
- */
-#define CONFIG_MODULE_CIRBUF 1
-#undef CONFIG_MODULE_CIRBUF_LARGE
-#undef CONFIG_MODULE_FIXED_POINT
-#undef CONFIG_MODULE_VECT2
-#undef CONFIG_MODULE_GEOMETRY
-#undef CONFIG_MODULE_HOSTSIM
-#define CONFIG_MODULE_SCHEDULER 1
-#define CONFIG_MODULE_SCHEDULER_STATS 1
-#define CONFIG_MODULE_SCHEDULER_CREATE_CONFIG 1
-#undef CONFIG_MODULE_SCHEDULER_USE_TIMERS
-#undef CONFIG_MODULE_SCHEDULER_TIMER0
-#define CONFIG_MODULE_SCHEDULER_MANUAL 1
-#define CONFIG_MODULE_TIME 1
-#define CONFIG_MODULE_TIME_CREATE_CONFIG 1
-#undef CONFIG_MODULE_TIME_EXT
-#undef CONFIG_MODULE_TIME_EXT_CREATE_CONFIG
-
-/*
- * Communication modules
- */
-#define CONFIG_MODULE_UART 1
-#undef CONFIG_MODULE_UART_9BITS
-#define CONFIG_MODULE_UART_CREATE_CONFIG 1
-#define CONFIG_MODULE_SPI 1
-#define CONFIG_MODULE_SPI_CREATE_CONFIG 1
-#define CONFIG_MODULE_I2C 1
-#define CONFIG_MODULE_I2C_MASTER 1
-#undef CONFIG_MODULE_I2C_MULTIMASTER
-#define CONFIG_MODULE_I2C_CREATE_CONFIG 1
-#undef CONFIG_MODULE_MF2_CLIENT
-#undef CONFIG_MODULE_MF2_CLIENT_USE_SCHEDULER
-#undef CONFIG_MODULE_MF2_CLIENT_CREATE_CONFIG
-#undef CONFIG_MODULE_MF2_SERVER
-#undef CONFIG_MODULE_MF2_SERVER_CREATE_CONFIG
-
-/*
- * Hardware modules
- */
-#define CONFIG_MODULE_TIMER 1
-#undef CONFIG_MODULE_TIMER_CREATE_CONFIG
-#undef CONFIG_MODULE_TIMER_DYNAMIC
-#undef CONFIG_MODULE_PWM
-#undef CONFIG_MODULE_PWM_CREATE_CONFIG
-#undef CONFIG_MODULE_PWM_NG
-#undef CONFIG_MODULE_ADC
-#undef CONFIG_MODULE_ADC_CREATE_CONFIG
-
-/*
- * IHM modules
- */
-#undef CONFIG_MODULE_MENU
-#define CONFIG_MODULE_VT100 1
-#define CONFIG_MODULE_RDLINE 1
-#define CONFIG_MODULE_RDLINE_CREATE_CONFIG 1
-#define CONFIG_MODULE_RDLINE_KILL_BUF 1
-#define CONFIG_MODULE_RDLINE_HISTORY 1
-#define CONFIG_MODULE_PARSE 1
-#undef CONFIG_MODULE_PARSE_NO_FLOAT
-
-/*
- * External devices modules
- */
-#undef CONFIG_MODULE_LCD
-#undef CONFIG_MODULE_LCD_CREATE_CONFIG
-#undef CONFIG_MODULE_MULTISERVO
-#undef CONFIG_MODULE_MULTISERVO_CREATE_CONFIG
-#undef CONFIG_MODULE_AX12
-#undef CONFIG_MODULE_AX12_CREATE_CONFIG
-
-/*
- * Brushless motor drivers (you should enable pwm modules to see all)
- */
-#undef CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL
-#undef CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_CREATE_CONFIG
-#undef CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE
-#undef CONFIG_MODULE_BRUSHLESS_3PHASE_DIGITAL_HALL_DOUBLE_CREATE_CONFIG
-
-/*
- * Encoders (you need comm/spi for encoders_spi)
- */
-#undef CONFIG_MODULE_ENCODERS_MICROB
-#undef CONFIG_MODULE_ENCODERS_MICROB_CREATE_CONFIG
-#undef CONFIG_MODULE_ENCODERS_EIRBOT
-#undef CONFIG_MODULE_ENCODERS_EIRBOT_CREATE_CONFIG
-#undef CONFIG_MODULE_ENCODERS_SPI
-#undef CONFIG_MODULE_ENCODERS_SPI_CREATE_CONFIG
-
-/*
- * Robot specific modules (fixed point lib may be needed)
- */
-#undef CONFIG_MODULE_ROBOT_SYSTEM
-#undef CONFIG_MODULE_ROBOT_SYSTEM_USE_F64
-#undef CONFIG_MODULE_ROBOT_SYSTEM_MOT_AND_EXT
-#undef CONFIG_MODULE_POSITION_MANAGER
-#undef CONFIG_MODULE_COMPENSATE_CENTRIFUGAL_FORCE
-#undef CONFIG_MODULE_TRAJECTORY_MANAGER
-#undef CONFIG_MODULE_BLOCKING_DETECTION_MANAGER
-#undef CONFIG_MODULE_OBSTACLE_AVOIDANCE
-#undef CONFIG_MODULE_OBSTACLE_AVOIDANCE_CREATE_CONFIG
-
-/*
- * Control system modules
- */
-#undef CONFIG_MODULE_CONTROL_SYSTEM_MANAGER
-#undef CONFIG_MODULE_PID
-#undef CONFIG_MODULE_PID_CREATE_CONFIG
-#undef CONFIG_MODULE_RAMP
-#undef CONFIG_MODULE_QUADRAMP
-#undef CONFIG_MODULE_QUADRAMP_DERIVATE
-#undef CONFIG_MODULE_BIQUAD
-
-/*
- * Radio devices
- */
-#undef CONFIG_MODULE_CC2420
-#undef CONFIG_MODULE_CC2420_CREATE_CONFIG
-
-/*
- * Crypto modules
- */
-#undef CONFIG_MODULE_AES
-#undef CONFIG_MODULE_AES_CTR
-#undef CONFIG_MODULE_MD5
-#undef CONFIG_MODULE_MD5_HMAC
-#undef CONFIG_MODULE_RC4
-
-/*
- * Encodings modules
- */
-#undef CONFIG_MODULE_BASE64
-#undef CONFIG_MODULE_HAMMING
-
-/*
- * Debug modules
- */
-#define CONFIG_MODULE_DIAGNOSTIC 1
-#define CONFIG_MODULE_DIAGNOSTIC_CREATE_CONFIG 1
-#define CONFIG_MODULE_ERROR 1
-#define CONFIG_MODULE_ERROR_CREATE_CONFIG 1
-
-/*
- * Programmer options
- */
-#undef CONFIG_AVRDUDE
-#define CONFIG_AVARICE 1
-
-/*
- * Avrdude
- */
-#undef CONFIG_AVRDUDE_PROG_FUTURELEC
-#undef CONFIG_AVRDUDE_PROG_ABCMINI
-#undef CONFIG_AVRDUDE_PROG_PICOWEB
-#undef CONFIG_AVRDUDE_PROG_SP12
-#undef CONFIG_AVRDUDE_PROG_ALF
-#undef CONFIG_AVRDUDE_PROG_BASCOM
-#undef CONFIG_AVRDUDE_PROG_DT006
-#undef CONFIG_AVRDUDE_PROG_PONY_STK200
-#define CONFIG_AVRDUDE_PROG_STK200 1
-#undef CONFIG_AVRDUDE_PROG_PAVR
-#undef CONFIG_AVRDUDE_PROG_BUTTERFLY
-#undef CONFIG_AVRDUDE_PROG_AVR910
-#undef CONFIG_AVRDUDE_PROG_STK500
-#undef CONFIG_AVRDUDE_PROG_AVRISP
-#undef CONFIG_AVRDUDE_PROG_BSD
-#undef CONFIG_AVRDUDE_PROG_DAPA
-#undef CONFIG_AVRDUDE_PROG_JTAG1
-#undef CONFIG_AVRDUDE_PROG_AVR109
-#define CONFIG_AVRDUDE_PORT "/dev/parport0"
-#define CONFIG_AVRDUDE_BAUDRATE (19200)
-
-/*
- * Avarice
- */
-#define CONFIG_AVARICE_PORT "/dev/ttyUSB0"
-#define CONFIG_AVARICE_DEBUG_PORT (1234)
-#define CONFIG_AVARICE_PROG_MKI 1
-#undef CONFIG_AVARICE_PROG_MKII
-#define CONFIG_AVRDUDE_CHECK_SIGNATURE 1
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2007)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: aversive.h,v 1.1.2.6 2009-05-18 12:19:51 zer0 Exp $
- *
- */
-
-/**
- * here are some cute little macros, and other stuff, microcontroller
- * related !
- */
-
-
-#ifndef _AVERSIVE_H_
-#define _AVERSIVE_H_
-
-#include <autoconf.h>
-
-#ifndef HOST_VERSION
-#include <avr/interrupt.h>
-#include <avr/io.h>
-#endif
-
-#include <aversive/types.h>
-#include <aversive/errno.h>
-#include <aversive/irq_lock.h>
-
-
-#ifndef __AVR_LIBC_VERSION__ /* version.h should be included by avr/io.h */
-#define __AVR_LIBC_VERSION__ 0UL
-#endif
-
-#ifndef HOST_VERSION
-#if __AVR_LIBC_VERSION__ < 10403UL
-#include <avr/signal.h>
-#endif
-#endif
-
-//#define F_CPU ((unsigned long)CONFIG_QUARTZ)
-
-#define Hz 1l
-#define KHz 1000l
-#define MHz 1000000l
-
-
-
-/*
- * a few "mathematical" macros : maximums and minimums
- */
-
-/**
- * signed maxmimum : both signs are tested
- */
-#define S_MAX(to_saturate, value_max) \
-do { \
- if (to_saturate > value_max) \
- to_saturate = value_max; \
- else if (to_saturate < -value_max) \
- to_saturate = -value_max; \
- } while(0)
-
-/**
- * unsigned maximum : result >0 is forced
- */
-#define U_MAX(to_saturate, value_max) \
-do { \
- if (to_saturate > value_max) \
- to_saturate = value_max; \
- else if (to_saturate < 0) \
- to_saturate = 0; \
- } while(0)
-
-/**
- * simple maximum
- */
-
-
-
-/** absolute
- * while the abs() function in the libc works only with int type
- * this macro works with every numerical type including floats
- */
-#define ABS(val) ({ \
- __typeof(val) __val = (val); \
- if (__val < 0) \
- __val = - __val; \
- __val; \
- })
-
-/*
- * Extract bytes and u16 from larger integer
- */
-
-#if __BYTE_ORDER != __LITTLE_ENDIAN && __BYTE_ORDER != __BIG_ENDIAN
-# error "Endianness not defined"
-#endif
-
-struct extract32 {
- union {
- struct {
-#if __BYTE_ORDER == __LITTLE_ENDIAN
- uint8_t u8_0;
- uint8_t u8_1;
- uint8_t u8_2;
- uint8_t u8_3;
-#elif __BYTE_ORDER == __BIG_ENDIAN
- uint8_t u8_3;
- uint8_t u8_2;
- uint8_t u8_1;
- uint8_t u8_0;
-#endif
- } __attribute__ ((packed)) u8;
- struct {
-#if __BYTE_ORDER == __LITTLE_ENDIAN
- uint16_t u16_0;
- uint16_t u16_1;
-#elif __BYTE_ORDER == __BIG_ENDIAN
- uint16_t u16_1;
- uint16_t u16_0;
-#endif
- } __attribute__ ((packed)) u16;
- struct {
-#if __BYTE_ORDER == __LITTLE_ENDIAN
- uint8_t u8_0;
- uint16_t u16_mid;
- uint8_t u8_3;
-#elif __BYTE_ORDER == __BIG_ENDIAN
- uint8_t u8_3;
- uint16_t u16_mid;
- uint8_t u8_0;
-#endif
- } __attribute__ ((packed)) u16_b;
- uint32_t u32;
- } __attribute__ ((packed)) u;
-} __attribute__ ((packed));
-
-#define extr32_08_0(i) ({ struct extract32 __x; __x.u.u32 = i; __x.u.u8.u8_0; })
-#define extr32_08_1(i) ({ struct extract32 __x; __x.u.u32 = i; __x.u.u8.u8_1; })
-#define extr32_08_2(i) ({ struct extract32 __x; __x.u.u32 = i; __x.u.u8.u8_2; })
-#define extr32_08_3(i) ({ struct extract32 __x; __x.u.u32 = i; __x.u.u8.u8_3; })
-
-#define extr32_16_0(i) ({ struct extract32 __x; __x.u.u32 = i; __x.u.u16.u16_0; })
-#define extr32_16_1(i) ({ struct extract32 __x; __x.u.u32 = i; __x.u.u16.u16_1; })
-#define extr32_16_mid(i) ({ struct extract32 __x; __x.u.u32 = i; __x.u.u16_b.u16_mid; })
-
-
-struct extract16 {
- union {
- struct {
-#if __BYTE_ORDER == __LITTLE_ENDIAN
- uint8_t u8_0;
- uint8_t u8_1;
-#elif __BYTE_ORDER == __BIG_ENDIAN
- uint8_t u8_1;
- uint8_t u8_0;
-#endif
- } __attribute__ ((packed)) u8;
- uint16_t u16;
- } __attribute__ ((packed)) u;
-} __attribute__ ((packed));
-
-#define extr16_08_0(i) ({ struct extract16 __x; __x.u.u16 = i; __x.u.u8.u8_0; })
-#define extr16_08_1(i) ({ struct extract16 __x; __x.u.u16 = i; __x.u.u8.u8_1; })
-
-
-
-/* a few asm utilities */
-
-#ifndef HOST_VERSION
-#ifndef nop
-#define nop() __asm__ __volatile__ ("NOP\n") /** nop instruction, 1 CPU cycle consumed */
-#endif
-#ifndef nothing
-#define nothing() __asm__ __volatile__ (" \n") /** nothing */
-#endif
-#ifndef cli
-#define cli() __asm__ __volatile__ ("CLI\n") /** disable interrupts */
-#endif
-#ifndef sei
-#define sei() __asm__ __volatile__ ("SEI\n") /** enable interrupts */
-#endif
-/** simple software reset, but doesn't initialize the registers */
-#ifndef reset
-#define reset() \
-do { \
- __asm__ __volatile__ ("ldi r30,0\n"); \
- __asm__ __volatile__ ("ldi r31,0\n"); \
- __asm__ __volatile__ ("ijmp\n"); \
-} while(0)
-#endif
-
-#else /* HOST_VERSION */
-#define nop() do {} while(0)
-#define nothing() do {} while(0)
-#define cli() do {} while(0)
-#define sei() do {} while(0)
-#define reset() exit(1)
-#endif /* HOST_VERSION */
-
-/**
- * little bit toggeling macro
- *
- * change pin state
- * usage :
- * BIT_TOGGLE(PORTB,2) to make the pin 2 of PORTB toggle
- */
-#define BIT_TOGGLE(port,bit) do {\
- if(bit_is_set(PIN(port),bit)) \
- cbi(port,bit); \
- else \
- sbi(port,bit); \
- } while(0)
-
-
-/** booleans */
-
-
-/** DDR and PINS from port adress */
-#define DDR(port) (*(&(port) -1))
-#define PIN(port) (*(&(port) -2))
-
-/** open collector simulation macros */
-#define OPEN_CO_INIT(port, bit) sbi(port,bit)
-#define OPEN_CO_HIGH(port, bit) cbi(DDR(port),bit)
-#define OPEN_CO_LOW(port, bit) cbi(DDR(port),bit)
-
-/** deprecated macros in libc, but they're almost used, so we implement them again ;) */
-#ifndef cbi
-#define cbi(sfr, bit) ( sfr &= ~ _BV(bit))
-#endif
-#ifndef sbi
-#define sbi(sfr, bit) ( sfr |= _BV(bit))
-#endif
-
-
-#endif /* ifndef _AVERSIVE_H_ */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: eeprom.h,v 1.1.2.4 2007-11-21 21:54:38 zer0 Exp $
- *
- */
-
-/**
- * This file is used for compatibility between host and avr : with
- * this we can emulate eeprom on a host.
- */
-
-#ifndef _AVERSIVE_EEPROM_H_
-#define _AVERSIVE_EEPROM_H_
-
-#ifndef HOST_VERSION
-
-#include <avr/eeprom.h>
-
-#else
-
-/* XXX */
-
-#endif /* HOST_VERSION */
-#endif /* _AVERSIVE_EEPROM_H_ */
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation (2011)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: md5c.c,v 1.3.4.1 2006-11-26 21:06:02 zer0 Exp $
- *
- */
-
-#ifndef _AVERSIVE_ENDIAN_H_
-#define _AVERSIVE_ENDIAN_H_
-
-static inline uint16_t bswap16(uint16_t x)
-{
- return (uint16_t)(((x & 0x00ffU) << 8) |
- ((x & 0xff00U) >> 8));
-}
-
-static inline uint32_t bswap32(uint32_t x)
-{
- return ((x & 0x000000ffUL) << 24) |
- ((x & 0x0000ff00UL) << 8) |
- ((x & 0x00ff0000UL) >> 8) |
- ((x & 0xff000000UL) >> 24);
-}
-
-static inline uint64_t bswap64(uint64_t x)
-{
- return ((x & 0x00000000000000ffULL) << 56) |
- ((x & 0x000000000000ff00ULL) << 40) |
- ((x & 0x0000000000ff0000ULL) << 24) |
- ((x & 0x00000000ff000000ULL) << 8) |
- ((x & 0x000000ff00000000ULL) >> 8) |
- ((x & 0x0000ff0000000000ULL) >> 24) |
- ((x & 0x00ff000000000000ULL) >> 40) |
- ((x & 0xff00000000000000ULL) >> 56);
-}
-
-#if BYTE_ORDER == LITTLE_ENDIAN
-#define ntohs(x) bswap16(x)
-#define ntohl(x) bswap32(x)
-#define ntohll(x) bswap64(x)
-#else
-#define ntohs(x) (x)
-#define ntohl(x) (x)
-#define ntohll(x) (x)
-#endif
-
-#define htons ntohs
-#define htonl ntohl
-#define htonll ntohll
-
-#endif
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: errno.h,v 1.1.2.2 2009-01-23 23:05:39 zer0 Exp $
- *
- */
-
-/* This file contains general errors that can be returned from functions
- * We have to be carreful and try to return these error as often as possible
- * isntead of a function-specific value
- */
-
-#ifndef _AVERSIVE_ERRNO_H_
-#define _AVERSIVE_ERRNO_H_
-
-/** No error */
-#define ESUCCESS 0
-
-#ifndef HOST_VERSION
-
-/* from avr-libc, does not define a lots of errors */
-#include <errno.h>
-
-/** Operation not permitted */
-#define EPERM 1
-/** No such file or directory */
-#define ENOENT 2
-/** I/O error */
-#define EIO 5
-/** No such device or address */
-#define ENXIO 6
-/** Argument list too long */
-#define E2BIG 7
-/** Try again */
-#define EAGAIN 11
-/** Out of memory */
-#define ENOMEM 12
-/** Bad address */
-#define EFAULT 14
-/** Device or resource busy */
-#define EBUSY 16
-/** Invalid argument */
-#define EINVAL 22
-/** Domain error */
-/* #define EDOM 33 */ /* in libc */
-/** Range error */
-/* #define ERANGE 34 */ /* in libc */
-/** Not supported */
-#define ENOTSUP 126 /* the correct number is 128 */
-/** Unkwow error */
-#define EUNKNOW 127
-
-/* must not be > 127 because it can be stored on an int8_t */
-
-#else /* HOST_VERSION */
-#include <sys/errno.h>
-
-#endif /* HOST_VERSION */
-
-#endif /* AVERSIVE_ERRNO_H_ */
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: error.h,v 1.1.2.2 2007-06-01 09:37:22 zer0 Exp $
- *
- */
-
-#ifndef _AVERSIVE_ERROR_H_
-#define _AVERSIVE_ERROR_H_
-
-#include <autoconf.h>
-
-#ifdef CONFIG_MODULE_ERROR
-#include <error.h>
-#else
-
-#define EMERG(num, text...) do {} while(0)
-
-#define ERROR(num, text...) do {} while(0)
-
-#define WARNING(num, text...) do {} while(0)
-
-#define NOTICE(num, text...) do {} while(0)
-
-#define DEBUG(num, text...) do {} while(0)
-
-#endif
-#endif
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: irq_lock.h,v 1.1.2.1 2007-05-23 17:18:09 zer0 Exp $
- *
- */
-
-/** \file modules/base/utils/irq_lock_macros.h
- * \brief Interface of the utils module
- *
- * here are defined the three macros :
- *
- * IRQ_LOCK(flags); this saves interrupt state
- * IRQ_UNLOCK(flags); this restores interrupt state
- *
- * code example follows:
- *
- * uint8_t flags;
- * IRQ_LOCK(flags);
- * // code to be protected against interrupts ...
- * IRQ_UNLOCK(flags); // needs to be associated with an unlock
- *
- */
-
-
-#ifndef _AVERSIVE_IRQ_LOCK_H_
-#define _AVERSIVE_IRQ_LOCK_H_
-
-#ifdef HOST_VERSION
-
-#ifdef CONFIG_MODULE_HOSTSIM
-#include <hostsim.h>
-
-/* we must use 'flags' to avoid a warning */
-#define IRQ_UNLOCK(flags) do { flags=0; /* hostsim_lock(); */ } while(0)
-#define IRQ_LOCK(flags) do { flags=0; /* hostsim_unlock(); */ } while(0)
-#define GLOBAL_IRQ_ARE_MASKED() hostsim_islocked()
-#else
-#define IRQ_UNLOCK(flags) do { flags=0; } while(0)
-#define IRQ_LOCK(flags) do { flags=0; } while(0)
-#define GLOBAL_IRQ_ARE_MASKED() (0)
-#endif /* CONFIG_MODULE_HOSTSIM */
-
-#else
-
-#define GLOBAL_IRQ_ARE_MASKED() (!(bit_is_set(SREG,7)))
-
-#define IRQ_LOCK(flags) do { \
- flags = SREG; \
- cli(); \
- } while(0)
-
-#define IRQ_UNLOCK(flags) do { \
- SREG = flags; \
- } while ( 0 )
-
-#endif /* ! HOST_VERSION */
-
-#endif /* _AVERSIVE_IRQ_LOCK_H_ */
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: list.h,v 1.1.2.4 2007-08-19 10:35:45 zer0 Exp $
- *
- */
-
-/**
- * This header file provides LISTs implemented in tables. Don't use
- * list size > 127.
- *
- * WARNING ---------------------
- * This header file will probably be deprecated in a soon.
- * future. Consider using the 'cirbuf' module (circular buffer) instead.
- * Indeed, the full-macro implementation of this header file is not
- * the most efficient in terms of code size.... :)
- * WARNING ---------------------
- *
- *
- * Header
- * ------
- *
- * struct list_hdr {
- * u08 size; < The size of the fifo
- * u08 cur_size; < number of data in the fifo
- * u08 beg_indice; < indice of the first elt
- * u08 read_cursor; < read cursor
- * } __attribute__ ((packed));
- *
- *
- * ---------------------------------------------
- * I I I I I
- * I size IcursizeI beg I rcurs I elements ...
- * I I I I I
- * ---------------------------------------------
- *
- * <------------------------------->
- * list_hdr
- *
- *
- * Data
- * ----
- *
- * Data are stored in a circular buffer, beginning is specified by
- * beg_indice in header.
- *
- *
- * Type
- * ----
- *
- * For example, the type of a list of u08 with 10 elements is :
- *
- * struct list_u08_10 {
- * struct list_hdr hdr;
- * u08 elt[10];
- * }
- *
- * - With this example, an empty list is :
- * size = 10
- * cursize = 0
- * beg = X
- * curs = X
- *
- * - A full list :
- * size = 10
- * cursize = 10
- * beg = X
- * curs = X
- *
- *
- * Functions & Macros
- * ------------------
- *
- * ********** Define and init
- *
- * LIST_TYPE(typename, elttype, size) -> define type :
- *
- * #define LIST_TYPE(typename, elttype, size)
- * typedef struct typename {
- * struct list_hdr hdr;
- * elttype elt[size];
- * } typename;
- *
- * LIST_INIT(list, beginning) -> flushes the list, and set size and beginning
- *
- *
- * ********** Control
- *
- * u08 LIST_FULL(list)
- * u08 LIST_EMPTY(list)
- *
- * u08 LIST_READ_GOTO(*elt, list, i) -> place the read cursor at position i (0 means
- * the beginning of the list) and set the elt if
- * pointer not NULL
- *
- * u08 LIST_READ_LEFT(*elt, list, i) -> move the read cursor left by i
- * u08 LIST_READ_RIGHT(*elt, list, i) -> move the read cursor right by i
- * u08 LIST_READ_START(*elt, list)
- * u08 LIST_READ_END(*elt, list)
- *
- * Examples :
- *
- * size | cursize | beg | cursor | elt0 | elt1 | elt2 | elt3 | elt4 | elt5 |
- * 6 3 2 3 X X A B C X
- *
- *
- * we do LIST_READ_LEFT(NULL, x,x, 1) :
- *
- * size | cursize | beg | cursor | elt0 | elt1 | elt2 | elt3 | elt4 | elt5 |
- * 6 3 2 2 X X A B C X
- *
- *
- * we do LIST_READ_LEFT(NULL, x,x, 1), but return 1 instead of 0 because we
- * overwrapped :
- *
- * size | cursize | beg | cursor | elt0 | elt1 | elt2 | elt3 | elt4 | elt5 |
- * 6 3 4 4 X X A B C X
- *
- *
- * we do LIST_READ_GOTO(NULL, x,x, 0) :
- *
- * size | cursize | beg | cursor | elt0 | elt1 | elt2 | elt3 | elt4 | elt5 |
- * 6 3 4 2 X X A B C X
- *
- *
- *
- * ********** accesses modifying the list
- *
- * u08 LIST_PUSH_START(elt, list) -> add at the beginning (prepend)
- * u08 LIST_PUSH_END(elt, list) -> add at the end (append)
- * u08 LIST_PULL_START(elt *, list) -> del at the beginning
- * u08 LIST_PULL_END(elt *, list) -> del at the end
- *
- * u08 LIST_ARRAY_PUSH_START(*elt, list, n) -> prepend n elts
- * from elt pointer
- * u08 LIST_ARRAY_PUSH_END(*elt, list, n) -> append n elts
- * u08 LIST_ARRAY_PULL_START(elt *, list, n) -> del n elts from buffer
- * u08 LIST_ARRAY_PULL_END(elt *, list, n) -> del at the end
- *
- * Examples :
- *
- * size | cursize | beg | cursor | elt0 | elt1 | elt2 | elt3 | elt4 | elt5 |
- * 6 4 2 3 X X B C D E
- *
- *
- * we do LIST_PUSH_START(A, l, u08) :
- *
- * size | cursize | beg | cursor | elt0 | elt1 | elt2 | elt3 | elt4 | elt5 |
- * 6 5 1 3 X A B C D E
- *
- *
- * we do LIST_PUSH_END(F, l, u08) :
- *
- * size | cursize | beg | cursor | elt0 | elt1 | elt2 | elt3 | elt4 | elt5 |
- * 6 6 1 3 F A B C D E
- *
- * we do LIST_PUSH_END(X, l, u08) -> return -1
- *
- *
- *
- * ********** Accesses NOT modifying the list
- *
- * u08 LIST_FIRST(elt *, list) -> Return the first elt
- * u08 LIST_LAST(elt *, list) -> Return the last elt
- *
- * u08 LIST_READ(elt *, list) -> Return the elt pointed by
- * the read cursor
- *
- * u08 LIST_ARRAY_READ(elt *, list, n) -> reads n elts from read cursor
- *
- * u08 LIST_READ_GET_PTR(list) -> return a pointer to the read
- * cursor. Warning, perhaps you need to do LIST_ALIGN_XXXX() before
- *
- * ********** loop functions
- *
- * #define LIST_FOREACH(list, elt)
- * for( u08 ret = LIST_READ_START(elt, list) ;
- * ret == 0 ;
- * ret = LIST_READ_RIGHT(*elt, list, 1) )
- *
- *
- * ********** Alignement functions
- *
- * these functions can by quite long to execute. If possible, try to
- * avoid using them by choosing a good place for the beg_indice when
- * calling init of list. If you need it, prefer using
- * LIST_ALIGN_CONTINUOUS if possible.
- *
- * u08 LIST_ALIGN_LEFT(list)
- * u08 LIST_ALIGN_RIGHT(list)
- * u08 LIST_ALIGN_CONTINUOUS(list) -> just try to put data in a
- * countinuous memory region in
- * minimum operations.
- *
- * Example :
- *
- * size | cursize | beg | cursor | elt0 | elt1 | elt2 | elt3 | elt4 | elt5 |
- * 6 4 3 4 D X X A B C
- *
- *
- * we do LIST_ALIGN_LEFT(list) :
- *
- * size | cursize | beg | cursor | elt0 | elt1 | elt2 | elt3 | elt4 | elt5 |
- * 6 4 0 1 A B C D X X
- *
- * we do LIST_ALIGN_RIGHT(list) :
- *
- * size | cursize | beg | cursor | elt0 | elt1 | elt2 | elt3 | elt4 | elt5 |
- * 6 4 2 3 X X A B C D
- *
- *
- * With these functions, you can easily imagine a network stack,
- * prepending headers to data, without copying the buffer multiple times.
- *
- * Example :
- *
- * LIST_INIT(mylist, 5)
- * size | cursize | beg | cursor | elt0 | elt1 | elt2 | elt3 | elt4 | elt5 |
- * 6 0 5 5 X X X X X X
- *
- * LIST_ARRAY_PUSH_START("DATA", mylist, u08, strlen("DATA"))
- * size | cursize | beg | cursor | elt0 | elt1 | elt2 | elt3 | elt4 | elt5 |
- * 6 4 2 5 X X D A T A
- *
- * LIST_PUSH_START('H', mylist, u08) (push header)
- * size | cursize | beg | cursor | elt0 | elt1 | elt2 | elt3 | elt4 | elt5 |
- * 6 5 1 5 X H D A T A
- *
- * LIST_PUSH_START('H', mylist, u08) (push another header)
- * size | cursize | beg | cursor | elt0 | elt1 | elt2 | elt3 | elt4 | elt5 |
- * 6 6 0 5 H H D A T A
- *
- */
-
-
-#ifndef _AVERSIVE_LIST_H_
-#define _AVERSIVE_LIST_H_
-
-#ifndef LIST_DEBUG
-#define LIST_DEBUG 0
-#endif
-
-#include <stdio.h>
-
-#define WOVERWRAPPED -1
-
-#ifdef HOST_VERSION
-#define CR "\n"
-#else
-#define CR "\r\n"
-#endif
-
-#include <aversive.h>
-
-/**
- * This structure is the header of a list type.
- */
-struct list_hdr {
- uint8_t size; /**< The size of the list (number of elements) */
- uint8_t cur_size; /**< number of data in the list */
- uint8_t beg_indice; /**< indice of the first elt */
- int8_t read_cursor; /**< read cursor */
-} __attribute__ ((packed));
-
-/**
- * This is a generic kind of list, in which we suppose that elements
- * are char
-*/
-struct generic_list {
- struct list_hdr hdr;
- char elt[0];
-} __attribute__ ((packed));
-
-
-/**
- * Define a new list type
- */
-#define LIST_TYPEDEF(typename, elttype, size) \
-typedef struct typename { \
- struct list_hdr hdr; \
- elttype elt[size]; \
-} typename;
-
-#define LIST_INIT(list, beginning) \
-do { \
- list.hdr.size = sizeof(list.elt)/sizeof(list.elt[0]); \
- list.hdr.cur_size = 0; \
- list.hdr.beg_indice = beginning; \
- list.hdr.read_cursor = beginning; \
-} while(0)
-
-
-/**
- * Return 1 if the list is full
- */
-#define LIST_FULL(list) (list.hdr.size == list.hdr.cur_size)
-
-/**
- * Return 1 if the list is empty
- */
-#define LIST_EMPTY(list) (list.hdr.cur_size == 0)
-
-/**
- * return current size of the list (number of used elements)
- */
-#define LIST_CURSIZE(list) (list.hdr.cur_size)
-
-/**
- * return size of the list (used + free elements)
- */
-#define LIST_SIZE(list) (list.hdr.size)
-
-/**
- * return the number of free elts
- */
-#define LIST_FREESIZE(list) (list.hdr.size-list.hdr.cur_size)
-
-
-
-#define LIST_READ_START(list, elt_p) ({ \
- uint8_t __ret=0; \
- list.hdr.read_cursor = 0 ; \
- *elt_p = list.elt[list.hdr.beg_indice] ; \
- if(LIST_DEBUG) \
- printf("LIST_READ_START(%s, %s) -> ret %d"CR,#list, #elt_p, __ret); \
- __ret; \
-})
-
-#define LIST_READ_END(list, elt_p) ({ \
- uint8_t __ret=0; \
- list.hdr.read_cursor = list.hdr.cur_size-1; \
- *elt_p = list.elt[(list.hdr.beg_indice-1+list.hdr.cur_size) % list.hdr.size] ; \
- if(LIST_DEBUG) \
- printf("LIST_READ_END(%s, %s) -> ret %d"CR,#list, #elt_p, __ret); \
- __ret; \
-})
-
-
-#define LIST_READ_GOTO(list, elt_p, i) ({ \
- uint8_t __ret=0; \
- if( (i<0) || (i>=list.hdr.cur_size) ) \
- __ret = EINVAL; \
- else { \
- list.hdr.read_cursor = i; \
- *elt_p = list.elt[(list.hdr.beg_indice+i) % list.hdr.size] ; \
- } \
- if(LIST_DEBUG) \
- printf("LIST_READ_GOTO(%s, %s, %d) -> ret %d"CR,#list, #elt_p, i, __ret); \
- __ret; \
-})
-
-#define LIST_READ_MOVE(list, elt_p, i) ({\
-uint8_t __ret=0; \
- if (i<0) { \
- if( (-i) > list.hdr.read_cursor ) \
- __ret = WOVERWRAPPED ; \
- list.hdr.read_cursor -= ((-i) % list.hdr.cur_size) ; \
- if (list.hdr.read_cursor < 0) \
- list.hdr.read_cursor += list.hdr.cur_size ; \
- } \
- else { \
- if( i >= list.hdr.cur_size - list.hdr.read_cursor ) \
- __ret = WOVERWRAPPED ; \
- list.hdr.read_cursor += (i % list.hdr.cur_size) ; \
- if (list.hdr.read_cursor >= list.hdr.cur_size) \
- list.hdr.read_cursor -= list.hdr.cur_size ; \
- } \
- if(LIST_DEBUG) \
- printf("LIST_READ_MOVE(%s, %s, %d) -> ret %d"CR,#list, #elt_p, i, __ret); \
- *elt_p = list.elt[(list.hdr.beg_indice+list.hdr.read_cursor) % list.hdr.size] ; \
- __ret; \
-})
-
-#define LIST_READ(list, elt_p) ({\
- *elt_p = list.elt[(list.hdr.beg_indice+list.hdr.read_cursor) % list.hdr.size] ; \
- 0; \
-})
-
-#define LIST_PUSH_START(list, e) ({ \
- uint8_t __ret=0; \
- if( LIST_FULL(list) ) \
- __ret=EINVAL; \
- else { \
- list.hdr.beg_indice = (list.hdr.beg_indice-1+list.hdr.size) % list.hdr.size; \
- list.elt [ list.hdr.beg_indice ] = e ; \
- list.hdr.cur_size ++ ; \
- } \
-if(LIST_DEBUG) \
- printf("LIST_PUSH_START(%s, %s) -> ret %d"CR,#list, #e, __ret); \
- __ret; \
-})
-
-#define LIST_PUSH_END(list, e) ({ \
- uint8_t __ret=0; \
- if( LIST_FULL(list) ) \
- __ret=EINVAL; \
- else { \
- list.elt [ (list.hdr.beg_indice+list.hdr.cur_size) % list.hdr.size ] = e ; \
- list.hdr.cur_size ++ ; \
- } \
-if(LIST_DEBUG) \
- printf("LIST_PUSH_END(%s, %s) -> ret %d"CR,#list, #e, __ret); \
- __ret; \
-})
-
-#define LIST_PULL_START(list, elt_p) ({ \
- uint8_t __ret=0; \
- if( LIST_EMPTY(list) ) \
- __ret=EINVAL; \
- else { \
- *elt_p = list.elt [ list.hdr.beg_indice ] ; \
- list.hdr.beg_indice = (list.hdr.beg_indice+1) % list.hdr.size; \
- list.hdr.cur_size -- ; \
- } \
-if(LIST_DEBUG) \
- printf("LIST_PULL_START(%s, %s) -> ret %d"CR,#list, #elt_p, __ret); \
- __ret; \
-})
-
-#define LIST_PULL_END(list, elt_p) ({ \
- uint8_t __ret=0; \
- if( LIST_EMPTY(list) ) \
- __ret=EINVAL; \
- else { \
- *elt_p = list.elt [ (list.hdr.beg_indice-1+list.hdr.cur_size) % list.hdr.size ] ; \
- list.hdr.cur_size -- ; \
- } \
-if(LIST_DEBUG) \
- printf("LIST_PULL_END(%s, %s) -> ret %d"CR,#list, #elt_p, __ret); \
- __ret; \
-})
-
-/* start by the last elt */
-#define LIST_ARRAY_PUSH_START(list, array, nb) ({\
- uint8_t __ret=0; \
- int8_t __i; \
- for(__i=nb-1 ; (__i>=0) && (!__ret) ; __i--) { \
- __ret=LIST_PUSH_START(list, array[__i]); \
- } \
- if(LIST_DEBUG) \
- printf("LIST_ARRAY_PUSH_START(%s, %s, %d) -> ret %d"CR,#list, #array, nb, __ret); \
- __ret; \
-})
-
-#define LIST_ARRAY_PUSH_END(list, array, nb) ({\
- uint8_t __ret=0, __i; \
- for(__i=0 ; (__i<nb) && (!__ret) ; __i++) { \
- __ret=LIST_PUSH_END(list, array[__i]); \
- } \
- if(LIST_DEBUG) \
- printf("LIST_ARRAY_PUSH_END(%s, %s, %d) -> ret %d"CR,#list, #array, nb, __ret); \
- __ret; \
-})
-
-#define LIST_ARRAY_PULL_START(list, array, nb) ({\
- uint8_t __ret=0, __i; \
- for(__i=0 ; (__i<nb) && (!__ret) ; __i++) { \
- __ret=LIST_PULL_START(list, (array+__i)); \
- } \
- if(LIST_DEBUG) \
- printf("LIST_ARRAY_PULL_START(%s, %s, %d) -> ret %d"CR,#list, #array, nb, __ret); \
- __ret; \
-})
-
-#define LIST_ARRAY_PULL_END(list, array, nb) ({\
- uint8_t __ret=0; \
- int8_t __i; \
- for(__i=nb-1 ; (__i>=0) && (!__ret) ; __i--) { \
- __ret=LIST_PULL_END(list, (array+__i)); \
- } \
- if(LIST_DEBUG) \
- printf("LIST_ARRAY_PULL_END(%s, %s, %d) -> ret %d"CR,#list, #array, nb, __ret); \
- __ret; \
-})
-
-
-/* convert a list to an array, copy nb elts or less
- * if list is too small, return number of copied elts */
-#define LIST_TO_ARRAY(list, array, nb) ({\
- int8_t __i; \
- for(__i=0 ; __i<nb && __i<list.hdr.cur_size ; __i++) { \
- array[__i] = list.elt[(__i+list.hdr.beg_indice) % list.hdr.size]; \
- } \
- if(LIST_DEBUG) \
- printf("LIST_TO_ARRAY(%s, %s, %d) -> ret %d"CR,#list, #array, nb, __i); \
- __i; \
-})
-
-
-#define LIST_ALIGN_LEFT(list) ({ \
-uint8_t __ret=0, __i; \
-if(list.hdr.beg_indice != 0) { \
- if(list.hdr.beg_indice+list.hdr.cur_size <= list.hdr.size) { \
- for(__i=0 ; __i<list.hdr.cur_size ; __i++) { \
- list.elt[__i] = list.elt[__i+list.hdr.beg_indice]; \
- } \
- } \
- else { \
- uint8_t buffer_size=(list.hdr.size - list.hdr.beg_indice < (list.hdr.cur_size + list.hdr.beg_indice)%list.hdr.size) ? \
- (list.hdr.size - list.hdr.beg_indice) * sizeof(list.elt[0]) : \
- ((list.hdr.cur_size + list.hdr.beg_indice)%list.hdr.size) * sizeof(list.elt[0]); \
- { \
- uint8_t buffer[buffer_size]; \
- memcpy(buffer, list.elt, buffer_size); \
- for(__i=0 ; __i<(list.hdr.cur_size - buffer_size/sizeof(list.elt[0])) ; __i++) { \
- list.elt[__i] = list.elt[__i+list.hdr.beg_indice]; \
- } \
- memcpy(&list.elt[list.hdr.cur_size - buffer_size/sizeof(list.elt[0])], buffer, buffer_size); \
- } \
- } \
- list.hdr.beg_indice=0; \
-} \
- if(LIST_DEBUG) \
- printf("LIST_ALIGN_LEFT()"CR); \
- __ret; \
-})
-
-#endif /* _AVERSIVE_LIST_H_ */
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-#ifndef _AVERSIVE_PARTS_H_
-#define _AVERSIVE_PARTS_H_
-
-#if defined (__AVR_AT86RF401__)
-#include <aversive/parts/AT86RF401.h>
-#elif defined (__AVR_AT89S51__)
-#include <aversive/parts/AT89S51.h>
-#elif defined (__AVR_AT89S52__)
-#include <aversive/parts/AT89S52.h>
-#elif defined (__AVR_AT90CAN128__)
-#include <aversive/parts/AT90CAN128.h>
-#elif defined (__AVR_AT90CAN32__)
-#include <aversive/parts/AT90CAN32.h>
-#elif defined (__AVR_AT90CAN64__)
-#include <aversive/parts/AT90CAN64.h>
-#elif defined (__AVR_AT90PWM2__)
-#include <aversive/parts/AT90PWM2.h>
-#elif defined (__AVR_AT90PWM216__)
-#include <aversive/parts/AT90PWM216.h>
-#elif defined (__AVR_AT90PWM2B__)
-#include <aversive/parts/AT90PWM2B.h>
-#elif defined (__AVR_AT90PWM3__)
-#include <aversive/parts/AT90PWM3.h>
-#elif defined (__AVR_AT90PWM316__)
-#include <aversive/parts/AT90PWM316.h>
-#elif defined (__AVR_AT90PWM3B__)
-#include <aversive/parts/AT90PWM3B.h>
-#elif defined (__AVR_AT90S1200__)
-#include <aversive/parts/AT90S1200.h>
-#elif defined (__AVR_AT90S2313__)
-#include <aversive/parts/AT90S2313.h>
-#elif defined (__AVR_AT90S2323__)
-#include <aversive/parts/AT90S2323.h>
-#elif defined (__AVR_AT90S2343__)
-#include <aversive/parts/AT90S2343.h>
-#elif defined (__AVR_AT90S4414__)
-#include <aversive/parts/AT90S4414.h>
-#elif defined (__AVR_AT90S4433__)
-#include <aversive/parts/AT90S4433.h>
-#elif defined (__AVR_AT90S4434__)
-#include <aversive/parts/AT90S4434.h>
-#elif defined (__AVR_AT90S8515__)
-#include <aversive/parts/AT90S8515.h>
-#elif defined (__AVR_AT90S8515comp__)
-#include <aversive/parts/AT90S8515comp.h>
-#elif defined (__AVR_AT90S8535__)
-#include <aversive/parts/AT90S8535.h>
-#elif defined (__AVR_AT90S8535comp__)
-#include <aversive/parts/AT90S8535comp.h>
-#elif defined (__AVR_AT90USB1286__)
-#include <aversive/parts/AT90USB1286.h>
-#elif defined (__AVR_AT90USB1287__)
-#include <aversive/parts/AT90USB1287.h>
-#elif defined (__AVR_AT90USB162__)
-#include <aversive/parts/AT90USB162.h>
-#elif defined (__AVR_AT90USB646__)
-#include <aversive/parts/AT90USB646.h>
-#elif defined (__AVR_AT90USB647__)
-#include <aversive/parts/AT90USB647.h>
-#elif defined (__AVR_AT90USB82__)
-#include <aversive/parts/AT90USB82.h>
-#elif defined (__AVR_ATmega103__)
-#include <aversive/parts/ATmega103.h>
-#elif defined (__AVR_ATmega103comp__)
-#include <aversive/parts/ATmega103comp.h>
-#elif defined (__AVR_ATmega128__)
-#include <aversive/parts/ATmega128.h>
-#elif defined (__AVR_ATmega1280__)
-#include <aversive/parts/ATmega1280.h>
-#elif defined (__AVR_ATmega1281__)
-#include <aversive/parts/ATmega1281.h>
-#elif defined (__AVR_ATmega1284P__)
-#include <aversive/parts/ATmega1284P.h>
-#elif defined (__AVR_ATmega128A__)
-#include <aversive/parts/ATmega128A.h>
-#elif defined (__AVR_ATmega16__)
-#include <aversive/parts/ATmega16.h>
-#elif defined (__AVR_ATmega161__)
-#include <aversive/parts/ATmega161.h>
-#elif defined (__AVR_ATmega161comp__)
-#include <aversive/parts/ATmega161comp.h>
-#elif defined (__AVR_ATmega162__)
-#include <aversive/parts/ATmega162.h>
-#elif defined (__AVR_ATmega163__)
-#include <aversive/parts/ATmega163.h>
-#elif defined (__AVR_ATmega164P__)
-#include <aversive/parts/ATmega164P.h>
-#elif defined (__AVR_ATmega165__)
-#include <aversive/parts/ATmega165.h>
-#elif defined (__AVR_ATmega165P__)
-#include <aversive/parts/ATmega165P.h>
-#elif defined (__AVR_ATmega168__)
-#include <aversive/parts/ATmega168.h>
-#elif defined (__AVR_ATmega168P__)
-#include <aversive/parts/ATmega168P.h>
-#elif defined (__AVR_ATmega168PA__)
-#include <aversive/parts/ATmega168PA.h>
-#elif defined (__AVR_ATmega169__)
-#include <aversive/parts/ATmega169.h>
-#elif defined (__AVR_ATmega169P__)
-#include <aversive/parts/ATmega169P.h>
-#elif defined (__AVR_ATmega16A__)
-#include <aversive/parts/ATmega16A.h>
-#elif defined (__AVR_ATmega16HVA__)
-#include <aversive/parts/ATmega16HVA.h>
-#elif defined (__AVR_ATmega16U4__)
-#include <aversive/parts/ATmega16U4.h>
-#elif defined (__AVR_ATmega2560__)
-#include <aversive/parts/ATmega2560.h>
-#elif defined (__AVR_ATmega2561__)
-#include <aversive/parts/ATmega2561.h>
-#elif defined (__AVR_ATmega32__)
-#include <aversive/parts/ATmega32.h>
-#elif defined (__AVR_ATmega323__)
-#include <aversive/parts/ATmega323.h>
-#elif defined (__AVR_ATmega324P__)
-#include <aversive/parts/ATmega324P.h>
-#elif defined (__AVR_ATmega324PA__)
-#include <aversive/parts/ATmega324PA.h>
-#elif defined (__AVR_ATmega325__)
-#include <aversive/parts/ATmega325.h>
-#elif defined (__AVR_ATmega3250__)
-#include <aversive/parts/ATmega3250.h>
-#elif defined (__AVR_ATmega3250P__)
-#include <aversive/parts/ATmega3250P.h>
-#elif defined (__AVR_ATmega325P__)
-#include <aversive/parts/ATmega325P.h>
-#elif defined (__AVR_ATmega328P__)
-#include <aversive/parts/ATmega328P.h>
-#elif defined (__AVR_ATmega329__)
-#include <aversive/parts/ATmega329.h>
-#elif defined (__AVR_ATmega3290__)
-#include <aversive/parts/ATmega3290.h>
-#elif defined (__AVR_ATmega3290P__)
-#include <aversive/parts/ATmega3290P.h>
-#elif defined (__AVR_ATmega329P__)
-#include <aversive/parts/ATmega329P.h>
-#elif defined (__AVR_ATmega32A__)
-#include <aversive/parts/ATmega32A.h>
-#elif defined (__AVR_ATmega32C1__)
-#include <aversive/parts/ATmega32C1.h>
-#elif defined (__AVR_ATmega32HVB__)
-#include <aversive/parts/ATmega32HVB.h>
-#elif defined (__AVR_ATmega32M1__)
-#include <aversive/parts/ATmega32M1.h>
-#elif defined (__AVR_ATmega32U4__)
-#include <aversive/parts/ATmega32U4.h>
-#elif defined (__AVR_ATmega32U6__)
-#include <aversive/parts/ATmega32U6.h>
-#elif defined (__AVR_ATmega406__)
-#include <aversive/parts/ATmega406.h>
-#elif defined (__AVR_ATmega48__)
-#include <aversive/parts/ATmega48.h>
-#elif defined (__AVR_ATmega48P__)
-#include <aversive/parts/ATmega48P.h>
-#elif defined (__AVR_ATmega64__)
-#include <aversive/parts/ATmega64.h>
-#elif defined (__AVR_ATmega640__)
-#include <aversive/parts/ATmega640.h>
-#elif defined (__AVR_ATmega644__)
-#include <aversive/parts/ATmega644.h>
-#elif defined (__AVR_ATmega644P__)
-#include <aversive/parts/ATmega644P.h>
-#elif defined (__AVR_ATmega645__)
-#include <aversive/parts/ATmega645.h>
-#elif defined (__AVR_ATmega6450__)
-#include <aversive/parts/ATmega6450.h>
-#elif defined (__AVR_ATmega649__)
-#include <aversive/parts/ATmega649.h>
-#elif defined (__AVR_ATmega6490__)
-#include <aversive/parts/ATmega6490.h>
-#elif defined (__AVR_ATmega64A__)
-#include <aversive/parts/ATmega64A.h>
-#elif defined (__AVR_ATmega8__)
-#include <aversive/parts/ATmega8.h>
-#elif defined (__AVR_ATmega8515__)
-#include <aversive/parts/ATmega8515.h>
-#elif defined (__AVR_ATmega8535__)
-#include <aversive/parts/ATmega8535.h>
-#elif defined (__AVR_ATmega88__)
-#include <aversive/parts/ATmega88.h>
-#elif defined (__AVR_ATmega88P__)
-#include <aversive/parts/ATmega88P.h>
-#elif defined (__AVR_ATmega88PA__)
-#include <aversive/parts/ATmega88PA.h>
-#elif defined (__AVR_ATmega8A__)
-#include <aversive/parts/ATmega8A.h>
-#elif defined (__AVR_ATtiny10__)
-#include <aversive/parts/ATtiny10.h>
-#elif defined (__AVR_ATtiny11__)
-#include <aversive/parts/ATtiny11.h>
-#elif defined (__AVR_ATtiny12__)
-#include <aversive/parts/ATtiny12.h>
-#elif defined (__AVR_ATtiny13__)
-#include <aversive/parts/ATtiny13.h>
-#elif defined (__AVR_ATtiny13A__)
-#include <aversive/parts/ATtiny13A.h>
-#elif defined (__AVR_ATtiny15__)
-#include <aversive/parts/ATtiny15.h>
-#elif defined (__AVR_ATtiny167__)
-#include <aversive/parts/ATtiny167.h>
-#elif defined (__AVR_ATtiny22__)
-#include <aversive/parts/ATtiny22.h>
-#elif defined (__AVR_ATtiny2313__)
-#include <aversive/parts/ATtiny2313.h>
-#elif defined (__AVR_ATtiny24__)
-#include <aversive/parts/ATtiny24.h>
-#elif defined (__AVR_ATtiny25__)
-#include <aversive/parts/ATtiny25.h>
-#elif defined (__AVR_ATtiny26__)
-#include <aversive/parts/ATtiny26.h>
-#elif defined (__AVR_ATtiny261__)
-#include <aversive/parts/ATtiny261.h>
-#elif defined (__AVR_ATtiny28__)
-#include <aversive/parts/ATtiny28.h>
-#elif defined (__AVR_ATtiny43U__)
-#include <aversive/parts/ATtiny43U.h>
-#elif defined (__AVR_ATtiny44__)
-#include <aversive/parts/ATtiny44.h>
-#elif defined (__AVR_ATtiny45__)
-#include <aversive/parts/ATtiny45.h>
-#elif defined (__AVR_ATtiny461__)
-#include <aversive/parts/ATtiny461.h>
-#elif defined (__AVR_ATtiny48__)
-#include <aversive/parts/ATtiny48.h>
-#elif defined (__AVR_ATtiny84__)
-#include <aversive/parts/ATtiny84.h>
-#elif defined (__AVR_ATtiny85__)
-#include <aversive/parts/ATtiny85.h>
-#elif defined (__AVR_ATtiny861__)
-#include <aversive/parts/ATtiny861.h>
-#elif defined (__AVR_ATtiny88__)
-#include <aversive/parts/ATtiny88.h>
-#elif defined (__AVR_ATxmega128A1__)
-#include <aversive/parts/ATxmega128A1.h>
-#elif defined (__AVR_ATxmega128A3__)
-#include <aversive/parts/ATxmega128A3.h>
-#elif defined (__AVR_ATxmega256A3__)
-#include <aversive/parts/ATxmega256A3.h>
-#elif defined (__AVR_ATxmega256A3B__)
-#include <aversive/parts/ATxmega256A3B.h>
-#elif defined (__AVR_ATxmega64A1__)
-#include <aversive/parts/ATxmega64A1.h>
-#elif defined (__AVR_ATxmega64A3__)
-#include <aversive/parts/ATxmega64A3.h>
-#else
-#ifndef HOST_VERSION
-#error "This arch is not implemented yet"
-#endif
-#endif
-
-#if defined(TIMER0_OVF_vect) && !defined(SIG_OVERFLOW0)
-#define SIG_OVERFLOW0 TIMER0_OVF_vect
-#endif
-
-#if defined(TIMER1_OVF_vect) && !defined(SIG_OVERFLOW1)
-#define SIG_OVERFLOW1 TIMER1_OVF_vect
-#endif
-
-#if defined(TIMER2_OVF_vect) && !defined(SIG_OVERFLOW2)
-#define SIG_OVERFLOW2 TIMER2_OVF_vect
-#endif
-
-#if defined(TIMER3_OVF_vect) && !defined(SIG_OVERFLOW3)
-#define SIG_OVERFLOW3 TIMER3_OVF_vect
-#endif
-
-#if defined(TIMER4_OVF_vect) && !defined(SIG_OVERFLOW4)
-#define SIG_OVERFLOW4 TIMER4_OVF_vect
-#endif
-
-#if defined(TIMER5_OVF_vect) && !defined(SIG_OVERFLOW5)
-#define SIG_OVERFLOW5 TIMER5_OVF_vect
-#endif
-
-#endif /* _AVERSIVE_PARTS_H_ */
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-#ifndef _AVERSIVE_PARTS_H_
-#define _AVERSIVE_PARTS_H_
-
-#if defined (__AVR_AT86RF401__)
-#include <aversive/parts/AT86RF401.h>
-#elif defined (__AVR_AT89S51__)
-#include <aversive/parts/AT89S51.h>
-#elif defined (__AVR_AT89S52__)
-#include <aversive/parts/AT89S52.h>
-#elif defined (__AVR_AT90CAN128__)
-#include <aversive/parts/AT90CAN128.h>
-#elif defined (__AVR_AT90CAN32__)
-#include <aversive/parts/AT90CAN32.h>
-#elif defined (__AVR_AT90CAN64__)
-#include <aversive/parts/AT90CAN64.h>
-#elif defined (__AVR_AT90PWM2__)
-#include <aversive/parts/AT90PWM2.h>
-#elif defined (__AVR_AT90PWM216__)
-#include <aversive/parts/AT90PWM216.h>
-#elif defined (__AVR_AT90PWM2B__)
-#include <aversive/parts/AT90PWM2B.h>
-#elif defined (__AVR_AT90PWM3__)
-#include <aversive/parts/AT90PWM3.h>
-#elif defined (__AVR_AT90PWM316__)
-#include <aversive/parts/AT90PWM316.h>
-#elif defined (__AVR_AT90PWM3B__)
-#include <aversive/parts/AT90PWM3B.h>
-#elif defined (__AVR_AT90S1200__)
-#include <aversive/parts/AT90S1200.h>
-#elif defined (__AVR_AT90S2313__)
-#include <aversive/parts/AT90S2313.h>
-#elif defined (__AVR_AT90S2323__)
-#include <aversive/parts/AT90S2323.h>
-#elif defined (__AVR_AT90S2343__)
-#include <aversive/parts/AT90S2343.h>
-#elif defined (__AVR_AT90S4414__)
-#include <aversive/parts/AT90S4414.h>
-#elif defined (__AVR_AT90S4433__)
-#include <aversive/parts/AT90S4433.h>
-#elif defined (__AVR_AT90S4434__)
-#include <aversive/parts/AT90S4434.h>
-#elif defined (__AVR_AT90S8515__)
-#include <aversive/parts/AT90S8515.h>
-#elif defined (__AVR_AT90S8515comp__)
-#include <aversive/parts/AT90S8515comp.h>
-#elif defined (__AVR_AT90S8535__)
-#include <aversive/parts/AT90S8535.h>
-#elif defined (__AVR_AT90S8535comp__)
-#include <aversive/parts/AT90S8535comp.h>
-#elif defined (__AVR_AT90USB1286__)
-#include <aversive/parts/AT90USB1286.h>
-#elif defined (__AVR_AT90USB1287__)
-#include <aversive/parts/AT90USB1287.h>
-#elif defined (__AVR_AT90USB162__)
-#include <aversive/parts/AT90USB162.h>
-#elif defined (__AVR_AT90USB646__)
-#include <aversive/parts/AT90USB646.h>
-#elif defined (__AVR_AT90USB647__)
-#include <aversive/parts/AT90USB647.h>
-#elif defined (__AVR_AT90USB82__)
-#include <aversive/parts/AT90USB82.h>
-#elif defined (__AVR_ATmega103__)
-#include <aversive/parts/ATmega103.h>
-#elif defined (__AVR_ATmega103comp__)
-#include <aversive/parts/ATmega103comp.h>
-#elif defined (__AVR_ATmega128__)
-#include <aversive/parts/ATmega128.h>
-#elif defined (__AVR_ATmega1280__)
-#include <aversive/parts/ATmega1280.h>
-#elif defined (__AVR_ATmega1281__)
-#include <aversive/parts/ATmega1281.h>
-#elif defined (__AVR_ATmega1284P__)
-#include <aversive/parts/ATmega1284P.h>
-#elif defined (__AVR_ATmega128A__)
-#include <aversive/parts/ATmega128A.h>
-#elif defined (__AVR_ATmega16__)
-#include <aversive/parts/ATmega16.h>
-#elif defined (__AVR_ATmega161__)
-#include <aversive/parts/ATmega161.h>
-#elif defined (__AVR_ATmega161comp__)
-#include <aversive/parts/ATmega161comp.h>
-#elif defined (__AVR_ATmega162__)
-#include <aversive/parts/ATmega162.h>
-#elif defined (__AVR_ATmega163__)
-#include <aversive/parts/ATmega163.h>
-#elif defined (__AVR_ATmega164P__)
-#include <aversive/parts/ATmega164P.h>
-#elif defined (__AVR_ATmega165__)
-#include <aversive/parts/ATmega165.h>
-#elif defined (__AVR_ATmega165P__)
-#include <aversive/parts/ATmega165P.h>
-#elif defined (__AVR_ATmega168__)
-#include <aversive/parts/ATmega168.h>
-#elif defined (__AVR_ATmega168P__)
-#include <aversive/parts/ATmega168P.h>
-#elif defined (__AVR_ATmega168PA__)
-#include <aversive/parts/ATmega168PA.h>
-#elif defined (__AVR_ATmega169__)
-#include <aversive/parts/ATmega169.h>
-#elif defined (__AVR_ATmega169P__)
-#include <aversive/parts/ATmega169P.h>
-#elif defined (__AVR_ATmega16A__)
-#include <aversive/parts/ATmega16A.h>
-#elif defined (__AVR_ATmega16HVA__)
-#include <aversive/parts/ATmega16HVA.h>
-#elif defined (__AVR_ATmega16U4__)
-#include <aversive/parts/ATmega16U4.h>
-#elif defined (__AVR_ATmega2560__)
-#include <aversive/parts/ATmega2560.h>
-#elif defined (__AVR_ATmega2561__)
-#include <aversive/parts/ATmega2561.h>
-#elif defined (__AVR_ATmega32__)
-#include <aversive/parts/ATmega32.h>
-#elif defined (__AVR_ATmega323__)
-#include <aversive/parts/ATmega323.h>
-#elif defined (__AVR_ATmega324P__)
-#include <aversive/parts/ATmega324P.h>
-#elif defined (__AVR_ATmega324PA__)
-#include <aversive/parts/ATmega324PA.h>
-#elif defined (__AVR_ATmega325__)
-#include <aversive/parts/ATmega325.h>
-#elif defined (__AVR_ATmega3250__)
-#include <aversive/parts/ATmega3250.h>
-#elif defined (__AVR_ATmega3250P__)
-#include <aversive/parts/ATmega3250P.h>
-#elif defined (__AVR_ATmega325P__)
-#include <aversive/parts/ATmega325P.h>
-#elif defined (__AVR_ATmega328P__)
-#include <aversive/parts/ATmega328P.h>
-#elif defined (__AVR_ATmega329__)
-#include <aversive/parts/ATmega329.h>
-#elif defined (__AVR_ATmega3290__)
-#include <aversive/parts/ATmega3290.h>
-#elif defined (__AVR_ATmega3290P__)
-#include <aversive/parts/ATmega3290P.h>
-#elif defined (__AVR_ATmega329P__)
-#include <aversive/parts/ATmega329P.h>
-#elif defined (__AVR_ATmega32A__)
-#include <aversive/parts/ATmega32A.h>
-#elif defined (__AVR_ATmega32C1__)
-#include <aversive/parts/ATmega32C1.h>
-#elif defined (__AVR_ATmega32HVB__)
-#include <aversive/parts/ATmega32HVB.h>
-#elif defined (__AVR_ATmega32M1__)
-#include <aversive/parts/ATmega32M1.h>
-#elif defined (__AVR_ATmega32U4__)
-#include <aversive/parts/ATmega32U4.h>
-#elif defined (__AVR_ATmega32U6__)
-#include <aversive/parts/ATmega32U6.h>
-#elif defined (__AVR_ATmega406__)
-#include <aversive/parts/ATmega406.h>
-#elif defined (__AVR_ATmega48__)
-#include <aversive/parts/ATmega48.h>
-#elif defined (__AVR_ATmega48P__)
-#include <aversive/parts/ATmega48P.h>
-#elif defined (__AVR_ATmega64__)
-#include <aversive/parts/ATmega64.h>
-#elif defined (__AVR_ATmega640__)
-#include <aversive/parts/ATmega640.h>
-#elif defined (__AVR_ATmega644__)
-#include <aversive/parts/ATmega644.h>
-#elif defined (__AVR_ATmega644P__)
-#include <aversive/parts/ATmega644P.h>
-#elif defined (__AVR_ATmega645__)
-#include <aversive/parts/ATmega645.h>
-#elif defined (__AVR_ATmega6450__)
-#include <aversive/parts/ATmega6450.h>
-#elif defined (__AVR_ATmega649__)
-#include <aversive/parts/ATmega649.h>
-#elif defined (__AVR_ATmega6490__)
-#include <aversive/parts/ATmega6490.h>
-#elif defined (__AVR_ATmega64A__)
-#include <aversive/parts/ATmega64A.h>
-#elif defined (__AVR_ATmega8__)
-#include <aversive/parts/ATmega8.h>
-#elif defined (__AVR_ATmega8515__)
-#include <aversive/parts/ATmega8515.h>
-#elif defined (__AVR_ATmega8535__)
-#include <aversive/parts/ATmega8535.h>
-#elif defined (__AVR_ATmega88__)
-#include <aversive/parts/ATmega88.h>
-#elif defined (__AVR_ATmega88P__)
-#include <aversive/parts/ATmega88P.h>
-#elif defined (__AVR_ATmega88PA__)
-#include <aversive/parts/ATmega88PA.h>
-#elif defined (__AVR_ATmega8A__)
-#include <aversive/parts/ATmega8A.h>
-#elif defined (__AVR_ATtiny10__)
-#include <aversive/parts/ATtiny10.h>
-#elif defined (__AVR_ATtiny11__)
-#include <aversive/parts/ATtiny11.h>
-#elif defined (__AVR_ATtiny12__)
-#include <aversive/parts/ATtiny12.h>
-#elif defined (__AVR_ATtiny13__)
-#include <aversive/parts/ATtiny13.h>
-#elif defined (__AVR_ATtiny13A__)
-#include <aversive/parts/ATtiny13A.h>
-#elif defined (__AVR_ATtiny15__)
-#include <aversive/parts/ATtiny15.h>
-#elif defined (__AVR_ATtiny167__)
-#include <aversive/parts/ATtiny167.h>
-#elif defined (__AVR_ATtiny22__)
-#include <aversive/parts/ATtiny22.h>
-#elif defined (__AVR_ATtiny2313__)
-#include <aversive/parts/ATtiny2313.h>
-#elif defined (__AVR_ATtiny24__)
-#include <aversive/parts/ATtiny24.h>
-#elif defined (__AVR_ATtiny25__)
-#include <aversive/parts/ATtiny25.h>
-#elif defined (__AVR_ATtiny26__)
-#include <aversive/parts/ATtiny26.h>
-#elif defined (__AVR_ATtiny261__)
-#include <aversive/parts/ATtiny261.h>
-#elif defined (__AVR_ATtiny28__)
-#include <aversive/parts/ATtiny28.h>
-#elif defined (__AVR_ATtiny43U__)
-#include <aversive/parts/ATtiny43U.h>
-#elif defined (__AVR_ATtiny44__)
-#include <aversive/parts/ATtiny44.h>
-#elif defined (__AVR_ATtiny45__)
-#include <aversive/parts/ATtiny45.h>
-#elif defined (__AVR_ATtiny461__)
-#include <aversive/parts/ATtiny461.h>
-#elif defined (__AVR_ATtiny48__)
-#include <aversive/parts/ATtiny48.h>
-#elif defined (__AVR_ATtiny84__)
-#include <aversive/parts/ATtiny84.h>
-#elif defined (__AVR_ATtiny85__)
-#include <aversive/parts/ATtiny85.h>
-#elif defined (__AVR_ATtiny861__)
-#include <aversive/parts/ATtiny861.h>
-#elif defined (__AVR_ATtiny88__)
-#include <aversive/parts/ATtiny88.h>
-#elif defined (__AVR_ATxmega128A1__)
-#include <aversive/parts/ATxmega128A1.h>
-#elif defined (__AVR_ATxmega128A3__)
-#include <aversive/parts/ATxmega128A3.h>
-#elif defined (__AVR_ATxmega256A3__)
-#include <aversive/parts/ATxmega256A3.h>
-#elif defined (__AVR_ATxmega256A3B__)
-#include <aversive/parts/ATxmega256A3B.h>
-#elif defined (__AVR_ATxmega64A1__)
-#include <aversive/parts/ATxmega64A1.h>
-#elif defined (__AVR_ATxmega64A3__)
-#include <aversive/parts/ATxmega64A3.h>
-#else
-#ifndef HOST_VERSION
-#error "This arch is not implemented yet"
-#endif
-#endif
-
-#if defined(TIMER0_OVF_vect) && !defined(SIG_OVERFLOW0)
-#define SIG_OVERFLOW0 TIMER0_OVF_vect
-#endif
-
-#if defined(TIMER1_OVF_vect) && !defined(SIG_OVERFLOW1)
-#define SIG_OVERFLOW1 TIMER1_OVF_vect
-#endif
-
-#if defined(TIMER2_OVF_vect) && !defined(SIG_OVERFLOW2)
-#define SIG_OVERFLOW2 TIMER2_OVF_vect
-#endif
-
-#if defined(TIMER3_OVF_vect) && !defined(SIG_OVERFLOW3)
-#define SIG_OVERFLOW3 TIMER3_OVF_vect
-#endif
-
-#if defined(TIMER4_OVF_vect) && !defined(SIG_OVERFLOW4)
-#define SIG_OVERFLOW4 TIMER4_OVF_vect
-#endif
-
-#if defined(TIMER5_OVF_vect) && !defined(SIG_OVERFLOW5)
-#define SIG_OVERFLOW5 TIMER5_OVF_vect
-#endif
-
-#endif /* _AVERSIVE_PARTS_H_ */
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-
-
-
-/* available timers */
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW_TOTAL_NUM 0
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0
-
-/* Pwm nums */
-#define PWM_TOTAL_NUM 0
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 0
-
-
-/* VCOTUNE */
-#define VCOTUNE0_REG VCOTUNE
-#define VCOTUNE1_REG VCOTUNE
-#define VCOTUNE2_REG VCOTUNE
-#define VCOTUNE3_REG VCOTUNE
-#define VCOTUNE4_REG VCOTUNE
-#define VCOVDET0_REG VCOTUNE
-#define VCOVDET1_REG VCOTUNE
-
-/* BL_CONFIG */
-#define BL0_REG BL_CONFIG
-#define BL1_REG BL_CONFIG
-#define BL2_REG BL_CONFIG
-#define BL3_REG BL_CONFIG
-#define BL4_REG BL_CONFIG
-#define BL5_REG BL_CONFIG
-#define BLV_REG BL_CONFIG
-#define BL_REG BL_CONFIG
-
-/* DEEDR */
-#define ED0_REG DEEDR
-#define ED1_REG DEEDR
-#define ED2_REG DEEDR
-#define ED3_REG DEEDR
-#define ED4_REG DEEDR
-#define ED5_REG DEEDR
-#define ED6_REG DEEDR
-#define ED7_REG DEEDR
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDTOE_REG WDTCR
-
-/* DEEAR */
-#define BA0_REG DEEAR
-#define BA1_REG DEEAR
-#define BA2_REG DEEAR
-#define PA3_REG DEEAR
-#define PA4_REG DEEAR
-#define PA5_REG DEEAR
-#define PA6_REG DEEAR
-
-/* AVR_CONFIG */
-#define BBM_REG AVR_CONFIG
-#define SLEEP_REG AVR_CONFIG
-#define BLI_REG AVR_CONFIG
-#define BD_REG AVR_CONFIG
-#define TM_REG AVR_CONFIG
-#define ACS0_REG AVR_CONFIG
-#define ACS1_REG AVR_CONFIG
-
-/* B_DET */
-#define BD0_REG B_DET
-#define BD1_REG B_DET
-#define BD2_REG B_DET
-#define BD3_REG B_DET
-#define BD4_REG B_DET
-#define BD5_REG B_DET
-
-/* LOCKDET2 */
-#define LC0_REG LOCKDET2
-#define LC1_REG LOCKDET2
-#define LC2_REG LOCKDET2
-#define ULC0_REG LOCKDET2
-#define ULC1_REG LOCKDET2
-#define ULC2_REG LOCKDET2
-#define LAT_REG LOCKDET2
-#define EUD_REG LOCKDET2
-
-/* TX_CNTL */
-#define LOC_REG TX_CNTL
-#define TXK_REG TX_CNTL
-#define TXE_REG TX_CNTL
-#define FSK_REG TX_CNTL
-
-/* BTCNT */
-#define C0_REG BTCNT
-#define C1_REG BTCNT
-#define C2_REG BTCNT
-#define C3_REG BTCNT
-#define C4_REG BTCNT
-#define C5_REG BTCNT
-#define C6_REG BTCNT
-#define C7_REG BTCNT
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* BTCR */
-#define F0_REG BTCR
-#define DATA_REG BTCR
-#define F2_REG BTCR
-#define IE_REG BTCR
-#define M0_REG BTCR
-#define M1_REG BTCR
-#define C8_REG BTCR
-#define C9_REG BTCR
-
-/* IO_DATIN */
-#define IOI0_REG IO_DATIN
-#define IOI1_REG IO_DATIN
-#define IOI2_REG IO_DATIN
-#define IOI3_REG IO_DATIN
-#define IOI4_REG IO_DATIN
-#define IOI5_REG IO_DATIN
-
-/* IO_ENAB */
-#define IOE0_REG IO_ENAB
-#define IOE1_REG IO_ENAB
-#define IOE2_REG IO_ENAB
-#define IOE3_REG IO_ENAB
-#define IOE4_REG IO_ENAB
-#define IOE5_REG IO_ENAB
-
-/* LOCKDET1 */
-#define CS0_REG LOCKDET1
-#define CS1_REG LOCKDET1
-#define BOD_REG LOCKDET1
-#define ENKO_REG LOCKDET1
-#define UPOK_REG LOCKDET1
-
-/* IO_DATOUT */
-#define IOO0_REG IO_DATOUT
-#define IOO1_REG IO_DATOUT
-#define IOO2_REG IO_DATOUT
-#define IOO3_REG IO_DATOUT
-#define IOO4_REG IO_DATOUT
-#define IOO5_REG IO_DATOUT
-
-/* DEECR */
-#define EER_REG DEECR
-#define EEL_REG DEECR
-#define EEU_REG DEECR
-#define BSY_REG DEECR
-
-/* PWR_ATTEN */
-#define PCF0_REG PWR_ATTEN
-#define PCF1_REG PWR_ATTEN
-#define PCF2_REG PWR_ATTEN
-#define PCC0_REG PWR_ATTEN
-#define PCC1_REG PWR_ATTEN
-#define PCC2_REG PWR_ATTEN
-
-/* pins mapping */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-
-/* available timers */
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW_TOTAL_NUM 0
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0
-
-/* Pwm nums */
-#define PWM_TOTAL_NUM 0
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 0
-
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* pins mapping */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-
-/* available timers */
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW_TOTAL_NUM 0
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0
-
-/* Pwm nums */
-#define PWM_TOTAL_NUM 0
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 0
-
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* pins mapping */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-/* prescalers timer 3 */
-#define TIMER3_PRESCALER_DIV_0 0
-#define TIMER3_PRESCALER_DIV_1 1
-#define TIMER3_PRESCALER_DIV_8 2
-#define TIMER3_PRESCALER_DIV_64 3
-#define TIMER3_PRESCALER_DIV_256 4
-#define TIMER3_PRESCALER_DIV_1024 5
-#define TIMER3_PRESCALER_DIV_FALL 6
-#define TIMER3_PRESCALER_DIV_RISE 7
-
-#define TIMER3_PRESCALER_REG_0 0
-#define TIMER3_PRESCALER_REG_1 1
-#define TIMER3_PRESCALER_REG_2 8
-#define TIMER3_PRESCALER_REG_3 64
-#define TIMER3_PRESCALER_REG_4 256
-#define TIMER3_PRESCALER_REG_5 1024
-#define TIMER3_PRESCALER_REG_6 -1
-#define TIMER3_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER1C_AVAILABLE
-#define TIMER2_AVAILABLE
-#define TIMER3_AVAILABLE
-#define TIMER3A_AVAILABLE
-#define TIMER3B_AVAILABLE
-#define TIMER3C_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW3_NUM 3
-#define SIG_OVERFLOW_TOTAL_NUM 4
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE1A_NUM 1
-#define SIG_OUTPUT_COMPARE1B_NUM 2
-#define SIG_OUTPUT_COMPARE1C_NUM 3
-#define SIG_OUTPUT_COMPARE2_NUM 4
-#define SIG_OUTPUT_COMPARE3A_NUM 5
-#define SIG_OUTPUT_COMPARE3B_NUM 6
-#define SIG_OUTPUT_COMPARE3C_NUM 7
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 8
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM1A_NUM 1
-#define PWM1B_NUM 2
-#define PWM1C_NUM 3
-#define PWM2_NUM 4
-#define PWM3A_NUM 5
-#define PWM3B_NUM 6
-#define PWM3C_NUM 7
-#define PWM_TOTAL_NUM 8
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE3_NUM 1
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 2
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* RAMPZ */
-#define RAMPZ0_REG RAMPZ
-
-/* OCR2A */
-#define OCR2A0_REG OCR2A
-#define OCR2A1_REG OCR2A
-#define OCR2A2_REG OCR2A
-#define OCR2A3_REG OCR2A
-#define OCR2A4_REG OCR2A
-#define OCR2A5_REG OCR2A
-#define OCR2A6_REG OCR2A
-#define OCR2A7_REG OCR2A
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-#define EEAR10_REG EEARH
-#define EEAR11_REG EEARH
-
-/* CANGSTA */
-#define ERRP_REG CANGSTA
-#define BOFF_REG CANGSTA
-#define ENFG_REG CANGSTA
-#define RXBSY_REG CANGSTA
-#define TXBSY_REG CANGSTA
-#define OVRG_REG CANGSTA
-
-/* CANGCON */
-#define SWRES_REG CANGCON
-#define ENASTB_REG CANGCON
-#define TEST_REG CANGCON
-#define LISTEN_REG CANGCON
-#define SYNTTC_REG CANGCON
-#define TTC_REG CANGCON
-#define OVRQ_REG CANGCON
-#define ABRQ_REG CANGCON
-
-/* PORTG */
-#define PORTG0_REG PORTG
-#define PORTG1_REG PORTG
-#define PORTG2_REG PORTG
-#define PORTG3_REG PORTG
-#define PORTG4_REG PORTG
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL0_REG UCSR0C
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* EEARL */
-#define EEARL0_REG EEARL
-#define EEARL1_REG EEARL
-#define EEARL2_REG EEARL
-#define EEARL3_REG EEARL
-#define EEARL4_REG EEARL
-#define EEARL5_REG EEARL
-#define EEARL6_REG EEARL
-#define EEARL7_REG EEARL
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-#define INT3_REG EIMSK
-#define INT4_REG EIMSK
-#define INT5_REG EIMSK
-#define INT6_REG EIMSK
-#define INT7_REG EIMSK
-
-/* UDR1 */
-#define UDR10_REG UDR1
-#define UDR11_REG UDR1
-#define UDR12_REG UDR1
-#define UDR13_REG UDR1
-#define UDR14_REG UDR1
-#define UDR15_REG UDR1
-#define UDR16_REG UDR1
-#define UDR17_REG UDR1
-
-/* UDR0 */
-#define UDR00_REG UDR0
-#define UDR01_REG UDR0
-#define UDR02_REG UDR0
-#define UDR03_REG UDR0
-#define UDR04_REG UDR0
-#define UDR05_REG UDR0
-#define UDR06_REG UDR0
-#define UDR07_REG UDR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* EICRB */
-#define ISC40_REG EICRB
-#define ISC41_REG EICRB
-#define ISC50_REG EICRB
-#define ISC51_REG EICRB
-#define ISC60_REG EICRB
-#define ISC61_REG EICRB
-#define ISC70_REG EICRB
-#define ISC71_REG EICRB
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-#define ISC20_REG EICRA
-#define ISC21_REG EICRA
-#define ISC30_REG EICRA
-#define ISC31_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* DDRF */
-#define DDF0_REG DDRF
-#define DDF1_REG DDRF
-#define DDF2_REG DDRF
-#define DDF3_REG DDRF
-#define DDF4_REG DDRF
-#define DDF5_REG DDRF
-#define DDF6_REG DDRF
-#define DDF7_REG DDRF
-
-/* ASSR */
-#define TCR2UB_REG ASSR
-#define OCR2UB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* CANIDM1 */
-#define IDMSK21_REG CANIDM1
-#define IDMSK22_REG CANIDM1
-#define IDMSK23_REG CANIDM1
-#define IDMSK24_REG CANIDM1
-#define IDMSK25_REG CANIDM1
-#define IDMSK26_REG CANIDM1
-#define IDMSK27_REG CANIDM1
-#define IDMSK28_REG CANIDM1
-
-/* CANIDM3 */
-#define IDMSK5_REG CANIDM3
-#define IDMSK6_REG CANIDM3
-#define IDMSK7_REG CANIDM3
-#define IDMSK8_REG CANIDM3
-#define IDMSK9_REG CANIDM3
-#define IDMSK10_REG CANIDM3
-#define IDMSK11_REG CANIDM3
-#define IDMSK12_REG CANIDM3
-
-/* CANIDM2 */
-#define IDMSK13_REG CANIDM2
-#define IDMSK14_REG CANIDM2
-#define IDMSK15_REG CANIDM2
-#define IDMSK16_REG CANIDM2
-#define IDMSK17_REG CANIDM2
-#define IDMSK18_REG CANIDM2
-#define IDMSK19_REG CANIDM2
-#define IDMSK20_REG CANIDM2
-
-/* CANIDM4 */
-#define IDEMSK_REG CANIDM4
-#define RTRMSK_REG CANIDM4
-#define IDMSK0_REG CANIDM4
-#define IDMSK1_REG CANIDM4
-#define IDMSK2_REG CANIDM4
-#define IDMSK3_REG CANIDM4
-#define IDMSK4_REG CANIDM4
-
-/* UBRR1L */
-/* #define UBRR0_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR1_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR2_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR3_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR4_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR5_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR6_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR7_REG UBRR1L */ /* dup in UBRR0L */
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* OCR3AL */
-#define OCR3AL0_REG OCR3AL
-#define OCR3AL1_REG OCR3AL
-#define OCR3AL2_REG OCR3AL
-#define OCR3AL3_REG OCR3AL
-#define OCR3AL4_REG OCR3AL
-#define OCR3AL5_REG OCR3AL
-#define OCR3AL6_REG OCR3AL
-#define OCR3AL7_REG OCR3AL
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* UBRR1H */
-/* #define UBRR8_REG UBRR1H */ /* dup in UBRR0H */
-/* #define UBRR9_REG UBRR1H */ /* dup in UBRR0H */
-/* #define UBRR10_REG UBRR1H */ /* dup in UBRR0H */
-/* #define UBRR11_REG UBRR1H */ /* dup in UBRR0H */
-
-/* DDRG */
-#define DDG0_REG DDRG
-#define DDG1_REG DDRG
-#define DDG2_REG DDRG
-#define DDG3_REG DDRG
-#define DDG4_REG DDRG
-
-/* OCR3AH */
-#define OCR3AH0_REG OCR3AH
-#define OCR3AH1_REG OCR3AH
-#define OCR3AH2_REG OCR3AH
-#define OCR3AH3_REG OCR3AH
-#define OCR3AH4_REG OCR3AH
-#define OCR3AH5_REG OCR3AH
-#define OCR3AH6_REG OCR3AH
-#define OCR3AH7_REG OCR3AH
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* CANGIT */
-#define AERG_REG CANGIT
-#define FERG_REG CANGIT
-#define CERG_REG CANGIT
-#define SERG_REG CANGIT
-#define BXOK_REG CANGIT
-#define OVRTIM_REG CANGIT
-#define BOFFIT_REG CANGIT
-#define CANIT_REG CANGIT
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* CANGIE */
-#define ENOVRT_REG CANGIE
-#define ENERG_REG CANGIE
-#define ENBX_REG CANGIE
-#define ENERR_REG CANGIE
-#define ENTX_REG CANGIE
-#define ENRX_REG CANGIE
-#define ENBOFF_REG CANGIE
-#define ENIT_REG CANGIE
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* CANIE2 */
-#define IEMOB0_REG CANIE2
-#define IEMOB1_REG CANIE2
-#define IEMOB2_REG CANIE2
-#define IEMOB3_REG CANIE2
-#define IEMOB4_REG CANIE2
-#define IEMOB5_REG CANIE2
-#define IEMOB6_REG CANIE2
-#define IEMOB7_REG CANIE2
-
-/* TCCR3C */
-#define FOC3C_REG TCCR3C
-#define FOC3B_REG TCCR3C
-#define FOC3A_REG TCCR3C
-
-/* CANIE1 */
-#define IEMOB8_REG CANIE1
-#define IEMOB9_REG CANIE1
-#define IEMOB10_REG CANIE1
-#define IEMOB11_REG CANIE1
-#define IEMOB12_REG CANIE1
-#define IEMOB13_REG CANIE1
-#define IEMOB14_REG CANIE1
-
-/* TCCR0A */
-#define CS00_REG TCCR0A
-#define CS01_REG TCCR0A
-#define CS02_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-#define WGM00_REG TCCR0A
-#define FOC0A_REG TCCR0A
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-
-/* TIFR3 */
-#define TOV3_REG TIFR3
-#define OCF3A_REG TIFR3
-#define OCF3B_REG TIFR3
-#define OCF3C_REG TIFR3
-#define ICF3_REG TIFR3
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define OCF1C_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* CANIDT4 */
-#define RB0TAG_REG CANIDT4
-#define RB1TAG_REG CANIDT4
-#define RTRTAG_REG CANIDT4
-#define IDT0_REG CANIDT4
-#define IDT1_REG CANIDT4
-#define IDT2_REG CANIDT4
-#define IDT3_REG CANIDT4
-#define IDT4_REG CANIDT4
-
-/* CANIDT2 */
-#define IDT13_REG CANIDT2
-#define IDT14_REG CANIDT2
-#define IDT15_REG CANIDT2
-#define IDT16_REG CANIDT2
-#define IDT17_REG CANIDT2
-#define IDT18_REG CANIDT2
-#define IDT19_REG CANIDT2
-#define IDT20_REG CANIDT2
-
-/* CANIDT3 */
-#define IDT5_REG CANIDT3
-#define IDT6_REG CANIDT3
-#define IDT7_REG CANIDT3
-#define IDT8_REG CANIDT3
-#define IDT9_REG CANIDT3
-#define IDT10_REG CANIDT3
-#define IDT11_REG CANIDT3
-#define IDT12_REG CANIDT3
-
-/* CANIDT1 */
-#define IDT21_REG CANIDT1
-#define IDT22_REG CANIDT1
-#define IDT23_REG CANIDT1
-#define IDT24_REG CANIDT1
-#define IDT25_REG CANIDT1
-#define IDT26_REG CANIDT1
-#define IDT27_REG CANIDT1
-#define IDT28_REG CANIDT1
-
-/* CANSIT1 */
-#define SIT8_REG CANSIT1
-#define SIT9_REG CANSIT1
-#define SIT10_REG CANSIT1
-#define SIT11_REG CANSIT1
-#define SIT12_REG CANSIT1
-#define SIT13_REG CANSIT1
-#define SIT14_REG CANSIT1
-
-/* OCR3CH */
-#define OCR3CH0_REG OCR3CH
-#define OCR3CH1_REG OCR3CH
-#define OCR3CH2_REG OCR3CH
-#define OCR3CH3_REG OCR3CH
-#define OCR3CH4_REG OCR3CH
-#define OCR3CH5_REG OCR3CH
-#define OCR3CH6_REG OCR3CH
-#define OCR3CH7_REG OCR3CH
-
-/* OCR3CL */
-#define OCR3CL0_REG OCR3CL
-#define OCR3CL1_REG OCR3CL
-#define OCR3CL2_REG OCR3CL
-#define OCR3CL3_REG OCR3CL
-#define OCR3CL4_REG OCR3CL
-#define OCR3CL5_REG OCR3CL
-#define OCR3CL6_REG OCR3CL
-#define OCR3CL7_REG OCR3CL
-
-/* GTCCR */
-#define PSR310_REG GTCCR
-#define TSM_REG GTCCR
-#define PSR2_REG GTCCR
-
-/* CANCDMOB */
-#define DLC0_REG CANCDMOB
-#define DLC1_REG CANCDMOB
-#define DLC2_REG CANCDMOB
-#define DLC3_REG CANCDMOB
-#define IDE_REG CANCDMOB
-#define RPLV_REG CANCDMOB
-#define CONMOB0_REG CANCDMOB
-#define CONMOB1_REG CANCDMOB
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* CANSIT2 */
-#define SIT0_REG CANSIT2
-#define SIT1_REG CANSIT2
-#define SIT2_REG CANSIT2
-#define SIT3_REG CANSIT2
-#define SIT4_REG CANSIT2
-#define SIT5_REG CANSIT2
-#define SIT6_REG CANSIT2
-#define SIT7_REG CANSIT2
-
-/* CANHPMOB */
-#define CGP0_REG CANHPMOB
-#define CGP1_REG CANHPMOB
-#define CGP2_REG CANHPMOB
-#define CGP3_REG CANHPMOB
-#define HPMOB0_REG CANHPMOB
-#define HPMOB1_REG CANHPMOB
-#define HPMOB2_REG CANHPMOB
-#define HPMOB3_REG CANHPMOB
-
-/* TCCR3B */
-#define CS30_REG TCCR3B
-#define CS31_REG TCCR3B
-#define CS32_REG TCCR3B
-#define WGM32_REG TCCR3B
-#define WGM33_REG TCCR3B
-#define ICES3_REG TCCR3B
-#define ICNC3_REG TCCR3B
-
-/* TCCR3A */
-#define WGM30_REG TCCR3A
-#define WGM31_REG TCCR3A
-#define COM3C0_REG TCCR3A
-#define COM3C1_REG TCCR3A
-#define COM3B0_REG TCCR3A
-#define COM3B1_REG TCCR3A
-#define COM3A0_REG TCCR3A
-#define COM3A1_REG TCCR3A
-
-/* PORTF */
-#define PORTF0_REG PORTF
-#define PORTF1_REG PORTF
-#define PORTF2_REG PORTF
-#define PORTF3_REG PORTF
-#define PORTF4_REG PORTF
-#define PORTF5_REG PORTF
-#define PORTF6_REG PORTF
-#define PORTF7_REG PORTF
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* TCNT3H */
-#define TCNT3H0_REG TCNT3H
-#define TCNT3H1_REG TCNT3H
-#define TCNT3H2_REG TCNT3H
-#define TCNT3H3_REG TCNT3H
-#define TCNT3H4_REG TCNT3H
-#define TCNT3H5_REG TCNT3H
-#define TCNT3H6_REG TCNT3H
-#define TCNT3H7_REG TCNT3H
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* TCNT3L */
-#define TCNT3L0_REG TCNT3L
-#define TCNT3L1_REG TCNT3L
-#define TCNT3L2_REG TCNT3L
-#define TCNT3L3_REG TCNT3L
-#define TCNT3L4_REG TCNT3L
-#define TCNT3L5_REG TCNT3L
-#define TCNT3L6_REG TCNT3L
-#define TCNT3L7_REG TCNT3L
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* MCUSR */
-#define JTRF_REG MCUSR
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* TCCR2A */
-#define CS20_REG TCCR2A
-#define CS21_REG TCCR2A
-#define CS22_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-#define WGM20_REG TCCR2A
-#define FOC2A_REG TCCR2A
-
-/* UBRR0H */
-/* #define UBRR8_REG UBRR0H */ /* dup in UBRR1H */
-/* #define UBRR9_REG UBRR0H */ /* dup in UBRR1H */
-/* #define UBRR10_REG UBRR0H */ /* dup in UBRR1H */
-/* #define UBRR11_REG UBRR0H */ /* dup in UBRR1H */
-
-/* UBRR0L */
-/* #define UBRR0_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR1_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR2_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR3_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR4_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR5_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR6_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR7_REG UBRR0L */ /* dup in UBRR1L */
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* CANPAGE */
-#define INDX0_REG CANPAGE
-#define INDX1_REG CANPAGE
-#define INDX2_REG CANPAGE
-#define AINC_REG CANPAGE
-#define MOBNB0_REG CANPAGE
-#define MOBNB1_REG CANPAGE
-#define MOBNB2_REG CANPAGE
-#define MOBNB3_REG CANPAGE
-
-/* MCUCR */
-#define JTD_REG MCUCR
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* OCR1CL */
-#define OCR1CL0_REG OCR1CL
-#define OCR1CL1_REG OCR1CL
-#define OCR1CL2_REG OCR1CL
-#define OCR1CL3_REG OCR1CL
-#define OCR1CL4_REG OCR1CL
-#define OCR1CL5_REG OCR1CL
-#define OCR1CL6_REG OCR1CL
-#define OCR1CL7_REG OCR1CL
-
-/* OCR1CH */
-#define OCR1CH0_REG OCR1CH
-#define OCR1CH1_REG OCR1CH
-#define OCR1CH2_REG OCR1CH
-#define OCR1CH3_REG OCR1CH
-#define OCR1CH4_REG OCR1CH
-#define OCR1CH5_REG OCR1CH
-#define OCR1CH6_REG OCR1CH
-#define OCR1CH7_REG OCR1CH
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* CANSTMOB */
-#define AERR_REG CANSTMOB
-#define FERR_REG CANSTMOB
-#define CERR_REG CANSTMOB
-#define SERR_REG CANSTMOB
-#define BERR_REG CANSTMOB
-#define RXOK_REG CANSTMOB
-#define TXOK_REG CANSTMOB
-#define DLCW_REG CANSTMOB
-
-/* UCSR1B */
-#define TXB81_REG UCSR1B
-#define RXB81_REG UCSR1B
-#define UCSZ12_REG UCSR1B
-#define TXEN1_REG UCSR1B
-#define RXEN1_REG UCSR1B
-#define UDRIE1_REG UCSR1B
-#define TXCIE1_REG UCSR1B
-#define RXCIE1_REG UCSR1B
-
-/* UCSR1C */
-#define UCPOL1_REG UCSR1C
-#define UCSZ10_REG UCSR1C
-#define UCSZ11_REG UCSR1C
-#define USBS1_REG UCSR1C
-#define UPM10_REG UCSR1C
-#define UPM11_REG UCSR1C
-#define UMSEL1_REG UCSR1C
-
-/* UCSR1A */
-#define MPCM1_REG UCSR1A
-#define U2X1_REG UCSR1A
-#define UPE1_REG UCSR1A
-#define DOR1_REG UCSR1A
-#define FE1_REG UCSR1A
-#define UDRE1_REG UCSR1A
-#define TXC1_REG UCSR1A
-#define RXC1_REG UCSR1A
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* CANEN2 */
-#define ENMOB0_REG CANEN2
-#define ENMOB1_REG CANEN2
-#define ENMOB2_REG CANEN2
-#define ENMOB3_REG CANEN2
-#define ENMOB4_REG CANEN2
-#define ENMOB5_REG CANEN2
-#define ENMOB6_REG CANEN2
-#define ENMOB7_REG CANEN2
-
-/* CANEN1 */
-#define ENMOB8_REG CANEN1
-#define ENMOB9_REG CANEN1
-#define ENMOB10_REG CANEN1
-#define ENMOB11_REG CANEN1
-#define ENMOB12_REG CANEN1
-#define ENMOB13_REG CANEN1
-#define ENMOB14_REG CANEN1
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ADHSM_REG ADCSRB
-#define ACME_REG ADCSRB
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1C0_REG TCCR1A
-#define COM1C1_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* OCR0A */
-#define OCR0A0_REG OCR0A
-#define OCR0A1_REG OCR0A
-#define OCR0A2_REG OCR0A
-#define OCR0A3_REG OCR0A
-#define OCR0A4_REG OCR0A
-#define OCR0A5_REG OCR0A
-#define OCR0A6_REG OCR0A
-#define OCR0A7_REG OCR0A
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* TCCR1C */
-#define FOC1C_REG TCCR1C
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* ICR3H */
-#define ICR3H0_REG ICR3H
-#define ICR3H1_REG ICR3H
-#define ICR3H2_REG ICR3H
-#define ICR3H3_REG ICR3H
-#define ICR3H4_REG ICR3H
-#define ICR3H5_REG ICR3H
-#define ICR3H6_REG ICR3H
-#define ICR3H7_REG ICR3H
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-#define DDE3_REG DDRE
-#define DDE4_REG DDRE
-#define DDE5_REG DDRE
-#define DDE6_REG DDRE
-#define DDE7_REG DDRE
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* ICR3L */
-#define ICR3L0_REG ICR3L
-#define ICR3L1_REG ICR3L
-#define ICR3L2_REG ICR3L
-#define ICR3L3_REG ICR3L
-#define ICR3L4_REG ICR3L
-#define ICR3L5_REG ICR3L
-#define ICR3L6_REG ICR3L
-#define ICR3L7_REG ICR3L
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-#define PORTE3_REG PORTE
-#define PORTE4_REG PORTE
-#define PORTE5_REG PORTE
-#define PORTE6_REG PORTE
-#define PORTE7_REG PORTE
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* CANBT2 */
-#define PRS0_REG CANBT2
-#define PRS1_REG CANBT2
-#define PRS2_REG CANBT2
-#define SJW0_REG CANBT2
-#define SJW1_REG CANBT2
-
-/* CANBT3 */
-#define SMP_REG CANBT3
-#define PHS10_REG CANBT3
-#define PHS11_REG CANBT3
-#define PHS12_REG CANBT3
-#define PHS20_REG CANBT3
-#define PHS21_REG CANBT3
-#define PHS22_REG CANBT3
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* CANBT1 */
-#define BRP0_REG CANBT1
-#define BRP1_REG CANBT1
-#define BRP2_REG CANBT1
-#define BRP3_REG CANBT1
-#define BRP4_REG CANBT1
-#define BRP5_REG CANBT1
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* OCR3BL */
-#define OCR3BL0_REG OCR3BL
-#define OCR3BL1_REG OCR3BL
-#define OCR3BL2_REG OCR3BL
-#define OCR3BL3_REG OCR3BL
-#define OCR3BL4_REG OCR3BL
-#define OCR3BL5_REG OCR3BL
-#define OCR3BL6_REG OCR3BL
-#define OCR3BL7_REG OCR3BL
-
-/* OCR3BH */
-#define OCR3BH0_REG OCR3BH
-#define OCR3BH1_REG OCR3BH
-#define OCR3BH2_REG OCR3BH
-#define OCR3BH3_REG OCR3BH
-#define OCR3BH4_REG OCR3BH
-#define OCR3BH5_REG OCR3BH
-#define OCR3BH6_REG OCR3BH
-#define OCR3BH7_REG OCR3BH
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-
-/* TIMSK3 */
-#define TOIE3_REG TIMSK3
-#define OCIE3A_REG TIMSK3
-#define OCIE3B_REG TIMSK3
-#define OCIE3C_REG TIMSK3
-#define ICIE3_REG TIMSK3
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define OCIE1C_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* XMCRB */
-#define XMM0_REG XMCRB
-#define XMM1_REG XMCRB
-#define XMM2_REG XMCRB
-#define XMBK_REG XMCRB
-
-/* XMCRA */
-#define SRW00_REG XMCRA
-#define SRW01_REG XMCRA
-#define SRW10_REG XMCRA
-#define SRW11_REG XMCRA
-#define SRL0_REG XMCRA
-#define SRL1_REG XMCRA
-#define SRL2_REG XMCRA
-#define SRE_REG XMCRA
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-#define INTF2_REG EIFR
-#define INTF3_REG EIFR
-#define INTF4_REG EIFR
-#define INTF5_REG EIFR
-#define INTF6_REG EIFR
-#define INTF7_REG EIFR
-
-/* PING */
-#define PING0_REG PING
-#define PING1_REG PING
-#define PING2_REG PING
-#define PING3_REG PING
-#define PING4_REG PING
-
-/* PINF */
-#define PINF0_REG PINF
-#define PINF1_REG PINF
-#define PINF2_REG PINF
-#define PINF3_REG PINF
-#define PINF4_REG PINF
-#define PINF5_REG PINF
-#define PINF6_REG PINF
-#define PINF7_REG PINF
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-#define PINE3_REG PINE
-#define PINE4_REG PINE
-#define PINE5_REG PINE
-#define PINE6_REG PINE
-#define PINE7_REG PINE
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-
-/* pins mapping */
-#define AD0_PORT PORTA
-#define AD0_BIT 0
-
-#define AD1_PORT PORTA
-#define AD1_BIT 1
-
-#define AD2_PORT PORTA
-#define AD2_BIT 2
-
-#define AD3_PORT PORTA
-#define AD3_BIT 3
-
-#define AD4_PORT PORTA
-#define AD4_BIT 4
-
-#define AD5_PORT PORTA
-#define AD5_BIT 5
-
-#define AD6_PORT PORTA
-#define AD6_BIT 6
-
-#define AD7_PORT PORTA
-#define AD7_BIT 7
-
-#define SS_PORT PORTB
-#define SS_BIT 0
-
-#define SCK_PORT PORTB
-#define SCK_BIT 1
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 2
-
-#define MISO_PORT PORTB
-#define MISO_BIT 3
-
-#define OC0_PORT PORTB
-#define OC0_BIT 4
-#define PWM0_PORT PORTB
-#define PWM0_BIT 4
-
-#define OC1A_PORT PORTB
-#define OC1A_BIT 5
-#define PWM1A_PORT PORTB
-#define PWM1A_BIT 5
-
-#define OC1B_PORT PORTB
-#define OC1B_BIT 6
-#define PWM1B_PORT PORTB
-#define PWM1B_BIT 6
-
-#define OC2_PORT PORTB
-#define OC2_BIT 7
-#define PWM2_PORT PORTB
-#define PWM2_BIT 7
-#define OC1C_PORT PORTB
-#define OC1C_BIT 7
-
-#define A8_PORT PORTC
-#define A8_BIT 0
-
-#define A9_PORT PORTC
-#define A9_BIT 1
-
-#define A10_PORT PORTC
-#define A10_BIT 2
-
-#define A11_PORT PORTC
-#define A11_BIT 3
-
-#define A12_PORT PORTC
-#define A12_BIT 4
-
-#define A13_PORT PORTC
-#define A13_BIT 5
-
-#define A14_PORT PORTC
-#define A14_BIT 6
-
-#define A15_PORT PORTC
-#define A15_BIT 7
-
-#define SCL_PORT PORTD
-#define SCL_BIT 0
-#define INT0_PORT PORTD
-#define INT0_BIT 0
-
-#define SDA_PORT PORTD
-#define SDA_BIT 1
-#define INT1_PORT PORTD
-#define INT1_BIT 1
-
-#define RXD1_PORT PORTD
-#define RXD1_BIT 2
-#define INT2_PORT PORTD
-#define INT2_BIT 2
-
-#define TXD1_PORT PORTD
-#define TXD1_BIT 3
-#define INT3_PORT PORTD
-#define INT3_BIT 3
-
-#define IC1_PORT PORTD
-#define IC1_BIT 4
-
-#define XCK1_PORT PORTD
-#define XCK1_BIT 5
-
-#define T1_PORT PORTD
-#define T1_BIT 6
-
-#define T2_PORT PORTD
-#define T2_BIT 7
-
-#define RXD0_PORT PORTE
-#define RXD0_BIT 0
-#define PDI_PORT PORTE
-#define PDI_BIT 0
-
-#define TXD0_PORT PORTE
-#define TXD0_BIT 1
-#define PDO_PORT PORTE
-#define PDO_BIT 1
-
-#define XCK0_PORT PORTE
-#define XCK0_BIT 2
-#define AIN0_PORT PORTE
-#define AIN0_BIT 2
-
-#define OC3A_PORT PORTE
-#define OC3A_BIT 3
-#define AIN1_PORT PORTE
-#define AIN1_BIT 3
-
-#define OC3B_PORT PORTE
-#define OC3B_BIT 4
-#define INT4_PORT PORTE
-#define INT4_BIT 4
-
-#define OC3C_PORT PORTE
-#define OC3C_BIT 5
-#define INT5_PORT PORTE
-#define INT5_BIT 5
-
-#define T3_PORT PORTE
-#define T3_BIT 6
-#define INT6_PORT PORTE
-#define INT6_BIT 6
-
-#define IC3_PORT PORTE
-#define IC3_BIT 7
-#define INT7_PORT PORTE
-#define INT7_BIT 7
-
-#define ADC0_PORT PORTF
-#define ADC0_BIT 0
-
-#define ADC1_PORT PORTF
-#define ADC1_BIT 1
-
-#define ADC2_PORT PORTF
-#define ADC2_BIT 2
-
-#define ADC3_PORT PORTF
-#define ADC3_BIT 3
-
-#define ADC4_PORT PORTF
-#define ADC4_BIT 4
-#define TCK_PORT PORTF
-#define TCK_BIT 4
-
-#define ADC5_PORT PORTF
-#define ADC5_BIT 5
-#define TMS_PORT PORTF
-#define TMS_BIT 5
-
-#define ADC6_PORT PORTF
-#define ADC6_BIT 6
-#define TD0_PORT PORTF
-#define TD0_BIT 6
-
-#define ADC7_PORT PORTF
-#define ADC7_BIT 7
-#define TDI_PORT PORTF
-#define TDI_BIT 7
-
-#define WR_PORT PORTG
-#define WR_BIT 0
-
-#define RD_PORT PORTG
-#define RD_BIT 1
-
-#define ALE_PORT PORTG
-#define ALE_BIT 2
-
-#define TOSC2_PORT PORTG
-#define TOSC2_BIT 3
-
-#define TOSC1_PORT PORTG
-#define TOSC1_BIT 4
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-/* prescalers timer 3 */
-#define TIMER3_PRESCALER_DIV_0 0
-#define TIMER3_PRESCALER_DIV_1 1
-#define TIMER3_PRESCALER_DIV_8 2
-#define TIMER3_PRESCALER_DIV_64 3
-#define TIMER3_PRESCALER_DIV_256 4
-#define TIMER3_PRESCALER_DIV_1024 5
-#define TIMER3_PRESCALER_DIV_FALL 6
-#define TIMER3_PRESCALER_DIV_RISE 7
-
-#define TIMER3_PRESCALER_REG_0 0
-#define TIMER3_PRESCALER_REG_1 1
-#define TIMER3_PRESCALER_REG_2 8
-#define TIMER3_PRESCALER_REG_3 64
-#define TIMER3_PRESCALER_REG_4 256
-#define TIMER3_PRESCALER_REG_5 1024
-#define TIMER3_PRESCALER_REG_6 -1
-#define TIMER3_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER1C_AVAILABLE
-#define TIMER2_AVAILABLE
-#define TIMER3_AVAILABLE
-#define TIMER3A_AVAILABLE
-#define TIMER3B_AVAILABLE
-#define TIMER3C_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW3_NUM 3
-#define SIG_OVERFLOW_TOTAL_NUM 4
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE1A_NUM 1
-#define SIG_OUTPUT_COMPARE1B_NUM 2
-#define SIG_OUTPUT_COMPARE1C_NUM 3
-#define SIG_OUTPUT_COMPARE2_NUM 4
-#define SIG_OUTPUT_COMPARE3A_NUM 5
-#define SIG_OUTPUT_COMPARE3B_NUM 6
-#define SIG_OUTPUT_COMPARE3C_NUM 7
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 8
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM1A_NUM 1
-#define PWM1B_NUM 2
-#define PWM1C_NUM 3
-#define PWM2_NUM 4
-#define PWM3A_NUM 5
-#define PWM3B_NUM 6
-#define PWM3C_NUM 7
-#define PWM_TOTAL_NUM 8
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE3_NUM 1
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 2
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* RAMPZ */
-#define RAMPZ0_REG RAMPZ
-
-/* OCR2A */
-#define OCR2A0_REG OCR2A
-#define OCR2A1_REG OCR2A
-#define OCR2A2_REG OCR2A
-#define OCR2A3_REG OCR2A
-#define OCR2A4_REG OCR2A
-#define OCR2A5_REG OCR2A
-#define OCR2A6_REG OCR2A
-#define OCR2A7_REG OCR2A
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-#define EEAR10_REG EEARH
-#define EEAR11_REG EEARH
-
-/* CANGSTA */
-#define ERRP_REG CANGSTA
-#define BOFF_REG CANGSTA
-#define ENFG_REG CANGSTA
-#define RXBSY_REG CANGSTA
-#define TXBSY_REG CANGSTA
-#define OVRG_REG CANGSTA
-
-/* CANGCON */
-#define SWRES_REG CANGCON
-#define ENASTB_REG CANGCON
-#define TEST_REG CANGCON
-#define LISTEN_REG CANGCON
-#define SYNTTC_REG CANGCON
-#define TTC_REG CANGCON
-#define OVRQ_REG CANGCON
-#define ABRQ_REG CANGCON
-
-/* PORTG */
-#define PORTG0_REG PORTG
-#define PORTG1_REG PORTG
-#define PORTG2_REG PORTG
-#define PORTG3_REG PORTG
-#define PORTG4_REG PORTG
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL0_REG UCSR0C
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* EEARL */
-#define EEARL0_REG EEARL
-#define EEARL1_REG EEARL
-#define EEARL2_REG EEARL
-#define EEARL3_REG EEARL
-#define EEARL4_REG EEARL
-#define EEARL5_REG EEARL
-#define EEARL6_REG EEARL
-#define EEARL7_REG EEARL
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-#define INT3_REG EIMSK
-#define INT4_REG EIMSK
-#define INT5_REG EIMSK
-#define INT6_REG EIMSK
-#define INT7_REG EIMSK
-
-/* UDR1 */
-#define UDR10_REG UDR1
-#define UDR11_REG UDR1
-#define UDR12_REG UDR1
-#define UDR13_REG UDR1
-#define UDR14_REG UDR1
-#define UDR15_REG UDR1
-#define UDR16_REG UDR1
-#define UDR17_REG UDR1
-
-/* UDR0 */
-#define UDR00_REG UDR0
-#define UDR01_REG UDR0
-#define UDR02_REG UDR0
-#define UDR03_REG UDR0
-#define UDR04_REG UDR0
-#define UDR05_REG UDR0
-#define UDR06_REG UDR0
-#define UDR07_REG UDR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* EICRB */
-#define ISC40_REG EICRB
-#define ISC41_REG EICRB
-#define ISC50_REG EICRB
-#define ISC51_REG EICRB
-#define ISC60_REG EICRB
-#define ISC61_REG EICRB
-#define ISC70_REG EICRB
-#define ISC71_REG EICRB
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-#define ISC20_REG EICRA
-#define ISC21_REG EICRA
-#define ISC30_REG EICRA
-#define ISC31_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* DDRF */
-#define DDF0_REG DDRF
-#define DDF1_REG DDRF
-#define DDF2_REG DDRF
-#define DDF3_REG DDRF
-#define DDF4_REG DDRF
-#define DDF5_REG DDRF
-#define DDF6_REG DDRF
-#define DDF7_REG DDRF
-
-/* ASSR */
-#define TCR2UB_REG ASSR
-#define OCR2UB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* CANIDM1 */
-#define IDMSK21_REG CANIDM1
-#define IDMSK22_REG CANIDM1
-#define IDMSK23_REG CANIDM1
-#define IDMSK24_REG CANIDM1
-#define IDMSK25_REG CANIDM1
-#define IDMSK26_REG CANIDM1
-#define IDMSK27_REG CANIDM1
-#define IDMSK28_REG CANIDM1
-
-/* CANIDM3 */
-#define IDMSK5_REG CANIDM3
-#define IDMSK6_REG CANIDM3
-#define IDMSK7_REG CANIDM3
-#define IDMSK8_REG CANIDM3
-#define IDMSK9_REG CANIDM3
-#define IDMSK10_REG CANIDM3
-#define IDMSK11_REG CANIDM3
-#define IDMSK12_REG CANIDM3
-
-/* CANIDM2 */
-#define IDMSK13_REG CANIDM2
-#define IDMSK14_REG CANIDM2
-#define IDMSK15_REG CANIDM2
-#define IDMSK16_REG CANIDM2
-#define IDMSK17_REG CANIDM2
-#define IDMSK18_REG CANIDM2
-#define IDMSK19_REG CANIDM2
-#define IDMSK20_REG CANIDM2
-
-/* CANIDM4 */
-#define IDEMSK_REG CANIDM4
-#define RTRMSK_REG CANIDM4
-#define IDMSK0_REG CANIDM4
-#define IDMSK1_REG CANIDM4
-#define IDMSK2_REG CANIDM4
-#define IDMSK3_REG CANIDM4
-#define IDMSK4_REG CANIDM4
-
-/* UBRR1L */
-/* #define UBRR0_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR1_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR2_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR3_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR4_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR5_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR6_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR7_REG UBRR1L */ /* dup in UBRR0L */
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* OCR3AL */
-#define OCR3AL0_REG OCR3AL
-#define OCR3AL1_REG OCR3AL
-#define OCR3AL2_REG OCR3AL
-#define OCR3AL3_REG OCR3AL
-#define OCR3AL4_REG OCR3AL
-#define OCR3AL5_REG OCR3AL
-#define OCR3AL6_REG OCR3AL
-#define OCR3AL7_REG OCR3AL
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* UBRR1H */
-/* #define UBRR8_REG UBRR1H */ /* dup in UBRR0H */
-/* #define UBRR9_REG UBRR1H */ /* dup in UBRR0H */
-/* #define UBRR10_REG UBRR1H */ /* dup in UBRR0H */
-/* #define UBRR11_REG UBRR1H */ /* dup in UBRR0H */
-
-/* DDRG */
-#define DDG0_REG DDRG
-#define DDG1_REG DDRG
-#define DDG2_REG DDRG
-#define DDG3_REG DDRG
-#define DDG4_REG DDRG
-
-/* OCR3AH */
-#define OCR3AH0_REG OCR3AH
-#define OCR3AH1_REG OCR3AH
-#define OCR3AH2_REG OCR3AH
-#define OCR3AH3_REG OCR3AH
-#define OCR3AH4_REG OCR3AH
-#define OCR3AH5_REG OCR3AH
-#define OCR3AH6_REG OCR3AH
-#define OCR3AH7_REG OCR3AH
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* CANGIT */
-#define AERG_REG CANGIT
-#define FERG_REG CANGIT
-#define CERG_REG CANGIT
-#define SERG_REG CANGIT
-#define BXOK_REG CANGIT
-#define OVRTIM_REG CANGIT
-#define BOFFIT_REG CANGIT
-#define CANIT_REG CANGIT
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* CANGIE */
-#define ENOVRT_REG CANGIE
-#define ENERG_REG CANGIE
-#define ENBX_REG CANGIE
-#define ENERR_REG CANGIE
-#define ENTX_REG CANGIE
-#define ENRX_REG CANGIE
-#define ENBOFF_REG CANGIE
-#define ENIT_REG CANGIE
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* CANIE2 */
-#define IEMOB0_REG CANIE2
-#define IEMOB1_REG CANIE2
-#define IEMOB2_REG CANIE2
-#define IEMOB3_REG CANIE2
-#define IEMOB4_REG CANIE2
-#define IEMOB5_REG CANIE2
-#define IEMOB6_REG CANIE2
-#define IEMOB7_REG CANIE2
-
-/* TCCR3C */
-#define FOC3C_REG TCCR3C
-#define FOC3B_REG TCCR3C
-#define FOC3A_REG TCCR3C
-
-/* CANIE1 */
-#define IEMOB8_REG CANIE1
-#define IEMOB9_REG CANIE1
-#define IEMOB10_REG CANIE1
-#define IEMOB11_REG CANIE1
-#define IEMOB12_REG CANIE1
-#define IEMOB13_REG CANIE1
-#define IEMOB14_REG CANIE1
-
-/* TCCR0A */
-#define CS00_REG TCCR0A
-#define CS01_REG TCCR0A
-#define CS02_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-#define WGM00_REG TCCR0A
-#define FOC0A_REG TCCR0A
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-
-/* TIFR3 */
-#define TOV3_REG TIFR3
-#define OCF3A_REG TIFR3
-#define OCF3B_REG TIFR3
-#define OCF3C_REG TIFR3
-#define ICF3_REG TIFR3
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define OCF1C_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* CANIDT4 */
-#define RB0TAG_REG CANIDT4
-#define RB1TAG_REG CANIDT4
-#define RTRTAG_REG CANIDT4
-#define IDT0_REG CANIDT4
-#define IDT1_REG CANIDT4
-#define IDT2_REG CANIDT4
-#define IDT3_REG CANIDT4
-#define IDT4_REG CANIDT4
-
-/* CANIDT2 */
-#define IDT13_REG CANIDT2
-#define IDT14_REG CANIDT2
-#define IDT15_REG CANIDT2
-#define IDT16_REG CANIDT2
-#define IDT17_REG CANIDT2
-#define IDT18_REG CANIDT2
-#define IDT19_REG CANIDT2
-#define IDT20_REG CANIDT2
-
-/* CANIDT3 */
-#define IDT5_REG CANIDT3
-#define IDT6_REG CANIDT3
-#define IDT7_REG CANIDT3
-#define IDT8_REG CANIDT3
-#define IDT9_REG CANIDT3
-#define IDT10_REG CANIDT3
-#define IDT11_REG CANIDT3
-#define IDT12_REG CANIDT3
-
-/* CANIDT1 */
-#define IDT21_REG CANIDT1
-#define IDT22_REG CANIDT1
-#define IDT23_REG CANIDT1
-#define IDT24_REG CANIDT1
-#define IDT25_REG CANIDT1
-#define IDT26_REG CANIDT1
-#define IDT27_REG CANIDT1
-#define IDT28_REG CANIDT1
-
-/* CANSIT1 */
-#define SIT8_REG CANSIT1
-#define SIT9_REG CANSIT1
-#define SIT10_REG CANSIT1
-#define SIT11_REG CANSIT1
-#define SIT12_REG CANSIT1
-#define SIT13_REG CANSIT1
-#define SIT14_REG CANSIT1
-
-/* OCR3CH */
-#define OCR3CH0_REG OCR3CH
-#define OCR3CH1_REG OCR3CH
-#define OCR3CH2_REG OCR3CH
-#define OCR3CH3_REG OCR3CH
-#define OCR3CH4_REG OCR3CH
-#define OCR3CH5_REG OCR3CH
-#define OCR3CH6_REG OCR3CH
-#define OCR3CH7_REG OCR3CH
-
-/* OCR3CL */
-#define OCR3CL0_REG OCR3CL
-#define OCR3CL1_REG OCR3CL
-#define OCR3CL2_REG OCR3CL
-#define OCR3CL3_REG OCR3CL
-#define OCR3CL4_REG OCR3CL
-#define OCR3CL5_REG OCR3CL
-#define OCR3CL6_REG OCR3CL
-#define OCR3CL7_REG OCR3CL
-
-/* GTCCR */
-#define PSR310_REG GTCCR
-#define TSM_REG GTCCR
-#define PSR2_REG GTCCR
-
-/* CANCDMOB */
-#define DLC0_REG CANCDMOB
-#define DLC1_REG CANCDMOB
-#define DLC2_REG CANCDMOB
-#define DLC3_REG CANCDMOB
-#define IDE_REG CANCDMOB
-#define RPLV_REG CANCDMOB
-#define CONMOB0_REG CANCDMOB
-#define CONMOB1_REG CANCDMOB
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* CANSIT2 */
-#define SIT0_REG CANSIT2
-#define SIT1_REG CANSIT2
-#define SIT2_REG CANSIT2
-#define SIT3_REG CANSIT2
-#define SIT4_REG CANSIT2
-#define SIT5_REG CANSIT2
-#define SIT6_REG CANSIT2
-#define SIT7_REG CANSIT2
-
-/* CANHPMOB */
-#define CGP0_REG CANHPMOB
-#define CGP1_REG CANHPMOB
-#define CGP2_REG CANHPMOB
-#define CGP3_REG CANHPMOB
-#define HPMOB0_REG CANHPMOB
-#define HPMOB1_REG CANHPMOB
-#define HPMOB2_REG CANHPMOB
-#define HPMOB3_REG CANHPMOB
-
-/* TCCR3B */
-#define CS30_REG TCCR3B
-#define CS31_REG TCCR3B
-#define CS32_REG TCCR3B
-#define WGM32_REG TCCR3B
-#define WGM33_REG TCCR3B
-#define ICES3_REG TCCR3B
-#define ICNC3_REG TCCR3B
-
-/* TCCR3A */
-#define WGM30_REG TCCR3A
-#define WGM31_REG TCCR3A
-#define COM3C0_REG TCCR3A
-#define COM3C1_REG TCCR3A
-#define COM3B0_REG TCCR3A
-#define COM3B1_REG TCCR3A
-#define COM3A0_REG TCCR3A
-#define COM3A1_REG TCCR3A
-
-/* PORTF */
-#define PORTF0_REG PORTF
-#define PORTF1_REG PORTF
-#define PORTF2_REG PORTF
-#define PORTF3_REG PORTF
-#define PORTF4_REG PORTF
-#define PORTF5_REG PORTF
-#define PORTF6_REG PORTF
-#define PORTF7_REG PORTF
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* TCNT3H */
-#define TCNT3H0_REG TCNT3H
-#define TCNT3H1_REG TCNT3H
-#define TCNT3H2_REG TCNT3H
-#define TCNT3H3_REG TCNT3H
-#define TCNT3H4_REG TCNT3H
-#define TCNT3H5_REG TCNT3H
-#define TCNT3H6_REG TCNT3H
-#define TCNT3H7_REG TCNT3H
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* TCNT3L */
-#define TCNT3L0_REG TCNT3L
-#define TCNT3L1_REG TCNT3L
-#define TCNT3L2_REG TCNT3L
-#define TCNT3L3_REG TCNT3L
-#define TCNT3L4_REG TCNT3L
-#define TCNT3L5_REG TCNT3L
-#define TCNT3L6_REG TCNT3L
-#define TCNT3L7_REG TCNT3L
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* MCUSR */
-#define JTRF_REG MCUSR
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* TCCR2A */
-#define CS20_REG TCCR2A
-#define CS21_REG TCCR2A
-#define CS22_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-#define WGM20_REG TCCR2A
-#define FOC2A_REG TCCR2A
-
-/* UBRR0H */
-/* #define UBRR8_REG UBRR0H */ /* dup in UBRR1H */
-/* #define UBRR9_REG UBRR0H */ /* dup in UBRR1H */
-/* #define UBRR10_REG UBRR0H */ /* dup in UBRR1H */
-/* #define UBRR11_REG UBRR0H */ /* dup in UBRR1H */
-
-/* UBRR0L */
-/* #define UBRR0_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR1_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR2_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR3_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR4_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR5_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR6_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR7_REG UBRR0L */ /* dup in UBRR1L */
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* CANPAGE */
-#define INDX0_REG CANPAGE
-#define INDX1_REG CANPAGE
-#define INDX2_REG CANPAGE
-#define AINC_REG CANPAGE
-#define MOBNB0_REG CANPAGE
-#define MOBNB1_REG CANPAGE
-#define MOBNB2_REG CANPAGE
-#define MOBNB3_REG CANPAGE
-
-/* MCUCR */
-#define JTD_REG MCUCR
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* OCR1CL */
-#define OCR1CL0_REG OCR1CL
-#define OCR1CL1_REG OCR1CL
-#define OCR1CL2_REG OCR1CL
-#define OCR1CL3_REG OCR1CL
-#define OCR1CL4_REG OCR1CL
-#define OCR1CL5_REG OCR1CL
-#define OCR1CL6_REG OCR1CL
-#define OCR1CL7_REG OCR1CL
-
-/* OCR1CH */
-#define OCR1CH0_REG OCR1CH
-#define OCR1CH1_REG OCR1CH
-#define OCR1CH2_REG OCR1CH
-#define OCR1CH3_REG OCR1CH
-#define OCR1CH4_REG OCR1CH
-#define OCR1CH5_REG OCR1CH
-#define OCR1CH6_REG OCR1CH
-#define OCR1CH7_REG OCR1CH
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* CANSTMOB */
-#define AERR_REG CANSTMOB
-#define FERR_REG CANSTMOB
-#define CERR_REG CANSTMOB
-#define SERR_REG CANSTMOB
-#define BERR_REG CANSTMOB
-#define RXOK_REG CANSTMOB
-#define TXOK_REG CANSTMOB
-#define DLCW_REG CANSTMOB
-
-/* UCSR1B */
-#define TXB81_REG UCSR1B
-#define RXB81_REG UCSR1B
-#define UCSZ12_REG UCSR1B
-#define TXEN1_REG UCSR1B
-#define RXEN1_REG UCSR1B
-#define UDRIE1_REG UCSR1B
-#define TXCIE1_REG UCSR1B
-#define RXCIE1_REG UCSR1B
-
-/* UCSR1C */
-#define UCPOL1_REG UCSR1C
-#define UCSZ10_REG UCSR1C
-#define UCSZ11_REG UCSR1C
-#define USBS1_REG UCSR1C
-#define UPM10_REG UCSR1C
-#define UPM11_REG UCSR1C
-#define UMSEL1_REG UCSR1C
-
-/* UCSR1A */
-#define MPCM1_REG UCSR1A
-#define U2X1_REG UCSR1A
-#define UPE1_REG UCSR1A
-#define DOR1_REG UCSR1A
-#define FE1_REG UCSR1A
-#define UDRE1_REG UCSR1A
-#define TXC1_REG UCSR1A
-#define RXC1_REG UCSR1A
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* CANEN2 */
-#define ENMOB0_REG CANEN2
-#define ENMOB1_REG CANEN2
-#define ENMOB2_REG CANEN2
-#define ENMOB3_REG CANEN2
-#define ENMOB4_REG CANEN2
-#define ENMOB5_REG CANEN2
-#define ENMOB6_REG CANEN2
-#define ENMOB7_REG CANEN2
-
-/* CANEN1 */
-#define ENMOB8_REG CANEN1
-#define ENMOB9_REG CANEN1
-#define ENMOB10_REG CANEN1
-#define ENMOB11_REG CANEN1
-#define ENMOB12_REG CANEN1
-#define ENMOB13_REG CANEN1
-#define ENMOB14_REG CANEN1
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ADHSM_REG ADCSRB
-#define ACME_REG ADCSRB
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1C0_REG TCCR1A
-#define COM1C1_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* OCR0A */
-#define OCR0A0_REG OCR0A
-#define OCR0A1_REG OCR0A
-#define OCR0A2_REG OCR0A
-#define OCR0A3_REG OCR0A
-#define OCR0A4_REG OCR0A
-#define OCR0A5_REG OCR0A
-#define OCR0A6_REG OCR0A
-#define OCR0A7_REG OCR0A
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* TCCR1C */
-#define FOC1C_REG TCCR1C
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* ICR3H */
-#define ICR3H0_REG ICR3H
-#define ICR3H1_REG ICR3H
-#define ICR3H2_REG ICR3H
-#define ICR3H3_REG ICR3H
-#define ICR3H4_REG ICR3H
-#define ICR3H5_REG ICR3H
-#define ICR3H6_REG ICR3H
-#define ICR3H7_REG ICR3H
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-#define DDE3_REG DDRE
-#define DDE4_REG DDRE
-#define DDE5_REG DDRE
-#define DDE6_REG DDRE
-#define DDE7_REG DDRE
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* ICR3L */
-#define ICR3L0_REG ICR3L
-#define ICR3L1_REG ICR3L
-#define ICR3L2_REG ICR3L
-#define ICR3L3_REG ICR3L
-#define ICR3L4_REG ICR3L
-#define ICR3L5_REG ICR3L
-#define ICR3L6_REG ICR3L
-#define ICR3L7_REG ICR3L
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-#define PORTE3_REG PORTE
-#define PORTE4_REG PORTE
-#define PORTE5_REG PORTE
-#define PORTE6_REG PORTE
-#define PORTE7_REG PORTE
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* CANBT2 */
-#define PRS0_REG CANBT2
-#define PRS1_REG CANBT2
-#define PRS2_REG CANBT2
-#define SJW0_REG CANBT2
-#define SJW1_REG CANBT2
-
-/* CANBT3 */
-#define SMP_REG CANBT3
-#define PHS10_REG CANBT3
-#define PHS11_REG CANBT3
-#define PHS12_REG CANBT3
-#define PHS20_REG CANBT3
-#define PHS21_REG CANBT3
-#define PHS22_REG CANBT3
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* CANBT1 */
-#define BRP0_REG CANBT1
-#define BRP1_REG CANBT1
-#define BRP2_REG CANBT1
-#define BRP3_REG CANBT1
-#define BRP4_REG CANBT1
-#define BRP5_REG CANBT1
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* OCR3BL */
-#define OCR3BL0_REG OCR3BL
-#define OCR3BL1_REG OCR3BL
-#define OCR3BL2_REG OCR3BL
-#define OCR3BL3_REG OCR3BL
-#define OCR3BL4_REG OCR3BL
-#define OCR3BL5_REG OCR3BL
-#define OCR3BL6_REG OCR3BL
-#define OCR3BL7_REG OCR3BL
-
-/* OCR3BH */
-#define OCR3BH0_REG OCR3BH
-#define OCR3BH1_REG OCR3BH
-#define OCR3BH2_REG OCR3BH
-#define OCR3BH3_REG OCR3BH
-#define OCR3BH4_REG OCR3BH
-#define OCR3BH5_REG OCR3BH
-#define OCR3BH6_REG OCR3BH
-#define OCR3BH7_REG OCR3BH
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-
-/* TIMSK3 */
-#define TOIE3_REG TIMSK3
-#define OCIE3A_REG TIMSK3
-#define OCIE3B_REG TIMSK3
-#define OCIE3C_REG TIMSK3
-#define ICIE3_REG TIMSK3
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define OCIE1C_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* XMCRB */
-#define XMM0_REG XMCRB
-#define XMM1_REG XMCRB
-#define XMM2_REG XMCRB
-#define XMBK_REG XMCRB
-
-/* XMCRA */
-#define SRW00_REG XMCRA
-#define SRW01_REG XMCRA
-#define SRW10_REG XMCRA
-#define SRW11_REG XMCRA
-#define SRL0_REG XMCRA
-#define SRL1_REG XMCRA
-#define SRL2_REG XMCRA
-#define SRE_REG XMCRA
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-#define INTF2_REG EIFR
-#define INTF3_REG EIFR
-#define INTF4_REG EIFR
-#define INTF5_REG EIFR
-#define INTF6_REG EIFR
-#define INTF7_REG EIFR
-
-/* PING */
-#define PING0_REG PING
-#define PING1_REG PING
-#define PING2_REG PING
-#define PING3_REG PING
-#define PING4_REG PING
-
-/* PINF */
-#define PINF0_REG PINF
-#define PINF1_REG PINF
-#define PINF2_REG PINF
-#define PINF3_REG PINF
-#define PINF4_REG PINF
-#define PINF5_REG PINF
-#define PINF6_REG PINF
-#define PINF7_REG PINF
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-#define PINE3_REG PINE
-#define PINE4_REG PINE
-#define PINE5_REG PINE
-#define PINE6_REG PINE
-#define PINE7_REG PINE
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-
-/* pins mapping */
-#define AD0_PORT PORTA
-#define AD0_BIT 0
-
-#define AD1_PORT PORTA
-#define AD1_BIT 1
-
-#define AD2_PORT PORTA
-#define AD2_BIT 2
-
-#define AD3_PORT PORTA
-#define AD3_BIT 3
-
-#define AD4_PORT PORTA
-#define AD4_BIT 4
-
-#define AD5_PORT PORTA
-#define AD5_BIT 5
-
-#define AD6_PORT PORTA
-#define AD6_BIT 6
-
-#define AD7_PORT PORTA
-#define AD7_BIT 7
-
-#define SS_PORT PORTB
-#define SS_BIT 0
-
-#define SCK_PORT PORTB
-#define SCK_BIT 1
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 2
-
-#define MISO_PORT PORTB
-#define MISO_BIT 3
-
-#define OC0_PORT PORTB
-#define OC0_BIT 4
-#define PWM0_PORT PORTB
-#define PWM0_BIT 4
-
-#define OC1A_PORT PORTB
-#define OC1A_BIT 5
-#define PWM1A_PORT PORTB
-#define PWM1A_BIT 5
-
-#define OC1B_PORT PORTB
-#define OC1B_BIT 6
-#define PWM1B_PORT PORTB
-#define PWM1B_BIT 6
-
-#define OC2_PORT PORTB
-#define OC2_BIT 7
-#define PWM2_PORT PORTB
-#define PWM2_BIT 7
-#define OC1C_PORT PORTB
-#define OC1C_BIT 7
-
-#define A8_PORT PORTC
-#define A8_BIT 0
-
-#define A9_PORT PORTC
-#define A9_BIT 1
-
-#define A10_PORT PORTC
-#define A10_BIT 2
-
-#define A11_PORT PORTC
-#define A11_BIT 3
-
-#define A12_PORT PORTC
-#define A12_BIT 4
-
-#define A13_PORT PORTC
-#define A13_BIT 5
-
-#define A14_PORT PORTC
-#define A14_BIT 6
-
-#define A15_PORT PORTC
-#define A15_BIT 7
-
-#define SCL_PORT PORTD
-#define SCL_BIT 0
-#define INT0_PORT PORTD
-#define INT0_BIT 0
-
-#define SDA_PORT PORTD
-#define SDA_BIT 1
-#define INT1_PORT PORTD
-#define INT1_BIT 1
-
-#define RXD1_PORT PORTD
-#define RXD1_BIT 2
-#define INT2_PORT PORTD
-#define INT2_BIT 2
-
-#define TXD1_PORT PORTD
-#define TXD1_BIT 3
-#define INT3_PORT PORTD
-#define INT3_BIT 3
-
-#define IC1_PORT PORTD
-#define IC1_BIT 4
-
-#define XCK1_PORT PORTD
-#define XCK1_BIT 5
-
-#define T1_PORT PORTD
-#define T1_BIT 6
-
-#define T2_PORT PORTD
-#define T2_BIT 7
-
-#define RXD0_PORT PORTE
-#define RXD0_BIT 0
-#define PDI_PORT PORTE
-#define PDI_BIT 0
-
-#define TXD0_PORT PORTE
-#define TXD0_BIT 1
-#define PDO_PORT PORTE
-#define PDO_BIT 1
-
-#define XCK0_PORT PORTE
-#define XCK0_BIT 2
-#define AIN0_PORT PORTE
-#define AIN0_BIT 2
-
-#define OC3A_PORT PORTE
-#define OC3A_BIT 3
-#define AIN1_PORT PORTE
-#define AIN1_BIT 3
-
-#define OC3B_PORT PORTE
-#define OC3B_BIT 4
-#define INT4_PORT PORTE
-#define INT4_BIT 4
-
-#define OC3C_PORT PORTE
-#define OC3C_BIT 5
-#define INT5_PORT PORTE
-#define INT5_BIT 5
-
-#define T3_PORT PORTE
-#define T3_BIT 6
-#define INT6_PORT PORTE
-#define INT6_BIT 6
-
-#define IC3_PORT PORTE
-#define IC3_BIT 7
-#define INT7_PORT PORTE
-#define INT7_BIT 7
-
-#define ADC0_PORT PORTF
-#define ADC0_BIT 0
-
-#define ADC1_PORT PORTF
-#define ADC1_BIT 1
-
-#define ADC2_PORT PORTF
-#define ADC2_BIT 2
-
-#define ADC3_PORT PORTF
-#define ADC3_BIT 3
-
-#define ADC4_PORT PORTF
-#define ADC4_BIT 4
-#define TCK_PORT PORTF
-#define TCK_BIT 4
-
-#define ADC5_PORT PORTF
-#define ADC5_BIT 5
-#define TMS_PORT PORTF
-#define TMS_BIT 5
-
-#define ADC6_PORT PORTF
-#define ADC6_BIT 6
-#define TD0_PORT PORTF
-#define TD0_BIT 6
-
-#define ADC7_PORT PORTF
-#define ADC7_BIT 7
-#define TDI_PORT PORTF
-#define TDI_BIT 7
-
-#define WR_PORT PORTG
-#define WR_BIT 0
-
-#define RD_PORT PORTG
-#define RD_BIT 1
-
-#define ALE_PORT PORTG
-#define ALE_BIT 2
-
-#define TOSC2_PORT PORTG
-#define TOSC2_BIT 3
-
-#define TOSC1_PORT PORTG
-#define TOSC1_BIT 4
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-/* prescalers timer 3 */
-#define TIMER3_PRESCALER_DIV_0 0
-#define TIMER3_PRESCALER_DIV_1 1
-#define TIMER3_PRESCALER_DIV_8 2
-#define TIMER3_PRESCALER_DIV_64 3
-#define TIMER3_PRESCALER_DIV_256 4
-#define TIMER3_PRESCALER_DIV_1024 5
-#define TIMER3_PRESCALER_DIV_FALL 6
-#define TIMER3_PRESCALER_DIV_RISE 7
-
-#define TIMER3_PRESCALER_REG_0 0
-#define TIMER3_PRESCALER_REG_1 1
-#define TIMER3_PRESCALER_REG_2 8
-#define TIMER3_PRESCALER_REG_3 64
-#define TIMER3_PRESCALER_REG_4 256
-#define TIMER3_PRESCALER_REG_5 1024
-#define TIMER3_PRESCALER_REG_6 -1
-#define TIMER3_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER1C_AVAILABLE
-#define TIMER2_AVAILABLE
-#define TIMER3_AVAILABLE
-#define TIMER3A_AVAILABLE
-#define TIMER3B_AVAILABLE
-#define TIMER3C_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW3_NUM 3
-#define SIG_OVERFLOW_TOTAL_NUM 4
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE1A_NUM 1
-#define SIG_OUTPUT_COMPARE1B_NUM 2
-#define SIG_OUTPUT_COMPARE1C_NUM 3
-#define SIG_OUTPUT_COMPARE2_NUM 4
-#define SIG_OUTPUT_COMPARE3A_NUM 5
-#define SIG_OUTPUT_COMPARE3B_NUM 6
-#define SIG_OUTPUT_COMPARE3C_NUM 7
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 8
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM1A_NUM 1
-#define PWM1B_NUM 2
-#define PWM1C_NUM 3
-#define PWM2_NUM 4
-#define PWM3A_NUM 5
-#define PWM3B_NUM 6
-#define PWM3C_NUM 7
-#define PWM_TOTAL_NUM 8
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE3_NUM 1
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 2
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* RAMPZ */
-#define RAMPZ0_REG RAMPZ
-
-/* OCR2A */
-#define OCR2A0_REG OCR2A
-#define OCR2A1_REG OCR2A
-#define OCR2A2_REG OCR2A
-#define OCR2A3_REG OCR2A
-#define OCR2A4_REG OCR2A
-#define OCR2A5_REG OCR2A
-#define OCR2A6_REG OCR2A
-#define OCR2A7_REG OCR2A
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-#define EEAR10_REG EEARH
-#define EEAR11_REG EEARH
-
-/* CANGSTA */
-#define ERRP_REG CANGSTA
-#define BOFF_REG CANGSTA
-#define ENFG_REG CANGSTA
-#define RXBSY_REG CANGSTA
-#define TXBSY_REG CANGSTA
-#define OVRG_REG CANGSTA
-
-/* CANGCON */
-#define SWRES_REG CANGCON
-#define ENASTB_REG CANGCON
-#define TEST_REG CANGCON
-#define LISTEN_REG CANGCON
-#define SYNTTC_REG CANGCON
-#define TTC_REG CANGCON
-#define OVRQ_REG CANGCON
-#define ABRQ_REG CANGCON
-
-/* PORTG */
-#define PORTG0_REG PORTG
-#define PORTG1_REG PORTG
-#define PORTG2_REG PORTG
-#define PORTG3_REG PORTG
-#define PORTG4_REG PORTG
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL0_REG UCSR0C
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* EEARL */
-#define EEARL0_REG EEARL
-#define EEARL1_REG EEARL
-#define EEARL2_REG EEARL
-#define EEARL3_REG EEARL
-#define EEARL4_REG EEARL
-#define EEARL5_REG EEARL
-#define EEARL6_REG EEARL
-#define EEARL7_REG EEARL
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-#define INT3_REG EIMSK
-#define INT4_REG EIMSK
-#define INT5_REG EIMSK
-#define INT6_REG EIMSK
-#define INT7_REG EIMSK
-
-/* UDR1 */
-#define UDR10_REG UDR1
-#define UDR11_REG UDR1
-#define UDR12_REG UDR1
-#define UDR13_REG UDR1
-#define UDR14_REG UDR1
-#define UDR15_REG UDR1
-#define UDR16_REG UDR1
-#define UDR17_REG UDR1
-
-/* UDR0 */
-#define UDR00_REG UDR0
-#define UDR01_REG UDR0
-#define UDR02_REG UDR0
-#define UDR03_REG UDR0
-#define UDR04_REG UDR0
-#define UDR05_REG UDR0
-#define UDR06_REG UDR0
-#define UDR07_REG UDR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* EICRB */
-#define ISC40_REG EICRB
-#define ISC41_REG EICRB
-#define ISC50_REG EICRB
-#define ISC51_REG EICRB
-#define ISC60_REG EICRB
-#define ISC61_REG EICRB
-#define ISC70_REG EICRB
-#define ISC71_REG EICRB
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-#define ISC20_REG EICRA
-#define ISC21_REG EICRA
-#define ISC30_REG EICRA
-#define ISC31_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* DDRF */
-#define DDF0_REG DDRF
-#define DDF1_REG DDRF
-#define DDF2_REG DDRF
-#define DDF3_REG DDRF
-#define DDF4_REG DDRF
-#define DDF5_REG DDRF
-#define DDF6_REG DDRF
-#define DDF7_REG DDRF
-
-/* ASSR */
-#define TCR2UB_REG ASSR
-#define OCR2UB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* CANIDM1 */
-#define IDMSK21_REG CANIDM1
-#define IDMSK22_REG CANIDM1
-#define IDMSK23_REG CANIDM1
-#define IDMSK24_REG CANIDM1
-#define IDMSK25_REG CANIDM1
-#define IDMSK26_REG CANIDM1
-#define IDMSK27_REG CANIDM1
-#define IDMSK28_REG CANIDM1
-
-/* CANIDM3 */
-#define IDMSK5_REG CANIDM3
-#define IDMSK6_REG CANIDM3
-#define IDMSK7_REG CANIDM3
-#define IDMSK8_REG CANIDM3
-#define IDMSK9_REG CANIDM3
-#define IDMSK10_REG CANIDM3
-#define IDMSK11_REG CANIDM3
-#define IDMSK12_REG CANIDM3
-
-/* CANIDM2 */
-#define IDMSK13_REG CANIDM2
-#define IDMSK14_REG CANIDM2
-#define IDMSK15_REG CANIDM2
-#define IDMSK16_REG CANIDM2
-#define IDMSK17_REG CANIDM2
-#define IDMSK18_REG CANIDM2
-#define IDMSK19_REG CANIDM2
-#define IDMSK20_REG CANIDM2
-
-/* CANIDM4 */
-#define IDEMSK_REG CANIDM4
-#define RTRMSK_REG CANIDM4
-#define IDMSK0_REG CANIDM4
-#define IDMSK1_REG CANIDM4
-#define IDMSK2_REG CANIDM4
-#define IDMSK3_REG CANIDM4
-#define IDMSK4_REG CANIDM4
-
-/* UBRR1L */
-/* #define UBRR0_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR1_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR2_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR3_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR4_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR5_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR6_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR7_REG UBRR1L */ /* dup in UBRR0L */
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* OCR3AL */
-#define OCR3AL0_REG OCR3AL
-#define OCR3AL1_REG OCR3AL
-#define OCR3AL2_REG OCR3AL
-#define OCR3AL3_REG OCR3AL
-#define OCR3AL4_REG OCR3AL
-#define OCR3AL5_REG OCR3AL
-#define OCR3AL6_REG OCR3AL
-#define OCR3AL7_REG OCR3AL
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* UBRR1H */
-/* #define UBRR8_REG UBRR1H */ /* dup in UBRR0H */
-/* #define UBRR9_REG UBRR1H */ /* dup in UBRR0H */
-/* #define UBRR10_REG UBRR1H */ /* dup in UBRR0H */
-/* #define UBRR11_REG UBRR1H */ /* dup in UBRR0H */
-
-/* DDRG */
-#define DDG0_REG DDRG
-#define DDG1_REG DDRG
-#define DDG2_REG DDRG
-#define DDG3_REG DDRG
-#define DDG4_REG DDRG
-
-/* OCR3AH */
-#define OCR3AH0_REG OCR3AH
-#define OCR3AH1_REG OCR3AH
-#define OCR3AH2_REG OCR3AH
-#define OCR3AH3_REG OCR3AH
-#define OCR3AH4_REG OCR3AH
-#define OCR3AH5_REG OCR3AH
-#define OCR3AH6_REG OCR3AH
-#define OCR3AH7_REG OCR3AH
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* CANGIT */
-#define AERG_REG CANGIT
-#define FERG_REG CANGIT
-#define CERG_REG CANGIT
-#define SERG_REG CANGIT
-#define BXOK_REG CANGIT
-#define OVRTIM_REG CANGIT
-#define BOFFIT_REG CANGIT
-#define CANIT_REG CANGIT
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* CANGIE */
-#define ENOVRT_REG CANGIE
-#define ENERG_REG CANGIE
-#define ENBX_REG CANGIE
-#define ENERR_REG CANGIE
-#define ENTX_REG CANGIE
-#define ENRX_REG CANGIE
-#define ENBOFF_REG CANGIE
-#define ENIT_REG CANGIE
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* CANIE2 */
-#define IEMOB0_REG CANIE2
-#define IEMOB1_REG CANIE2
-#define IEMOB2_REG CANIE2
-#define IEMOB3_REG CANIE2
-#define IEMOB4_REG CANIE2
-#define IEMOB5_REG CANIE2
-#define IEMOB6_REG CANIE2
-#define IEMOB7_REG CANIE2
-
-/* TCCR3C */
-#define FOC3C_REG TCCR3C
-#define FOC3B_REG TCCR3C
-#define FOC3A_REG TCCR3C
-
-/* CANIE1 */
-#define IEMOB8_REG CANIE1
-#define IEMOB9_REG CANIE1
-#define IEMOB10_REG CANIE1
-#define IEMOB11_REG CANIE1
-#define IEMOB12_REG CANIE1
-#define IEMOB13_REG CANIE1
-#define IEMOB14_REG CANIE1
-
-/* TCCR0A */
-#define CS00_REG TCCR0A
-#define CS01_REG TCCR0A
-#define CS02_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-#define WGM00_REG TCCR0A
-#define FOC0A_REG TCCR0A
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-
-/* TIFR3 */
-#define TOV3_REG TIFR3
-#define OCF3A_REG TIFR3
-#define OCF3B_REG TIFR3
-#define OCF3C_REG TIFR3
-#define ICF3_REG TIFR3
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define OCF1C_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* CANIDT4 */
-#define RB0TAG_REG CANIDT4
-#define RB1TAG_REG CANIDT4
-#define RTRTAG_REG CANIDT4
-#define IDT0_REG CANIDT4
-#define IDT1_REG CANIDT4
-#define IDT2_REG CANIDT4
-#define IDT3_REG CANIDT4
-#define IDT4_REG CANIDT4
-
-/* CANIDT2 */
-#define IDT13_REG CANIDT2
-#define IDT14_REG CANIDT2
-#define IDT15_REG CANIDT2
-#define IDT16_REG CANIDT2
-#define IDT17_REG CANIDT2
-#define IDT18_REG CANIDT2
-#define IDT19_REG CANIDT2
-#define IDT20_REG CANIDT2
-
-/* CANIDT3 */
-#define IDT5_REG CANIDT3
-#define IDT6_REG CANIDT3
-#define IDT7_REG CANIDT3
-#define IDT8_REG CANIDT3
-#define IDT9_REG CANIDT3
-#define IDT10_REG CANIDT3
-#define IDT11_REG CANIDT3
-#define IDT12_REG CANIDT3
-
-/* CANIDT1 */
-#define IDT21_REG CANIDT1
-#define IDT22_REG CANIDT1
-#define IDT23_REG CANIDT1
-#define IDT24_REG CANIDT1
-#define IDT25_REG CANIDT1
-#define IDT26_REG CANIDT1
-#define IDT27_REG CANIDT1
-#define IDT28_REG CANIDT1
-
-/* CANSIT1 */
-#define SIT8_REG CANSIT1
-#define SIT9_REG CANSIT1
-#define SIT10_REG CANSIT1
-#define SIT11_REG CANSIT1
-#define SIT12_REG CANSIT1
-#define SIT13_REG CANSIT1
-#define SIT14_REG CANSIT1
-
-/* OCR3CH */
-#define OCR3CH0_REG OCR3CH
-#define OCR3CH1_REG OCR3CH
-#define OCR3CH2_REG OCR3CH
-#define OCR3CH3_REG OCR3CH
-#define OCR3CH4_REG OCR3CH
-#define OCR3CH5_REG OCR3CH
-#define OCR3CH6_REG OCR3CH
-#define OCR3CH7_REG OCR3CH
-
-/* OCR3CL */
-#define OCR3CL0_REG OCR3CL
-#define OCR3CL1_REG OCR3CL
-#define OCR3CL2_REG OCR3CL
-#define OCR3CL3_REG OCR3CL
-#define OCR3CL4_REG OCR3CL
-#define OCR3CL5_REG OCR3CL
-#define OCR3CL6_REG OCR3CL
-#define OCR3CL7_REG OCR3CL
-
-/* GTCCR */
-#define PSR310_REG GTCCR
-#define TSM_REG GTCCR
-#define PSR2_REG GTCCR
-
-/* CANCDMOB */
-#define DLC0_REG CANCDMOB
-#define DLC1_REG CANCDMOB
-#define DLC2_REG CANCDMOB
-#define DLC3_REG CANCDMOB
-#define IDE_REG CANCDMOB
-#define RPLV_REG CANCDMOB
-#define CONMOB0_REG CANCDMOB
-#define CONMOB1_REG CANCDMOB
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* CANSIT2 */
-#define SIT0_REG CANSIT2
-#define SIT1_REG CANSIT2
-#define SIT2_REG CANSIT2
-#define SIT3_REG CANSIT2
-#define SIT4_REG CANSIT2
-#define SIT5_REG CANSIT2
-#define SIT6_REG CANSIT2
-#define SIT7_REG CANSIT2
-
-/* CANHPMOB */
-#define CGP0_REG CANHPMOB
-#define CGP1_REG CANHPMOB
-#define CGP2_REG CANHPMOB
-#define CGP3_REG CANHPMOB
-#define HPMOB0_REG CANHPMOB
-#define HPMOB1_REG CANHPMOB
-#define HPMOB2_REG CANHPMOB
-#define HPMOB3_REG CANHPMOB
-
-/* TCCR3B */
-#define CS30_REG TCCR3B
-#define CS31_REG TCCR3B
-#define CS32_REG TCCR3B
-#define WGM32_REG TCCR3B
-#define WGM33_REG TCCR3B
-#define ICES3_REG TCCR3B
-#define ICNC3_REG TCCR3B
-
-/* TCCR3A */
-#define WGM30_REG TCCR3A
-#define WGM31_REG TCCR3A
-#define COM3C0_REG TCCR3A
-#define COM3C1_REG TCCR3A
-#define COM3B0_REG TCCR3A
-#define COM3B1_REG TCCR3A
-#define COM3A0_REG TCCR3A
-#define COM3A1_REG TCCR3A
-
-/* PORTF */
-#define PORTF0_REG PORTF
-#define PORTF1_REG PORTF
-#define PORTF2_REG PORTF
-#define PORTF3_REG PORTF
-#define PORTF4_REG PORTF
-#define PORTF5_REG PORTF
-#define PORTF6_REG PORTF
-#define PORTF7_REG PORTF
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* TCNT3H */
-#define TCNT3H0_REG TCNT3H
-#define TCNT3H1_REG TCNT3H
-#define TCNT3H2_REG TCNT3H
-#define TCNT3H3_REG TCNT3H
-#define TCNT3H4_REG TCNT3H
-#define TCNT3H5_REG TCNT3H
-#define TCNT3H6_REG TCNT3H
-#define TCNT3H7_REG TCNT3H
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* TCNT3L */
-#define TCNT3L0_REG TCNT3L
-#define TCNT3L1_REG TCNT3L
-#define TCNT3L2_REG TCNT3L
-#define TCNT3L3_REG TCNT3L
-#define TCNT3L4_REG TCNT3L
-#define TCNT3L5_REG TCNT3L
-#define TCNT3L6_REG TCNT3L
-#define TCNT3L7_REG TCNT3L
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* MCUSR */
-#define JTRF_REG MCUSR
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* TCCR2A */
-#define CS20_REG TCCR2A
-#define CS21_REG TCCR2A
-#define CS22_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-#define WGM20_REG TCCR2A
-#define FOC2A_REG TCCR2A
-
-/* UBRR0H */
-/* #define UBRR8_REG UBRR0H */ /* dup in UBRR1H */
-/* #define UBRR9_REG UBRR0H */ /* dup in UBRR1H */
-/* #define UBRR10_REG UBRR0H */ /* dup in UBRR1H */
-/* #define UBRR11_REG UBRR0H */ /* dup in UBRR1H */
-
-/* UBRR0L */
-/* #define UBRR0_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR1_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR2_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR3_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR4_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR5_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR6_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR7_REG UBRR0L */ /* dup in UBRR1L */
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* CANPAGE */
-#define INDX0_REG CANPAGE
-#define INDX1_REG CANPAGE
-#define INDX2_REG CANPAGE
-#define AINC_REG CANPAGE
-#define MOBNB0_REG CANPAGE
-#define MOBNB1_REG CANPAGE
-#define MOBNB2_REG CANPAGE
-#define MOBNB3_REG CANPAGE
-
-/* MCUCR */
-#define JTD_REG MCUCR
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* OCR1CL */
-#define OCR1CL0_REG OCR1CL
-#define OCR1CL1_REG OCR1CL
-#define OCR1CL2_REG OCR1CL
-#define OCR1CL3_REG OCR1CL
-#define OCR1CL4_REG OCR1CL
-#define OCR1CL5_REG OCR1CL
-#define OCR1CL6_REG OCR1CL
-#define OCR1CL7_REG OCR1CL
-
-/* OCR1CH */
-#define OCR1CH0_REG OCR1CH
-#define OCR1CH1_REG OCR1CH
-#define OCR1CH2_REG OCR1CH
-#define OCR1CH3_REG OCR1CH
-#define OCR1CH4_REG OCR1CH
-#define OCR1CH5_REG OCR1CH
-#define OCR1CH6_REG OCR1CH
-#define OCR1CH7_REG OCR1CH
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* CANSTMOB */
-#define AERR_REG CANSTMOB
-#define FERR_REG CANSTMOB
-#define CERR_REG CANSTMOB
-#define SERR_REG CANSTMOB
-#define BERR_REG CANSTMOB
-#define RXOK_REG CANSTMOB
-#define TXOK_REG CANSTMOB
-#define DLCW_REG CANSTMOB
-
-/* UCSR1B */
-#define TXB81_REG UCSR1B
-#define RXB81_REG UCSR1B
-#define UCSZ12_REG UCSR1B
-#define TXEN1_REG UCSR1B
-#define RXEN1_REG UCSR1B
-#define UDRIE1_REG UCSR1B
-#define TXCIE1_REG UCSR1B
-#define RXCIE1_REG UCSR1B
-
-/* UCSR1C */
-#define UCPOL1_REG UCSR1C
-#define UCSZ10_REG UCSR1C
-#define UCSZ11_REG UCSR1C
-#define USBS1_REG UCSR1C
-#define UPM10_REG UCSR1C
-#define UPM11_REG UCSR1C
-#define UMSEL1_REG UCSR1C
-
-/* UCSR1A */
-#define MPCM1_REG UCSR1A
-#define U2X1_REG UCSR1A
-#define UPE1_REG UCSR1A
-#define DOR1_REG UCSR1A
-#define FE1_REG UCSR1A
-#define UDRE1_REG UCSR1A
-#define TXC1_REG UCSR1A
-#define RXC1_REG UCSR1A
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* CANEN2 */
-#define ENMOB0_REG CANEN2
-#define ENMOB1_REG CANEN2
-#define ENMOB2_REG CANEN2
-#define ENMOB3_REG CANEN2
-#define ENMOB4_REG CANEN2
-#define ENMOB5_REG CANEN2
-#define ENMOB6_REG CANEN2
-#define ENMOB7_REG CANEN2
-
-/* CANEN1 */
-#define ENMOB8_REG CANEN1
-#define ENMOB9_REG CANEN1
-#define ENMOB10_REG CANEN1
-#define ENMOB11_REG CANEN1
-#define ENMOB12_REG CANEN1
-#define ENMOB13_REG CANEN1
-#define ENMOB14_REG CANEN1
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ADHSM_REG ADCSRB
-#define ACME_REG ADCSRB
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1C0_REG TCCR1A
-#define COM1C1_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* OCR0A */
-#define OCR0A0_REG OCR0A
-#define OCR0A1_REG OCR0A
-#define OCR0A2_REG OCR0A
-#define OCR0A3_REG OCR0A
-#define OCR0A4_REG OCR0A
-#define OCR0A5_REG OCR0A
-#define OCR0A6_REG OCR0A
-#define OCR0A7_REG OCR0A
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* TCCR1C */
-#define FOC1C_REG TCCR1C
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* ICR3H */
-#define ICR3H0_REG ICR3H
-#define ICR3H1_REG ICR3H
-#define ICR3H2_REG ICR3H
-#define ICR3H3_REG ICR3H
-#define ICR3H4_REG ICR3H
-#define ICR3H5_REG ICR3H
-#define ICR3H6_REG ICR3H
-#define ICR3H7_REG ICR3H
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-#define DDE3_REG DDRE
-#define DDE4_REG DDRE
-#define DDE5_REG DDRE
-#define DDE6_REG DDRE
-#define DDE7_REG DDRE
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* ICR3L */
-#define ICR3L0_REG ICR3L
-#define ICR3L1_REG ICR3L
-#define ICR3L2_REG ICR3L
-#define ICR3L3_REG ICR3L
-#define ICR3L4_REG ICR3L
-#define ICR3L5_REG ICR3L
-#define ICR3L6_REG ICR3L
-#define ICR3L7_REG ICR3L
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-#define PORTE3_REG PORTE
-#define PORTE4_REG PORTE
-#define PORTE5_REG PORTE
-#define PORTE6_REG PORTE
-#define PORTE7_REG PORTE
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* CANBT2 */
-#define PRS0_REG CANBT2
-#define PRS1_REG CANBT2
-#define PRS2_REG CANBT2
-#define SJW0_REG CANBT2
-#define SJW1_REG CANBT2
-
-/* CANBT3 */
-#define SMP_REG CANBT3
-#define PHS10_REG CANBT3
-#define PHS11_REG CANBT3
-#define PHS12_REG CANBT3
-#define PHS20_REG CANBT3
-#define PHS21_REG CANBT3
-#define PHS22_REG CANBT3
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* CANBT1 */
-#define BRP0_REG CANBT1
-#define BRP1_REG CANBT1
-#define BRP2_REG CANBT1
-#define BRP3_REG CANBT1
-#define BRP4_REG CANBT1
-#define BRP5_REG CANBT1
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* OCR3BL */
-#define OCR3BL0_REG OCR3BL
-#define OCR3BL1_REG OCR3BL
-#define OCR3BL2_REG OCR3BL
-#define OCR3BL3_REG OCR3BL
-#define OCR3BL4_REG OCR3BL
-#define OCR3BL5_REG OCR3BL
-#define OCR3BL6_REG OCR3BL
-#define OCR3BL7_REG OCR3BL
-
-/* OCR3BH */
-#define OCR3BH0_REG OCR3BH
-#define OCR3BH1_REG OCR3BH
-#define OCR3BH2_REG OCR3BH
-#define OCR3BH3_REG OCR3BH
-#define OCR3BH4_REG OCR3BH
-#define OCR3BH5_REG OCR3BH
-#define OCR3BH6_REG OCR3BH
-#define OCR3BH7_REG OCR3BH
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-
-/* TIMSK3 */
-#define TOIE3_REG TIMSK3
-#define OCIE3A_REG TIMSK3
-#define OCIE3B_REG TIMSK3
-#define OCIE3C_REG TIMSK3
-#define ICIE3_REG TIMSK3
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define OCIE1C_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* XMCRB */
-#define XMM0_REG XMCRB
-#define XMM1_REG XMCRB
-#define XMM2_REG XMCRB
-#define XMBK_REG XMCRB
-
-/* XMCRA */
-#define SRW00_REG XMCRA
-#define SRW01_REG XMCRA
-#define SRW10_REG XMCRA
-#define SRW11_REG XMCRA
-#define SRL0_REG XMCRA
-#define SRL1_REG XMCRA
-#define SRL2_REG XMCRA
-#define SRE_REG XMCRA
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-#define INTF2_REG EIFR
-#define INTF3_REG EIFR
-#define INTF4_REG EIFR
-#define INTF5_REG EIFR
-#define INTF6_REG EIFR
-#define INTF7_REG EIFR
-
-/* PING */
-#define PING0_REG PING
-#define PING1_REG PING
-#define PING2_REG PING
-#define PING3_REG PING
-#define PING4_REG PING
-
-/* PINF */
-#define PINF0_REG PINF
-#define PINF1_REG PINF
-#define PINF2_REG PINF
-#define PINF3_REG PINF
-#define PINF4_REG PINF
-#define PINF5_REG PINF
-#define PINF6_REG PINF
-#define PINF7_REG PINF
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-#define PINE3_REG PINE
-#define PINE4_REG PINE
-#define PINE5_REG PINE
-#define PINE6_REG PINE
-#define PINE7_REG PINE
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-
-/* pins mapping */
-#define AD0_PORT PORTA
-#define AD0_BIT 0
-
-#define AD1_PORT PORTA
-#define AD1_BIT 1
-
-#define AD2_PORT PORTA
-#define AD2_BIT 2
-
-#define AD3_PORT PORTA
-#define AD3_BIT 3
-
-#define AD4_PORT PORTA
-#define AD4_BIT 4
-
-#define AD5_PORT PORTA
-#define AD5_BIT 5
-
-#define AD6_PORT PORTA
-#define AD6_BIT 6
-
-#define AD7_PORT PORTA
-#define AD7_BIT 7
-
-#define SS_PORT PORTB
-#define SS_BIT 0
-
-#define SCK_PORT PORTB
-#define SCK_BIT 1
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 2
-
-#define MISO_PORT PORTB
-#define MISO_BIT 3
-
-#define OC0_PORT PORTB
-#define OC0_BIT 4
-#define PWM0_PORT PORTB
-#define PWM0_BIT 4
-
-#define OC1A_PORT PORTB
-#define OC1A_BIT 5
-#define PWM1A_PORT PORTB
-#define PWM1A_BIT 5
-
-#define OC1B_PORT PORTB
-#define OC1B_BIT 6
-#define PWM1B_PORT PORTB
-#define PWM1B_BIT 6
-
-#define OC2_PORT PORTB
-#define OC2_BIT 7
-#define PWM2_PORT PORTB
-#define PWM2_BIT 7
-#define OC1C_PORT PORTB
-#define OC1C_BIT 7
-
-#define A8_PORT PORTC
-#define A8_BIT 0
-
-#define A9_PORT PORTC
-#define A9_BIT 1
-
-#define A10_PORT PORTC
-#define A10_BIT 2
-
-#define A11_PORT PORTC
-#define A11_BIT 3
-
-#define A12_PORT PORTC
-#define A12_BIT 4
-
-#define A13_PORT PORTC
-#define A13_BIT 5
-
-#define A14_PORT PORTC
-#define A14_BIT 6
-
-#define A15_PORT PORTC
-#define A15_BIT 7
-
-#define SCL_PORT PORTD
-#define SCL_BIT 0
-#define INT0_PORT PORTD
-#define INT0_BIT 0
-
-#define SDA_PORT PORTD
-#define SDA_BIT 1
-#define INT1_PORT PORTD
-#define INT1_BIT 1
-
-#define RXD1_PORT PORTD
-#define RXD1_BIT 2
-#define INT2_PORT PORTD
-#define INT2_BIT 2
-
-#define TXD1_PORT PORTD
-#define TXD1_BIT 3
-#define INT3_PORT PORTD
-#define INT3_BIT 3
-
-#define IC1_PORT PORTD
-#define IC1_BIT 4
-
-#define XCK1_PORT PORTD
-#define XCK1_BIT 5
-
-#define T1_PORT PORTD
-#define T1_BIT 6
-
-#define T2_PORT PORTD
-#define T2_BIT 7
-
-#define RXD0_PORT PORTE
-#define RXD0_BIT 0
-#define PDI_PORT PORTE
-#define PDI_BIT 0
-
-#define TXD0_PORT PORTE
-#define TXD0_BIT 1
-#define PDO_PORT PORTE
-#define PDO_BIT 1
-
-#define XCK0_PORT PORTE
-#define XCK0_BIT 2
-#define AIN0_PORT PORTE
-#define AIN0_BIT 2
-
-#define OC3A_PORT PORTE
-#define OC3A_BIT 3
-#define AIN1_PORT PORTE
-#define AIN1_BIT 3
-
-#define OC3B_PORT PORTE
-#define OC3B_BIT 4
-#define INT4_PORT PORTE
-#define INT4_BIT 4
-
-#define OC3C_PORT PORTE
-#define OC3C_BIT 5
-#define INT5_PORT PORTE
-#define INT5_BIT 5
-
-#define T3_PORT PORTE
-#define T3_BIT 6
-#define INT6_PORT PORTE
-#define INT6_BIT 6
-
-#define IC3_PORT PORTE
-#define IC3_BIT 7
-#define INT7_PORT PORTE
-#define INT7_BIT 7
-
-#define ADC0_PORT PORTF
-#define ADC0_BIT 0
-
-#define ADC1_PORT PORTF
-#define ADC1_BIT 1
-
-#define ADC2_PORT PORTF
-#define ADC2_BIT 2
-
-#define ADC3_PORT PORTF
-#define ADC3_BIT 3
-
-#define ADC4_PORT PORTF
-#define ADC4_BIT 4
-#define TCK_PORT PORTF
-#define TCK_BIT 4
-
-#define ADC5_PORT PORTF
-#define ADC5_BIT 5
-#define TMS_PORT PORTF
-#define TMS_BIT 5
-
-#define ADC6_PORT PORTF
-#define ADC6_BIT 6
-#define TD0_PORT PORTF
-#define TD0_BIT 6
-
-#define ADC7_PORT PORTF
-#define ADC7_BIT 7
-#define TDI_PORT PORTF
-#define TDI_BIT 7
-
-#define WR_PORT PORTG
-#define WR_BIT 0
-
-#define RD_PORT PORTG
-#define RD_BIT 1
-
-#define ALE_PORT PORTG
-#define ALE_BIT 2
-
-#define TOSC2_PORT PORTG
-#define TOSC2_BIT 3
-
-#define TOSC1_PORT PORTG
-#define TOSC1_BIT 4
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW_TOTAL_NUM 2
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* EUDR */
-#define EUDR0_REG EUDR
-#define EUDR1_REG EUDR
-#define EUDR2_REG EUDR
-#define EUDR3_REG EUDR
-#define EUDR4_REG EUDR
-#define EUDR5_REG EUDR
-#define EUDR6_REG EUDR
-#define EUDR7_REG EUDR
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* OCR2SBH */
-#define OCR2SB_8_REG OCR2SBH
-#define OCR2SB_9_REG OCR2SBH
-#define OCR2SB_10_REG OCR2SBH
-#define OCR2SB_11_REG OCR2SBH
-
-/* OCR2SBL */
-#define OCR2SB_0_REG OCR2SBL
-#define OCR2SB_1_REG OCR2SBL
-#define OCR2SB_2_REG OCR2SBL
-#define OCR2SB_3_REG OCR2SBL
-#define OCR2SB_4_REG OCR2SBL
-#define OCR2SB_5_REG OCR2SBL
-#define OCR2SB_6_REG OCR2SBL
-#define OCR2SB_7_REG OCR2SBL
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* OCR0B */
-/* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */
-
-/* OCR0SAL */
-#define OCR0SA_0_REG OCR0SAL
-#define OCR0SA_1_REG OCR0SAL
-#define OCR0SA_2_REG OCR0SAL
-#define OCR0SA_3_REG OCR0SAL
-#define OCR0SA_4_REG OCR0SAL
-#define OCR0SA_5_REG OCR0SAL
-#define OCR0SA_6_REG OCR0SAL
-#define OCR0SA_7_REG OCR0SAL
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* UCSRA */
-#define MPCM_REG UCSRA
-#define U2X_REG UCSRA
-#define UPE_REG UCSRA
-#define DOR_REG UCSRA
-#define FE_REG UCSRA
-#define UDRE_REG UCSRA
-#define TXC_REG UCSRA
-#define RXC_REG UCSRA
-
-/* UCSRB */
-#define TXB8_REG UCSRB
-#define RXB8_REG UCSRB
-#define UCSZ2_REG UCSRB
-#define TXEN_REG UCSRB
-#define RXEN_REG UCSRB
-#define UDRIE_REG UCSRB
-#define TXCIE_REG UCSRB
-#define RXCIE_REG UCSRB
-
-/* UCSRC */
-#define UCPOL_REG UCSRC
-#define UCSZ0_REG UCSRC
-#define UCSZ1_REG UCSRC
-#define USBS_REG UCSRC
-#define UPM0_REG UCSRC
-#define UPM1_REG UCSRC
-#define UMSEL0_REG UCSRC
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* AC1CON */
-#define AC1M0_REG AC1CON
-#define AC1M1_REG AC1CON
-#define AC1M2_REG AC1CON
-#define AC1ICE_REG AC1CON
-#define AC1IS0_REG AC1CON
-#define AC1IS1_REG AC1CON
-#define AC1IE_REG AC1CON
-#define AC1EN_REG AC1CON
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSART0_REG PRR
-#define PRSPI_REG PRR
-#define PRTIM0_REG PRR
-#define PRTIM1_REG PRR
-#define PRPSC0_REG PRR
-#define PRPSC1_REG PRR
-#define PRPSC2_REG PRR
-
-/* PCNF0 */
-#define PCLKSEL0_REG PCNF0
-#define POP0_REG PCNF0
-#define PMODE00_REG PCNF0
-#define PMODE01_REG PCNF0
-#define PLOCK0_REG PCNF0
-#define PALOCK0_REG PCNF0
-#define PFIFTY0_REG PCNF0
-
-/* PCNF2 */
-#define POME2_REG PCNF2
-#define PCLKSEL2_REG PCNF2
-#define POP2_REG PCNF2
-#define PMODE20_REG PCNF2
-#define PMODE21_REG PCNF2
-#define PLOCK2_REG PCNF2
-#define PALOCK2_REG PCNF2
-#define PFIFTY2_REG PCNF2
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* AMP1CSR */
-#define AMP1TS0_REG AMP1CSR
-#define AMP1TS1_REG AMP1CSR
-#define AMP1G0_REG AMP1CSR
-#define AMP1G1_REG AMP1CSR
-#define AMP1IS_REG AMP1CSR
-#define AMP1EN_REG AMP1CSR
-
-/* AC2CON */
-#define AC2M0_REG AC2CON
-#define AC2M1_REG AC2CON
-#define AC2M2_REG AC2CON
-#define AC2IS0_REG AC2CON
-#define AC2IS1_REG AC2CON
-#define AC2IE_REG AC2CON
-#define AC2EN_REG AC2CON
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-
-/* PFRC0A */
-#define PRFM0A0_REG PFRC0A
-#define PRFM0A1_REG PFRC0A
-#define PRFM0A2_REG PFRC0A
-#define PRFM0A3_REG PFRC0A
-#define PFLTE0A_REG PFRC0A
-#define PELEV0A_REG PFRC0A
-#define PISEL0A_REG PFRC0A
-#define PCAE0A_REG PFRC0A
-
-/* PFRC0B */
-#define PRFM0B0_REG PFRC0B
-#define PRFM0B1_REG PFRC0B
-#define PRFM0B2_REG PFRC0B
-#define PRFM0B3_REG PFRC0B
-#define PFLTE0B_REG PFRC0B
-#define PELEV0B_REG PFRC0B
-#define PISEL0B_REG PFRC0B
-#define PCAE0B_REG PFRC0B
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-#define ISC20_REG EICRA
-#define ISC21_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define ADC8D_REG DIDR1
-#define ADC9D_REG DIDR1
-#define ADC10D_REG DIDR1
-#define AMP0ND_REG DIDR1
-#define AMP0PD_REG DIDR1
-#define ACMP0D_REG DIDR1
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* OCR0RBH */
-#define OCR0RB_8_REG OCR0RBH
-#define OCR0RB_9_REG OCR0RBH
-#define OCR0RB_00_REG OCR0RBH
-#define OCR0RB_01_REG OCR0RBH
-#define OCR0RB_02_REG OCR0RBH
-#define OCR0RB_03_REG OCR0RBH
-#define OCR0RB_04_REG OCR0RBH
-#define OCR0RB_05_REG OCR0RBH
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* PIM2 */
-#define PEOPE2_REG PIM2
-#define PEVE2A_REG PIM2
-#define PEVE2B_REG PIM2
-#define PSEIE2_REG PIM2
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-
-/* OCR0RAL */
-#define OCR0RA_0_REG OCR0RAL
-#define OCR0RA_1_REG OCR0RAL
-#define OCR0RA_2_REG OCR0RAL
-#define OCR0RA_3_REG OCR0RAL
-#define OCR0RA_4_REG OCR0RAL
-#define OCR0RA_5_REG OCR0RAL
-#define OCR0RA_6_REG OCR0RAL
-#define OCR0RA_7_REG OCR0RAL
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR3 */
-#define GPIOR30_REG GPIOR3
-#define GPIOR31_REG GPIOR3
-#define GPIOR32_REG GPIOR3
-#define GPIOR33_REG GPIOR3
-#define GPIOR34_REG GPIOR3
-#define GPIOR35_REG GPIOR3
-#define GPIOR36_REG GPIOR3
-#define GPIOR37_REG GPIOR3
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* PIFR0 */
-#define PEOP0_REG PIFR0
-#define PRN00_REG PIFR0
-#define PRN01_REG PIFR0
-#define PEV0A_REG PIFR0
-#define PEV0B_REG PIFR0
-#define PSEI0_REG PIFR0
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* PFRC2B */
-#define PRFM2B0_REG PFRC2B
-#define PRFM2B1_REG PFRC2B
-#define PRFM2B2_REG PFRC2B
-#define PRFM2B3_REG PFRC2B
-#define PFLTE2B_REG PFRC2B
-#define PELEV2B_REG PFRC2B
-#define PISEL2B_REG PFRC2B
-#define PCAE2B_REG PFRC2B
-
-/* PFRC2A */
-#define PRFM2A0_REG PFRC2A
-#define PRFM2A1_REG PFRC2A
-#define PRFM2A2_REG PFRC2A
-#define PRFM2A3_REG PFRC2A
-#define PFLTE2A_REG PFRC2A
-#define PELEV2A_REG PFRC2A
-#define PISEL2A_REG PFRC2A
-#define PCAE2A_REG PFRC2A
-
-/* OCR2SAL */
-#define OCR2SA_0_REG OCR2SAL
-#define OCR2SA_1_REG OCR2SAL
-#define OCR2SA_2_REG OCR2SAL
-#define OCR2SA_3_REG OCR2SAL
-#define OCR2SA_4_REG OCR2SAL
-#define OCR2SA_5_REG OCR2SAL
-#define OCR2SA_6_REG OCR2SAL
-#define OCR2SA_7_REG OCR2SAL
-
-/* EUCSRA */
-#define URxS0_REG EUCSRA
-#define URxS1_REG EUCSRA
-#define URxS2_REG EUCSRA
-#define URxS3_REG EUCSRA
-#define UTxS0_REG EUCSRA
-#define UTxS1_REG EUCSRA
-#define UTxS2_REG EUCSRA
-#define UTxS3_REG EUCSRA
-
-/* EUCSRB */
-#define BODR_REG EUCSRB
-#define EMCH_REG EUCSRB
-#define EUSBS_REG EUCSRB
-#define EUSART_REG EUCSRB
-
-/* EUCSRC */
-#define STP0_REG EUCSRC
-#define STP1_REG EUCSRC
-#define F1617_REG EUCSRC
-#define FEM_REG EUCSRC
-
-/* PCTL0 */
-#define PRUN0_REG PCTL0
-#define PCCYC0_REG PCTL0
-#define PARUN0_REG PCTL0
-#define PAOC0A_REG PCTL0
-#define PAOC0B_REG PCTL0
-#define PBFM0_REG PCTL0
-#define PPRE00_REG PCTL0
-#define PPRE01_REG PCTL0
-
-/* PCTL2 */
-#define PRUN2_REG PCTL2
-#define PCCYC2_REG PCTL2
-#define PARUN2_REG PCTL2
-#define PAOC2A_REG PCTL2
-#define PAOC2B_REG PCTL2
-#define PBFM2_REG PCTL2
-#define PPRE20_REG PCTL2
-#define PPRE21_REG PCTL2
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* GTCCR */
-#define PSR10_REG GTCCR
-#define ICPSEL1_REG GTCCR
-#define TSM_REG GTCCR
-#define PSRSYNC_REG GTCCR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* POM2 */
-#define POMV2A0_REG POM2
-#define POMV2A1_REG POM2
-#define POMV2A2_REG POM2
-#define POMV2A3_REG POM2
-#define POMV2B0_REG POM2
-#define POMV2B1_REG POM2
-#define POMV2B2_REG POM2
-#define POMV2B3_REG POM2
-
-/* OCR2RBL */
-#define OCR2RB_0_REG OCR2RBL
-#define OCR2RB_1_REG OCR2RBL
-#define OCR2RB_2_REG OCR2RBL
-#define OCR2RB_3_REG OCR2RBL
-#define OCR2RB_4_REG OCR2RBL
-#define OCR2RB_5_REG OCR2RBL
-#define OCR2RB_6_REG OCR2RBL
-#define OCR2RB_7_REG OCR2RBL
-
-/* PICR2H */
-#define PICR2_8_REG PICR2H
-#define PICR2_9_REG PICR2H
-#define PICR2_10_REG PICR2H
-#define PICR2_11_REG PICR2H
-
-/* OCR2RBH */
-#define OCR2RB_8_REG OCR2RBH
-#define OCR2RB_9_REG OCR2RBH
-#define OCR2RB_10_REG OCR2RBH
-#define OCR2RB_11_REG OCR2RBH
-#define OCR2RB_12_REG OCR2RBH
-#define OCR2RB_13_REG OCR2RBH
-#define OCR2RB_14_REG OCR2RBH
-#define OCR2RB_15_REG OCR2RBH
-
-/* PICR2L */
-#define PICR2_0_REG PICR2L
-#define PICR2_1_REG PICR2L
-#define PICR2_2_REG PICR2L
-#define PICR2_3_REG PICR2L
-#define PICR2_4_REG PICR2L
-#define PICR2_5_REG PICR2L
-#define PICR2_6_REG PICR2L
-#define PICR2_7_REG PICR2L
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* PLLCSR */
-#define PLOCK_REG PLLCSR
-#define PLLE_REG PLLCSR
-#define PLLF_REG PLLCSR
-
-/* OCR2RAH */
-#define OCR2RA_8_REG OCR2RAH
-#define OCR2RA_9_REG OCR2RAH
-#define OCR2RA_10_REG OCR2RAH
-#define OCR2RA_11_REG OCR2RAH
-
-/* OCR2RAL */
-#define OCR2RA_0_REG OCR2RAL
-#define OCR2RA_1_REG OCR2RAL
-#define OCR2RA_2_REG OCR2RAL
-#define OCR2RA_3_REG OCR2RAL
-#define OCR2RA_4_REG OCR2RAL
-#define OCR2RA_5_REG OCR2RAL
-#define OCR2RA_6_REG OCR2RAL
-#define OCR2RA_7_REG OCR2RAL
-
-/* OCR0RBL */
-#define OCR0RB_0_REG OCR0RBL
-#define OCR0RB_1_REG OCR0RBL
-#define OCR0RB_2_REG OCR0RBL
-#define OCR0RB_3_REG OCR0RBL
-#define OCR0RB_4_REG OCR0RBL
-#define OCR0RB_5_REG OCR0RBL
-#define OCR0RB_6_REG OCR0RBL
-#define OCR0RB_7_REG OCR0RBL
-
-/* OCR0SAH */
-#define OCR0SA_8_REG OCR0SAH
-#define OCR0SA_9_REG OCR0SAH
-#define OCR0SA_00_REG OCR0SAH
-#define OCR0SA_01_REG OCR0SAH
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-#define EEAR10_REG EEARH
-#define EEAR11_REG EEARH
-
-/* EEARL */
-#define EEARL0_REG EEARL
-#define EEARL1_REG EEARL
-#define EEARL2_REG EEARL
-#define EEARL3_REG EEARL
-#define EEARL4_REG EEARL
-#define EEARL5_REG EEARL
-#define EEARL6_REG EEARL
-#define EEARL7_REG EEARL
-
-/* MCUCR */
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-#define SPIPS_REG MCUCR
-
-/* PICR0H */
-#define PICR0_8_REG PICR0H
-#define PICR0_9_REG PICR0H
-#define PICR0_10_REG PICR0H
-#define PICR0_11_REG PICR0H
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-#define INTF2_REG EIFR
-
-/* MUBRRL */
-#define MUBRR0_REG MUBRRL
-#define MUBRR1_REG MUBRRL
-#define MUBRR2_REG MUBRRL
-#define MUBRR3_REG MUBRRL
-#define MUBRR4_REG MUBRRL
-#define MUBRR5_REG MUBRRL
-#define MUBRR6_REG MUBRRL
-#define MUBRR7_REG MUBRRL
-
-/* MUBRRH */
-#define MUBRR8_REG MUBRRH
-#define MUBRR9_REG MUBRRH
-#define MUBRR10_REG MUBRRH
-#define MUBRR11_REG MUBRRH
-#define MUBRR12_REG MUBRRH
-#define MUBRR13_REG MUBRRH
-#define MUBRR14_REG MUBRRH
-#define MUBRR15_REG MUBRRH
-
-/* OCR2SAH */
-#define OCR2SA_8_REG OCR2SAH
-#define OCR2SA_9_REG OCR2SAH
-#define OCR2SA_10_REG OCR2SAH
-#define OCR2SA_11_REG OCR2SAH
-
-/* OCR0SBL */
-#define OCR0SB_0_REG OCR0SBL
-#define OCR0SB_1_REG OCR0SBL
-#define OCR0SB_2_REG OCR0SBL
-#define OCR0SB_3_REG OCR0SBL
-#define OCR0SB_4_REG OCR0SBL
-#define OCR0SB_5_REG OCR0SBL
-#define OCR0SB_6_REG OCR0SBL
-#define OCR0SB_7_REG OCR0SBL
-
-/* OCR0SBH */
-#define OCR0SB_8_REG OCR0SBH
-#define OCR0SB_9_REG OCR0SBH
-#define OCR0SB_00_REG OCR0SBH
-#define OCR0SB_01_REG OCR0SBH
-
-/* PICR0L */
-#define PICR0_0_REG PICR0L
-#define PICR0_1_REG PICR0L
-#define PICR0_2_REG PICR0L
-#define PICR0_3_REG PICR0L
-#define PICR0_4_REG PICR0L
-#define PICR0_5_REG PICR0L
-#define PICR0_6_REG PICR0L
-#define PICR0_7_REG PICR0L
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* PSOC0 */
-#define POEN0A_REG PSOC0
-#define POEN0B_REG PSOC0
-#define PSYNC00_REG PSOC0
-#define PSYNC01_REG PSOC0
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ADTS3_REG ADCSRB
-#define ADASCR_REG ADCSRB
-#define ADHSM_REG ADCSRB
-
-/* OCR0A */
-/* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */
-
-/* ACSR */
-#define AC0O_REG ACSR
-#define AC1O_REG ACSR
-#define AC2O_REG ACSR
-#define AC0IF_REG ACSR
-#define AC1IF_REG ACSR
-#define AC2IF_REG ACSR
-#define ACCKDIV_REG ACSR
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* UBRRH */
-#define UBRR8_REG UBRRH
-#define UBRR9_REG UBRRH
-#define UBRR10_REG UBRRH
-#define UBRR11_REG UBRRH
-
-/* DACL */
-#define DACL0_REG DACL
-#define DACL1_REG DACL
-#define DACL2_REG DACL
-#define DACL3_REG DACL
-#define DACL4_REG DACL
-#define DACL5_REG DACL
-#define DACL6_REG DACL
-#define DACL7_REG DACL
-
-/* UBRRL */
-#define UBRR0_REG UBRRL
-#define UBRR1_REG UBRRL
-#define UBRR2_REG UBRRL
-#define UBRR3_REG UBRRL
-#define UBRR4_REG UBRRL
-#define UBRR5_REG UBRRL
-#define UBRR6_REG UBRRL
-#define UBRR7_REG UBRRL
-
-/* DACH */
-#define DACH0_REG DACH
-#define DACH1_REG DACH
-#define DACH2_REG DACH
-#define DACH3_REG DACH
-#define DACH4_REG DACH
-#define DACH5_REG DACH
-#define DACH6_REG DACH
-#define DACH7_REG DACH
-
-/* OCR0RAH */
-#define OCR0RA_8_REG OCR0RAH
-#define OCR0RA_9_REG OCR0RAH
-#define OCR0RA_00_REG OCR0RAH
-#define OCR0RA_01_REG OCR0RAH
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* PIM0 */
-#define PEOPE0_REG PIM0
-#define PEVE0A_REG PIM0
-#define PEVE0B_REG PIM0
-#define PSEIE0_REG PIM0
-
-/* PIFR2 */
-#define PEOP2_REG PIFR2
-#define PRN20_REG PIFR2
-#define PRN21_REG PIFR2
-#define PEV2A_REG PIFR2
-#define PEV2B_REG PIFR2
-#define PSEI2_REG PIFR2
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* PSOC2 */
-#define POEN2A_REG PSOC2
-#define POEN2C_REG PSOC2
-#define POEN2B_REG PSOC2
-#define POEN2D_REG PSOC2
-#define PSYNC2_0_REG PSOC2
-#define PSYNC2_1_REG PSOC2
-#define POS22_REG PSOC2
-#define POS23_REG PSOC2
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* AMP0CSR */
-#define AMP0TS0_REG AMP0CSR
-#define AMP0TS1_REG AMP0CSR
-#define AMP0G0_REG AMP0CSR
-#define AMP0G1_REG AMP0CSR
-#define AMP0IS_REG AMP0CSR
-#define AMP0EN_REG AMP0CSR
-
-/* UDR */
-#define UDR0_REG UDR
-#define UDR1_REG UDR
-#define UDR2_REG UDR
-#define UDR3_REG UDR
-#define UDR4_REG UDR
-#define UDR5_REG UDR
-#define UDR6_REG UDR
-#define UDR7_REG UDR
-
-/* DACON */
-#define DAEN_REG DACON
-#define DALA_REG DACON
-#define DATS0_REG DACON
-#define DATS1_REG DACON
-#define DATS2_REG DACON
-#define DAATE_REG DACON
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* AC0CON */
-#define AC0M0_REG AC0CON
-#define AC0M1_REG AC0CON
-#define AC0M2_REG AC0CON
-#define AC0IS0_REG AC0CON
-#define AC0IS1_REG AC0CON
-#define AC0IE_REG AC0CON
-#define AC0EN_REG AC0CON
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* pins mapping */
-#define MISO_PORT PORTB
-#define MISO_BIT 0
-#define PSCOUT20_PORT PORTB
-#define PSCOUT20_BIT 0
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 1
-#define PSCOUT21_PORT PORTB
-#define PSCOUT21_BIT 1
-
-#define ADC5_PORT PORTB
-#define ADC5_BIT 2
-#define INT1_PORT PORTB
-#define INT1_BIT 2
-
-#define AMP0-_PORT PORTB
-#define AMP0-_BIT 3
-
-#define AMP0+_PORT PORTB
-#define AMP0+_BIT 4
-
-#define ADC6_PORT PORTB
-#define ADC6_BIT 5
-#define INT2_PORT PORTB
-#define INT2_BIT 5
-
-#define ADC7_PORT PORTB
-#define ADC7_BIT 6
-#define PSCOUT11_PORT PORTB
-#define PSCOUT11_BIT 6
-#define ICP1B_PORT PORTB
-#define ICP1B_BIT 6
-
-#define ADC4_PORT PORTB
-#define ADC4_BIT 7
-#define PSCOUT01_PORT PORTB
-#define PSCOUT01_BIT 7
-#define SCK_PORT PORTB
-#define SCK_BIT 7
-
-#define PSCOUT00_PORT PORTD
-#define PSCOUT00_BIT 0
-#define XCK_PORT PORTD
-#define XCK_BIT 0
-#define SSA_PORT PORTD
-#define SSA_BIT 0
-
-#define PSCIN0_PORT PORTD
-#define PSCIN0_BIT 1
-#define CLK0_PORT PORTD
-#define CLK0_BIT 1
-
-#define PSCIN2_PORT PORTD
-#define PSCIN2_BIT 2
-#define OC1A_PORT PORTD
-#define OC1A_BIT 2
-#define MISO_A_PORT PORTD
-#define MISO_A_BIT 2
-
-#define TXD_PORT PORTD
-#define TXD_BIT 3
-#define DALI_PORT PORTD
-#define DALI_BIT 3
-#define OC0A_PORT PORTD
-#define OC0A_BIT 3
-#define SS_PORT PORTD
-#define SS_BIT 3
-#define MOSI_A_PORT PORTD
-#define MOSI_A_BIT 3
-
-#define ADC1_PORT PORTD
-#define ADC1_BIT 4
-#define RXD_PORT PORTD
-#define RXD_BIT 4
-#define DALI_PORT PORTD
-#define DALI_BIT 4
-#define ICP1_PORT PORTD
-#define ICP1_BIT 4
-#define SCK_A_PORT PORTD
-#define SCK_A_BIT 4
-
-#define ADC2_PORT PORTD
-#define ADC2_BIT 5
-#define ACMP2_PORT PORTD
-#define ACMP2_BIT 5
-
-#define ADC3_PORT PORTD
-#define ADC3_BIT 6
-#define ACMPM_PORT PORTD
-#define ACMPM_BIT 6
-#define INT0_PORT PORTD
-#define INT0_BIT 6
-
-#define ACMP0_PORT PORTD
-#define ACMP0_BIT 7
-
-#define RESET_PORT PORTE
-#define RESET_BIT 0
-#define OCD_PORT PORTE
-#define OCD_BIT 0
-
-#define OC0B_PORT PORTE
-#define OC0B_BIT 1
-#define XTAL1_PORT PORTE
-#define XTAL1_BIT 1
-
-#define ADC0_PORT PORTE
-#define ADC0_BIT 2
-#define XTAL2_PORT PORTE
-#define XTAL2_BIT 2
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW_TOTAL_NUM 2
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* EUDR */
-#define EUDR0_REG EUDR
-#define EUDR1_REG EUDR
-#define EUDR2_REG EUDR
-#define EUDR3_REG EUDR
-#define EUDR4_REG EUDR
-#define EUDR5_REG EUDR
-#define EUDR6_REG EUDR
-#define EUDR7_REG EUDR
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* OCR2SBH */
-#define OCR2SB_8_REG OCR2SBH
-#define OCR2SB_9_REG OCR2SBH
-#define OCR2SB_10_REG OCR2SBH
-#define OCR2SB_11_REG OCR2SBH
-
-/* OCR2SBL */
-#define OCR2SB_0_REG OCR2SBL
-#define OCR2SB_1_REG OCR2SBL
-#define OCR2SB_2_REG OCR2SBL
-#define OCR2SB_3_REG OCR2SBL
-#define OCR2SB_4_REG OCR2SBL
-#define OCR2SB_5_REG OCR2SBL
-#define OCR2SB_6_REG OCR2SBL
-#define OCR2SB_7_REG OCR2SBL
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* OCR0B */
-/* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */
-
-/* OCR0SAL */
-#define OCR0SA_0_REG OCR0SAL
-#define OCR0SA_1_REG OCR0SAL
-#define OCR0SA_2_REG OCR0SAL
-#define OCR0SA_3_REG OCR0SAL
-#define OCR0SA_4_REG OCR0SAL
-#define OCR0SA_5_REG OCR0SAL
-#define OCR0SA_6_REG OCR0SAL
-#define OCR0SA_7_REG OCR0SAL
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* UCSRA */
-#define MPCM_REG UCSRA
-#define U2X_REG UCSRA
-#define UPE_REG UCSRA
-#define DOR_REG UCSRA
-#define FE_REG UCSRA
-#define UDRE_REG UCSRA
-#define TXC_REG UCSRA
-#define RXC_REG UCSRA
-
-/* UCSRB */
-#define TXB8_REG UCSRB
-#define RXB8_REG UCSRB
-#define UCSZ2_REG UCSRB
-#define TXEN_REG UCSRB
-#define RXEN_REG UCSRB
-#define UDRIE_REG UCSRB
-#define TXCIE_REG UCSRB
-#define RXCIE_REG UCSRB
-
-/* UCSRC */
-#define UCPOL_REG UCSRC
-#define UCSZ0_REG UCSRC
-#define UCSZ1_REG UCSRC
-#define USBS_REG UCSRC
-#define UPM0_REG UCSRC
-#define UPM1_REG UCSRC
-#define UMSEL0_REG UCSRC
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* AC1CON */
-#define AC1M0_REG AC1CON
-#define AC1M1_REG AC1CON
-#define AC1M2_REG AC1CON
-#define AC1ICE_REG AC1CON
-#define AC1IS0_REG AC1CON
-#define AC1IS1_REG AC1CON
-#define AC1IE_REG AC1CON
-#define AC1EN_REG AC1CON
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSART0_REG PRR
-#define PRSPI_REG PRR
-#define PRTIM0_REG PRR
-#define PRTIM1_REG PRR
-#define PRPSC0_REG PRR
-#define PRPSC1_REG PRR
-#define PRPSC2_REG PRR
-
-/* PCNF0 */
-#define PCLKSEL0_REG PCNF0
-#define POP0_REG PCNF0
-#define PMODE00_REG PCNF0
-#define PMODE01_REG PCNF0
-#define PLOCK0_REG PCNF0
-#define PALOCK0_REG PCNF0
-#define PFIFTY0_REG PCNF0
-
-/* PCNF2 */
-#define POME2_REG PCNF2
-#define PCLKSEL2_REG PCNF2
-#define POP2_REG PCNF2
-#define PMODE20_REG PCNF2
-#define PMODE21_REG PCNF2
-#define PLOCK2_REG PCNF2
-#define PALOCK2_REG PCNF2
-#define PFIFTY2_REG PCNF2
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* AMP1CSR */
-#define AMP1TS0_REG AMP1CSR
-#define AMP1TS1_REG AMP1CSR
-#define AMP1G0_REG AMP1CSR
-#define AMP1G1_REG AMP1CSR
-#define AMP1IS_REG AMP1CSR
-#define AMP1EN_REG AMP1CSR
-
-/* AC2CON */
-#define AC2M0_REG AC2CON
-#define AC2M1_REG AC2CON
-#define AC2M2_REG AC2CON
-#define AC2IS0_REG AC2CON
-#define AC2IS1_REG AC2CON
-#define AC2IE_REG AC2CON
-#define AC2EN_REG AC2CON
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-
-/* PFRC0A */
-#define PRFM0A0_REG PFRC0A
-#define PRFM0A1_REG PFRC0A
-#define PRFM0A2_REG PFRC0A
-#define PRFM0A3_REG PFRC0A
-#define PFLTE0A_REG PFRC0A
-#define PELEV0A_REG PFRC0A
-#define PISEL0A_REG PFRC0A
-#define PCAE0A_REG PFRC0A
-
-/* PFRC0B */
-#define PRFM0B0_REG PFRC0B
-#define PRFM0B1_REG PFRC0B
-#define PRFM0B2_REG PFRC0B
-#define PRFM0B3_REG PFRC0B
-#define PFLTE0B_REG PFRC0B
-#define PELEV0B_REG PFRC0B
-#define PISEL0B_REG PFRC0B
-#define PCAE0B_REG PFRC0B
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-#define ISC20_REG EICRA
-#define ISC21_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define ADC8D_REG DIDR1
-#define ADC9D_REG DIDR1
-#define ADC10D_REG DIDR1
-#define AMP0ND_REG DIDR1
-#define AMP0PD_REG DIDR1
-#define ACMP0D_REG DIDR1
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* OCR0RBH */
-#define OCR0RB_8_REG OCR0RBH
-#define OCR0RB_9_REG OCR0RBH
-#define OCR0RB_00_REG OCR0RBH
-#define OCR0RB_01_REG OCR0RBH
-#define OCR0RB_02_REG OCR0RBH
-#define OCR0RB_03_REG OCR0RBH
-#define OCR0RB_04_REG OCR0RBH
-#define OCR0RB_05_REG OCR0RBH
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* PIM2 */
-#define PEOPE2_REG PIM2
-#define PEVE2A_REG PIM2
-#define PEVE2B_REG PIM2
-#define PSEIE2_REG PIM2
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-
-/* OCR0RAL */
-#define OCR0RA_0_REG OCR0RAL
-#define OCR0RA_1_REG OCR0RAL
-#define OCR0RA_2_REG OCR0RAL
-#define OCR0RA_3_REG OCR0RAL
-#define OCR0RA_4_REG OCR0RAL
-#define OCR0RA_5_REG OCR0RAL
-#define OCR0RA_6_REG OCR0RAL
-#define OCR0RA_7_REG OCR0RAL
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR3 */
-#define GPIOR30_REG GPIOR3
-#define GPIOR31_REG GPIOR3
-#define GPIOR32_REG GPIOR3
-#define GPIOR33_REG GPIOR3
-#define GPIOR34_REG GPIOR3
-#define GPIOR35_REG GPIOR3
-#define GPIOR36_REG GPIOR3
-#define GPIOR37_REG GPIOR3
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* PIFR0 */
-#define PEOP0_REG PIFR0
-#define PRN00_REG PIFR0
-#define PRN01_REG PIFR0
-#define PEV0A_REG PIFR0
-#define PEV0B_REG PIFR0
-#define PSEI0_REG PIFR0
-#define POAC0A_REG PIFR0
-#define POAC0B_REG PIFR0
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* PFRC2B */
-#define PRFM2B0_REG PFRC2B
-#define PRFM2B1_REG PFRC2B
-#define PRFM2B2_REG PFRC2B
-#define PRFM2B3_REG PFRC2B
-#define PFLTE2B_REG PFRC2B
-#define PELEV2B_REG PFRC2B
-#define PISEL2B_REG PFRC2B
-#define PCAE2B_REG PFRC2B
-
-/* PFRC2A */
-#define PRFM2A0_REG PFRC2A
-#define PRFM2A1_REG PFRC2A
-#define PRFM2A2_REG PFRC2A
-#define PRFM2A3_REG PFRC2A
-#define PFLTE2A_REG PFRC2A
-#define PELEV2A_REG PFRC2A
-#define PISEL2A_REG PFRC2A
-#define PCAE2A_REG PFRC2A
-
-/* OCR2SAL */
-#define OCR2SA_0_REG OCR2SAL
-#define OCR2SA_1_REG OCR2SAL
-#define OCR2SA_2_REG OCR2SAL
-#define OCR2SA_3_REG OCR2SAL
-#define OCR2SA_4_REG OCR2SAL
-#define OCR2SA_5_REG OCR2SAL
-#define OCR2SA_6_REG OCR2SAL
-#define OCR2SA_7_REG OCR2SAL
-
-/* EUCSRA */
-#define URxS0_REG EUCSRA
-#define URxS1_REG EUCSRA
-#define URxS2_REG EUCSRA
-#define URxS3_REG EUCSRA
-#define UTxS0_REG EUCSRA
-#define UTxS1_REG EUCSRA
-#define UTxS2_REG EUCSRA
-#define UTxS3_REG EUCSRA
-
-/* EUCSRB */
-#define BODR_REG EUCSRB
-#define EMCH_REG EUCSRB
-#define EUSBS_REG EUCSRB
-#define EUSART_REG EUCSRB
-
-/* EUCSRC */
-#define STP0_REG EUCSRC
-#define STP1_REG EUCSRC
-#define F1617_REG EUCSRC
-#define FEM_REG EUCSRC
-
-/* PCTL0 */
-#define PRUN0_REG PCTL0
-#define PCCYC0_REG PCTL0
-#define PARUN0_REG PCTL0
-#define PAOC0A_REG PCTL0
-#define PAOC0B_REG PCTL0
-#define PBFM0_REG PCTL0
-#define PPRE00_REG PCTL0
-#define PPRE01_REG PCTL0
-
-/* PCTL2 */
-#define PRUN2_REG PCTL2
-#define PCCYC2_REG PCTL2
-#define PARUN2_REG PCTL2
-#define PAOC2A_REG PCTL2
-#define PAOC2B_REG PCTL2
-#define PBFM2_REG PCTL2
-#define PPRE20_REG PCTL2
-#define PPRE21_REG PCTL2
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* GTCCR */
-#define PSR10_REG GTCCR
-#define ICPSEL1_REG GTCCR
-#define TSM_REG GTCCR
-#define PSRSYNC_REG GTCCR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* POM2 */
-#define POMV2A0_REG POM2
-#define POMV2A1_REG POM2
-#define POMV2A2_REG POM2
-#define POMV2A3_REG POM2
-#define POMV2B0_REG POM2
-#define POMV2B1_REG POM2
-#define POMV2B2_REG POM2
-#define POMV2B3_REG POM2
-
-/* OCR2RBL */
-#define OCR2RB_0_REG OCR2RBL
-#define OCR2RB_1_REG OCR2RBL
-#define OCR2RB_2_REG OCR2RBL
-#define OCR2RB_3_REG OCR2RBL
-#define OCR2RB_4_REG OCR2RBL
-#define OCR2RB_5_REG OCR2RBL
-#define OCR2RB_6_REG OCR2RBL
-#define OCR2RB_7_REG OCR2RBL
-
-/* PICR2H */
-#define PICR2_8_REG PICR2H
-#define PICR2_9_REG PICR2H
-#define PICR2_10_REG PICR2H
-#define PICR2_11_REG PICR2H
-#define PCST2_REG PICR2H
-
-/* OCR2RBH */
-#define OCR2RB_8_REG OCR2RBH
-#define OCR2RB_9_REG OCR2RBH
-#define OCR2RB_10_REG OCR2RBH
-#define OCR2RB_11_REG OCR2RBH
-#define OCR2RB_12_REG OCR2RBH
-#define OCR2RB_13_REG OCR2RBH
-#define OCR2RB_14_REG OCR2RBH
-#define OCR2RB_15_REG OCR2RBH
-
-/* PICR2L */
-#define PICR2_0_REG PICR2L
-#define PICR2_1_REG PICR2L
-#define PICR2_2_REG PICR2L
-#define PICR2_3_REG PICR2L
-#define PICR2_4_REG PICR2L
-#define PICR2_5_REG PICR2L
-#define PICR2_6_REG PICR2L
-#define PICR2_7_REG PICR2L
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* PLLCSR */
-#define PLOCK_REG PLLCSR
-#define PLLE_REG PLLCSR
-#define PLLF_REG PLLCSR
-
-/* OCR2RAH */
-#define OCR2RA_8_REG OCR2RAH
-#define OCR2RA_9_REG OCR2RAH
-#define OCR2RA_10_REG OCR2RAH
-#define OCR2RA_11_REG OCR2RAH
-
-/* OCR2RAL */
-#define OCR2RA_0_REG OCR2RAL
-#define OCR2RA_1_REG OCR2RAL
-#define OCR2RA_2_REG OCR2RAL
-#define OCR2RA_3_REG OCR2RAL
-#define OCR2RA_4_REG OCR2RAL
-#define OCR2RA_5_REG OCR2RAL
-#define OCR2RA_6_REG OCR2RAL
-#define OCR2RA_7_REG OCR2RAL
-
-/* OCR0RBL */
-#define OCR0RB_0_REG OCR0RBL
-#define OCR0RB_1_REG OCR0RBL
-#define OCR0RB_2_REG OCR0RBL
-#define OCR0RB_3_REG OCR0RBL
-#define OCR0RB_4_REG OCR0RBL
-#define OCR0RB_5_REG OCR0RBL
-#define OCR0RB_6_REG OCR0RBL
-#define OCR0RB_7_REG OCR0RBL
-
-/* OCR0SAH */
-#define OCR0SA_8_REG OCR0SAH
-#define OCR0SA_9_REG OCR0SAH
-#define OCR0SA_00_REG OCR0SAH
-#define OCR0SA_01_REG OCR0SAH
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-#define EEAR10_REG EEARH
-#define EEAR11_REG EEARH
-
-/* EEARL */
-#define EEARL0_REG EEARL
-#define EEARL1_REG EEARL
-#define EEARL2_REG EEARL
-#define EEARL3_REG EEARL
-#define EEARL4_REG EEARL
-#define EEARL5_REG EEARL
-#define EEARL6_REG EEARL
-#define EEARL7_REG EEARL
-
-/* MCUCR */
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-#define SPIPS_REG MCUCR
-
-/* PICR0H */
-#define PICR0_8_REG PICR0H
-#define PICR0_9_REG PICR0H
-#define PICR0_10_REG PICR0H
-#define PICR0_11_REG PICR0H
-#define PCST0_REG PICR0H
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-#define INTF2_REG EIFR
-
-/* MUBRRL */
-#define MUBRR0_REG MUBRRL
-#define MUBRR1_REG MUBRRL
-#define MUBRR2_REG MUBRRL
-#define MUBRR3_REG MUBRRL
-#define MUBRR4_REG MUBRRL
-#define MUBRR5_REG MUBRRL
-#define MUBRR6_REG MUBRRL
-#define MUBRR7_REG MUBRRL
-
-/* MUBRRH */
-#define MUBRR8_REG MUBRRH
-#define MUBRR9_REG MUBRRH
-#define MUBRR10_REG MUBRRH
-#define MUBRR11_REG MUBRRH
-#define MUBRR12_REG MUBRRH
-#define MUBRR13_REG MUBRRH
-#define MUBRR14_REG MUBRRH
-#define MUBRR15_REG MUBRRH
-
-/* OCR2SAH */
-#define OCR2SA_8_REG OCR2SAH
-#define OCR2SA_9_REG OCR2SAH
-#define OCR2SA_10_REG OCR2SAH
-#define OCR2SA_11_REG OCR2SAH
-
-/* OCR0SBL */
-#define OCR0SB_0_REG OCR0SBL
-#define OCR0SB_1_REG OCR0SBL
-#define OCR0SB_2_REG OCR0SBL
-#define OCR0SB_3_REG OCR0SBL
-#define OCR0SB_4_REG OCR0SBL
-#define OCR0SB_5_REG OCR0SBL
-#define OCR0SB_6_REG OCR0SBL
-#define OCR0SB_7_REG OCR0SBL
-
-/* OCR0SBH */
-#define OCR0SB_8_REG OCR0SBH
-#define OCR0SB_9_REG OCR0SBH
-#define OCR0SB_00_REG OCR0SBH
-#define OCR0SB_01_REG OCR0SBH
-
-/* PICR0L */
-#define PICR0_0_REG PICR0L
-#define PICR0_1_REG PICR0L
-#define PICR0_2_REG PICR0L
-#define PICR0_3_REG PICR0L
-#define PICR0_4_REG PICR0L
-#define PICR0_5_REG PICR0L
-#define PICR0_6_REG PICR0L
-#define PICR0_7_REG PICR0L
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* PSOC0 */
-#define POEN0A_REG PSOC0
-#define POEN0B_REG PSOC0
-#define PSYNC00_REG PSOC0
-#define PSYNC01_REG PSOC0
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ADTS3_REG ADCSRB
-#define ADASCR_REG ADCSRB
-#define ADHSM_REG ADCSRB
-
-/* OCR0A */
-/* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */
-
-/* ACSR */
-#define AC0O_REG ACSR
-#define AC1O_REG ACSR
-#define AC2O_REG ACSR
-#define AC0IF_REG ACSR
-#define AC1IF_REG ACSR
-#define AC2IF_REG ACSR
-#define ACCKDIV_REG ACSR
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* UBRRH */
-#define UBRR8_REG UBRRH
-#define UBRR9_REG UBRRH
-#define UBRR10_REG UBRRH
-#define UBRR11_REG UBRRH
-
-/* DACL */
-#define DACL0_REG DACL
-#define DACL1_REG DACL
-#define DACL2_REG DACL
-#define DACL3_REG DACL
-#define DACL4_REG DACL
-#define DACL5_REG DACL
-#define DACL6_REG DACL
-#define DACL7_REG DACL
-
-/* UBRRL */
-#define UBRR0_REG UBRRL
-#define UBRR1_REG UBRRL
-#define UBRR2_REG UBRRL
-#define UBRR3_REG UBRRL
-#define UBRR4_REG UBRRL
-#define UBRR5_REG UBRRL
-#define UBRR6_REG UBRRL
-#define UBRR7_REG UBRRL
-
-/* DACH */
-#define DACH0_REG DACH
-#define DACH1_REG DACH
-#define DACH2_REG DACH
-#define DACH3_REG DACH
-#define DACH4_REG DACH
-#define DACH5_REG DACH
-#define DACH6_REG DACH
-#define DACH7_REG DACH
-
-/* OCR0RAH */
-#define OCR0RA_8_REG OCR0RAH
-#define OCR0RA_9_REG OCR0RAH
-#define OCR0RA_00_REG OCR0RAH
-#define OCR0RA_01_REG OCR0RAH
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* PIM0 */
-#define PEOPE0_REG PIM0
-#define PEVE0A_REG PIM0
-#define PEVE0B_REG PIM0
-#define PSEIE0_REG PIM0
-
-/* PIFR2 */
-#define PEOP2_REG PIFR2
-#define PRN20_REG PIFR2
-#define PRN21_REG PIFR2
-#define PEV2A_REG PIFR2
-#define PEV2B_REG PIFR2
-#define PSEI2_REG PIFR2
-#define POAC2A_REG PIFR2
-#define POAC2B_REG PIFR2
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* PSOC2 */
-#define POEN2A_REG PSOC2
-#define POEN2C_REG PSOC2
-#define POEN2B_REG PSOC2
-#define POEN2D_REG PSOC2
-#define PSYNC2_0_REG PSOC2
-#define PSYNC2_1_REG PSOC2
-#define POS22_REG PSOC2
-#define POS23_REG PSOC2
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* AMP0CSR */
-#define AMP0TS0_REG AMP0CSR
-#define AMP0TS1_REG AMP0CSR
-#define AMP0G0_REG AMP0CSR
-#define AMP0G1_REG AMP0CSR
-#define AMP0IS_REG AMP0CSR
-#define AMP0EN_REG AMP0CSR
-
-/* UDR */
-#define UDR0_REG UDR
-#define UDR1_REG UDR
-#define UDR2_REG UDR
-#define UDR3_REG UDR
-#define UDR4_REG UDR
-#define UDR5_REG UDR
-#define UDR6_REG UDR
-#define UDR7_REG UDR
-
-/* DACON */
-#define DAEN_REG DACON
-#define DALA_REG DACON
-#define DATS0_REG DACON
-#define DATS1_REG DACON
-#define DATS2_REG DACON
-#define DAATE_REG DACON
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* AC0CON */
-#define AC0M0_REG AC0CON
-#define AC0M1_REG AC0CON
-#define AC0M2_REG AC0CON
-#define AC0IS0_REG AC0CON
-#define AC0IS1_REG AC0CON
-#define AC0IE_REG AC0CON
-#define AC0EN_REG AC0CON
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* pins mapping */
-#define MISO_PORT PORTB
-#define MISO_BIT 0
-#define PSCOUT20_PORT PORTB
-#define PSCOUT20_BIT 0
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 1
-#define PSCOUT21_PORT PORTB
-#define PSCOUT21_BIT 1
-
-#define ADC5_PORT PORTB
-#define ADC5_BIT 2
-#define INT1_PORT PORTB
-#define INT1_BIT 2
-
-#define AMP0-_PORT PORTB
-#define AMP0-_BIT 3
-
-#define AMP0+_PORT PORTB
-#define AMP0+_BIT 4
-
-#define ADC6_PORT PORTB
-#define ADC6_BIT 5
-#define INT2_PORT PORTB
-#define INT2_BIT 5
-
-#define ADC7_PORT PORTB
-#define ADC7_BIT 6
-#define PSCOUT11_PORT PORTB
-#define PSCOUT11_BIT 6
-#define ICP1B_PORT PORTB
-#define ICP1B_BIT 6
-
-#define ADC4_PORT PORTB
-#define ADC4_BIT 7
-#define PSCOUT01_PORT PORTB
-#define PSCOUT01_BIT 7
-#define SCK_PORT PORTB
-#define SCK_BIT 7
-
-#define PSCOUT00_PORT PORTD
-#define PSCOUT00_BIT 0
-#define XCK_PORT PORTD
-#define XCK_BIT 0
-#define SSA_PORT PORTD
-#define SSA_BIT 0
-
-#define PSCIN0_PORT PORTD
-#define PSCIN0_BIT 1
-#define CLK0_PORT PORTD
-#define CLK0_BIT 1
-
-#define PSCIN2_PORT PORTD
-#define PSCIN2_BIT 2
-#define OC1A_PORT PORTD
-#define OC1A_BIT 2
-#define MISO_A_PORT PORTD
-#define MISO_A_BIT 2
-
-#define TXD_PORT PORTD
-#define TXD_BIT 3
-#define DALI_PORT PORTD
-#define DALI_BIT 3
-#define OC0A_PORT PORTD
-#define OC0A_BIT 3
-#define SS_PORT PORTD
-#define SS_BIT 3
-#define MOSI_A_PORT PORTD
-#define MOSI_A_BIT 3
-
-#define ADC1_PORT PORTD
-#define ADC1_BIT 4
-#define RXD_PORT PORTD
-#define RXD_BIT 4
-#define DALI_PORT PORTD
-#define DALI_BIT 4
-#define ICP1_PORT PORTD
-#define ICP1_BIT 4
-#define SCK_A_PORT PORTD
-#define SCK_A_BIT 4
-
-#define ADC2_PORT PORTD
-#define ADC2_BIT 5
-#define ACMP2_PORT PORTD
-#define ACMP2_BIT 5
-
-#define ADC3_PORT PORTD
-#define ADC3_BIT 6
-#define ACMPM_PORT PORTD
-#define ACMPM_BIT 6
-#define INT0_PORT PORTD
-#define INT0_BIT 6
-
-#define ACMP0_PORT PORTD
-#define ACMP0_BIT 7
-
-#define RESET_PORT PORTE
-#define RESET_BIT 0
-#define OCD_PORT PORTE
-#define OCD_BIT 0
-
-#define OC0B_PORT PORTE
-#define OC0B_BIT 1
-#define XTAL1_PORT PORTE
-#define XTAL1_BIT 1
-
-#define ADC0_PORT PORTE
-#define ADC0_BIT 2
-#define XTAL2_PORT PORTE
-#define XTAL2_BIT 2
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW_TOTAL_NUM 2
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* EUDR */
-#define EUDR0_REG EUDR
-#define EUDR1_REG EUDR
-#define EUDR2_REG EUDR
-#define EUDR3_REG EUDR
-#define EUDR4_REG EUDR
-#define EUDR5_REG EUDR
-#define EUDR6_REG EUDR
-#define EUDR7_REG EUDR
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* OCR2SBH */
-#define OCR2SB_8_REG OCR2SBH
-#define OCR2SB_9_REG OCR2SBH
-#define OCR2SB_10_REG OCR2SBH
-#define OCR2SB_11_REG OCR2SBH
-
-/* OCR2SBL */
-#define OCR2SB_0_REG OCR2SBL
-#define OCR2SB_1_REG OCR2SBL
-#define OCR2SB_2_REG OCR2SBL
-#define OCR2SB_3_REG OCR2SBL
-#define OCR2SB_4_REG OCR2SBL
-#define OCR2SB_5_REG OCR2SBL
-#define OCR2SB_6_REG OCR2SBL
-#define OCR2SB_7_REG OCR2SBL
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* OCR0B */
-/* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */
-
-/* OCR0SAL */
-#define OCR0SA_0_REG OCR0SAL
-#define OCR0SA_1_REG OCR0SAL
-#define OCR0SA_2_REG OCR0SAL
-#define OCR0SA_3_REG OCR0SAL
-#define OCR0SA_4_REG OCR0SAL
-#define OCR0SA_5_REG OCR0SAL
-#define OCR0SA_6_REG OCR0SAL
-#define OCR0SA_7_REG OCR0SAL
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* UCSRA */
-#define MPCM_REG UCSRA
-#define U2X_REG UCSRA
-#define UPE_REG UCSRA
-#define DOR_REG UCSRA
-#define FE_REG UCSRA
-#define UDRE_REG UCSRA
-#define TXC_REG UCSRA
-#define RXC_REG UCSRA
-
-/* UCSRB */
-#define TXB8_REG UCSRB
-#define RXB8_REG UCSRB
-#define UCSZ2_REG UCSRB
-#define TXEN_REG UCSRB
-#define RXEN_REG UCSRB
-#define UDRIE_REG UCSRB
-#define TXCIE_REG UCSRB
-#define RXCIE_REG UCSRB
-
-/* UCSRC */
-#define UCPOL_REG UCSRC
-#define UCSZ0_REG UCSRC
-#define UCSZ1_REG UCSRC
-#define USBS_REG UCSRC
-#define UPM0_REG UCSRC
-#define UPM1_REG UCSRC
-#define UMSEL0_REG UCSRC
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* AC1CON */
-#define AC1M0_REG AC1CON
-#define AC1M1_REG AC1CON
-#define AC1M2_REG AC1CON
-#define AC1ICE_REG AC1CON
-#define AC1IS0_REG AC1CON
-#define AC1IS1_REG AC1CON
-#define AC1IE_REG AC1CON
-#define AC1EN_REG AC1CON
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSART0_REG PRR
-#define PRSPI_REG PRR
-#define PRTIM0_REG PRR
-#define PRTIM1_REG PRR
-#define PRPSC0_REG PRR
-#define PRPSC1_REG PRR
-#define PRPSC2_REG PRR
-
-/* PCNF0 */
-#define PCLKSEL0_REG PCNF0
-#define POP0_REG PCNF0
-#define PMODE00_REG PCNF0
-#define PMODE01_REG PCNF0
-#define PLOCK0_REG PCNF0
-#define PALOCK0_REG PCNF0
-#define PFIFTY0_REG PCNF0
-
-/* PCNF2 */
-#define POME2_REG PCNF2
-#define PCLKSEL2_REG PCNF2
-#define POP2_REG PCNF2
-#define PMODE20_REG PCNF2
-#define PMODE21_REG PCNF2
-#define PLOCK2_REG PCNF2
-#define PALOCK2_REG PCNF2
-#define PFIFTY2_REG PCNF2
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* AMP1CSR */
-#define AMP1TS0_REG AMP1CSR
-#define AMP1TS1_REG AMP1CSR
-#define AMP1G0_REG AMP1CSR
-#define AMP1G1_REG AMP1CSR
-#define AMP1IS_REG AMP1CSR
-#define AMP1EN_REG AMP1CSR
-
-/* AC2CON */
-#define AC2M0_REG AC2CON
-#define AC2M1_REG AC2CON
-#define AC2M2_REG AC2CON
-#define AC2IS0_REG AC2CON
-#define AC2IS1_REG AC2CON
-#define AC2IE_REG AC2CON
-#define AC2EN_REG AC2CON
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-
-/* PFRC0A */
-#define PRFM0A0_REG PFRC0A
-#define PRFM0A1_REG PFRC0A
-#define PRFM0A2_REG PFRC0A
-#define PRFM0A3_REG PFRC0A
-#define PFLTE0A_REG PFRC0A
-#define PELEV0A_REG PFRC0A
-#define PISEL0A_REG PFRC0A
-#define PCAE0A_REG PFRC0A
-
-/* PFRC0B */
-#define PRFM0B0_REG PFRC0B
-#define PRFM0B1_REG PFRC0B
-#define PRFM0B2_REG PFRC0B
-#define PRFM0B3_REG PFRC0B
-#define PFLTE0B_REG PFRC0B
-#define PELEV0B_REG PFRC0B
-#define PISEL0B_REG PFRC0B
-#define PCAE0B_REG PFRC0B
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-#define ISC20_REG EICRA
-#define ISC21_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define ADC8D_REG DIDR1
-#define ADC9D_REG DIDR1
-#define ADC10D_REG DIDR1
-#define AMP0ND_REG DIDR1
-#define AMP0PD_REG DIDR1
-#define ACMP0D_REG DIDR1
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* OCR0RBH */
-#define OCR0RB_8_REG OCR0RBH
-#define OCR0RB_9_REG OCR0RBH
-#define OCR0RB_00_REG OCR0RBH
-#define OCR0RB_01_REG OCR0RBH
-#define OCR0RB_02_REG OCR0RBH
-#define OCR0RB_03_REG OCR0RBH
-#define OCR0RB_04_REG OCR0RBH
-#define OCR0RB_05_REG OCR0RBH
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* PIM2 */
-#define PEOPE2_REG PIM2
-#define PEVE2A_REG PIM2
-#define PEVE2B_REG PIM2
-#define PSEIE2_REG PIM2
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-
-/* OCR0RAL */
-#define OCR0RA_0_REG OCR0RAL
-#define OCR0RA_1_REG OCR0RAL
-#define OCR0RA_2_REG OCR0RAL
-#define OCR0RA_3_REG OCR0RAL
-#define OCR0RA_4_REG OCR0RAL
-#define OCR0RA_5_REG OCR0RAL
-#define OCR0RA_6_REG OCR0RAL
-#define OCR0RA_7_REG OCR0RAL
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR3 */
-#define GPIOR30_REG GPIOR3
-#define GPIOR31_REG GPIOR3
-#define GPIOR32_REG GPIOR3
-#define GPIOR33_REG GPIOR3
-#define GPIOR34_REG GPIOR3
-#define GPIOR35_REG GPIOR3
-#define GPIOR36_REG GPIOR3
-#define GPIOR37_REG GPIOR3
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* PIFR0 */
-#define PEOP0_REG PIFR0
-#define PRN00_REG PIFR0
-#define PRN01_REG PIFR0
-#define PEV0A_REG PIFR0
-#define PEV0B_REG PIFR0
-#define PSEI0_REG PIFR0
-#define POAC0A_REG PIFR0
-#define POAC0B_REG PIFR0
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* PFRC2B */
-#define PRFM2B0_REG PFRC2B
-#define PRFM2B1_REG PFRC2B
-#define PRFM2B2_REG PFRC2B
-#define PRFM2B3_REG PFRC2B
-#define PFLTE2B_REG PFRC2B
-#define PELEV2B_REG PFRC2B
-#define PISEL2B_REG PFRC2B
-#define PCAE2B_REG PFRC2B
-
-/* PFRC2A */
-#define PRFM2A0_REG PFRC2A
-#define PRFM2A1_REG PFRC2A
-#define PRFM2A2_REG PFRC2A
-#define PRFM2A3_REG PFRC2A
-#define PFLTE2A_REG PFRC2A
-#define PELEV2A_REG PFRC2A
-#define PISEL2A_REG PFRC2A
-#define PCAE2A_REG PFRC2A
-
-/* OCR2SAL */
-#define OCR2SA_0_REG OCR2SAL
-#define OCR2SA_1_REG OCR2SAL
-#define OCR2SA_2_REG OCR2SAL
-#define OCR2SA_3_REG OCR2SAL
-#define OCR2SA_4_REG OCR2SAL
-#define OCR2SA_5_REG OCR2SAL
-#define OCR2SA_6_REG OCR2SAL
-#define OCR2SA_7_REG OCR2SAL
-
-/* EUCSRA */
-#define URxS0_REG EUCSRA
-#define URxS1_REG EUCSRA
-#define URxS2_REG EUCSRA
-#define URxS3_REG EUCSRA
-#define UTxS0_REG EUCSRA
-#define UTxS1_REG EUCSRA
-#define UTxS2_REG EUCSRA
-#define UTxS3_REG EUCSRA
-
-/* EUCSRB */
-#define BODR_REG EUCSRB
-#define EMCH_REG EUCSRB
-#define EUSBS_REG EUCSRB
-#define EUSART_REG EUCSRB
-
-/* EUCSRC */
-#define STP0_REG EUCSRC
-#define STP1_REG EUCSRC
-#define F1617_REG EUCSRC
-#define FEM_REG EUCSRC
-
-/* PCTL0 */
-#define PRUN0_REG PCTL0
-#define PCCYC0_REG PCTL0
-#define PARUN0_REG PCTL0
-#define PAOC0A_REG PCTL0
-#define PAOC0B_REG PCTL0
-#define PBFM0_REG PCTL0
-#define PPRE00_REG PCTL0
-#define PPRE01_REG PCTL0
-
-/* PCTL2 */
-#define PRUN2_REG PCTL2
-#define PCCYC2_REG PCTL2
-#define PARUN2_REG PCTL2
-#define PAOC2A_REG PCTL2
-#define PAOC2B_REG PCTL2
-#define PBFM2_REG PCTL2
-#define PPRE20_REG PCTL2
-#define PPRE21_REG PCTL2
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* GTCCR */
-#define PSR10_REG GTCCR
-#define ICPSEL1_REG GTCCR
-#define TSM_REG GTCCR
-#define PSRSYNC_REG GTCCR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* POM2 */
-#define POMV2A0_REG POM2
-#define POMV2A1_REG POM2
-#define POMV2A2_REG POM2
-#define POMV2A3_REG POM2
-#define POMV2B0_REG POM2
-#define POMV2B1_REG POM2
-#define POMV2B2_REG POM2
-#define POMV2B3_REG POM2
-
-/* OCR2RBL */
-#define OCR2RB_0_REG OCR2RBL
-#define OCR2RB_1_REG OCR2RBL
-#define OCR2RB_2_REG OCR2RBL
-#define OCR2RB_3_REG OCR2RBL
-#define OCR2RB_4_REG OCR2RBL
-#define OCR2RB_5_REG OCR2RBL
-#define OCR2RB_6_REG OCR2RBL
-#define OCR2RB_7_REG OCR2RBL
-
-/* PICR2H */
-#define PICR2_8_REG PICR2H
-#define PICR2_9_REG PICR2H
-#define PICR2_10_REG PICR2H
-#define PICR2_11_REG PICR2H
-#define PCST2_REG PICR2H
-
-/* OCR2RBH */
-#define OCR2RB_8_REG OCR2RBH
-#define OCR2RB_9_REG OCR2RBH
-#define OCR2RB_10_REG OCR2RBH
-#define OCR2RB_11_REG OCR2RBH
-#define OCR2RB_12_REG OCR2RBH
-#define OCR2RB_13_REG OCR2RBH
-#define OCR2RB_14_REG OCR2RBH
-#define OCR2RB_15_REG OCR2RBH
-
-/* PICR2L */
-#define PICR2_0_REG PICR2L
-#define PICR2_1_REG PICR2L
-#define PICR2_2_REG PICR2L
-#define PICR2_3_REG PICR2L
-#define PICR2_4_REG PICR2L
-#define PICR2_5_REG PICR2L
-#define PICR2_6_REG PICR2L
-#define PICR2_7_REG PICR2L
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* PLLCSR */
-#define PLOCK_REG PLLCSR
-#define PLLE_REG PLLCSR
-#define PLLF_REG PLLCSR
-
-/* OCR2RAH */
-#define OCR2RA_8_REG OCR2RAH
-#define OCR2RA_9_REG OCR2RAH
-#define OCR2RA_10_REG OCR2RAH
-#define OCR2RA_11_REG OCR2RAH
-
-/* OCR2RAL */
-#define OCR2RA_0_REG OCR2RAL
-#define OCR2RA_1_REG OCR2RAL
-#define OCR2RA_2_REG OCR2RAL
-#define OCR2RA_3_REG OCR2RAL
-#define OCR2RA_4_REG OCR2RAL
-#define OCR2RA_5_REG OCR2RAL
-#define OCR2RA_6_REG OCR2RAL
-#define OCR2RA_7_REG OCR2RAL
-
-/* OCR0RBL */
-#define OCR0RB_0_REG OCR0RBL
-#define OCR0RB_1_REG OCR0RBL
-#define OCR0RB_2_REG OCR0RBL
-#define OCR0RB_3_REG OCR0RBL
-#define OCR0RB_4_REG OCR0RBL
-#define OCR0RB_5_REG OCR0RBL
-#define OCR0RB_6_REG OCR0RBL
-#define OCR0RB_7_REG OCR0RBL
-
-/* OCR0SAH */
-#define OCR0SA_8_REG OCR0SAH
-#define OCR0SA_9_REG OCR0SAH
-#define OCR0SA_00_REG OCR0SAH
-#define OCR0SA_01_REG OCR0SAH
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-#define EEAR10_REG EEARH
-#define EEAR11_REG EEARH
-
-/* EEARL */
-#define EEARL0_REG EEARL
-#define EEARL1_REG EEARL
-#define EEARL2_REG EEARL
-#define EEARL3_REG EEARL
-#define EEARL4_REG EEARL
-#define EEARL5_REG EEARL
-#define EEARL6_REG EEARL
-#define EEARL7_REG EEARL
-
-/* MCUCR */
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-#define SPIPS_REG MCUCR
-
-/* PICR0H */
-#define PICR0_8_REG PICR0H
-#define PICR0_9_REG PICR0H
-#define PICR0_10_REG PICR0H
-#define PICR0_11_REG PICR0H
-#define PCST0_REG PICR0H
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-#define INTF2_REG EIFR
-
-/* MUBRRL */
-#define MUBRR0_REG MUBRRL
-#define MUBRR1_REG MUBRRL
-#define MUBRR2_REG MUBRRL
-#define MUBRR3_REG MUBRRL
-#define MUBRR4_REG MUBRRL
-#define MUBRR5_REG MUBRRL
-#define MUBRR6_REG MUBRRL
-#define MUBRR7_REG MUBRRL
-
-/* MUBRRH */
-#define MUBRR8_REG MUBRRH
-#define MUBRR9_REG MUBRRH
-#define MUBRR10_REG MUBRRH
-#define MUBRR11_REG MUBRRH
-#define MUBRR12_REG MUBRRH
-#define MUBRR13_REG MUBRRH
-#define MUBRR14_REG MUBRRH
-#define MUBRR15_REG MUBRRH
-
-/* OCR2SAH */
-#define OCR2SA_8_REG OCR2SAH
-#define OCR2SA_9_REG OCR2SAH
-#define OCR2SA_10_REG OCR2SAH
-#define OCR2SA_11_REG OCR2SAH
-
-/* OCR0SBL */
-#define OCR0SB_0_REG OCR0SBL
-#define OCR0SB_1_REG OCR0SBL
-#define OCR0SB_2_REG OCR0SBL
-#define OCR0SB_3_REG OCR0SBL
-#define OCR0SB_4_REG OCR0SBL
-#define OCR0SB_5_REG OCR0SBL
-#define OCR0SB_6_REG OCR0SBL
-#define OCR0SB_7_REG OCR0SBL
-
-/* OCR0SBH */
-#define OCR0SB_8_REG OCR0SBH
-#define OCR0SB_9_REG OCR0SBH
-#define OCR0SB_00_REG OCR0SBH
-#define OCR0SB_01_REG OCR0SBH
-
-/* PICR0L */
-#define PICR0_0_REG PICR0L
-#define PICR0_1_REG PICR0L
-#define PICR0_2_REG PICR0L
-#define PICR0_3_REG PICR0L
-#define PICR0_4_REG PICR0L
-#define PICR0_5_REG PICR0L
-#define PICR0_6_REG PICR0L
-#define PICR0_7_REG PICR0L
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* PSOC0 */
-#define POEN0A_REG PSOC0
-#define POEN0B_REG PSOC0
-#define PSYNC00_REG PSOC0
-#define PSYNC01_REG PSOC0
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ADTS3_REG ADCSRB
-#define ADASCR_REG ADCSRB
-#define ADHSM_REG ADCSRB
-
-/* OCR0A */
-/* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */
-
-/* ACSR */
-#define AC0O_REG ACSR
-#define AC1O_REG ACSR
-#define AC2O_REG ACSR
-#define AC0IF_REG ACSR
-#define AC1IF_REG ACSR
-#define AC2IF_REG ACSR
-#define ACCKDIV_REG ACSR
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* UBRRH */
-#define UBRR8_REG UBRRH
-#define UBRR9_REG UBRRH
-#define UBRR10_REG UBRRH
-#define UBRR11_REG UBRRH
-
-/* DACL */
-#define DACL0_REG DACL
-#define DACL1_REG DACL
-#define DACL2_REG DACL
-#define DACL3_REG DACL
-#define DACL4_REG DACL
-#define DACL5_REG DACL
-#define DACL6_REG DACL
-#define DACL7_REG DACL
-
-/* UBRRL */
-#define UBRR0_REG UBRRL
-#define UBRR1_REG UBRRL
-#define UBRR2_REG UBRRL
-#define UBRR3_REG UBRRL
-#define UBRR4_REG UBRRL
-#define UBRR5_REG UBRRL
-#define UBRR6_REG UBRRL
-#define UBRR7_REG UBRRL
-
-/* DACH */
-#define DACH0_REG DACH
-#define DACH1_REG DACH
-#define DACH2_REG DACH
-#define DACH3_REG DACH
-#define DACH4_REG DACH
-#define DACH5_REG DACH
-#define DACH6_REG DACH
-#define DACH7_REG DACH
-
-/* OCR0RAH */
-#define OCR0RA_8_REG OCR0RAH
-#define OCR0RA_9_REG OCR0RAH
-#define OCR0RA_00_REG OCR0RAH
-#define OCR0RA_01_REG OCR0RAH
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* PIM0 */
-#define PEOPE0_REG PIM0
-#define PEVE0A_REG PIM0
-#define PEVE0B_REG PIM0
-#define PSEIE0_REG PIM0
-
-/* PIFR2 */
-#define PEOP2_REG PIFR2
-#define PRN20_REG PIFR2
-#define PRN21_REG PIFR2
-#define PEV2A_REG PIFR2
-#define PEV2B_REG PIFR2
-#define PSEI2_REG PIFR2
-#define POAC2A_REG PIFR2
-#define POAC2B_REG PIFR2
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* PSOC2 */
-#define POEN2A_REG PSOC2
-#define POEN2C_REG PSOC2
-#define POEN2B_REG PSOC2
-#define POEN2D_REG PSOC2
-#define PSYNC2_0_REG PSOC2
-#define PSYNC2_1_REG PSOC2
-#define POS22_REG PSOC2
-#define POS23_REG PSOC2
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* AMP0CSR */
-#define AMP0TS0_REG AMP0CSR
-#define AMP0TS1_REG AMP0CSR
-#define AMP0G0_REG AMP0CSR
-#define AMP0G1_REG AMP0CSR
-#define AMP0IS_REG AMP0CSR
-#define AMP0EN_REG AMP0CSR
-
-/* UDR */
-#define UDR0_REG UDR
-#define UDR1_REG UDR
-#define UDR2_REG UDR
-#define UDR3_REG UDR
-#define UDR4_REG UDR
-#define UDR5_REG UDR
-#define UDR6_REG UDR
-#define UDR7_REG UDR
-
-/* DACON */
-#define DAEN_REG DACON
-#define DALA_REG DACON
-#define DATS0_REG DACON
-#define DATS1_REG DACON
-#define DATS2_REG DACON
-#define DAATE_REG DACON
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* AC0CON */
-#define AC0M0_REG AC0CON
-#define AC0M1_REG AC0CON
-#define AC0M2_REG AC0CON
-#define AC0IS0_REG AC0CON
-#define AC0IS1_REG AC0CON
-#define AC0IE_REG AC0CON
-#define AC0EN_REG AC0CON
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* pins mapping */
-#define MISO_PORT PORTB
-#define MISO_BIT 0
-#define PSCOUT20_PORT PORTB
-#define PSCOUT20_BIT 0
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 1
-#define PSCOUT21_PORT PORTB
-#define PSCOUT21_BIT 1
-
-#define ADC5_PORT PORTB
-#define ADC5_BIT 2
-#define INT1_PORT PORTB
-#define INT1_BIT 2
-
-#define AMP0-_PORT PORTB
-#define AMP0-_BIT 3
-
-#define AMP0+_PORT PORTB
-#define AMP0+_BIT 4
-
-#define ADC6_PORT PORTB
-#define ADC6_BIT 5
-#define INT2_PORT PORTB
-#define INT2_BIT 5
-
-#define ADC7_PORT PORTB
-#define ADC7_BIT 6
-#define PSCOUT11_PORT PORTB
-#define PSCOUT11_BIT 6
-#define ICP1B_PORT PORTB
-#define ICP1B_BIT 6
-
-#define ADC4_PORT PORTB
-#define ADC4_BIT 7
-#define PSCOUT01_PORT PORTB
-#define PSCOUT01_BIT 7
-#define SCK_PORT PORTB
-#define SCK_BIT 7
-
-#define PSCOUT00_PORT PORTD
-#define PSCOUT00_BIT 0
-#define XCK_PORT PORTD
-#define XCK_BIT 0
-#define SSA_PORT PORTD
-#define SSA_BIT 0
-
-#define PSCIN0_PORT PORTD
-#define PSCIN0_BIT 1
-#define CLK0_PORT PORTD
-#define CLK0_BIT 1
-
-#define PSCIN2_PORT PORTD
-#define PSCIN2_BIT 2
-#define OC1A_PORT PORTD
-#define OC1A_BIT 2
-#define MISO_A_PORT PORTD
-#define MISO_A_BIT 2
-
-#define TXD_PORT PORTD
-#define TXD_BIT 3
-#define DALI_PORT PORTD
-#define DALI_BIT 3
-#define OC0A_PORT PORTD
-#define OC0A_BIT 3
-#define SS_PORT PORTD
-#define SS_BIT 3
-#define MOSI_A_PORT PORTD
-#define MOSI_A_BIT 3
-
-#define ADC1_PORT PORTD
-#define ADC1_BIT 4
-#define RXD_PORT PORTD
-#define RXD_BIT 4
-#define DALI_PORT PORTD
-#define DALI_BIT 4
-#define ICP1_PORT PORTD
-#define ICP1_BIT 4
-#define SCK_A_PORT PORTD
-#define SCK_A_BIT 4
-
-#define ADC2_PORT PORTD
-#define ADC2_BIT 5
-#define ACMP2_PORT PORTD
-#define ACMP2_BIT 5
-
-#define ADC3_PORT PORTD
-#define ADC3_BIT 6
-#define ACMPM_PORT PORTD
-#define ACMPM_BIT 6
-#define INT0_PORT PORTD
-#define INT0_BIT 6
-
-#define ACMP0_PORT PORTD
-#define ACMP0_BIT 7
-
-#define RESET_PORT PORTE
-#define RESET_BIT 0
-#define OCD_PORT PORTE
-#define OCD_BIT 0
-
-#define OC0B_PORT PORTE
-#define OC0B_BIT 1
-#define XTAL1_PORT PORTE
-#define XTAL1_BIT 1
-
-#define ADC0_PORT PORTE
-#define ADC0_BIT 2
-#define XTAL2_PORT PORTE
-#define XTAL2_BIT 2
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW_TOTAL_NUM 2
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* EUDR */
-#define EUDR0_REG EUDR
-#define EUDR1_REG EUDR
-#define EUDR2_REG EUDR
-#define EUDR3_REG EUDR
-#define EUDR4_REG EUDR
-#define EUDR5_REG EUDR
-#define EUDR6_REG EUDR
-#define EUDR7_REG EUDR
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* OCR2SBH */
-#define OCR2SB_8_REG OCR2SBH
-#define OCR2SB_9_REG OCR2SBH
-#define OCR2SB_10_REG OCR2SBH
-#define OCR2SB_11_REG OCR2SBH
-
-/* OCR2SBL */
-#define OCR2SB_0_REG OCR2SBL
-#define OCR2SB_1_REG OCR2SBL
-#define OCR2SB_2_REG OCR2SBL
-#define OCR2SB_3_REG OCR2SBL
-#define OCR2SB_4_REG OCR2SBL
-#define OCR2SB_5_REG OCR2SBL
-#define OCR2SB_6_REG OCR2SBL
-#define OCR2SB_7_REG OCR2SBL
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* OCR0B */
-/* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* UCSRA */
-#define MPCM_REG UCSRA
-#define U2X_REG UCSRA
-#define UPE_REG UCSRA
-#define DOR_REG UCSRA
-#define FE_REG UCSRA
-#define UDRE_REG UCSRA
-#define TXC_REG UCSRA
-#define RXC_REG UCSRA
-
-/* UCSRB */
-#define TXB8_REG UCSRB
-#define RXB8_REG UCSRB
-#define UCSZ2_REG UCSRB
-#define TXEN_REG UCSRB
-#define RXEN_REG UCSRB
-#define UDRIE_REG UCSRB
-#define TXCIE_REG UCSRB
-#define RXCIE_REG UCSRB
-
-/* UCSRC */
-#define UCPOL_REG UCSRC
-#define UCSZ0_REG UCSRC
-#define UCSZ1_REG UCSRC
-#define USBS_REG UCSRC
-#define UPM0_REG UCSRC
-#define UPM1_REG UCSRC
-#define UMSEL0_REG UCSRC
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* AC1CON */
-#define AC1M0_REG AC1CON
-#define AC1M1_REG AC1CON
-#define AC1M2_REG AC1CON
-#define AC1ICE_REG AC1CON
-#define AC1IS0_REG AC1CON
-#define AC1IS1_REG AC1CON
-#define AC1IE_REG AC1CON
-#define AC1EN_REG AC1CON
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSART0_REG PRR
-#define PRSPI_REG PRR
-#define PRTIM0_REG PRR
-#define PRTIM1_REG PRR
-#define PRPSC0_REG PRR
-#define PRPSC1_REG PRR
-#define PRPSC2_REG PRR
-
-/* PCNF0 */
-#define PCLKSEL0_REG PCNF0
-#define POP0_REG PCNF0
-#define PMODE00_REG PCNF0
-#define PMODE01_REG PCNF0
-#define PLOCK0_REG PCNF0
-#define PALOCK0_REG PCNF0
-#define PFIFTY0_REG PCNF0
-
-/* PCNF1 */
-#define PCLKSEL1_REG PCNF1
-#define POP1_REG PCNF1
-#define PMODE10_REG PCNF1
-#define PMODE11_REG PCNF1
-#define PLOCK1_REG PCNF1
-#define PALOCK1_REG PCNF1
-#define PFIFTY1_REG PCNF1
-
-/* PCNF2 */
-#define POME2_REG PCNF2
-#define PCLKSEL2_REG PCNF2
-#define POP2_REG PCNF2
-#define PMODE20_REG PCNF2
-#define PMODE21_REG PCNF2
-#define PLOCK2_REG PCNF2
-#define PALOCK2_REG PCNF2
-#define PFIFTY2_REG PCNF2
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* AMP1CSR */
-#define AMP1TS0_REG AMP1CSR
-#define AMP1TS1_REG AMP1CSR
-#define AMP1G0_REG AMP1CSR
-#define AMP1G1_REG AMP1CSR
-#define AMP1IS_REG AMP1CSR
-#define AMP1EN_REG AMP1CSR
-
-/* AC2CON */
-#define AC2M0_REG AC2CON
-#define AC2M1_REG AC2CON
-#define AC2M2_REG AC2CON
-#define AC2IS0_REG AC2CON
-#define AC2IS1_REG AC2CON
-#define AC2IE_REG AC2CON
-#define AC2EN_REG AC2CON
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-#define INT3_REG EIMSK
-
-/* PFRC0A */
-#define PRFM0A0_REG PFRC0A
-#define PRFM0A1_REG PFRC0A
-#define PRFM0A2_REG PFRC0A
-#define PRFM0A3_REG PFRC0A
-#define PFLTE0A_REG PFRC0A
-#define PELEV0A_REG PFRC0A
-#define PISEL0A_REG PFRC0A
-#define PCAE0A_REG PFRC0A
-
-/* PFRC0B */
-#define PRFM0B0_REG PFRC0B
-#define PRFM0B1_REG PFRC0B
-#define PRFM0B2_REG PFRC0B
-#define PRFM0B3_REG PFRC0B
-#define PFLTE0B_REG PFRC0B
-#define PELEV0B_REG PFRC0B
-#define PISEL0B_REG PFRC0B
-#define PCAE0B_REG PFRC0B
-
-/* PICR1H */
-#define PICR1_8_REG PICR1H
-#define PICR1_9_REG PICR1H
-#define PICR1_10_REG PICR1H
-#define PICR1_11_REG PICR1H
-
-/* PICR1L */
-#define PICR1_0_REG PICR1L
-#define PICR1_1_REG PICR1L
-#define PICR1_2_REG PICR1L
-#define PICR1_3_REG PICR1L
-#define PICR1_4_REG PICR1L
-#define PICR1_5_REG PICR1L
-#define PICR1_6_REG PICR1L
-#define PICR1_7_REG PICR1L
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-#define ISC20_REG EICRA
-#define ISC21_REG EICRA
-#define ISC30_REG EICRA
-#define ISC31_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define ADC8D_REG DIDR1
-#define ADC9D_REG DIDR1
-#define ADC10D_REG DIDR1
-#define AMP0ND_REG DIDR1
-#define AMP0PD_REG DIDR1
-#define ACMP0D_REG DIDR1
-
-/* OCR1RAH */
-#define OCR1RA_8_REG OCR1RAH
-#define OCR1RA_9_REG OCR1RAH
-#define OCR1RA_10_REG OCR1RAH
-#define OCR1RA_11_REG OCR1RAH
-
-/* OCR1RAL */
-#define OCR1RA_0_REG OCR1RAL
-#define OCR1RA_1_REG OCR1RAL
-#define OCR1RA_2_REG OCR1RAL
-#define OCR1RA_3_REG OCR1RAL
-#define OCR1RA_4_REG OCR1RAL
-#define OCR1RA_5_REG OCR1RAL
-#define OCR1RA_6_REG OCR1RAL
-#define OCR1RA_7_REG OCR1RAL
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* OCR0RBH */
-#define OCR0RB_8_REG OCR0RBH
-#define OCR0RB_9_REG OCR0RBH
-#define OCR0RB_00_REG OCR0RBH
-#define OCR0RB_01_REG OCR0RBH
-#define OCR0RB_02_REG OCR0RBH
-#define OCR0RB_03_REG OCR0RBH
-#define OCR0RB_04_REG OCR0RBH
-#define OCR0RB_05_REG OCR0RBH
-
-/* OCR0RBL */
-#define OCR0RB_0_REG OCR0RBL
-#define OCR0RB_1_REG OCR0RBL
-#define OCR0RB_2_REG OCR0RBL
-#define OCR0RB_3_REG OCR0RBL
-#define OCR0RB_4_REG OCR0RBL
-#define OCR0RB_5_REG OCR0RBL
-#define OCR0RB_6_REG OCR0RBL
-#define OCR0RB_7_REG OCR0RBL
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-
-/* OCR0RAL */
-#define OCR0RA_0_REG OCR0RAL
-#define OCR0RA_1_REG OCR0RAL
-#define OCR0RA_2_REG OCR0RAL
-#define OCR0RA_3_REG OCR0RAL
-#define OCR0RA_4_REG OCR0RAL
-#define OCR0RA_5_REG OCR0RAL
-#define OCR0RA_6_REG OCR0RAL
-#define OCR0RA_7_REG OCR0RAL
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR3 */
-#define GPIOR30_REG GPIOR3
-#define GPIOR31_REG GPIOR3
-#define GPIOR32_REG GPIOR3
-#define GPIOR33_REG GPIOR3
-#define GPIOR34_REG GPIOR3
-#define GPIOR35_REG GPIOR3
-#define GPIOR36_REG GPIOR3
-#define GPIOR37_REG GPIOR3
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* PFRC2B */
-#define PRFM2B0_REG PFRC2B
-#define PRFM2B1_REG PFRC2B
-#define PRFM2B2_REG PFRC2B
-#define PRFM2B3_REG PFRC2B
-#define PFLTE2B_REG PFRC2B
-#define PELEV2B_REG PFRC2B
-#define PISEL2B_REG PFRC2B
-#define PCAE2B_REG PFRC2B
-
-/* PFRC2A */
-#define PRFM2A0_REG PFRC2A
-#define PRFM2A1_REG PFRC2A
-#define PRFM2A2_REG PFRC2A
-#define PRFM2A3_REG PFRC2A
-#define PFLTE2A_REG PFRC2A
-#define PELEV2A_REG PFRC2A
-#define PISEL2A_REG PFRC2A
-#define PCAE2A_REG PFRC2A
-
-/* OCR2SAL */
-#define OCR2SA_0_REG OCR2SAL
-#define OCR2SA_1_REG OCR2SAL
-#define OCR2SA_2_REG OCR2SAL
-#define OCR2SA_3_REG OCR2SAL
-#define OCR2SA_4_REG OCR2SAL
-#define OCR2SA_5_REG OCR2SAL
-#define OCR2SA_6_REG OCR2SAL
-#define OCR2SA_7_REG OCR2SAL
-
-/* EUCSRA */
-#define URxS0_REG EUCSRA
-#define URxS1_REG EUCSRA
-#define URxS2_REG EUCSRA
-#define URxS3_REG EUCSRA
-#define UTxS0_REG EUCSRA
-#define UTxS1_REG EUCSRA
-#define UTxS2_REG EUCSRA
-#define UTxS3_REG EUCSRA
-
-/* EUCSRB */
-#define BODR_REG EUCSRB
-#define EMCH_REG EUCSRB
-#define EUSBS_REG EUCSRB
-#define EUSART_REG EUCSRB
-
-/* EUCSRC */
-#define STP0_REG EUCSRC
-#define STP1_REG EUCSRC
-#define F1617_REG EUCSRC
-#define FEM_REG EUCSRC
-
-/* PCTL0 */
-#define PRUN0_REG PCTL0
-#define PCCYC0_REG PCTL0
-#define PARUN0_REG PCTL0
-#define PAOC0A_REG PCTL0
-#define PAOC0B_REG PCTL0
-#define PBFM0_REG PCTL0
-#define PPRE00_REG PCTL0
-#define PPRE01_REG PCTL0
-
-/* PCTL1 */
-#define PRUN1_REG PCTL1
-#define PCCYC1_REG PCTL1
-#define PARUN1_REG PCTL1
-#define PAOC1A_REG PCTL1
-#define PAOC1B_REG PCTL1
-#define PBFM1_REG PCTL1
-#define PPRE10_REG PCTL1
-#define PPRE11_REG PCTL1
-
-/* PCTL2 */
-#define PRUN2_REG PCTL2
-#define PCCYC2_REG PCTL2
-#define PARUN2_REG PCTL2
-#define PAOC2A_REG PCTL2
-#define PAOC2B_REG PCTL2
-#define PBFM2_REG PCTL2
-#define PPRE20_REG PCTL2
-#define PPRE21_REG PCTL2
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* GTCCR */
-#define PSR10_REG GTCCR
-#define ICPSEL1_REG GTCCR
-#define TSM_REG GTCCR
-#define PSRSYNC_REG GTCCR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* POM2 */
-#define POMV2A0_REG POM2
-#define POMV2A1_REG POM2
-#define POMV2A2_REG POM2
-#define POMV2A3_REG POM2
-#define POMV2B0_REG POM2
-#define POMV2B1_REG POM2
-#define POMV2B2_REG POM2
-#define POMV2B3_REG POM2
-
-/* OCR2RBL */
-#define OCR2RB_0_REG OCR2RBL
-#define OCR2RB_1_REG OCR2RBL
-#define OCR2RB_2_REG OCR2RBL
-#define OCR2RB_3_REG OCR2RBL
-#define OCR2RB_4_REG OCR2RBL
-#define OCR2RB_5_REG OCR2RBL
-#define OCR2RB_6_REG OCR2RBL
-#define OCR2RB_7_REG OCR2RBL
-
-/* PICR2H */
-#define PICR2_8_REG PICR2H
-#define PICR2_9_REG PICR2H
-#define PICR2_10_REG PICR2H
-#define PICR2_11_REG PICR2H
-
-/* OCR2RBH */
-#define OCR2RB_8_REG OCR2RBH
-#define OCR2RB_9_REG OCR2RBH
-#define OCR2RB_10_REG OCR2RBH
-#define OCR2RB_11_REG OCR2RBH
-#define OCR2RB_12_REG OCR2RBH
-#define OCR2RB_13_REG OCR2RBH
-#define OCR2RB_14_REG OCR2RBH
-#define OCR2RB_15_REG OCR2RBH
-
-/* PICR2L */
-#define PICR2_0_REG PICR2L
-#define PICR2_1_REG PICR2L
-#define PICR2_2_REG PICR2L
-#define PICR2_3_REG PICR2L
-#define PICR2_4_REG PICR2L
-#define PICR2_5_REG PICR2L
-#define PICR2_6_REG PICR2L
-#define PICR2_7_REG PICR2L
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* PLLCSR */
-#define PLOCK_REG PLLCSR
-#define PLLE_REG PLLCSR
-#define PLLF_REG PLLCSR
-
-/* OCR2RAH */
-#define OCR2RA_8_REG OCR2RAH
-#define OCR2RA_9_REG OCR2RAH
-#define OCR2RA_10_REG OCR2RAH
-#define OCR2RA_11_REG OCR2RAH
-
-/* OCR2RAL */
-#define OCR2RA_0_REG OCR2RAL
-#define OCR2RA_1_REG OCR2RAL
-#define OCR2RA_2_REG OCR2RAL
-#define OCR2RA_3_REG OCR2RAL
-#define OCR2RA_4_REG OCR2RAL
-#define OCR2RA_5_REG OCR2RAL
-#define OCR2RA_6_REG OCR2RAL
-#define OCR2RA_7_REG OCR2RAL
-
-/* OCR0SAL */
-#define OCR0SA_0_REG OCR0SAL
-#define OCR0SA_1_REG OCR0SAL
-#define OCR0SA_2_REG OCR0SAL
-#define OCR0SA_3_REG OCR0SAL
-#define OCR0SA_4_REG OCR0SAL
-#define OCR0SA_5_REG OCR0SAL
-#define OCR0SA_6_REG OCR0SAL
-#define OCR0SA_7_REG OCR0SAL
-
-/* OCR0SAH */
-#define OCR0SA_8_REG OCR0SAH
-#define OCR0SA_9_REG OCR0SAH
-#define OCR0SA_00_REG OCR0SAH
-#define OCR0SA_01_REG OCR0SAH
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-#define EEAR10_REG EEARH
-#define EEAR11_REG EEARH
-
-/* EEARL */
-#define EEARL0_REG EEARL
-#define EEARL1_REG EEARL
-#define EEARL2_REG EEARL
-#define EEARL3_REG EEARL
-#define EEARL4_REG EEARL
-#define EEARL5_REG EEARL
-#define EEARL6_REG EEARL
-#define EEARL7_REG EEARL
-
-/* MCUCR */
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-#define SPIPS_REG MCUCR
-
-/* PICR0H */
-#define PICR0_8_REG PICR0H
-#define PICR0_9_REG PICR0H
-#define PICR0_10_REG PICR0H
-#define PICR0_11_REG PICR0H
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-#define INTF2_REG EIFR
-#define INTF3_REG EIFR
-
-/* MUBRRL */
-#define MUBRR0_REG MUBRRL
-#define MUBRR1_REG MUBRRL
-#define MUBRR2_REG MUBRRL
-#define MUBRR3_REG MUBRRL
-#define MUBRR4_REG MUBRRL
-#define MUBRR5_REG MUBRRL
-#define MUBRR6_REG MUBRRL
-#define MUBRR7_REG MUBRRL
-
-/* MUBRRH */
-#define MUBRR8_REG MUBRRH
-#define MUBRR9_REG MUBRRH
-#define MUBRR10_REG MUBRRH
-#define MUBRR11_REG MUBRRH
-#define MUBRR12_REG MUBRRH
-#define MUBRR13_REG MUBRRH
-#define MUBRR14_REG MUBRRH
-#define MUBRR15_REG MUBRRH
-
-/* OCR2SAH */
-#define OCR2SA_8_REG OCR2SAH
-#define OCR2SA_9_REG OCR2SAH
-#define OCR2SA_10_REG OCR2SAH
-#define OCR2SA_11_REG OCR2SAH
-
-/* OCR0SBL */
-#define OCR0SB_0_REG OCR0SBL
-#define OCR0SB_1_REG OCR0SBL
-#define OCR0SB_2_REG OCR0SBL
-#define OCR0SB_3_REG OCR0SBL
-#define OCR0SB_4_REG OCR0SBL
-#define OCR0SB_5_REG OCR0SBL
-#define OCR0SB_6_REG OCR0SBL
-#define OCR0SB_7_REG OCR0SBL
-
-/* OCR0SBH */
-#define OCR0SB_8_REG OCR0SBH
-#define OCR0SB_9_REG OCR0SBH
-#define OCR0SB_00_REG OCR0SBH
-#define OCR0SB_01_REG OCR0SBH
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* PFRC1B */
-#define PRFM1B0_REG PFRC1B
-#define PRFM1B1_REG PFRC1B
-#define PRFM1B2_REG PFRC1B
-#define PRFM1B3_REG PFRC1B
-#define PFLTE1B_REG PFRC1B
-#define PELEV1B_REG PFRC1B
-#define PISEL1B_REG PFRC1B
-#define PCAE1B_REG PFRC1B
-
-/* PFRC1A */
-#define PRFM1A0_REG PFRC1A
-#define PRFM1A1_REG PFRC1A
-#define PRFM1A2_REG PFRC1A
-#define PRFM1A3_REG PFRC1A
-#define PFLTE1A_REG PFRC1A
-#define PELEV1A_REG PFRC1A
-#define PISEL1A_REG PFRC1A
-#define PCAE1A_REG PFRC1A
-
-/* PICR0L */
-#define PICR0_0_REG PICR0L
-#define PICR0_1_REG PICR0L
-#define PICR0_2_REG PICR0L
-#define PICR0_3_REG PICR0L
-#define PICR0_4_REG PICR0L
-#define PICR0_5_REG PICR0L
-#define PICR0_6_REG PICR0L
-#define PICR0_7_REG PICR0L
-
-/* OCR1SAL */
-#define OCR1SA_0_REG OCR1SAL
-#define OCR1SA_1_REG OCR1SAL
-#define OCR1SA_2_REG OCR1SAL
-#define OCR1SA_3_REG OCR1SAL
-#define OCR1SA_4_REG OCR1SAL
-#define OCR1SA_5_REG OCR1SAL
-#define OCR1SA_6_REG OCR1SAL
-#define OCR1SA_7_REG OCR1SAL
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* PSOC0 */
-#define POEN0A_REG PSOC0
-#define POEN0B_REG PSOC0
-#define PSYNC00_REG PSOC0
-#define PSYNC01_REG PSOC0
-
-/* PSOC1 */
-#define POEN1A_REG PSOC1
-#define POEN1B_REG PSOC1
-#define PSYNC1_0_REG PSOC1
-#define PSYNC1_1_REG PSOC1
-
-/* OCR0A */
-/* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */
-
-/* ACSR */
-#define AC0O_REG ACSR
-#define AC1O_REG ACSR
-#define AC2O_REG ACSR
-#define AC0IF_REG ACSR
-#define AC1IF_REG ACSR
-#define AC2IF_REG ACSR
-#define ACCKDIV_REG ACSR
-
-/* OCR1RBL */
-#define OCR1RB_0_REG OCR1RBL
-#define OCR1RB_1_REG OCR1RBL
-#define OCR1RB_2_REG OCR1RBL
-#define OCR1RB_3_REG OCR1RBL
-#define OCR1RB_4_REG OCR1RBL
-#define OCR1RB_5_REG OCR1RBL
-#define OCR1RB_6_REG OCR1RBL
-#define OCR1RB_7_REG OCR1RBL
-
-/* OCR1SBH */
-#define OCR1SB_8_REG OCR1SBH
-#define OCR1SB_9_REG OCR1SBH
-#define OCR1SB_10_REG OCR1SBH
-#define OCR1SB_11_REG OCR1SBH
-
-/* OCR1RBH */
-#define OCR1RB_8_REG OCR1RBH
-#define OCR1RB_9_REG OCR1RBH
-#define OCR1RB_10_REG OCR1RBH
-#define OCR1RB_11_REG OCR1RBH
-#define OCR1RB_12_REG OCR1RBH
-#define OCR1RB_13_REG OCR1RBH
-#define OCR1RB_14_REG OCR1RBH
-#define OCR1RB_15_REG OCR1RBH
-
-/* OCR1SBL */
-#define OCR1SB_0_REG OCR1SBL
-#define OCR1SB_1_REG OCR1SBL
-#define OCR1SB_2_REG OCR1SBL
-#define OCR1SB_3_REG OCR1SBL
-#define OCR1SB_4_REG OCR1SBL
-#define OCR1SB_5_REG OCR1SBL
-#define OCR1SB_6_REG OCR1SBL
-#define OCR1SB_7_REG OCR1SBL
-
-/* OCR1SAH */
-#define OCR1SA_8_REG OCR1SAH
-#define OCR1SA_9_REG OCR1SAH
-#define OCR1SA_10_REG OCR1SAH
-#define OCR1SA_11_REG OCR1SAH
-
-/* UBRRH */
-#define UBRR8_REG UBRRH
-#define UBRR9_REG UBRRH
-#define UBRR10_REG UBRRH
-#define UBRR11_REG UBRRH
-
-/* DACL */
-#define DACL0_REG DACL
-#define DACL1_REG DACL
-#define DACL2_REG DACL
-#define DACL3_REG DACL
-#define DACL4_REG DACL
-#define DACL5_REG DACL
-#define DACL6_REG DACL
-#define DACL7_REG DACL
-
-/* UBRRL */
-#define UBRR0_REG UBRRL
-#define UBRR1_REG UBRRL
-#define UBRR2_REG UBRRL
-#define UBRR3_REG UBRRL
-#define UBRR4_REG UBRRL
-#define UBRR5_REG UBRRL
-#define UBRR6_REG UBRRL
-#define UBRR7_REG UBRRL
-
-/* DACH */
-#define DACH0_REG DACH
-#define DACH1_REG DACH
-#define DACH2_REG DACH
-#define DACH3_REG DACH
-#define DACH4_REG DACH
-#define DACH5_REG DACH
-#define DACH6_REG DACH
-#define DACH7_REG DACH
-
-/* OCR0RAH */
-#define OCR0RA_8_REG OCR0RAH
-#define OCR0RA_9_REG OCR0RAH
-#define OCR0RA_00_REG OCR0RAH
-#define OCR0RA_01_REG OCR0RAH
-
-/* PIM2 */
-#define PEOPE2_REG PIM2
-#define PEVE2A_REG PIM2
-#define PEVE2B_REG PIM2
-#define PSEIE2_REG PIM2
-
-/* PIM0 */
-#define PEOPE0_REG PIM0
-#define PEVE0A_REG PIM0
-#define PEVE0B_REG PIM0
-#define PSEIE0_REG PIM0
-
-/* PIM1 */
-#define PEOPE1_REG PIM1
-#define PEVE1A_REG PIM1
-#define PEVE1B_REG PIM1
-#define PSEIE1_REG PIM1
-
-/* PIFR2 */
-#define PEOP2_REG PIFR2
-#define PRN20_REG PIFR2
-#define PRN21_REG PIFR2
-#define PEV2A_REG PIFR2
-#define PEV2B_REG PIFR2
-#define PSEI2_REG PIFR2
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* PIFR0 */
-#define PEOP0_REG PIFR0
-#define PRN00_REG PIFR0
-#define PRN01_REG PIFR0
-#define PEV0A_REG PIFR0
-#define PEV0B_REG PIFR0
-#define PSEI0_REG PIFR0
-
-/* PIFR1 */
-#define PEOP1_REG PIFR1
-#define PRN10_REG PIFR1
-#define PRN11_REG PIFR1
-#define PEV1A_REG PIFR1
-#define PEV1B_REG PIFR1
-#define PSEI1_REG PIFR1
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* PSOC2 */
-#define POEN2A_REG PSOC2
-#define POEN2C_REG PSOC2
-#define POEN2B_REG PSOC2
-#define POEN2D_REG PSOC2
-#define PSYNC2_0_REG PSOC2
-#define PSYNC2_1_REG PSOC2
-#define POS22_REG PSOC2
-#define POS23_REG PSOC2
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* AMP0CSR */
-#define AMP0TS0_REG AMP0CSR
-#define AMP0TS1_REG AMP0CSR
-#define AMP0G0_REG AMP0CSR
-#define AMP0G1_REG AMP0CSR
-#define AMP0IS_REG AMP0CSR
-#define AMP0EN_REG AMP0CSR
-
-/* UDR */
-#define UDR0_REG UDR
-#define UDR1_REG UDR
-#define UDR2_REG UDR
-#define UDR3_REG UDR
-#define UDR4_REG UDR
-#define UDR5_REG UDR
-#define UDR6_REG UDR
-#define UDR7_REG UDR
-
-/* DACON */
-#define DAEN_REG DACON
-#define DALA_REG DACON
-#define DATS0_REG DACON
-#define DATS1_REG DACON
-#define DATS2_REG DACON
-#define DAATE_REG DACON
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* AC0CON */
-#define AC0M0_REG AC0CON
-#define AC0M1_REG AC0CON
-#define AC0M2_REG AC0CON
-#define AC0IS0_REG AC0CON
-#define AC0IS1_REG AC0CON
-#define AC0IE_REG AC0CON
-#define AC0EN_REG AC0CON
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ADTS3_REG ADCSRB
-#define ADASCR_REG ADCSRB
-#define ADHSM_REG ADCSRB
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* pins mapping */
-#define MISO_PORT PORTB
-#define MISO_BIT 0
-#define PSCOUT20_PORT PORTB
-#define PSCOUT20_BIT 0
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 1
-#define PSCOUT21_PORT PORTB
-#define PSCOUT21_BIT 1
-
-#define ADC5_PORT PORTB
-#define ADC5_BIT 2
-#define INT1_PORT PORTB
-#define INT1_BIT 2
-
-#define AMP0-_PORT PORTB
-#define AMP0-_BIT 3
-
-#define AMP0+_PORT PORTB
-#define AMP0+_BIT 4
-
-#define ADC6_PORT PORTB
-#define ADC6_BIT 5
-#define INT2_PORT PORTB
-#define INT2_BIT 5
-
-#define ADC7_PORT PORTB
-#define ADC7_BIT 6
-#define PSCOUT11_PORT PORTB
-#define PSCOUT11_BIT 6
-#define ICP1B_PORT PORTB
-#define ICP1B_BIT 6
-
-#define ADC4_PORT PORTB
-#define ADC4_BIT 7
-#define PSCOUT01_PORT PORTB
-#define PSCOUT01_BIT 7
-#define SCK_PORT PORTB
-#define SCK_BIT 7
-
-#define INT3_PORT PORTC
-#define INT3_BIT 0
-#define PSCOUT10_PORT PORTC
-#define PSCOUT10_BIT 0
-
-#define PSCIN1_PORT PORTC
-#define PSCIN1_BIT 1
-#define OC1B_PORT PORTC
-#define OC1B_BIT 1
-
-#define T0_PORT PORTC
-#define T0_BIT 2
-#define PSCOUT22_PORT PORTC
-#define PSCOUT22_BIT 2
-
-#define T1_PORT PORTC
-#define T1_BIT 3
-#define PSCOUT23_PORT PORTC
-#define PSCOUT23_BIT 3
-
-#define ADC8_PORT PORTC
-#define ADC8_BIT 4
-#define AMP1-_PORT PORTC
-#define AMP1-_BIT 4
-
-#define ADC9_PORT PORTC
-#define ADC9_BIT 5
-#define AMP1+_PORT PORTC
-#define AMP1+_BIT 5
-
-#define ADC10_PORT PORTC
-#define ADC10_BIT 6
-#define ACMP1_PORT PORTC
-#define ACMP1_BIT 6
-
-#define D2A_PORT PORTC
-#define D2A_BIT 7
-
-#define PSCOUT00_PORT PORTD
-#define PSCOUT00_BIT 0
-#define XCK_PORT PORTD
-#define XCK_BIT 0
-#define SSA_PORT PORTD
-#define SSA_BIT 0
-
-#define PSCIN0_PORT PORTD
-#define PSCIN0_BIT 1
-#define CLK0_PORT PORTD
-#define CLK0_BIT 1
-
-#define PSCIN2_PORT PORTD
-#define PSCIN2_BIT 2
-#define OC1A_PORT PORTD
-#define OC1A_BIT 2
-#define MISO_A_PORT PORTD
-#define MISO_A_BIT 2
-
-#define TXD_PORT PORTD
-#define TXD_BIT 3
-#define DALI_PORT PORTD
-#define DALI_BIT 3
-#define OC0A_PORT PORTD
-#define OC0A_BIT 3
-#define SS_PORT PORTD
-#define SS_BIT 3
-#define MOSI_A_PORT PORTD
-#define MOSI_A_BIT 3
-
-#define ADC1_PORT PORTD
-#define ADC1_BIT 4
-#define RXD_PORT PORTD
-#define RXD_BIT 4
-#define DALI_PORT PORTD
-#define DALI_BIT 4
-#define ICP1_PORT PORTD
-#define ICP1_BIT 4
-#define SCK_A_PORT PORTD
-#define SCK_A_BIT 4
-
-#define ADC2_PORT PORTD
-#define ADC2_BIT 5
-#define ACOMP2_PORT PORTD
-#define ACOMP2_BIT 5
-
-#define ADC3_PORT PORTD
-#define ADC3_BIT 6
-#define ACMPM_PORT PORTD
-#define ACMPM_BIT 6
-#define INT0_PORT PORTD
-#define INT0_BIT 6
-
-#define ACMP0_PORT PORTD
-#define ACMP0_BIT 7
-
-#define RESET_PORT PORTE
-#define RESET_BIT 0
-#define OCD_PORT PORTE
-#define OCD_BIT 0
-
-#define OC0B_PORT PORTE
-#define OC0B_BIT 1
-#define XTAL1_PORT PORTE
-#define XTAL1_BIT 1
-
-#define ADC0_PORT PORTE
-#define ADC0_BIT 2
-#define XTAL2_PORT PORTE
-#define XTAL2_BIT 2
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW_TOTAL_NUM 2
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* EUDR */
-#define EUDR0_REG EUDR
-#define EUDR1_REG EUDR
-#define EUDR2_REG EUDR
-#define EUDR3_REG EUDR
-#define EUDR4_REG EUDR
-#define EUDR5_REG EUDR
-#define EUDR6_REG EUDR
-#define EUDR7_REG EUDR
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* OCR2SBH */
-#define OCR2SB_8_REG OCR2SBH
-#define OCR2SB_9_REG OCR2SBH
-#define OCR2SB_10_REG OCR2SBH
-#define OCR2SB_11_REG OCR2SBH
-
-/* OCR2SBL */
-#define OCR2SB_0_REG OCR2SBL
-#define OCR2SB_1_REG OCR2SBL
-#define OCR2SB_2_REG OCR2SBL
-#define OCR2SB_3_REG OCR2SBL
-#define OCR2SB_4_REG OCR2SBL
-#define OCR2SB_5_REG OCR2SBL
-#define OCR2SB_6_REG OCR2SBL
-#define OCR2SB_7_REG OCR2SBL
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* OCR0B */
-/* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* UCSRA */
-#define MPCM_REG UCSRA
-#define U2X_REG UCSRA
-#define UPE_REG UCSRA
-#define DOR_REG UCSRA
-#define FE_REG UCSRA
-#define UDRE_REG UCSRA
-#define TXC_REG UCSRA
-#define RXC_REG UCSRA
-
-/* UCSRB */
-#define TXB8_REG UCSRB
-#define RXB8_REG UCSRB
-#define UCSZ2_REG UCSRB
-#define TXEN_REG UCSRB
-#define RXEN_REG UCSRB
-#define UDRIE_REG UCSRB
-#define TXCIE_REG UCSRB
-#define RXCIE_REG UCSRB
-
-/* UCSRC */
-#define UCPOL_REG UCSRC
-#define UCSZ0_REG UCSRC
-#define UCSZ1_REG UCSRC
-#define USBS_REG UCSRC
-#define UPM0_REG UCSRC
-#define UPM1_REG UCSRC
-#define UMSEL0_REG UCSRC
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* AC1CON */
-#define AC1M0_REG AC1CON
-#define AC1M1_REG AC1CON
-#define AC1M2_REG AC1CON
-#define AC1ICE_REG AC1CON
-#define AC1IS0_REG AC1CON
-#define AC1IS1_REG AC1CON
-#define AC1IE_REG AC1CON
-#define AC1EN_REG AC1CON
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSART0_REG PRR
-#define PRSPI_REG PRR
-#define PRTIM0_REG PRR
-#define PRTIM1_REG PRR
-#define PRPSC0_REG PRR
-#define PRPSC1_REG PRR
-#define PRPSC2_REG PRR
-
-/* PCNF0 */
-#define PCLKSEL0_REG PCNF0
-#define POP0_REG PCNF0
-#define PMODE00_REG PCNF0
-#define PMODE01_REG PCNF0
-#define PLOCK0_REG PCNF0
-#define PALOCK0_REG PCNF0
-#define PFIFTY0_REG PCNF0
-
-/* PCNF1 */
-#define PCLKSEL1_REG PCNF1
-#define POP1_REG PCNF1
-#define PMODE10_REG PCNF1
-#define PMODE11_REG PCNF1
-#define PLOCK1_REG PCNF1
-#define PALOCK1_REG PCNF1
-#define PFIFTY1_REG PCNF1
-
-/* PCNF2 */
-#define POME2_REG PCNF2
-#define PCLKSEL2_REG PCNF2
-#define POP2_REG PCNF2
-#define PMODE20_REG PCNF2
-#define PMODE21_REG PCNF2
-#define PLOCK2_REG PCNF2
-#define PALOCK2_REG PCNF2
-#define PFIFTY2_REG PCNF2
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* AMP1CSR */
-#define AMP1TS0_REG AMP1CSR
-#define AMP1TS1_REG AMP1CSR
-#define AMP1G0_REG AMP1CSR
-#define AMP1G1_REG AMP1CSR
-#define AMP1IS_REG AMP1CSR
-#define AMP1EN_REG AMP1CSR
-
-/* AC2CON */
-#define AC2M0_REG AC2CON
-#define AC2M1_REG AC2CON
-#define AC2M2_REG AC2CON
-#define AC2IS0_REG AC2CON
-#define AC2IS1_REG AC2CON
-#define AC2IE_REG AC2CON
-#define AC2EN_REG AC2CON
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-#define INT3_REG EIMSK
-
-/* PFRC0A */
-#define PRFM0A0_REG PFRC0A
-#define PRFM0A1_REG PFRC0A
-#define PRFM0A2_REG PFRC0A
-#define PRFM0A3_REG PFRC0A
-#define PFLTE0A_REG PFRC0A
-#define PELEV0A_REG PFRC0A
-#define PISEL0A_REG PFRC0A
-#define PCAE0A_REG PFRC0A
-
-/* PFRC0B */
-#define PRFM0B0_REG PFRC0B
-#define PRFM0B1_REG PFRC0B
-#define PRFM0B2_REG PFRC0B
-#define PRFM0B3_REG PFRC0B
-#define PFLTE0B_REG PFRC0B
-#define PELEV0B_REG PFRC0B
-#define PISEL0B_REG PFRC0B
-#define PCAE0B_REG PFRC0B
-
-/* PICR1H */
-#define PICR1_8_REG PICR1H
-#define PICR1_9_REG PICR1H
-#define PICR1_10_REG PICR1H
-#define PICR1_11_REG PICR1H
-#define PCST1_REG PICR1H
-
-/* PICR1L */
-#define PICR1_0_REG PICR1L
-#define PICR1_1_REG PICR1L
-#define PICR1_2_REG PICR1L
-#define PICR1_3_REG PICR1L
-#define PICR1_4_REG PICR1L
-#define PICR1_5_REG PICR1L
-#define PICR1_6_REG PICR1L
-#define PICR1_7_REG PICR1L
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-#define ISC20_REG EICRA
-#define ISC21_REG EICRA
-#define ISC30_REG EICRA
-#define ISC31_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define ADC8D_REG DIDR1
-#define ADC9D_REG DIDR1
-#define ADC10D_REG DIDR1
-#define AMP0ND_REG DIDR1
-#define AMP0PD_REG DIDR1
-#define ACMP0D_REG DIDR1
-
-/* OCR1RAH */
-#define OCR1RA_8_REG OCR1RAH
-#define OCR1RA_9_REG OCR1RAH
-#define OCR1RA_10_REG OCR1RAH
-#define OCR1RA_11_REG OCR1RAH
-
-/* OCR1RAL */
-#define OCR1RA_0_REG OCR1RAL
-#define OCR1RA_1_REG OCR1RAL
-#define OCR1RA_2_REG OCR1RAL
-#define OCR1RA_3_REG OCR1RAL
-#define OCR1RA_4_REG OCR1RAL
-#define OCR1RA_5_REG OCR1RAL
-#define OCR1RA_6_REG OCR1RAL
-#define OCR1RA_7_REG OCR1RAL
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* OCR0RBH */
-#define OCR0RB_8_REG OCR0RBH
-#define OCR0RB_9_REG OCR0RBH
-#define OCR0RB_00_REG OCR0RBH
-#define OCR0RB_01_REG OCR0RBH
-#define OCR0RB_02_REG OCR0RBH
-#define OCR0RB_03_REG OCR0RBH
-#define OCR0RB_04_REG OCR0RBH
-#define OCR0RB_05_REG OCR0RBH
-
-/* OCR0RBL */
-#define OCR0RB_0_REG OCR0RBL
-#define OCR0RB_1_REG OCR0RBL
-#define OCR0RB_2_REG OCR0RBL
-#define OCR0RB_3_REG OCR0RBL
-#define OCR0RB_4_REG OCR0RBL
-#define OCR0RB_5_REG OCR0RBL
-#define OCR0RB_6_REG OCR0RBL
-#define OCR0RB_7_REG OCR0RBL
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-
-/* OCR0RAL */
-#define OCR0RA_0_REG OCR0RAL
-#define OCR0RA_1_REG OCR0RAL
-#define OCR0RA_2_REG OCR0RAL
-#define OCR0RA_3_REG OCR0RAL
-#define OCR0RA_4_REG OCR0RAL
-#define OCR0RA_5_REG OCR0RAL
-#define OCR0RA_6_REG OCR0RAL
-#define OCR0RA_7_REG OCR0RAL
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR3 */
-#define GPIOR30_REG GPIOR3
-#define GPIOR31_REG GPIOR3
-#define GPIOR32_REG GPIOR3
-#define GPIOR33_REG GPIOR3
-#define GPIOR34_REG GPIOR3
-#define GPIOR35_REG GPIOR3
-#define GPIOR36_REG GPIOR3
-#define GPIOR37_REG GPIOR3
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* PFRC2B */
-#define PRFM2B0_REG PFRC2B
-#define PRFM2B1_REG PFRC2B
-#define PRFM2B2_REG PFRC2B
-#define PRFM2B3_REG PFRC2B
-#define PFLTE2B_REG PFRC2B
-#define PELEV2B_REG PFRC2B
-#define PISEL2B_REG PFRC2B
-#define PCAE2B_REG PFRC2B
-
-/* PFRC2A */
-#define PRFM2A0_REG PFRC2A
-#define PRFM2A1_REG PFRC2A
-#define PRFM2A2_REG PFRC2A
-#define PRFM2A3_REG PFRC2A
-#define PFLTE2A_REG PFRC2A
-#define PELEV2A_REG PFRC2A
-#define PISEL2A_REG PFRC2A
-#define PCAE2A_REG PFRC2A
-
-/* OCR2SAL */
-#define OCR2SA_0_REG OCR2SAL
-#define OCR2SA_1_REG OCR2SAL
-#define OCR2SA_2_REG OCR2SAL
-#define OCR2SA_3_REG OCR2SAL
-#define OCR2SA_4_REG OCR2SAL
-#define OCR2SA_5_REG OCR2SAL
-#define OCR2SA_6_REG OCR2SAL
-#define OCR2SA_7_REG OCR2SAL
-
-/* EUCSRA */
-#define URxS0_REG EUCSRA
-#define URxS1_REG EUCSRA
-#define URxS2_REG EUCSRA
-#define URxS3_REG EUCSRA
-#define UTxS0_REG EUCSRA
-#define UTxS1_REG EUCSRA
-#define UTxS2_REG EUCSRA
-#define UTxS3_REG EUCSRA
-
-/* EUCSRB */
-#define BODR_REG EUCSRB
-#define EMCH_REG EUCSRB
-#define EUSBS_REG EUCSRB
-#define EUSART_REG EUCSRB
-
-/* EUCSRC */
-#define STP0_REG EUCSRC
-#define STP1_REG EUCSRC
-#define F1617_REG EUCSRC
-#define FEM_REG EUCSRC
-
-/* PCTL0 */
-#define PRUN0_REG PCTL0
-#define PCCYC0_REG PCTL0
-#define PARUN0_REG PCTL0
-#define PAOC0A_REG PCTL0
-#define PAOC0B_REG PCTL0
-#define PBFM0_REG PCTL0
-#define PPRE00_REG PCTL0
-#define PPRE01_REG PCTL0
-
-/* PCTL1 */
-#define PRUN1_REG PCTL1
-#define PCCYC1_REG PCTL1
-#define PARUN1_REG PCTL1
-#define PAOC1A_REG PCTL1
-#define PAOC1B_REG PCTL1
-#define PBFM1_REG PCTL1
-#define PPRE10_REG PCTL1
-#define PPRE11_REG PCTL1
-
-/* PCTL2 */
-#define PRUN2_REG PCTL2
-#define PCCYC2_REG PCTL2
-#define PARUN2_REG PCTL2
-#define PAOC2A_REG PCTL2
-#define PAOC2B_REG PCTL2
-#define PBFM2_REG PCTL2
-#define PPRE20_REG PCTL2
-#define PPRE21_REG PCTL2
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* GTCCR */
-#define PSR10_REG GTCCR
-#define ICPSEL1_REG GTCCR
-#define TSM_REG GTCCR
-#define PSRSYNC_REG GTCCR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* POM2 */
-#define POMV2A0_REG POM2
-#define POMV2A1_REG POM2
-#define POMV2A2_REG POM2
-#define POMV2A3_REG POM2
-#define POMV2B0_REG POM2
-#define POMV2B1_REG POM2
-#define POMV2B2_REG POM2
-#define POMV2B3_REG POM2
-
-/* OCR2RBL */
-#define OCR2RB_0_REG OCR2RBL
-#define OCR2RB_1_REG OCR2RBL
-#define OCR2RB_2_REG OCR2RBL
-#define OCR2RB_3_REG OCR2RBL
-#define OCR2RB_4_REG OCR2RBL
-#define OCR2RB_5_REG OCR2RBL
-#define OCR2RB_6_REG OCR2RBL
-#define OCR2RB_7_REG OCR2RBL
-
-/* PICR2H */
-#define PICR2_8_REG PICR2H
-#define PICR2_9_REG PICR2H
-#define PICR2_10_REG PICR2H
-#define PICR2_11_REG PICR2H
-#define PCST2_REG PICR2H
-
-/* OCR2RBH */
-#define OCR2RB_8_REG OCR2RBH
-#define OCR2RB_9_REG OCR2RBH
-#define OCR2RB_10_REG OCR2RBH
-#define OCR2RB_11_REG OCR2RBH
-#define OCR2RB_12_REG OCR2RBH
-#define OCR2RB_13_REG OCR2RBH
-#define OCR2RB_14_REG OCR2RBH
-#define OCR2RB_15_REG OCR2RBH
-
-/* PICR2L */
-#define PICR2_0_REG PICR2L
-#define PICR2_1_REG PICR2L
-#define PICR2_2_REG PICR2L
-#define PICR2_3_REG PICR2L
-#define PICR2_4_REG PICR2L
-#define PICR2_5_REG PICR2L
-#define PICR2_6_REG PICR2L
-#define PICR2_7_REG PICR2L
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* PLLCSR */
-#define PLOCK_REG PLLCSR
-#define PLLE_REG PLLCSR
-#define PLLF_REG PLLCSR
-
-/* OCR2RAH */
-#define OCR2RA_8_REG OCR2RAH
-#define OCR2RA_9_REG OCR2RAH
-#define OCR2RA_10_REG OCR2RAH
-#define OCR2RA_11_REG OCR2RAH
-
-/* OCR2RAL */
-#define OCR2RA_0_REG OCR2RAL
-#define OCR2RA_1_REG OCR2RAL
-#define OCR2RA_2_REG OCR2RAL
-#define OCR2RA_3_REG OCR2RAL
-#define OCR2RA_4_REG OCR2RAL
-#define OCR2RA_5_REG OCR2RAL
-#define OCR2RA_6_REG OCR2RAL
-#define OCR2RA_7_REG OCR2RAL
-
-/* OCR0SAL */
-#define OCR0SA_0_REG OCR0SAL
-#define OCR0SA_1_REG OCR0SAL
-#define OCR0SA_2_REG OCR0SAL
-#define OCR0SA_3_REG OCR0SAL
-#define OCR0SA_4_REG OCR0SAL
-#define OCR0SA_5_REG OCR0SAL
-#define OCR0SA_6_REG OCR0SAL
-#define OCR0SA_7_REG OCR0SAL
-
-/* OCR0SAH */
-#define OCR0SA_8_REG OCR0SAH
-#define OCR0SA_9_REG OCR0SAH
-#define OCR0SA_00_REG OCR0SAH
-#define OCR0SA_01_REG OCR0SAH
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-#define EEAR10_REG EEARH
-#define EEAR11_REG EEARH
-
-/* EEARL */
-#define EEARL0_REG EEARL
-#define EEARL1_REG EEARL
-#define EEARL2_REG EEARL
-#define EEARL3_REG EEARL
-#define EEARL4_REG EEARL
-#define EEARL5_REG EEARL
-#define EEARL6_REG EEARL
-#define EEARL7_REG EEARL
-
-/* MCUCR */
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-#define SPIPS_REG MCUCR
-
-/* PICR0H */
-#define PICR0_8_REG PICR0H
-#define PICR0_9_REG PICR0H
-#define PICR0_10_REG PICR0H
-#define PICR0_11_REG PICR0H
-#define PCST0_REG PICR0H
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-#define INTF2_REG EIFR
-#define INTF3_REG EIFR
-
-/* MUBRRL */
-#define MUBRR0_REG MUBRRL
-#define MUBRR1_REG MUBRRL
-#define MUBRR2_REG MUBRRL
-#define MUBRR3_REG MUBRRL
-#define MUBRR4_REG MUBRRL
-#define MUBRR5_REG MUBRRL
-#define MUBRR6_REG MUBRRL
-#define MUBRR7_REG MUBRRL
-
-/* MUBRRH */
-#define MUBRR8_REG MUBRRH
-#define MUBRR9_REG MUBRRH
-#define MUBRR10_REG MUBRRH
-#define MUBRR11_REG MUBRRH
-#define MUBRR12_REG MUBRRH
-#define MUBRR13_REG MUBRRH
-#define MUBRR14_REG MUBRRH
-#define MUBRR15_REG MUBRRH
-
-/* OCR2SAH */
-#define OCR2SA_8_REG OCR2SAH
-#define OCR2SA_9_REG OCR2SAH
-#define OCR2SA_10_REG OCR2SAH
-#define OCR2SA_11_REG OCR2SAH
-
-/* OCR0SBL */
-#define OCR0SB_0_REG OCR0SBL
-#define OCR0SB_1_REG OCR0SBL
-#define OCR0SB_2_REG OCR0SBL
-#define OCR0SB_3_REG OCR0SBL
-#define OCR0SB_4_REG OCR0SBL
-#define OCR0SB_5_REG OCR0SBL
-#define OCR0SB_6_REG OCR0SBL
-#define OCR0SB_7_REG OCR0SBL
-
-/* OCR0SBH */
-#define OCR0SB_8_REG OCR0SBH
-#define OCR0SB_9_REG OCR0SBH
-#define OCR0SB_00_REG OCR0SBH
-#define OCR0SB_01_REG OCR0SBH
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* PFRC1B */
-#define PRFM1B0_REG PFRC1B
-#define PRFM1B1_REG PFRC1B
-#define PRFM1B2_REG PFRC1B
-#define PRFM1B3_REG PFRC1B
-#define PFLTE1B_REG PFRC1B
-#define PELEV1B_REG PFRC1B
-#define PISEL1B_REG PFRC1B
-#define PCAE1B_REG PFRC1B
-
-/* PFRC1A */
-#define PRFM1A0_REG PFRC1A
-#define PRFM1A1_REG PFRC1A
-#define PRFM1A2_REG PFRC1A
-#define PRFM1A3_REG PFRC1A
-#define PFLTE1A_REG PFRC1A
-#define PELEV1A_REG PFRC1A
-#define PISEL1A_REG PFRC1A
-#define PCAE1A_REG PFRC1A
-
-/* PICR0L */
-#define PICR0_0_REG PICR0L
-#define PICR0_1_REG PICR0L
-#define PICR0_2_REG PICR0L
-#define PICR0_3_REG PICR0L
-#define PICR0_4_REG PICR0L
-#define PICR0_5_REG PICR0L
-#define PICR0_6_REG PICR0L
-#define PICR0_7_REG PICR0L
-
-/* OCR1SAL */
-#define OCR1SA_0_REG OCR1SAL
-#define OCR1SA_1_REG OCR1SAL
-#define OCR1SA_2_REG OCR1SAL
-#define OCR1SA_3_REG OCR1SAL
-#define OCR1SA_4_REG OCR1SAL
-#define OCR1SA_5_REG OCR1SAL
-#define OCR1SA_6_REG OCR1SAL
-#define OCR1SA_7_REG OCR1SAL
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* PSOC0 */
-#define POEN0A_REG PSOC0
-#define POEN0B_REG PSOC0
-#define PSYNC00_REG PSOC0
-#define PSYNC01_REG PSOC0
-
-/* PSOC1 */
-#define POEN1A_REG PSOC1
-#define POEN1B_REG PSOC1
-#define PSYNC1_0_REG PSOC1
-#define PSYNC1_1_REG PSOC1
-
-/* OCR0A */
-/* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */
-
-/* ACSR */
-#define AC0O_REG ACSR
-#define AC1O_REG ACSR
-#define AC2O_REG ACSR
-#define AC0IF_REG ACSR
-#define AC1IF_REG ACSR
-#define AC2IF_REG ACSR
-#define ACCKDIV_REG ACSR
-
-/* OCR1RBL */
-#define OCR1RB_0_REG OCR1RBL
-#define OCR1RB_1_REG OCR1RBL
-#define OCR1RB_2_REG OCR1RBL
-#define OCR1RB_3_REG OCR1RBL
-#define OCR1RB_4_REG OCR1RBL
-#define OCR1RB_5_REG OCR1RBL
-#define OCR1RB_6_REG OCR1RBL
-#define OCR1RB_7_REG OCR1RBL
-
-/* OCR1SBH */
-#define OCR1SB_8_REG OCR1SBH
-#define OCR1SB_9_REG OCR1SBH
-#define OCR1SB_10_REG OCR1SBH
-#define OCR1SB_11_REG OCR1SBH
-
-/* OCR1RBH */
-#define OCR1RB_8_REG OCR1RBH
-#define OCR1RB_9_REG OCR1RBH
-#define OCR1RB_10_REG OCR1RBH
-#define OCR1RB_11_REG OCR1RBH
-#define OCR1RB_12_REG OCR1RBH
-#define OCR1RB_13_REG OCR1RBH
-#define OCR1RB_14_REG OCR1RBH
-#define OCR1RB_15_REG OCR1RBH
-
-/* OCR1SBL */
-#define OCR1SB_0_REG OCR1SBL
-#define OCR1SB_1_REG OCR1SBL
-#define OCR1SB_2_REG OCR1SBL
-#define OCR1SB_3_REG OCR1SBL
-#define OCR1SB_4_REG OCR1SBL
-#define OCR1SB_5_REG OCR1SBL
-#define OCR1SB_6_REG OCR1SBL
-#define OCR1SB_7_REG OCR1SBL
-
-/* OCR1SAH */
-#define OCR1SA_8_REG OCR1SAH
-#define OCR1SA_9_REG OCR1SAH
-#define OCR1SA_10_REG OCR1SAH
-#define OCR1SA_11_REG OCR1SAH
-
-/* UBRRH */
-#define UBRR8_REG UBRRH
-#define UBRR9_REG UBRRH
-#define UBRR10_REG UBRRH
-#define UBRR11_REG UBRRH
-
-/* DACL */
-#define DACL0_REG DACL
-#define DACL1_REG DACL
-#define DACL2_REG DACL
-#define DACL3_REG DACL
-#define DACL4_REG DACL
-#define DACL5_REG DACL
-#define DACL6_REG DACL
-#define DACL7_REG DACL
-
-/* UBRRL */
-#define UBRR0_REG UBRRL
-#define UBRR1_REG UBRRL
-#define UBRR2_REG UBRRL
-#define UBRR3_REG UBRRL
-#define UBRR4_REG UBRRL
-#define UBRR5_REG UBRRL
-#define UBRR6_REG UBRRL
-#define UBRR7_REG UBRRL
-
-/* DACH */
-#define DACH0_REG DACH
-#define DACH1_REG DACH
-#define DACH2_REG DACH
-#define DACH3_REG DACH
-#define DACH4_REG DACH
-#define DACH5_REG DACH
-#define DACH6_REG DACH
-#define DACH7_REG DACH
-
-/* OCR0RAH */
-#define OCR0RA_8_REG OCR0RAH
-#define OCR0RA_9_REG OCR0RAH
-#define OCR0RA_00_REG OCR0RAH
-#define OCR0RA_01_REG OCR0RAH
-
-/* PIM2 */
-#define PEOPE2_REG PIM2
-#define PEVE2A_REG PIM2
-#define PEVE2B_REG PIM2
-#define PSEIE2_REG PIM2
-
-/* PIM0 */
-#define PEOPE0_REG PIM0
-#define PEVE0A_REG PIM0
-#define PEVE0B_REG PIM0
-#define PSEIE0_REG PIM0
-
-/* PIM1 */
-#define PEOPE1_REG PIM1
-#define PEVE1A_REG PIM1
-#define PEVE1B_REG PIM1
-#define PSEIE1_REG PIM1
-
-/* PIFR2 */
-#define PEOP2_REG PIFR2
-#define PRN20_REG PIFR2
-#define PRN21_REG PIFR2
-#define PEV2A_REG PIFR2
-#define PEV2B_REG PIFR2
-#define PSEI2_REG PIFR2
-#define POAC2A_REG PIFR2
-#define POAC2B_REG PIFR2
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* PIFR0 */
-#define PEOP0_REG PIFR0
-#define PRN00_REG PIFR0
-#define PRN01_REG PIFR0
-#define PEV0A_REG PIFR0
-#define PEV0B_REG PIFR0
-#define PSEI0_REG PIFR0
-#define POAC0A_REG PIFR0
-#define POAC0B_REG PIFR0
-
-/* PIFR1 */
-#define PEOP1_REG PIFR1
-#define PRN10_REG PIFR1
-#define PRN11_REG PIFR1
-#define PEV1A_REG PIFR1
-#define PEV1B_REG PIFR1
-#define PSEI1_REG PIFR1
-#define POAC1A_REG PIFR1
-#define POAC1B_REG PIFR1
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* PSOC2 */
-#define POEN2A_REG PSOC2
-#define POEN2C_REG PSOC2
-#define POEN2B_REG PSOC2
-#define POEN2D_REG PSOC2
-#define PSYNC2_0_REG PSOC2
-#define PSYNC2_1_REG PSOC2
-#define POS22_REG PSOC2
-#define POS23_REG PSOC2
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* AMP0CSR */
-#define AMP0TS0_REG AMP0CSR
-#define AMP0TS1_REG AMP0CSR
-#define AMP0G0_REG AMP0CSR
-#define AMP0G1_REG AMP0CSR
-#define AMP0IS_REG AMP0CSR
-#define AMP0EN_REG AMP0CSR
-
-/* UDR */
-#define UDR0_REG UDR
-#define UDR1_REG UDR
-#define UDR2_REG UDR
-#define UDR3_REG UDR
-#define UDR4_REG UDR
-#define UDR5_REG UDR
-#define UDR6_REG UDR
-#define UDR7_REG UDR
-
-/* DACON */
-#define DAEN_REG DACON
-#define DALA_REG DACON
-#define DATS0_REG DACON
-#define DATS1_REG DACON
-#define DATS2_REG DACON
-#define DAATE_REG DACON
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* AC0CON */
-#define AC0M0_REG AC0CON
-#define AC0M1_REG AC0CON
-#define AC0M2_REG AC0CON
-#define AC0IS0_REG AC0CON
-#define AC0IS1_REG AC0CON
-#define AC0IE_REG AC0CON
-#define AC0EN_REG AC0CON
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ADTS3_REG ADCSRB
-#define ADASCR_REG ADCSRB
-#define ADHSM_REG ADCSRB
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* pins mapping */
-#define MISO_PORT PORTB
-#define MISO_BIT 0
-#define PSCOUT20_PORT PORTB
-#define PSCOUT20_BIT 0
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 1
-#define PSCOUT21_PORT PORTB
-#define PSCOUT21_BIT 1
-
-#define ADC5_PORT PORTB
-#define ADC5_BIT 2
-#define INT1_PORT PORTB
-#define INT1_BIT 2
-
-#define AMP0-_PORT PORTB
-#define AMP0-_BIT 3
-
-#define AMP0+_PORT PORTB
-#define AMP0+_BIT 4
-
-#define ADC6_PORT PORTB
-#define ADC6_BIT 5
-#define INT2_PORT PORTB
-#define INT2_BIT 5
-
-#define ADC7_PORT PORTB
-#define ADC7_BIT 6
-#define PSCOUT11_PORT PORTB
-#define PSCOUT11_BIT 6
-#define ICP1B_PORT PORTB
-#define ICP1B_BIT 6
-
-#define ADC4_PORT PORTB
-#define ADC4_BIT 7
-#define PSCOUT01_PORT PORTB
-#define PSCOUT01_BIT 7
-#define SCK_PORT PORTB
-#define SCK_BIT 7
-
-#define INT3_PORT PORTC
-#define INT3_BIT 0
-#define PSCOUT10_PORT PORTC
-#define PSCOUT10_BIT 0
-
-#define PSCIN1_PORT PORTC
-#define PSCIN1_BIT 1
-#define OC1B_PORT PORTC
-#define OC1B_BIT 1
-
-#define T0_PORT PORTC
-#define T0_BIT 2
-#define PSCOUT22_PORT PORTC
-#define PSCOUT22_BIT 2
-
-#define T1_PORT PORTC
-#define T1_BIT 3
-#define PSCOUT23_PORT PORTC
-#define PSCOUT23_BIT 3
-
-#define ADC8_PORT PORTC
-#define ADC8_BIT 4
-#define AMP1-_PORT PORTC
-#define AMP1-_BIT 4
-
-#define ADC9_PORT PORTC
-#define ADC9_BIT 5
-#define AMP1+_PORT PORTC
-#define AMP1+_BIT 5
-
-#define ADC10_PORT PORTC
-#define ADC10_BIT 6
-#define ACMP1_PORT PORTC
-#define ACMP1_BIT 6
-
-#define D2A_PORT PORTC
-#define D2A_BIT 7
-
-#define PSCOUT00_PORT PORTD
-#define PSCOUT00_BIT 0
-#define XCK_PORT PORTD
-#define XCK_BIT 0
-#define SSA_PORT PORTD
-#define SSA_BIT 0
-
-#define PSCIN0_PORT PORTD
-#define PSCIN0_BIT 1
-#define CLK0_PORT PORTD
-#define CLK0_BIT 1
-
-#define PSCIN2_PORT PORTD
-#define PSCIN2_BIT 2
-#define OC1A_PORT PORTD
-#define OC1A_BIT 2
-#define MISO_A_PORT PORTD
-#define MISO_A_BIT 2
-
-#define TXD_PORT PORTD
-#define TXD_BIT 3
-#define DALI_PORT PORTD
-#define DALI_BIT 3
-#define OC0A_PORT PORTD
-#define OC0A_BIT 3
-#define SS_PORT PORTD
-#define SS_BIT 3
-#define MOSI_A_PORT PORTD
-#define MOSI_A_BIT 3
-
-#define ADC1_PORT PORTD
-#define ADC1_BIT 4
-#define RXD_PORT PORTD
-#define RXD_BIT 4
-#define DALI_PORT PORTD
-#define DALI_BIT 4
-#define ICP1_PORT PORTD
-#define ICP1_BIT 4
-#define SCK_A_PORT PORTD
-#define SCK_A_BIT 4
-
-#define ADC2_PORT PORTD
-#define ADC2_BIT 5
-#define ACOMP2_PORT PORTD
-#define ACOMP2_BIT 5
-
-#define ADC3_PORT PORTD
-#define ADC3_BIT 6
-#define ACMPM_PORT PORTD
-#define ACMPM_BIT 6
-#define INT0_PORT PORTD
-#define INT0_BIT 6
-
-#define ACMP0_PORT PORTD
-#define ACMP0_BIT 7
-
-#define RESET_PORT PORTE
-#define RESET_BIT 0
-#define OCD_PORT PORTE
-#define OCD_BIT 0
-
-#define OC0B_PORT PORTE
-#define OC0B_BIT 1
-#define XTAL1_PORT PORTE
-#define XTAL1_BIT 1
-
-#define ADC0_PORT PORTE
-#define ADC0_BIT 2
-#define XTAL2_PORT PORTE
-#define XTAL2_BIT 2
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW_TOTAL_NUM 2
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* EUDR */
-#define EUDR0_REG EUDR
-#define EUDR1_REG EUDR
-#define EUDR2_REG EUDR
-#define EUDR3_REG EUDR
-#define EUDR4_REG EUDR
-#define EUDR5_REG EUDR
-#define EUDR6_REG EUDR
-#define EUDR7_REG EUDR
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* OCR2SBH */
-#define OCR2SB_8_REG OCR2SBH
-#define OCR2SB_9_REG OCR2SBH
-#define OCR2SB_10_REG OCR2SBH
-#define OCR2SB_11_REG OCR2SBH
-
-/* OCR2SBL */
-#define OCR2SB_0_REG OCR2SBL
-#define OCR2SB_1_REG OCR2SBL
-#define OCR2SB_2_REG OCR2SBL
-#define OCR2SB_3_REG OCR2SBL
-#define OCR2SB_4_REG OCR2SBL
-#define OCR2SB_5_REG OCR2SBL
-#define OCR2SB_6_REG OCR2SBL
-#define OCR2SB_7_REG OCR2SBL
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* OCR0B */
-/* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* UCSRA */
-#define MPCM_REG UCSRA
-#define U2X_REG UCSRA
-#define UPE_REG UCSRA
-#define DOR_REG UCSRA
-#define FE_REG UCSRA
-#define UDRE_REG UCSRA
-#define TXC_REG UCSRA
-#define RXC_REG UCSRA
-
-/* UCSRB */
-#define TXB8_REG UCSRB
-#define RXB8_REG UCSRB
-#define UCSZ2_REG UCSRB
-#define TXEN_REG UCSRB
-#define RXEN_REG UCSRB
-#define UDRIE_REG UCSRB
-#define TXCIE_REG UCSRB
-#define RXCIE_REG UCSRB
-
-/* UCSRC */
-#define UCPOL_REG UCSRC
-#define UCSZ0_REG UCSRC
-#define UCSZ1_REG UCSRC
-#define USBS_REG UCSRC
-#define UPM0_REG UCSRC
-#define UPM1_REG UCSRC
-#define UMSEL0_REG UCSRC
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* AC1CON */
-#define AC1M0_REG AC1CON
-#define AC1M1_REG AC1CON
-#define AC1M2_REG AC1CON
-#define AC1ICE_REG AC1CON
-#define AC1IS0_REG AC1CON
-#define AC1IS1_REG AC1CON
-#define AC1IE_REG AC1CON
-#define AC1EN_REG AC1CON
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSART0_REG PRR
-#define PRSPI_REG PRR
-#define PRTIM0_REG PRR
-#define PRTIM1_REG PRR
-#define PRPSC0_REG PRR
-#define PRPSC1_REG PRR
-#define PRPSC2_REG PRR
-
-/* PCNF0 */
-#define PCLKSEL0_REG PCNF0
-#define POP0_REG PCNF0
-#define PMODE00_REG PCNF0
-#define PMODE01_REG PCNF0
-#define PLOCK0_REG PCNF0
-#define PALOCK0_REG PCNF0
-#define PFIFTY0_REG PCNF0
-
-/* PCNF1 */
-#define PCLKSEL1_REG PCNF1
-#define POP1_REG PCNF1
-#define PMODE10_REG PCNF1
-#define PMODE11_REG PCNF1
-#define PLOCK1_REG PCNF1
-#define PALOCK1_REG PCNF1
-#define PFIFTY1_REG PCNF1
-
-/* PCNF2 */
-#define POME2_REG PCNF2
-#define PCLKSEL2_REG PCNF2
-#define POP2_REG PCNF2
-#define PMODE20_REG PCNF2
-#define PMODE21_REG PCNF2
-#define PLOCK2_REG PCNF2
-#define PALOCK2_REG PCNF2
-#define PFIFTY2_REG PCNF2
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* AMP1CSR */
-#define AMP1TS0_REG AMP1CSR
-#define AMP1TS1_REG AMP1CSR
-#define AMP1G0_REG AMP1CSR
-#define AMP1G1_REG AMP1CSR
-#define AMP1IS_REG AMP1CSR
-#define AMP1EN_REG AMP1CSR
-
-/* AC2CON */
-#define AC2M0_REG AC2CON
-#define AC2M1_REG AC2CON
-#define AC2M2_REG AC2CON
-#define AC2IS0_REG AC2CON
-#define AC2IS1_REG AC2CON
-#define AC2IE_REG AC2CON
-#define AC2EN_REG AC2CON
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-#define INT3_REG EIMSK
-
-/* PFRC0A */
-#define PRFM0A0_REG PFRC0A
-#define PRFM0A1_REG PFRC0A
-#define PRFM0A2_REG PFRC0A
-#define PRFM0A3_REG PFRC0A
-#define PFLTE0A_REG PFRC0A
-#define PELEV0A_REG PFRC0A
-#define PISEL0A_REG PFRC0A
-#define PCAE0A_REG PFRC0A
-
-/* PFRC0B */
-#define PRFM0B0_REG PFRC0B
-#define PRFM0B1_REG PFRC0B
-#define PRFM0B2_REG PFRC0B
-#define PRFM0B3_REG PFRC0B
-#define PFLTE0B_REG PFRC0B
-#define PELEV0B_REG PFRC0B
-#define PISEL0B_REG PFRC0B
-#define PCAE0B_REG PFRC0B
-
-/* PICR1H */
-#define PICR1_8_REG PICR1H
-#define PICR1_9_REG PICR1H
-#define PICR1_10_REG PICR1H
-#define PICR1_11_REG PICR1H
-#define PCST1_REG PICR1H
-
-/* PICR1L */
-#define PICR1_0_REG PICR1L
-#define PICR1_1_REG PICR1L
-#define PICR1_2_REG PICR1L
-#define PICR1_3_REG PICR1L
-#define PICR1_4_REG PICR1L
-#define PICR1_5_REG PICR1L
-#define PICR1_6_REG PICR1L
-#define PICR1_7_REG PICR1L
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-#define ISC20_REG EICRA
-#define ISC21_REG EICRA
-#define ISC30_REG EICRA
-#define ISC31_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define ADC8D_REG DIDR1
-#define ADC9D_REG DIDR1
-#define ADC10D_REG DIDR1
-#define AMP0ND_REG DIDR1
-#define AMP0PD_REG DIDR1
-#define ACMP0D_REG DIDR1
-
-/* OCR1RAH */
-#define OCR1RA_8_REG OCR1RAH
-#define OCR1RA_9_REG OCR1RAH
-#define OCR1RA_10_REG OCR1RAH
-#define OCR1RA_11_REG OCR1RAH
-
-/* OCR1RAL */
-#define OCR1RA_0_REG OCR1RAL
-#define OCR1RA_1_REG OCR1RAL
-#define OCR1RA_2_REG OCR1RAL
-#define OCR1RA_3_REG OCR1RAL
-#define OCR1RA_4_REG OCR1RAL
-#define OCR1RA_5_REG OCR1RAL
-#define OCR1RA_6_REG OCR1RAL
-#define OCR1RA_7_REG OCR1RAL
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* OCR0RBH */
-#define OCR0RB_8_REG OCR0RBH
-#define OCR0RB_9_REG OCR0RBH
-#define OCR0RB_00_REG OCR0RBH
-#define OCR0RB_01_REG OCR0RBH
-#define OCR0RB_02_REG OCR0RBH
-#define OCR0RB_03_REG OCR0RBH
-#define OCR0RB_04_REG OCR0RBH
-#define OCR0RB_05_REG OCR0RBH
-
-/* OCR0RBL */
-#define OCR0RB_0_REG OCR0RBL
-#define OCR0RB_1_REG OCR0RBL
-#define OCR0RB_2_REG OCR0RBL
-#define OCR0RB_3_REG OCR0RBL
-#define OCR0RB_4_REG OCR0RBL
-#define OCR0RB_5_REG OCR0RBL
-#define OCR0RB_6_REG OCR0RBL
-#define OCR0RB_7_REG OCR0RBL
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-
-/* OCR0RAL */
-#define OCR0RA_0_REG OCR0RAL
-#define OCR0RA_1_REG OCR0RAL
-#define OCR0RA_2_REG OCR0RAL
-#define OCR0RA_3_REG OCR0RAL
-#define OCR0RA_4_REG OCR0RAL
-#define OCR0RA_5_REG OCR0RAL
-#define OCR0RA_6_REG OCR0RAL
-#define OCR0RA_7_REG OCR0RAL
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR3 */
-#define GPIOR30_REG GPIOR3
-#define GPIOR31_REG GPIOR3
-#define GPIOR32_REG GPIOR3
-#define GPIOR33_REG GPIOR3
-#define GPIOR34_REG GPIOR3
-#define GPIOR35_REG GPIOR3
-#define GPIOR36_REG GPIOR3
-#define GPIOR37_REG GPIOR3
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* PFRC2B */
-#define PRFM2B0_REG PFRC2B
-#define PRFM2B1_REG PFRC2B
-#define PRFM2B2_REG PFRC2B
-#define PRFM2B3_REG PFRC2B
-#define PFLTE2B_REG PFRC2B
-#define PELEV2B_REG PFRC2B
-#define PISEL2B_REG PFRC2B
-#define PCAE2B_REG PFRC2B
-
-/* PFRC2A */
-#define PRFM2A0_REG PFRC2A
-#define PRFM2A1_REG PFRC2A
-#define PRFM2A2_REG PFRC2A
-#define PRFM2A3_REG PFRC2A
-#define PFLTE2A_REG PFRC2A
-#define PELEV2A_REG PFRC2A
-#define PISEL2A_REG PFRC2A
-#define PCAE2A_REG PFRC2A
-
-/* OCR2SAL */
-#define OCR2SA_0_REG OCR2SAL
-#define OCR2SA_1_REG OCR2SAL
-#define OCR2SA_2_REG OCR2SAL
-#define OCR2SA_3_REG OCR2SAL
-#define OCR2SA_4_REG OCR2SAL
-#define OCR2SA_5_REG OCR2SAL
-#define OCR2SA_6_REG OCR2SAL
-#define OCR2SA_7_REG OCR2SAL
-
-/* EUCSRA */
-#define URxS0_REG EUCSRA
-#define URxS1_REG EUCSRA
-#define URxS2_REG EUCSRA
-#define URxS3_REG EUCSRA
-#define UTxS0_REG EUCSRA
-#define UTxS1_REG EUCSRA
-#define UTxS2_REG EUCSRA
-#define UTxS3_REG EUCSRA
-
-/* EUCSRB */
-#define BODR_REG EUCSRB
-#define EMCH_REG EUCSRB
-#define EUSBS_REG EUCSRB
-#define EUSART_REG EUCSRB
-
-/* EUCSRC */
-#define STP0_REG EUCSRC
-#define STP1_REG EUCSRC
-#define F1617_REG EUCSRC
-#define FEM_REG EUCSRC
-
-/* PCTL0 */
-#define PRUN0_REG PCTL0
-#define PCCYC0_REG PCTL0
-#define PARUN0_REG PCTL0
-#define PAOC0A_REG PCTL0
-#define PAOC0B_REG PCTL0
-#define PBFM0_REG PCTL0
-#define PPRE00_REG PCTL0
-#define PPRE01_REG PCTL0
-
-/* PCTL1 */
-#define PRUN1_REG PCTL1
-#define PCCYC1_REG PCTL1
-#define PARUN1_REG PCTL1
-#define PAOC1A_REG PCTL1
-#define PAOC1B_REG PCTL1
-#define PBFM1_REG PCTL1
-#define PPRE10_REG PCTL1
-#define PPRE11_REG PCTL1
-
-/* PCTL2 */
-#define PRUN2_REG PCTL2
-#define PCCYC2_REG PCTL2
-#define PARUN2_REG PCTL2
-#define PAOC2A_REG PCTL2
-#define PAOC2B_REG PCTL2
-#define PBFM2_REG PCTL2
-#define PPRE20_REG PCTL2
-#define PPRE21_REG PCTL2
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* GTCCR */
-#define PSR10_REG GTCCR
-#define ICPSEL1_REG GTCCR
-#define TSM_REG GTCCR
-#define PSRSYNC_REG GTCCR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* POM2 */
-#define POMV2A0_REG POM2
-#define POMV2A1_REG POM2
-#define POMV2A2_REG POM2
-#define POMV2A3_REG POM2
-#define POMV2B0_REG POM2
-#define POMV2B1_REG POM2
-#define POMV2B2_REG POM2
-#define POMV2B3_REG POM2
-
-/* OCR2RBL */
-#define OCR2RB_0_REG OCR2RBL
-#define OCR2RB_1_REG OCR2RBL
-#define OCR2RB_2_REG OCR2RBL
-#define OCR2RB_3_REG OCR2RBL
-#define OCR2RB_4_REG OCR2RBL
-#define OCR2RB_5_REG OCR2RBL
-#define OCR2RB_6_REG OCR2RBL
-#define OCR2RB_7_REG OCR2RBL
-
-/* PICR2H */
-#define PICR2_8_REG PICR2H
-#define PICR2_9_REG PICR2H
-#define PICR2_10_REG PICR2H
-#define PICR2_11_REG PICR2H
-#define PCST2_REG PICR2H
-
-/* OCR2RBH */
-#define OCR2RB_8_REG OCR2RBH
-#define OCR2RB_9_REG OCR2RBH
-#define OCR2RB_10_REG OCR2RBH
-#define OCR2RB_11_REG OCR2RBH
-#define OCR2RB_12_REG OCR2RBH
-#define OCR2RB_13_REG OCR2RBH
-#define OCR2RB_14_REG OCR2RBH
-#define OCR2RB_15_REG OCR2RBH
-
-/* PICR2L */
-#define PICR2_0_REG PICR2L
-#define PICR2_1_REG PICR2L
-#define PICR2_2_REG PICR2L
-#define PICR2_3_REG PICR2L
-#define PICR2_4_REG PICR2L
-#define PICR2_5_REG PICR2L
-#define PICR2_6_REG PICR2L
-#define PICR2_7_REG PICR2L
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* PLLCSR */
-#define PLOCK_REG PLLCSR
-#define PLLE_REG PLLCSR
-#define PLLF_REG PLLCSR
-
-/* OCR2RAH */
-#define OCR2RA_8_REG OCR2RAH
-#define OCR2RA_9_REG OCR2RAH
-#define OCR2RA_10_REG OCR2RAH
-#define OCR2RA_11_REG OCR2RAH
-
-/* OCR2RAL */
-#define OCR2RA_0_REG OCR2RAL
-#define OCR2RA_1_REG OCR2RAL
-#define OCR2RA_2_REG OCR2RAL
-#define OCR2RA_3_REG OCR2RAL
-#define OCR2RA_4_REG OCR2RAL
-#define OCR2RA_5_REG OCR2RAL
-#define OCR2RA_6_REG OCR2RAL
-#define OCR2RA_7_REG OCR2RAL
-
-/* OCR0SAL */
-#define OCR0SA_0_REG OCR0SAL
-#define OCR0SA_1_REG OCR0SAL
-#define OCR0SA_2_REG OCR0SAL
-#define OCR0SA_3_REG OCR0SAL
-#define OCR0SA_4_REG OCR0SAL
-#define OCR0SA_5_REG OCR0SAL
-#define OCR0SA_6_REG OCR0SAL
-#define OCR0SA_7_REG OCR0SAL
-
-/* OCR0SAH */
-#define OCR0SA_8_REG OCR0SAH
-#define OCR0SA_9_REG OCR0SAH
-#define OCR0SA_00_REG OCR0SAH
-#define OCR0SA_01_REG OCR0SAH
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-#define EEAR10_REG EEARH
-#define EEAR11_REG EEARH
-
-/* EEARL */
-#define EEARL0_REG EEARL
-#define EEARL1_REG EEARL
-#define EEARL2_REG EEARL
-#define EEARL3_REG EEARL
-#define EEARL4_REG EEARL
-#define EEARL5_REG EEARL
-#define EEARL6_REG EEARL
-#define EEARL7_REG EEARL
-
-/* MCUCR */
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-#define SPIPS_REG MCUCR
-
-/* PICR0H */
-#define PICR0_8_REG PICR0H
-#define PICR0_9_REG PICR0H
-#define PICR0_10_REG PICR0H
-#define PICR0_11_REG PICR0H
-#define PCST0_REG PICR0H
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-#define INTF2_REG EIFR
-#define INTF3_REG EIFR
-
-/* MUBRRL */
-#define MUBRR0_REG MUBRRL
-#define MUBRR1_REG MUBRRL
-#define MUBRR2_REG MUBRRL
-#define MUBRR3_REG MUBRRL
-#define MUBRR4_REG MUBRRL
-#define MUBRR5_REG MUBRRL
-#define MUBRR6_REG MUBRRL
-#define MUBRR7_REG MUBRRL
-
-/* MUBRRH */
-#define MUBRR8_REG MUBRRH
-#define MUBRR9_REG MUBRRH
-#define MUBRR10_REG MUBRRH
-#define MUBRR11_REG MUBRRH
-#define MUBRR12_REG MUBRRH
-#define MUBRR13_REG MUBRRH
-#define MUBRR14_REG MUBRRH
-#define MUBRR15_REG MUBRRH
-
-/* OCR2SAH */
-#define OCR2SA_8_REG OCR2SAH
-#define OCR2SA_9_REG OCR2SAH
-#define OCR2SA_10_REG OCR2SAH
-#define OCR2SA_11_REG OCR2SAH
-
-/* OCR0SBL */
-#define OCR0SB_0_REG OCR0SBL
-#define OCR0SB_1_REG OCR0SBL
-#define OCR0SB_2_REG OCR0SBL
-#define OCR0SB_3_REG OCR0SBL
-#define OCR0SB_4_REG OCR0SBL
-#define OCR0SB_5_REG OCR0SBL
-#define OCR0SB_6_REG OCR0SBL
-#define OCR0SB_7_REG OCR0SBL
-
-/* OCR0SBH */
-#define OCR0SB_8_REG OCR0SBH
-#define OCR0SB_9_REG OCR0SBH
-#define OCR0SB_00_REG OCR0SBH
-#define OCR0SB_01_REG OCR0SBH
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* PFRC1B */
-#define PRFM1B0_REG PFRC1B
-#define PRFM1B1_REG PFRC1B
-#define PRFM1B2_REG PFRC1B
-#define PRFM1B3_REG PFRC1B
-#define PFLTE1B_REG PFRC1B
-#define PELEV1B_REG PFRC1B
-#define PISEL1B_REG PFRC1B
-#define PCAE1B_REG PFRC1B
-
-/* PFRC1A */
-#define PRFM1A0_REG PFRC1A
-#define PRFM1A1_REG PFRC1A
-#define PRFM1A2_REG PFRC1A
-#define PRFM1A3_REG PFRC1A
-#define PFLTE1A_REG PFRC1A
-#define PELEV1A_REG PFRC1A
-#define PISEL1A_REG PFRC1A
-#define PCAE1A_REG PFRC1A
-
-/* PICR0L */
-#define PICR0_0_REG PICR0L
-#define PICR0_1_REG PICR0L
-#define PICR0_2_REG PICR0L
-#define PICR0_3_REG PICR0L
-#define PICR0_4_REG PICR0L
-#define PICR0_5_REG PICR0L
-#define PICR0_6_REG PICR0L
-#define PICR0_7_REG PICR0L
-
-/* OCR1SAL */
-#define OCR1SA_0_REG OCR1SAL
-#define OCR1SA_1_REG OCR1SAL
-#define OCR1SA_2_REG OCR1SAL
-#define OCR1SA_3_REG OCR1SAL
-#define OCR1SA_4_REG OCR1SAL
-#define OCR1SA_5_REG OCR1SAL
-#define OCR1SA_6_REG OCR1SAL
-#define OCR1SA_7_REG OCR1SAL
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* PSOC0 */
-#define POEN0A_REG PSOC0
-#define POEN0B_REG PSOC0
-#define PSYNC00_REG PSOC0
-#define PSYNC01_REG PSOC0
-
-/* PSOC1 */
-#define POEN1A_REG PSOC1
-#define POEN1B_REG PSOC1
-#define PSYNC1_0_REG PSOC1
-#define PSYNC1_1_REG PSOC1
-
-/* OCR0A */
-/* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */
-
-/* ACSR */
-#define AC0O_REG ACSR
-#define AC1O_REG ACSR
-#define AC2O_REG ACSR
-#define AC0IF_REG ACSR
-#define AC1IF_REG ACSR
-#define AC2IF_REG ACSR
-#define ACCKDIV_REG ACSR
-
-/* OCR1RBL */
-#define OCR1RB_0_REG OCR1RBL
-#define OCR1RB_1_REG OCR1RBL
-#define OCR1RB_2_REG OCR1RBL
-#define OCR1RB_3_REG OCR1RBL
-#define OCR1RB_4_REG OCR1RBL
-#define OCR1RB_5_REG OCR1RBL
-#define OCR1RB_6_REG OCR1RBL
-#define OCR1RB_7_REG OCR1RBL
-
-/* OCR1SBH */
-#define OCR1SB_8_REG OCR1SBH
-#define OCR1SB_9_REG OCR1SBH
-#define OCR1SB_10_REG OCR1SBH
-#define OCR1SB_11_REG OCR1SBH
-
-/* OCR1RBH */
-#define OCR1RB_8_REG OCR1RBH
-#define OCR1RB_9_REG OCR1RBH
-#define OCR1RB_10_REG OCR1RBH
-#define OCR1RB_11_REG OCR1RBH
-#define OCR1RB_12_REG OCR1RBH
-#define OCR1RB_13_REG OCR1RBH
-#define OCR1RB_14_REG OCR1RBH
-#define OCR1RB_15_REG OCR1RBH
-
-/* OCR1SBL */
-#define OCR1SB_0_REG OCR1SBL
-#define OCR1SB_1_REG OCR1SBL
-#define OCR1SB_2_REG OCR1SBL
-#define OCR1SB_3_REG OCR1SBL
-#define OCR1SB_4_REG OCR1SBL
-#define OCR1SB_5_REG OCR1SBL
-#define OCR1SB_6_REG OCR1SBL
-#define OCR1SB_7_REG OCR1SBL
-
-/* OCR1SAH */
-#define OCR1SA_8_REG OCR1SAH
-#define OCR1SA_9_REG OCR1SAH
-#define OCR1SA_10_REG OCR1SAH
-#define OCR1SA_11_REG OCR1SAH
-
-/* UBRRH */
-#define UBRR8_REG UBRRH
-#define UBRR9_REG UBRRH
-#define UBRR10_REG UBRRH
-#define UBRR11_REG UBRRH
-
-/* DACL */
-#define DACL0_REG DACL
-#define DACL1_REG DACL
-#define DACL2_REG DACL
-#define DACL3_REG DACL
-#define DACL4_REG DACL
-#define DACL5_REG DACL
-#define DACL6_REG DACL
-#define DACL7_REG DACL
-
-/* UBRRL */
-#define UBRR0_REG UBRRL
-#define UBRR1_REG UBRRL
-#define UBRR2_REG UBRRL
-#define UBRR3_REG UBRRL
-#define UBRR4_REG UBRRL
-#define UBRR5_REG UBRRL
-#define UBRR6_REG UBRRL
-#define UBRR7_REG UBRRL
-
-/* DACH */
-#define DACH0_REG DACH
-#define DACH1_REG DACH
-#define DACH2_REG DACH
-#define DACH3_REG DACH
-#define DACH4_REG DACH
-#define DACH5_REG DACH
-#define DACH6_REG DACH
-#define DACH7_REG DACH
-
-/* OCR0RAH */
-#define OCR0RA_8_REG OCR0RAH
-#define OCR0RA_9_REG OCR0RAH
-#define OCR0RA_00_REG OCR0RAH
-#define OCR0RA_01_REG OCR0RAH
-
-/* PIM2 */
-#define PEOPE2_REG PIM2
-#define PEVE2A_REG PIM2
-#define PEVE2B_REG PIM2
-#define PSEIE2_REG PIM2
-
-/* PIM0 */
-#define PEOPE0_REG PIM0
-#define PEVE0A_REG PIM0
-#define PEVE0B_REG PIM0
-#define PSEIE0_REG PIM0
-
-/* PIM1 */
-#define PEOPE1_REG PIM1
-#define PEVE1A_REG PIM1
-#define PEVE1B_REG PIM1
-#define PSEIE1_REG PIM1
-
-/* PIFR2 */
-#define PEOP2_REG PIFR2
-#define PRN20_REG PIFR2
-#define PRN21_REG PIFR2
-#define PEV2A_REG PIFR2
-#define PEV2B_REG PIFR2
-#define PSEI2_REG PIFR2
-#define POAC2A_REG PIFR2
-#define POAC2B_REG PIFR2
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* PIFR0 */
-#define PEOP0_REG PIFR0
-#define PRN00_REG PIFR0
-#define PRN01_REG PIFR0
-#define PEV0A_REG PIFR0
-#define PEV0B_REG PIFR0
-#define PSEI0_REG PIFR0
-#define POAC0A_REG PIFR0
-#define POAC0B_REG PIFR0
-
-/* PIFR1 */
-#define PEOP1_REG PIFR1
-#define PRN10_REG PIFR1
-#define PRN11_REG PIFR1
-#define PEV1A_REG PIFR1
-#define PEV1B_REG PIFR1
-#define PSEI1_REG PIFR1
-#define POAC1A_REG PIFR1
-#define POAC1B_REG PIFR1
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* PSOC2 */
-#define POEN2A_REG PSOC2
-#define POEN2C_REG PSOC2
-#define POEN2B_REG PSOC2
-#define POEN2D_REG PSOC2
-#define PSYNC2_0_REG PSOC2
-#define PSYNC2_1_REG PSOC2
-#define POS22_REG PSOC2
-#define POS23_REG PSOC2
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* AMP0CSR */
-#define AMP0TS0_REG AMP0CSR
-#define AMP0TS1_REG AMP0CSR
-#define AMP0G0_REG AMP0CSR
-#define AMP0G1_REG AMP0CSR
-#define AMP0IS_REG AMP0CSR
-#define AMP0EN_REG AMP0CSR
-
-/* UDR */
-#define UDR0_REG UDR
-#define UDR1_REG UDR
-#define UDR2_REG UDR
-#define UDR3_REG UDR
-#define UDR4_REG UDR
-#define UDR5_REG UDR
-#define UDR6_REG UDR
-#define UDR7_REG UDR
-
-/* DACON */
-#define DAEN_REG DACON
-#define DALA_REG DACON
-#define DATS0_REG DACON
-#define DATS1_REG DACON
-#define DATS2_REG DACON
-#define DAATE_REG DACON
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* AC0CON */
-#define AC0M0_REG AC0CON
-#define AC0M1_REG AC0CON
-#define AC0M2_REG AC0CON
-#define AC0IS0_REG AC0CON
-#define AC0IS1_REG AC0CON
-#define AC0IE_REG AC0CON
-#define AC0EN_REG AC0CON
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ADTS3_REG ADCSRB
-#define ADASCR_REG ADCSRB
-#define ADHSM_REG ADCSRB
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* pins mapping */
-#define MISO_PORT PORTB
-#define MISO_BIT 0
-#define PSCOUT20_PORT PORTB
-#define PSCOUT20_BIT 0
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 1
-#define PSCOUT21_PORT PORTB
-#define PSCOUT21_BIT 1
-
-#define ADC5_PORT PORTB
-#define ADC5_BIT 2
-#define INT1_PORT PORTB
-#define INT1_BIT 2
-
-#define AMP0-_PORT PORTB
-#define AMP0-_BIT 3
-
-#define AMP0+_PORT PORTB
-#define AMP0+_BIT 4
-
-#define ADC6_PORT PORTB
-#define ADC6_BIT 5
-#define INT2_PORT PORTB
-#define INT2_BIT 5
-
-#define ADC7_PORT PORTB
-#define ADC7_BIT 6
-#define PSCOUT11_PORT PORTB
-#define PSCOUT11_BIT 6
-#define ICP1B_PORT PORTB
-#define ICP1B_BIT 6
-
-#define ADC4_PORT PORTB
-#define ADC4_BIT 7
-#define PSCOUT01_PORT PORTB
-#define PSCOUT01_BIT 7
-#define SCK_PORT PORTB
-#define SCK_BIT 7
-
-#define INT3_PORT PORTC
-#define INT3_BIT 0
-#define PSCOUT10_PORT PORTC
-#define PSCOUT10_BIT 0
-
-#define PSCIN1_PORT PORTC
-#define PSCIN1_BIT 1
-#define OC1B_PORT PORTC
-#define OC1B_BIT 1
-
-#define T0_PORT PORTC
-#define T0_BIT 2
-#define PSCOUT22_PORT PORTC
-#define PSCOUT22_BIT 2
-
-#define T1_PORT PORTC
-#define T1_BIT 3
-#define PSCOUT23_PORT PORTC
-#define PSCOUT23_BIT 3
-
-#define ADC8_PORT PORTC
-#define ADC8_BIT 4
-#define AMP1-_PORT PORTC
-#define AMP1-_BIT 4
-
-#define ADC9_PORT PORTC
-#define ADC9_BIT 5
-#define AMP1+_PORT PORTC
-#define AMP1+_BIT 5
-
-#define ADC10_PORT PORTC
-#define ADC10_BIT 6
-#define ACMP1_PORT PORTC
-#define ACMP1_BIT 6
-
-#define D2A_PORT PORTC
-#define D2A_BIT 7
-
-#define PSCOUT00_PORT PORTD
-#define PSCOUT00_BIT 0
-#define XCK_PORT PORTD
-#define XCK_BIT 0
-#define SSA_PORT PORTD
-#define SSA_BIT 0
-
-#define PSCIN0_PORT PORTD
-#define PSCIN0_BIT 1
-#define CLK0_PORT PORTD
-#define CLK0_BIT 1
-
-#define PSCIN2_PORT PORTD
-#define PSCIN2_BIT 2
-#define OC1A_PORT PORTD
-#define OC1A_BIT 2
-#define MISO_A_PORT PORTD
-#define MISO_A_BIT 2
-
-#define TXD_PORT PORTD
-#define TXD_BIT 3
-#define DALI_PORT PORTD
-#define DALI_BIT 3
-#define OC0A_PORT PORTD
-#define OC0A_BIT 3
-#define SS_PORT PORTD
-#define SS_BIT 3
-#define MOSI_A_PORT PORTD
-#define MOSI_A_BIT 3
-
-#define ADC1_PORT PORTD
-#define ADC1_BIT 4
-#define RXD_PORT PORTD
-#define RXD_BIT 4
-#define DALI_PORT PORTD
-#define DALI_BIT 4
-#define ICP1_PORT PORTD
-#define ICP1_BIT 4
-#define SCK_A_PORT PORTD
-#define SCK_A_BIT 4
-
-#define ADC2_PORT PORTD
-#define ADC2_BIT 5
-#define ACOMP2_PORT PORTD
-#define ACOMP2_BIT 5
-
-#define ADC3_PORT PORTD
-#define ADC3_BIT 6
-#define ACMPM_PORT PORTD
-#define ACMPM_BIT 6
-#define INT0_PORT PORTD
-#define INT0_BIT 6
-
-#define ACMP0_PORT PORTD
-#define ACMP0_BIT 7
-
-#define RESET_PORT PORTE
-#define RESET_BIT 0
-#define OCD_PORT PORTE
-#define OCD_BIT 0
-
-#define OC0B_PORT PORTE
-#define OC0B_BIT 1
-#define XTAL1_PORT PORTE
-#define XTAL1_BIT 1
-
-#define ADC0_PORT PORTE
-#define ADC0_BIT 2
-#define XTAL2_PORT PORTE
-#define XTAL2_BIT 2
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW_TOTAL_NUM 1
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0
-
-/* Pwm nums */
-#define PWM_TOTAL_NUM 0
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 0
-
-
-/* TIMSK */
-#define TOIE0_REG TIMSK
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-
-/* GIMSK */
-#define INT0_REG GIMSK
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-
-/* EEAR */
-#define EEAR0_REG EEAR
-#define EEAR1_REG EEAR
-#define EEAR2_REG EEAR
-#define EEAR3_REG EEAR
-#define EEAR4_REG EEAR
-#define EEAR5_REG EEAR
-#define EEAR6_REG EEAR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* TCCR0 */
-#define CS00_REG TCCR0
-#define CS01_REG TCCR0
-#define CS02_REG TCCR0
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define SM_REG MCUCR
-#define SE_REG MCUCR
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* TCNT0 */
-#define TCNT00_REG TCNT0
-#define TCNT01_REG TCNT0
-#define TCNT02_REG TCNT0
-#define TCNT03_REG TCNT0
-#define TCNT04_REG TCNT0
-#define TCNT05_REG TCNT0
-#define TCNT06_REG TCNT0
-#define TCNT07_REG TCNT0
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACD_REG ACSR
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* TIFR */
-#define TOV0_REG TIFR
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-
-/* pins mapping */
-#define AIN0_PORT PORTB
-#define AIN0_BIT 0
-
-#define AIN1_PORT PORTB
-#define AIN1_BIT 1
-
-
-
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 5
-
-#define MISO_PORT PORTB
-#define MISO_BIT 6
-
-#define SCK_PORT PORTB
-#define SCK_BIT 7
-
-
-
-#define INT0_PORT PORTD
-#define INT0_BIT 2
-
-
-#define T0_PORT PORTD
-#define T0_BIT 4
-
-
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW_TOTAL_NUM 2
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE1_NUM 0
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 1
-
-/* Pwm nums */
-#define PWM1_NUM 0
-#define PWM_TOTAL_NUM 1
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDTOE_REG WDTCR
-
-/* GIMSK */
-#define INT0_REG GIMSK
-#define INT1_REG GIMSK
-
-/* TCCR0 */
-#define CS00_REG TCCR0
-#define CS01_REG TCCR0
-#define CS02_REG TCCR0
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* USR */
-#define OR_REG USR
-#define FE_REG USR
-#define UDRE_REG USR
-#define TXC_REG USR
-#define RXC_REG USR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-
-/* TCCR1A */
-#define PWM10_REG TCCR1A
-#define PWM11_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define CTC1_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* GIFR */
-#define INTF0_REG GIFR
-#define INTF1_REG GIFR
-
-/* TIMSK */
-#define TOIE0_REG TIMSK
-#define TICIE1_REG TIMSK
-#define OCIE1A_REG TIMSK
-#define TOIE1_REG TIMSK
-
-/* UCR */
-#define TXB8_REG UCR
-#define RXB8_REG UCR
-#define CHR9_REG UCR
-#define TXEN_REG UCR
-#define RXEN_REG UCR
-#define UDRIE_REG UCR
-#define TXCIE_REG UCR
-#define RXCIE_REG UCR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACD_REG ACSR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-
-/* EEAR */
-#define EEAR0_REG EEAR
-#define EEAR1_REG EEAR
-#define EEAR2_REG EEAR
-#define EEAR3_REG EEAR
-#define EEAR4_REG EEAR
-#define EEAR5_REG EEAR
-#define EEAR6_REG EEAR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* TCNT0 */
-#define TCNT00_REG TCNT0
-#define TCNT01_REG TCNT0
-#define TCNT02_REG TCNT0
-#define TCNT03_REG TCNT0
-#define TCNT04_REG TCNT0
-#define TCNT05_REG TCNT0
-#define TCNT06_REG TCNT0
-#define TCNT07_REG TCNT0
-
-/* UBRR */
-#define UBRR0_REG UBRR
-#define UBRR1_REG UBRR
-#define UBRR2_REG UBRR
-#define UBRR3_REG UBRR
-#define UBRR4_REG UBRR
-#define UBRR5_REG UBRR
-#define UBRR6_REG UBRR
-#define UBRR7_REG UBRR
-
-/* TIFR */
-#define TOV0_REG TIFR
-#define ICF1_REG TIFR
-#define OCF1A_REG TIFR
-#define TOV1_REG TIFR
-
-/* UDR */
-#define UDR0_REG UDR
-#define UDR1_REG UDR
-#define UDR2_REG UDR
-#define UDR3_REG UDR
-#define UDR4_REG UDR
-#define UDR5_REG UDR
-#define UDR6_REG UDR
-#define UDR7_REG UDR
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define ISC10_REG MCUCR
-#define ISC11_REG MCUCR
-#define SM_REG MCUCR
-#define SE_REG MCUCR
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* pins mapping */
-#define AIN0_PORT PORTB
-#define AIN0_BIT 0
-
-#define AIN1_PORT PORTB
-#define AIN1_BIT 1
-
-
-#define OC1_PORT PORTB
-#define OC1_BIT 3
-
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 5
-
-#define MISO_PORT PORTB
-#define MISO_BIT 6
-
-#define SCK_PORT PORTB
-#define SCK_BIT 7
-
-#define RXD_PORT PORTD
-#define RXD_BIT 0
-
-#define TXD_PORT PORTD
-#define TXD_BIT 1
-
-#define INT0_PORT PORTD
-#define INT0_BIT 2
-
-#define INT1_PORT PORTD
-#define INT1_BIT 3
-
-#define T0_PORT PORTD
-#define T0_BIT 4
-
-#define T1_PORT PORTD
-#define T1_BIT 5
-
-#define ICP_PORT PORTD
-#define ICP_BIT 6
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW_TOTAL_NUM 1
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0
-
-/* Pwm nums */
-#define PWM_TOTAL_NUM 0
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 0
-
-
-/* GIFR */
-#define INTF0_REG GIFR
-
-/* TIMSK */
-#define TOIE0_REG TIMSK
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDTOE_REG WDTCR
-
-/* GIMSK */
-#define INT0_REG GIMSK
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-
-/* EEAR */
-#define EEAR0_REG EEAR
-#define EEAR1_REG EEAR
-#define EEAR2_REG EEAR
-#define EEAR3_REG EEAR
-#define EEAR4_REG EEAR
-#define EEAR5_REG EEAR
-#define EEAR6_REG EEAR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-
-/* TCCR0 */
-#define CS00_REG TCCR0
-#define CS01_REG TCCR0
-#define CS02_REG TCCR0
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-
-/* TCNT0 */
-#define TCNT00_REG TCNT0
-#define TCNT01_REG TCNT0
-#define TCNT02_REG TCNT0
-#define TCNT03_REG TCNT0
-#define TCNT04_REG TCNT0
-#define TCNT05_REG TCNT0
-#define TCNT06_REG TCNT0
-#define TCNT07_REG TCNT0
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define SM_REG MCUCR
-#define SE_REG MCUCR
-
-/* TIFR */
-#define TOV0_REG TIFR
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-
-/* pins mapping */
-#define MOSI_PORT PORTB
-#define MOSI_BIT 0
-
-#define MISO_PORT PORTB
-#define MISO_BIT 1
-#define INT0_PORT PORTB
-#define INT0_BIT 1
-
-#define SCK_PORT PORTB
-#define SCK_BIT 2
-#define T0_PORT PORTB
-#define T0_BIT 2
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW_TOTAL_NUM 1
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0
-
-/* Pwm nums */
-#define PWM_TOTAL_NUM 0
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 0
-
-
-/* GIFR */
-#define INTF0_REG GIFR
-
-/* TIMSK */
-#define TOIE0_REG TIMSK
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDTOE_REG WDTCR
-
-/* GIMSK */
-#define INT0_REG GIMSK
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-
-/* EEAR */
-#define EEAR0_REG EEAR
-#define EEAR1_REG EEAR
-#define EEAR2_REG EEAR
-#define EEAR3_REG EEAR
-#define EEAR4_REG EEAR
-#define EEAR5_REG EEAR
-#define EEAR6_REG EEAR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-
-/* TCCR0 */
-#define CS00_REG TCCR0
-#define CS01_REG TCCR0
-#define CS02_REG TCCR0
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-
-/* TCNT0 */
-#define TCNT00_REG TCNT0
-#define TCNT01_REG TCNT0
-#define TCNT02_REG TCNT0
-#define TCNT03_REG TCNT0
-#define TCNT04_REG TCNT0
-#define TCNT05_REG TCNT0
-#define TCNT06_REG TCNT0
-#define TCNT07_REG TCNT0
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define SM_REG MCUCR
-#define SE_REG MCUCR
-
-/* TIFR */
-#define TOV0_REG TIFR
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-
-/* pins mapping */
-#define MOSI_PORT PORTB
-#define MOSI_BIT 0
-
-#define MISO_PORT PORTB
-#define MISO_BIT 1
-#define INT0_PORT PORTB
-#define INT0_BIT 1
-
-#define SCK_PORT PORTB
-#define SCK_BIT 2
-#define T0_PORT PORTB
-#define T0_BIT 2
-
-#define CLOCK_PORT PORTB
-#define CLOCK_BIT 3
-
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW_TOTAL_NUM 2
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE1A_NUM 0
-#define SIG_OUTPUT_COMPARE1B_NUM 1
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 2
-
-/* Pwm nums */
-#define PWM1A_NUM 0
-#define PWM1B_NUM 1
-#define PWM_TOTAL_NUM 2
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDTOE_REG WDTCR
-
-/* GIMSK */
-#define INT0_REG GIMSK
-#define INT1_REG GIMSK
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* TCCR0 */
-#define CS00_REG TCCR0
-#define CS01_REG TCCR0
-#define CS02_REG TCCR0
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* USR */
-#define OR_REG USR
-#define FE_REG USR
-#define UDRE_REG USR
-#define TXC_REG USR
-#define RXC_REG USR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* TCCR1A */
-#define PWM10_REG TCCR1A
-#define PWM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define CTC1_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* GIFR */
-#define INTF0_REG GIFR
-#define INTF1_REG GIFR
-
-/* TIMSK */
-#define TICIE1_REG TIMSK
-#define OCIE1B_REG TIMSK
-#define OCIE1A_REG TIMSK
-#define TOIE1_REG TIMSK
-#define TOIE0_REG TIMSK
-
-/* UCR */
-#define TXB8_REG UCR
-#define RXB8_REG UCR
-#define CHR9_REG UCR
-#define TXEN_REG UCR
-#define RXEN_REG UCR
-#define UDRIE_REG UCR
-#define TXCIE_REG UCR
-#define RXCIE_REG UCR
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACD_REG ACSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* EEAR */
-#define EEAR0_REG EEAR
-#define EEAR1_REG EEAR
-#define EEAR2_REG EEAR
-#define EEAR3_REG EEAR
-#define EEAR4_REG EEAR
-#define EEAR5_REG EEAR
-#define EEAR6_REG EEAR
-#define EEAR7_REG EEAR
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* TCNT0 */
-#define TCNT00_REG TCNT0
-#define TCNT01_REG TCNT0
-#define TCNT02_REG TCNT0
-#define TCNT03_REG TCNT0
-#define TCNT04_REG TCNT0
-#define TCNT05_REG TCNT0
-#define TCNT06_REG TCNT0
-#define TCNT07_REG TCNT0
-
-/* UBRR */
-#define UBRR0_REG UBRR
-#define UBRR1_REG UBRR
-#define UBRR2_REG UBRR
-#define UBRR3_REG UBRR
-#define UBRR4_REG UBRR
-#define UBRR5_REG UBRR
-#define UBRR6_REG UBRR
-#define UBRR7_REG UBRR
-
-/* TIFR */
-#define ICF1_REG TIFR
-#define OCF1B_REG TIFR
-#define OCF1A_REG TIFR
-#define TOV1_REG TIFR
-#define TOV0_REG TIFR
-
-/* UDR */
-#define UDR0_REG UDR
-#define UDR1_REG UDR
-#define UDR2_REG UDR
-#define UDR3_REG UDR
-#define UDR4_REG UDR
-#define UDR5_REG UDR
-#define UDR6_REG UDR
-#define UDR7_REG UDR
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define ISC10_REG MCUCR
-#define ISC11_REG MCUCR
-#define SM_REG MCUCR
-#define SE_REG MCUCR
-#define SRW_REG MCUCR
-#define SRE_REG MCUCR
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* pins mapping */
-#define AD0_PORT PORTA
-#define AD0_BIT 0
-
-#define AD1_PORT PORTA
-#define AD1_BIT 1
-
-#define AD2_PORT PORTA
-#define AD2_BIT 2
-
-#define AD3_PORT PORTA
-#define AD3_BIT 3
-
-#define AD4_PORT PORTA
-#define AD4_BIT 4
-
-#define AD5_PORT PORTA
-#define AD5_BIT 5
-
-#define AD6_PORT PORTA
-#define AD6_BIT 6
-
-#define AD7_PORT PORTA
-#define AD7_BIT 7
-
-#define T0_PORT PORTB
-#define T0_BIT 0
-
-#define T1_PORT PORTB
-#define T1_BIT 1
-
-#define AIN0_PORT PORTB
-#define AIN0_BIT 2
-
-#define AIN1_PORT PORTB
-#define AIN1_BIT 3
-
-#define SS_PORT PORTB
-#define SS_BIT 4
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 5
-
-#define MISO_PORT PORTB
-#define MISO_BIT 6
-
-#define SCK_PORT PORTB
-#define SCK_BIT 7
-
-#define A8_PORT PORTC
-#define A8_BIT 0
-
-#define A9_PORT PORTC
-#define A9_BIT 1
-
-#define A10_PORT PORTC
-#define A10_BIT 2
-
-#define A11_PORT PORTC
-#define A11_BIT 3
-
-#define A12_PORT PORTC
-#define A12_BIT 4
-
-#define A13_PORT PORTC
-#define A13_BIT 5
-
-#define A14_PORT PORTC
-#define A14_BIT 6
-
-#define A15_PORT PORTC
-#define A15_BIT 7
-
-#define RXD_PORT PORTD
-#define RXD_BIT 0
-
-#define TXD_PORT PORTD
-#define TXD_BIT 1
-
-#define INT0_PORT PORTD
-#define INT0_BIT 2
-
-#define INT1_PORT PORTD
-#define INT1_BIT 3
-
-
-#define OC1A_PORT PORTD
-#define OC1A_BIT 5
-
-#define WR_PORT PORTD
-#define WR_BIT 6
-
-#define RD_PORT PORTD
-#define RD_BIT 7
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW_TOTAL_NUM 2
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE1_NUM 0
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 1
-
-/* Pwm nums */
-#define PWM1_NUM 0
-#define PWM_TOTAL_NUM 1
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDTOE_REG WDTCR
-
-/* GIMSK */
-#define INT0_REG GIMSK
-#define INT1_REG GIMSK
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define ADCBG_REG ADMUX
-
-/* TCCR0 */
-#define CS00_REG TCCR0
-#define CS01_REG TCCR0
-#define CS02_REG TCCR0
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* TCCR1A */
-#define PWM10_REG TCCR1A
-#define PWM11_REG TCCR1A
-#define COM10_REG TCCR1A
-#define COM11_REG TCCR1A
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define CTC1_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* GIFR */
-#define INTF0_REG GIFR
-#define INTF1_REG GIFR
-
-/* TIMSK */
-#define TOIE0_REG TIMSK
-#define TICIE1_REG TIMSK
-#define OCIE1_REG TIMSK
-#define TOIE1_REG TIMSK
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* UBRRHI */
-#define UBRRHI0_REG UBRRHI
-#define UBRRHI1_REG UBRRHI
-#define UBRRHI2_REG UBRRHI
-#define UBRRHI3_REG UBRRHI
-
-/* SPSR */
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define AINBG_REG ACSR
-#define ACD_REG ACSR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* UCSRA */
-#define MPCM_REG UCSRA
-#define OR_REG UCSRA
-#define FE_REG UCSRA
-#define UDRE_REG UCSRA
-#define TXC_REG UCSRA
-#define RXC_REG UCSRA
-
-/* UCSRB */
-#define TXB8_REG UCSRB
-#define RXB8_REG UCSRB
-#define CHR9_REG UCSRB
-#define TXEN_REG UCSRB
-#define RXEN_REG UCSRB
-#define UDRIE_REG UCSRB
-#define TXCIE_REG UCSRB
-#define RXCIE_REG UCSRB
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* UBRR */
-#define UBRR0_REG UBRR
-#define UBRR1_REG UBRR
-#define UBRR2_REG UBRR
-#define UBRR3_REG UBRR
-#define UBRR4_REG UBRR
-#define UBRR5_REG UBRR
-#define UBRR6_REG UBRR
-#define UBRR7_REG UBRR
-
-/* ADCL */
-#define ADC0_REG ADCL
-#define ADC1_REG ADCL
-#define ADC2_REG ADCL
-#define ADC3_REG ADCL
-#define ADC4_REG ADCL
-#define ADC5_REG ADCL
-#define ADC6_REG ADCL
-#define ADC7_REG ADCL
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* EEAR */
-#define EEAR0_REG EEAR
-#define EEAR1_REG EEAR
-#define EEAR2_REG EEAR
-#define EEAR3_REG EEAR
-#define EEAR4_REG EEAR
-#define EEAR5_REG EEAR
-#define EEAR6_REG EEAR
-#define EEAR7_REG EEAR
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-
-/* ADCH */
-#define ADC8_REG ADCH
-#define ADC9_REG ADCH
-
-/* TCNT0 */
-#define TCNT00_REG TCNT0
-#define TCNT01_REG TCNT0
-#define TCNT02_REG TCNT0
-#define TCNT03_REG TCNT0
-#define TCNT04_REG TCNT0
-#define TCNT05_REG TCNT0
-#define TCNT06_REG TCNT0
-#define TCNT07_REG TCNT0
-
-/* TIFR */
-#define TOV0_REG TIFR
-#define ICF1_REG TIFR
-#define OCF1_REG TIFR
-#define TOV1_REG TIFR
-
-/* UDR */
-#define UDR0_REG UDR
-#define UDR1_REG UDR
-#define UDR2_REG UDR
-#define UDR3_REG UDR
-#define UDR4_REG UDR
-#define UDR5_REG UDR
-#define UDR6_REG UDR
-#define UDR7_REG UDR
-
-/* OCR1L */
-#define OCR1AL0_REG OCR1L
-#define OCR1AL1_REG OCR1L
-#define OCR1AL2_REG OCR1L
-#define OCR1AL3_REG OCR1L
-#define OCR1AL4_REG OCR1L
-#define OCR1AL5_REG OCR1L
-#define OCR1AL6_REG OCR1L
-#define OCR1AL7_REG OCR1L
-
-/* ADCSR */
-#define ADPS0_REG ADCSR
-#define ADPS1_REG ADCSR
-#define ADPS2_REG ADCSR
-#define ADIE_REG ADCSR
-#define ADIF_REG ADCSR
-#define ADFR_REG ADCSR
-#define ADSC_REG ADCSR
-#define ADEN_REG ADCSR
-
-/* OCR1H */
-#define OCR1AH0_REG OCR1H
-#define OCR1AH1_REG OCR1H
-#define OCR1AH2_REG OCR1H
-#define OCR1AH3_REG OCR1H
-#define OCR1AH4_REG OCR1H
-#define OCR1AH5_REG OCR1H
-#define OCR1AH6_REG OCR1H
-#define OCR1AH7_REG OCR1H
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-
-/* SP */
-#define SP0_REG SP
-#define SP1_REG SP
-#define SP2_REG SP
-#define SP3_REG SP
-#define SP4_REG SP
-#define SP5_REG SP
-#define SP6_REG SP
-#define SP7_REG SP
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define ISC10_REG MCUCR
-#define ISC11_REG MCUCR
-#define SM_REG MCUCR
-#define SE_REG MCUCR
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* pins mapping */
-#define ADC0_PORT PORTC
-#define ADC0_BIT 0
-
-#define ADC1_PORT PORTC
-#define ADC1_BIT 1
-
-#define ADC2_PORT PORTC
-#define ADC2_BIT 2
-
-#define ADC3_PORT PORTC
-#define ADC3_BIT 3
-
-#define ADC4_PORT PORTC
-#define ADC4_BIT 4
-
-#define ADC5_PORT PORTC
-#define ADC5_BIT 5
-
-#define RXD_PORT PORTD
-#define RXD_BIT 0
-
-#define TXD_PORT PORTD
-#define TXD_BIT 1
-
-#define INT0_PORT PORTD
-#define INT0_BIT 2
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE1A_NUM 0
-#define SIG_OUTPUT_COMPARE1B_NUM 1
-#define SIG_OUTPUT_COMPARE2_NUM 2
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 3
-
-/* Pwm nums */
-#define PWM1A_NUM 0
-#define PWM1B_NUM 1
-#define PWM2_NUM 2
-#define PWM_TOTAL_NUM 3
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDTOE_REG WDTCR
-
-/* GIMSK */
-#define INT0_REG GIMSK
-#define INT1_REG GIMSK
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-
-/* TCCR0 */
-#define CS00_REG TCCR0
-#define CS01_REG TCCR0
-#define CS02_REG TCCR0
-
-/* TCCR2 */
-#define CS20_REG TCCR2
-#define CS21_REG TCCR2
-#define CS22_REG TCCR2
-#define CTC2_REG TCCR2
-#define COM20_REG TCCR2
-#define COM21_REG TCCR2
-#define PWM2_REG TCCR2
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* USR */
-#define OR_REG USR
-#define FE_REG USR
-#define UDRE_REG USR
-#define TXC_REG USR
-#define RXC_REG USR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* TCCR1A */
-#define PWM10_REG TCCR1A
-#define PWM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define CTC1_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* GIFR */
-#define INTF0_REG GIFR
-#define INTF1_REG GIFR
-
-/* TIMSK */
-#define TOIE0_REG TIMSK
-#define TOIE1_REG TIMSK
-#define OCIE1B_REG TIMSK
-#define OCIE1A_REG TIMSK
-#define TICIE1_REG TIMSK
-#define TOIE2_REG TIMSK
-#define OCIE2_REG TIMSK
-
-/* UCR */
-#define TXB8_REG UCR
-#define RXB8_REG UCR
-#define CHR9_REG UCR
-#define TXEN_REG UCR
-#define RXEN_REG UCR
-#define UDRIE_REG UCR
-#define TXCIE_REG UCR
-#define RXCIE_REG UCR
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACD_REG ACSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* ADCL */
-#define ADC0_REG ADCL
-#define ADC1_REG ADCL
-#define ADC2_REG ADCL
-#define ADC3_REG ADCL
-#define ADC4_REG ADCL
-#define ADC5_REG ADCL
-#define ADC6_REG ADCL
-#define ADC7_REG ADCL
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* ADCH */
-#define ADC8_REG ADCH
-#define ADC9_REG ADCH
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT00_REG TCNT0
-#define TCNT01_REG TCNT0
-#define TCNT02_REG TCNT0
-#define TCNT03_REG TCNT0
-#define TCNT04_REG TCNT0
-#define TCNT05_REG TCNT0
-#define TCNT06_REG TCNT0
-#define TCNT07_REG TCNT0
-
-/* UDR */
-#define UDR0_REG UDR
-#define UDR1_REG UDR
-#define UDR2_REG UDR
-#define UDR3_REG UDR
-#define UDR4_REG UDR
-#define UDR5_REG UDR
-#define UDR6_REG UDR
-#define UDR7_REG UDR
-
-/* UBRR */
-#define UBRR0_REG UBRR
-#define UBRR1_REG UBRR
-#define UBRR2_REG UBRR
-#define UBRR3_REG UBRR
-#define UBRR4_REG UBRR
-#define UBRR5_REG UBRR
-#define UBRR6_REG UBRR
-#define UBRR7_REG UBRR
-
-/* ADCSR */
-#define ADPS0_REG ADCSR
-#define ADPS1_REG ADCSR
-#define ADPS2_REG ADCSR
-#define ADIE_REG ADCSR
-#define ADIF_REG ADCSR
-#define ADFR_REG ADCSR
-#define ADSC_REG ADCSR
-#define ADEN_REG ADCSR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* TIFR */
-#define TOV0_REG TIFR
-#define TOV1_REG TIFR
-#define OCF1B_REG TIFR
-#define OCF1A_REG TIFR
-#define ICF1_REG TIFR
-#define TOV2_REG TIFR
-#define OCF2_REG TIFR
-
-/* EEARH */
-#define EEAR8_REG EEARH
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define ISC10_REG MCUCR
-#define ISC11_REG MCUCR
-#define SM0_REG MCUCR
-#define SM1_REG MCUCR
-#define SE_REG MCUCR
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* OCR2 */
-#define OCR2_0_REG OCR2
-#define OCR2_1_REG OCR2
-#define OCR2_2_REG OCR2
-#define OCR2_3_REG OCR2
-#define OCR2_4_REG OCR2
-#define OCR2_5_REG OCR2
-#define OCR2_6_REG OCR2
-#define OCR2_7_REG OCR2
-
-/* ASSR */
-#define TCR2UB_REG ASSR
-#define OCR2UB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-
-/* pins mapping */
-#define ADC0_PORT PORTA
-#define ADC0_BIT 0
-
-#define ADC1_PORT PORTA
-#define ADC1_BIT 1
-
-#define ADC2_PORT PORTA
-#define ADC2_BIT 2
-
-#define ADC3_PORT PORTA
-#define ADC3_BIT 3
-
-#define ADC4_PORT PORTA
-#define ADC4_BIT 4
-
-#define ADc5_PORT PORTA
-#define ADc5_BIT 5
-
-#define ADC6_PORT PORTA
-#define ADC6_BIT 6
-
-#define ADC7_PORT PORTA
-#define ADC7_BIT 7
-
-#define T0_PORT PORTB
-#define T0_BIT 0
-
-#define T1_PORT PORTB
-#define T1_BIT 1
-
-#define AIN0_PORT PORTB
-#define AIN0_BIT 2
-
-#define AIN1_PORT PORTB
-#define AIN1_BIT 3
-
-#define SS_PORT PORTB
-#define SS_BIT 4
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 5
-
-#define MISO_PORT PORTB
-#define MISO_BIT 6
-
-
-
-
-
-
-
-
-#define TOSC1_PORT PORTC
-#define TOSC1_BIT 6
-
-#define TOSC2_PORT PORTC
-#define TOSC2_BIT 7
-
-#define RXD_PORT PORTD
-#define RXD_BIT 0
-
-#define TXD_PORT PORTD
-#define TXD_BIT 1
-
-#define INT0_PORT PORTD
-#define INT0_BIT 2
-
-#define INT1_PORT PORTD
-#define INT1_BIT 3
-
-#define OC1B_PORT PORTD
-#define OC1B_BIT 4
-
-#define OC1A_PORT PORTD
-#define OC1A_BIT 5
-
-#define ICP_PORT PORTD
-#define ICP_BIT 6
-
-#define OC2_PORT PORTD
-#define OC2_BIT 7
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW_TOTAL_NUM 2
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE1A_NUM 0
-#define SIG_OUTPUT_COMPARE1B_NUM 1
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 2
-
-/* Pwm nums */
-#define PWM1A_NUM 0
-#define PWM1B_NUM 1
-#define PWM_TOTAL_NUM 2
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDTOE_REG WDTCR
-
-/* GIMSK */
-#define INT0_REG GIMSK
-#define INT1_REG GIMSK
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* TCCR0 */
-#define CS00_REG TCCR0
-#define CS01_REG TCCR0
-#define CS02_REG TCCR0
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* USR */
-#define OR_REG USR
-#define FE_REG USR
-#define UDRE_REG USR
-#define TXC_REG USR
-#define RXC_REG USR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* TCCR1A */
-#define PWM10_REG TCCR1A
-#define PWM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define CTC1_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* GIFR */
-#define INTF0_REG GIFR
-#define INTF1_REG GIFR
-
-/* TIMSK */
-#define TICIE1_REG TIMSK
-#define OCIE1B_REG TIMSK
-#define OCIE1A_REG TIMSK
-#define TOIE1_REG TIMSK
-#define TOIE0_REG TIMSK
-
-/* UCR */
-#define TXB8_REG UCR
-#define RXB8_REG UCR
-#define CHR9_REG UCR
-#define TXEN_REG UCR
-#define RXEN_REG UCR
-#define UDRIE_REG UCR
-#define TXCIE_REG UCR
-#define RXCIE_REG UCR
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACD_REG ACSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* TCNT0 */
-#define TCNT00_REG TCNT0
-#define TCNT01_REG TCNT0
-#define TCNT02_REG TCNT0
-#define TCNT03_REG TCNT0
-#define TCNT04_REG TCNT0
-#define TCNT05_REG TCNT0
-#define TCNT06_REG TCNT0
-#define TCNT07_REG TCNT0
-
-/* UDR */
-#define UDR0_REG UDR
-#define UDR1_REG UDR
-#define UDR2_REG UDR
-#define UDR3_REG UDR
-#define UDR4_REG UDR
-#define UDR5_REG UDR
-#define UDR6_REG UDR
-#define UDR7_REG UDR
-
-/* UBRR */
-#define UBRR0_REG UBRR
-#define UBRR1_REG UBRR
-#define UBRR2_REG UBRR
-#define UBRR3_REG UBRR
-#define UBRR4_REG UBRR
-#define UBRR5_REG UBRR
-#define UBRR6_REG UBRR
-#define UBRR7_REG UBRR
-
-/* TIFR */
-#define ICF1_REG TIFR
-#define OCF1B_REG TIFR
-#define OCF1A_REG TIFR
-#define TOV1_REG TIFR
-#define TOV0_REG TIFR
-
-/* EEARH */
-#define EEAR8_REG EEARH
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define ISC10_REG MCUCR
-#define ISC11_REG MCUCR
-#define SM_REG MCUCR
-#define SE_REG MCUCR
-#define SRW_REG MCUCR
-#define SRE_REG MCUCR
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* pins mapping */
-#define AD0_PORT PORTA
-#define AD0_BIT 0
-
-#define AD1_PORT PORTA
-#define AD1_BIT 1
-
-#define AD2_PORT PORTA
-#define AD2_BIT 2
-
-#define AD3_PORT PORTA
-#define AD3_BIT 3
-
-#define AD4_PORT PORTA
-#define AD4_BIT 4
-
-#define AD5_PORT PORTA
-#define AD5_BIT 5
-
-#define AD6_PORT PORTA
-#define AD6_BIT 6
-
-#define AD7_PORT PORTA
-#define AD7_BIT 7
-
-#define T0_PORT PORTB
-#define T0_BIT 0
-
-#define T1_PORT PORTB
-#define T1_BIT 1
-
-#define AIN0_PORT PORTB
-#define AIN0_BIT 2
-
-#define AIN1_PORT PORTB
-#define AIN1_BIT 3
-
-#define SS_PORT PORTB
-#define SS_BIT 4
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 5
-
-#define MISO_PORT PORTB
-#define MISO_BIT 6
-
-#define SCK_PORT PORTB
-#define SCK_BIT 7
-
-#define A8_PORT PORTC
-#define A8_BIT 0
-
-#define A9_PORT PORTC
-#define A9_BIT 1
-
-#define A10_PORT PORTC
-#define A10_BIT 2
-
-#define A11_PORT PORTC
-#define A11_BIT 3
-
-#define A12_PORT PORTC
-#define A12_BIT 4
-
-#define A13_PORT PORTC
-#define A13_BIT 5
-
-#define A14_PORT PORTC
-#define A14_BIT 6
-
-#define A15_PORT PORTC
-#define A15_BIT 7
-
-#define RXD_PORT PORTD
-#define RXD_BIT 0
-
-#define TXD_PORT PORTD
-#define TXD_BIT 1
-
-#define INT0_PORT PORTD
-#define INT0_BIT 2
-
-#define INT1_PORT PORTD
-#define INT1_BIT 3
-
-
-#define OC1A_PORT PORTD
-#define OC1A_BIT 5
-
-#define WR_PORT PORTD
-#define WR_BIT 6
-
-#define RD_PORT PORTD
-#define RD_BIT 7
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW_TOTAL_NUM 2
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE1A_NUM 1
-#define SIG_OUTPUT_COMPARE1B_NUM 2
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 3
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM1A_NUM 1
-#define PWM1B_NUM 2
-#define PWM_TOTAL_NUM 3
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* UCSRC */
-#define UCPOL_REG UCSRC
-#define UCSZ0_REG UCSRC
-#define UCSZ1_REG UCSRC
-#define USBS_REG UCSRC
-#define UPM0_REG UCSRC
-#define UPM1_REG UCSRC
-#define UMSEL_REG UCSRC
-/* #define URSEL_REG UCSRC */ /* dup in UBRRH */
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* TCCR0 */
-#define CS00_REG TCCR0
-#define CS01_REG TCCR0
-#define CS02_REG TCCR0
-#define WGM01_REG TCCR0
-#define COM00_REG TCCR0
-#define COM01_REG TCCR0
-#define WGM00_REG TCCR0
-#define FOC0_REG TCCR0
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* GICR */
-#define IVCE_REG GICR
-#define IVSEL_REG GICR
-#define INT2_REG GICR
-#define INT0_REG GICR
-#define INT1_REG GICR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define FOC1B_REG TCCR1A
-#define FOC1A_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* GIFR */
-#define INTF2_REG GIFR
-#define INTF0_REG GIFR
-#define INTF1_REG GIFR
-
-/* TIMSK */
-#define OCIE0_REG TIMSK
-#define TOIE0_REG TIMSK
-#define TICIE1_REG TIMSK
-#define OCIE1B_REG TIMSK
-#define OCIE1A_REG TIMSK
-#define TOIE1_REG TIMSK
-
-/* UCSRA */
-#define MPCM_REG UCSRA
-#define U2X_REG UCSRA
-#define UPE_REG UCSRA
-#define DOR_REG UCSRA
-#define FE_REG UCSRA
-#define UDRE_REG UCSRA
-#define TXC_REG UCSRA
-#define RXC_REG UCSRA
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SFIOR */
-#define PSR10_REG SFIOR
-#define PUD_REG SFIOR
-#define XMM0_REG SFIOR
-#define XMM1_REG SFIOR
-#define XMM2_REG SFIOR
-#define XMBK_REG SFIOR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* UCSRB */
-#define TXB8_REG UCSRB
-#define RXB8_REG UCSRB
-#define UCSZ2_REG UCSRB
-#define TXEN_REG UCSRB
-#define RXEN_REG UCSRB
-#define UDRIE_REG UCSRB
-#define TXCIE_REG UCSRB
-#define RXCIE_REG UCSRB
-
-/* EMCUCR */
-#define ISC2_REG EMCUCR
-#define SRW11_REG EMCUCR
-#define SRW00_REG EMCUCR
-#define SRW01_REG EMCUCR
-#define SRL0_REG EMCUCR
-#define SRL1_REG EMCUCR
-#define SRL2_REG EMCUCR
-#define SM0_REG EMCUCR
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* UDR */
-#define UDR0_REG UDR
-#define UDR1_REG UDR
-#define UDR2_REG UDR
-#define UDR3_REG UDR
-#define UDR4_REG UDR
-#define UDR5_REG UDR
-#define UDR6_REG UDR
-#define UDR7_REG UDR
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* SPMCR */
-#define SPMEN_REG SPMCR
-#define PGERS_REG SPMCR
-#define PGWRT_REG SPMCR
-#define BLBSET_REG SPMCR
-#define RWWSRE_REG SPMCR
-#define RWWSB_REG SPMCR
-#define SPMIE_REG SPMCR
-
-/* UBRRH */
-#define UBRR8_REG UBRRH
-#define UBRR9_REG UBRRH
-#define UBRR10_REG UBRRH
-#define UBRR11_REG UBRRH
-/* #define URSEL_REG UBRRH */ /* dup in UCSRC */
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-
-/* UBRRL */
-#define UBRR0_REG UBRRL
-#define UBRR1_REG UBRRL
-#define UBRR2_REG UBRRL
-#define UBRR3_REG UBRRL
-#define UBRR4_REG UBRRL
-#define UBRR5_REG UBRRL
-#define UBRR6_REG UBRRL
-#define UBRR7_REG UBRRL
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* MCUCSR */
-#define PORF_REG MCUCSR
-#define EXTRF_REG MCUCSR
-#define BORF_REG MCUCSR
-#define WDRF_REG MCUCSR
-#define SM2_REG MCUCSR
-
-/* TIFR */
-#define OCF0_REG TIFR
-#define TOV0_REG TIFR
-#define ICF1_REG TIFR
-#define OCF1B_REG TIFR
-#define OCF1A_REG TIFR
-#define TOV1_REG TIFR
-
-/* EEARH */
-#define EEAR8_REG EEARH
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define ISC10_REG MCUCR
-#define ISC11_REG MCUCR
-#define SM1_REG MCUCR
-#define SE_REG MCUCR
-#define SRW10_REG MCUCR
-#define SRE_REG MCUCR
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* OCR0 */
-#define OCR0_0_REG OCR0
-#define OCR0_1_REG OCR0
-#define OCR0_2_REG OCR0
-#define OCR0_3_REG OCR0
-#define OCR0_4_REG OCR0
-#define OCR0_5_REG OCR0
-#define OCR0_6_REG OCR0
-#define OCR0_7_REG OCR0
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* pins mapping */
-#define AD0_PORT PORTA
-#define AD0_BIT 0
-
-#define AD1_PORT PORTA
-#define AD1_BIT 1
-
-#define AD2_PORT PORTA
-#define AD2_BIT 2
-
-#define AD3_PORT PORTA
-#define AD3_BIT 3
-
-#define AD4_PORT PORTA
-#define AD4_BIT 4
-
-#define AD5_PORT PORTA
-#define AD5_BIT 5
-
-#define AD6_PORT PORTA
-#define AD6_BIT 6
-
-#define AD7_PORT PORTA
-#define AD7_BIT 7
-
-#define OC0_PORT PORTB
-#define OC0_BIT 0
-#define T0_PORT PORTB
-#define T0_BIT 0
-
-#define T1_PORT PORTB
-#define T1_BIT 1
-
-#define AIN0_PORT PORTB
-#define AIN0_BIT 2
-
-#define AIN1_PORT PORTB
-#define AIN1_BIT 3
-
-#define SS_PORT PORTB
-#define SS_BIT 4
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 5
-
-#define MISO_PORT PORTB
-#define MISO_BIT 6
-
-#define SCK_PORT PORTB
-#define SCK_BIT 7
-
-#define A8_PORT PORTC
-#define A8_BIT 0
-
-#define A9_PORT PORTC
-#define A9_BIT 1
-
-#define A10_PORT PORTC
-#define A10_BIT 2
-
-#define A11_PORT PORTC
-#define A11_BIT 3
-
-#define A12_PORT PORTC
-#define A12_BIT 4
-
-#define A13_PORT PORTC
-#define A13_BIT 5
-
-#define A14_PORT PORTC
-#define A14_BIT 6
-
-#define A15_PORT PORTC
-#define A15_BIT 7
-
-#define RXD_PORT PORTD
-#define RXD_BIT 0
-
-#define TXD_PORT PORTD
-#define TXD_BIT 1
-
-#define INT0_PORT PORTD
-#define INT0_BIT 2
-
-#define INT1_PORT PORTD
-#define INT1_BIT 3
-
-#define XCK_PORT PORTD
-#define XCK_BIT 4
-
-#define OC1A_PORT PORTD
-#define OC1A_BIT 5
-
-#define WR_PORT PORTD
-#define WR_BIT 6
-
-#define RD_PORT PORTD
-#define RD_BIT 7
-
-#define ICP_PORT PORTE
-#define ICP_BIT 0
-#define INT2_PORT PORTE
-#define INT2_BIT 0
-
-#define ALE_PORT PORTE
-#define ALE_BIT 1
-
-#define OC1B_PORT PORTE
-#define OC1B_BIT 2
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE1A_NUM 0
-#define SIG_OUTPUT_COMPARE1B_NUM 1
-#define SIG_OUTPUT_COMPARE2_NUM 2
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 3
-
-/* Pwm nums */
-#define PWM1A_NUM 0
-#define PWM1B_NUM 1
-#define PWM2_NUM 2
-#define PWM_TOTAL_NUM 3
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDTOE_REG WDTCR
-
-/* GIMSK */
-#define INT0_REG GIMSK
-#define INT1_REG GIMSK
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-
-/* TCCR0 */
-#define CS00_REG TCCR0
-#define CS01_REG TCCR0
-#define CS02_REG TCCR0
-
-/* TCCR2 */
-#define CS20_REG TCCR2
-#define CS21_REG TCCR2
-#define CS22_REG TCCR2
-#define CTC2_REG TCCR2
-#define COM20_REG TCCR2
-#define COM21_REG TCCR2
-#define PWM2_REG TCCR2
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* USR */
-#define OR_REG USR
-#define FE_REG USR
-#define UDRE_REG USR
-#define TXC_REG USR
-#define RXC_REG USR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* TCCR1A */
-#define PWM10_REG TCCR1A
-#define PWM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define CTC1_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* GIFR */
-#define INTF0_REG GIFR
-#define INTF1_REG GIFR
-
-/* TIMSK */
-#define TOIE0_REG TIMSK
-#define TOIE1_REG TIMSK
-#define OCIE1B_REG TIMSK
-#define OCIE1A_REG TIMSK
-#define TICIE1_REG TIMSK
-#define TOIE2_REG TIMSK
-#define OCIE2_REG TIMSK
-
-/* UCR */
-#define TXB8_REG UCR
-#define RXB8_REG UCR
-#define CHR9_REG UCR
-#define TXEN_REG UCR
-#define RXEN_REG UCR
-#define UDRIE_REG UCR
-#define TXCIE_REG UCR
-#define RXCIE_REG UCR
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACD_REG ACSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* ADCL */
-#define ADC0_REG ADCL
-#define ADC1_REG ADCL
-#define ADC2_REG ADCL
-#define ADC3_REG ADCL
-#define ADC4_REG ADCL
-#define ADC5_REG ADCL
-#define ADC6_REG ADCL
-#define ADC7_REG ADCL
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* ADCH */
-#define ADC8_REG ADCH
-#define ADC9_REG ADCH
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT00_REG TCNT0
-#define TCNT01_REG TCNT0
-#define TCNT02_REG TCNT0
-#define TCNT03_REG TCNT0
-#define TCNT04_REG TCNT0
-#define TCNT05_REG TCNT0
-#define TCNT06_REG TCNT0
-#define TCNT07_REG TCNT0
-
-/* UDR */
-#define UDR0_REG UDR
-#define UDR1_REG UDR
-#define UDR2_REG UDR
-#define UDR3_REG UDR
-#define UDR4_REG UDR
-#define UDR5_REG UDR
-#define UDR6_REG UDR
-#define UDR7_REG UDR
-
-/* UBRR */
-#define UBRR0_REG UBRR
-#define UBRR1_REG UBRR
-#define UBRR2_REG UBRR
-#define UBRR3_REG UBRR
-#define UBRR4_REG UBRR
-#define UBRR5_REG UBRR
-#define UBRR6_REG UBRR
-#define UBRR7_REG UBRR
-
-/* ADCSR */
-#define ADPS0_REG ADCSR
-#define ADPS1_REG ADCSR
-#define ADPS2_REG ADCSR
-#define ADIE_REG ADCSR
-#define ADIF_REG ADCSR
-#define ADFR_REG ADCSR
-#define ADSC_REG ADCSR
-#define ADEN_REG ADCSR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* TIFR */
-#define TOV0_REG TIFR
-#define TOV1_REG TIFR
-#define OCF1B_REG TIFR
-#define OCF1A_REG TIFR
-#define ICF1_REG TIFR
-#define TOV2_REG TIFR
-#define OCF2_REG TIFR
-
-/* EEARH */
-#define EEAR8_REG EEARH
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define ISC10_REG MCUCR
-#define ISC11_REG MCUCR
-#define SM0_REG MCUCR
-#define SM1_REG MCUCR
-#define SE_REG MCUCR
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* OCR2 */
-#define OCR2_0_REG OCR2
-#define OCR2_1_REG OCR2
-#define OCR2_2_REG OCR2
-#define OCR2_3_REG OCR2
-#define OCR2_4_REG OCR2
-#define OCR2_5_REG OCR2
-#define OCR2_6_REG OCR2
-#define OCR2_7_REG OCR2
-
-/* ASSR */
-#define TCR2UB_REG ASSR
-#define OCR2UB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-
-/* pins mapping */
-#define ADC0_PORT PORTA
-#define ADC0_BIT 0
-
-#define ADC1_PORT PORTA
-#define ADC1_BIT 1
-
-#define ADC2_PORT PORTA
-#define ADC2_BIT 2
-
-#define ADC3_PORT PORTA
-#define ADC3_BIT 3
-
-#define ADC4_PORT PORTA
-#define ADC4_BIT 4
-
-#define ADc5_PORT PORTA
-#define ADc5_BIT 5
-
-#define ADC6_PORT PORTA
-#define ADC6_BIT 6
-
-#define ADC7_PORT PORTA
-#define ADC7_BIT 7
-
-#define T0_PORT PORTB
-#define T0_BIT 0
-
-#define T1_PORT PORTB
-#define T1_BIT 1
-
-#define AIN0_PORT PORTB
-#define AIN0_BIT 2
-
-#define AIN1_PORT PORTB
-#define AIN1_BIT 3
-
-#define SS_PORT PORTB
-#define SS_BIT 4
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 5
-
-#define MISO_PORT PORTB
-#define MISO_BIT 6
-
-
-
-
-
-
-
-
-#define TOSC1_PORT PORTC
-#define TOSC1_BIT 6
-
-#define TOSC2_PORT PORTC
-#define TOSC2_BIT 7
-
-#define RXD_PORT PORTD
-#define RXD_BIT 0
-
-#define TXD_PORT PORTD
-#define TXD_BIT 1
-
-#define INT0_PORT PORTD
-#define INT0_BIT 2
-
-#define INT1_PORT PORTD
-#define INT1_BIT 3
-
-#define OC1B_PORT PORTD
-#define OC1B_BIT 4
-
-#define OC1A_PORT PORTD
-#define OC1A_BIT 5
-
-#define ICP_PORT PORTD
-#define ICP_BIT 6
-
-#define OC2_PORT PORTD
-#define OC2_BIT 7
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE1A_NUM 1
-#define SIG_OUTPUT_COMPARE1B_NUM 2
-#define SIG_OUTPUT_COMPARE2_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM1A_NUM 1
-#define PWM1B_NUM 2
-#define PWM2_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* TCCR0 */
-#define CS00_REG TCCR0
-#define CS01_REG TCCR0
-#define CS02_REG TCCR0
-#define WGM01_REG TCCR0
-#define COM00_REG TCCR0
-#define COM01_REG TCCR0
-#define WGM00_REG TCCR0
-#define FOC0_REG TCCR0
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* GICR */
-#define IVCE_REG GICR
-#define IVSEL_REG GICR
-#define INT2_REG GICR
-#define INT0_REG GICR
-#define INT1_REG GICR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define FOC1B_REG TCCR1A
-#define FOC1A_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* GIFR */
-#define INTF2_REG GIFR
-#define INTF0_REG GIFR
-#define INTF1_REG GIFR
-
-/* TIMSK */
-#define TOIE0_REG TIMSK
-#define OCIE0_REG TIMSK
-#define TOIE1_REG TIMSK
-#define OCIE1B_REG TIMSK
-#define OCIE1A_REG TIMSK
-#define TICIE1_REG TIMSK
-#define TOIE2_REG TIMSK
-#define OCIE2_REG TIMSK
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* UCSRA */
-#define MPCM_REG UCSRA
-#define U2X_REG UCSRA
-#define UPE_REG UCSRA
-#define DOR_REG UCSRA
-#define FE_REG UCSRA
-#define UDRE_REG UCSRA
-#define TXC_REG UCSRA
-#define RXC_REG UCSRA
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SFIOR */
-#define ADTS0_REG SFIOR
-#define ADTS1_REG SFIOR
-#define ADTS2_REG SFIOR
-#define PSR10_REG SFIOR
-#define PSR2_REG SFIOR
-#define PUD_REG SFIOR
-#define ACME_REG SFIOR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* UCSRB */
-#define TXB8_REG UCSRB
-#define RXB8_REG UCSRB
-#define UCSZ2_REG UCSRB
-#define TXEN_REG UCSRB
-#define RXEN_REG UCSRB
-#define UDRIE_REG UCSRB
-#define TXCIE_REG UCSRB
-#define RXCIE_REG UCSRB
-
-/* UCSRC */
-#define UCPOL_REG UCSRC
-#define UCSZ0_REG UCSRC
-#define UCSZ1_REG UCSRC
-#define USBS_REG UCSRC
-#define UPM0_REG UCSRC
-#define UPM1_REG UCSRC
-#define UMSEL_REG UCSRC
-/* #define URSEL_REG UCSRC */ /* dup in UBRRH */
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* UDR */
-#define UDR0_REG UDR
-#define UDR1_REG UDR
-#define UDR2_REG UDR
-#define UDR3_REG UDR
-#define UDR4_REG UDR
-#define UDR5_REG UDR
-#define UDR6_REG UDR
-#define UDR7_REG UDR
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* SPMCR */
-#define SPMEN_REG SPMCR
-#define PGERS_REG SPMCR
-#define PGWRT_REG SPMCR
-#define BLBSET_REG SPMCR
-#define RWWSRE_REG SPMCR
-#define RWWSB_REG SPMCR
-#define SPMIE_REG SPMCR
-
-/* UBRRH */
-#define UBRR8_REG UBRRH
-#define UBRR9_REG UBRRH
-#define UBRR10_REG UBRRH
-#define UBRR11_REG UBRRH
-/* #define URSEL_REG UBRRH */ /* dup in UCSRC */
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* UBRRL */
-#define UBRR0_REG UBRRL
-#define UBRR1_REG UBRRL
-#define UBRR2_REG UBRRL
-#define UBRR3_REG UBRRL
-#define UBRR4_REG UBRRL
-#define UBRR5_REG UBRRL
-#define UBRR6_REG UBRRL
-#define UBRR7_REG UBRRL
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* MCUCSR */
-#define ISC2_REG MCUCSR
-#define PORF_REG MCUCSR
-#define EXTRF_REG MCUCSR
-#define BORF_REG MCUCSR
-#define WDRF_REG MCUCSR
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* TCCR2 */
-#define CS20_REG TCCR2
-#define CS21_REG TCCR2
-#define CS22_REG TCCR2
-#define WGM21_REG TCCR2
-#define COM20_REG TCCR2
-#define COM21_REG TCCR2
-#define WGM20_REG TCCR2
-#define FOC2_REG TCCR2
-
-/* TIFR */
-#define TOV0_REG TIFR
-#define OCF0_REG TIFR
-#define TOV1_REG TIFR
-#define OCF1B_REG TIFR
-#define OCF1A_REG TIFR
-#define ICF1_REG TIFR
-#define TOV2_REG TIFR
-#define OCF2_REG TIFR
-
-/* EEARH */
-#define EEAR8_REG EEARH
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define ISC10_REG MCUCR
-#define ISC11_REG MCUCR
-#define SM0_REG MCUCR
-#define SM1_REG MCUCR
-#define SE_REG MCUCR
-#define SM2_REG MCUCR
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* ASSR */
-#define TCR2UB_REG ASSR
-#define OCR2UB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-
-/* OCR0 */
-#define OCR0_0_REG OCR0
-#define OCR0_1_REG OCR0
-#define OCR0_2_REG OCR0
-#define OCR0_3_REG OCR0
-#define OCR0_4_REG OCR0
-#define OCR0_5_REG OCR0
-#define OCR0_6_REG OCR0
-#define OCR0_7_REG OCR0
-
-/* OCR2 */
-#define OCR2_0_REG OCR2
-#define OCR2_1_REG OCR2
-#define OCR2_2_REG OCR2
-#define OCR2_3_REG OCR2
-#define OCR2_4_REG OCR2
-#define OCR2_5_REG OCR2
-#define OCR2_6_REG OCR2
-#define OCR2_7_REG OCR2
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* pins mapping */
-#define ADC0_PORT PORTA
-#define ADC0_BIT 0
-
-#define ADC1_PORT PORTA
-#define ADC1_BIT 1
-
-#define ADC2_PORT PORTA
-#define ADC2_BIT 2
-
-#define ADC3_PORT PORTA
-#define ADC3_BIT 3
-
-#define ADC4_PORT PORTA
-#define ADC4_BIT 4
-
-#define ADc5_PORT PORTA
-#define ADc5_BIT 5
-
-#define ADC6_PORT PORTA
-#define ADC6_BIT 6
-
-#define ADC7_PORT PORTA
-#define ADC7_BIT 7
-
-#define XCK_PORT PORTB
-#define XCK_BIT 0
-#define T0_PORT PORTB
-#define T0_BIT 0
-
-#define T1_PORT PORTB
-#define T1_BIT 1
-
-#define AIN0_PORT PORTB
-#define AIN0_BIT 2
-#define INT2_PORT PORTB
-#define INT2_BIT 2
-
-#define AIN1_PORT PORTB
-#define AIN1_BIT 3
-#define OC0_PORT PORTB
-#define OC0_BIT 3
-
-#define SS_PORT PORTB
-#define SS_BIT 4
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 5
-
-#define MISO_PORT PORTB
-#define MISO_BIT 6
-
-#define SCK_PORT PORTB
-#define SCK_BIT 7
-
-#define SCL_PORT PORTC
-#define SCL_BIT 0
-
-#define SDA_PORT PORTC
-#define SDA_BIT 1
-
-
-
-
-
-#define TOSC1_PORT PORTC
-#define TOSC1_BIT 6
-
-#define TOSC2_PORT PORTC
-#define TOSC2_BIT 7
-
-#define RXD_PORT PORTD
-#define RXD_BIT 0
-
-#define TXD_PORT PORTD
-#define TXD_BIT 1
-
-#define INT0_PORT PORTD
-#define INT0_BIT 2
-
-#define INT1_PORT PORTD
-#define INT1_BIT 3
-
-#define OC1B_PORT PORTD
-#define OC1B_BIT 4
-
-#define OC1A_PORT PORTD
-#define OC1A_BIT 5
-
-#define ICP_PORT PORTD
-#define ICP_BIT 6
-
-#define OC2_PORT PORTD
-#define OC2_BIT 7
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-/* prescalers timer 3 */
-#define TIMER3_PRESCALER_DIV_0 0
-#define TIMER3_PRESCALER_DIV_1 1
-#define TIMER3_PRESCALER_DIV_8 2
-#define TIMER3_PRESCALER_DIV_64 3
-#define TIMER3_PRESCALER_DIV_256 4
-#define TIMER3_PRESCALER_DIV_1024 5
-#define TIMER3_PRESCALER_DIV_FALL 6
-#define TIMER3_PRESCALER_DIV_RISE 7
-
-#define TIMER3_PRESCALER_REG_0 0
-#define TIMER3_PRESCALER_REG_1 1
-#define TIMER3_PRESCALER_REG_2 8
-#define TIMER3_PRESCALER_REG_3 64
-#define TIMER3_PRESCALER_REG_4 256
-#define TIMER3_PRESCALER_REG_5 1024
-#define TIMER3_PRESCALER_REG_6 -1
-#define TIMER3_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER1C_AVAILABLE
-#define TIMER2_AVAILABLE
-#define TIMER2A_AVAILABLE
-#define TIMER2B_AVAILABLE
-#define TIMER3_AVAILABLE
-#define TIMER3A_AVAILABLE
-#define TIMER3B_AVAILABLE
-#define TIMER3C_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW3_NUM 3
-#define SIG_OVERFLOW_TOTAL_NUM 4
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE1C_NUM 4
-#define SIG_OUTPUT_COMPARE2A_NUM 5
-#define SIG_OUTPUT_COMPARE2B_NUM 6
-#define SIG_OUTPUT_COMPARE3A_NUM 7
-#define SIG_OUTPUT_COMPARE3B_NUM 8
-#define SIG_OUTPUT_COMPARE3C_NUM 9
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 10
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM1C_NUM 4
-#define PWM2A_NUM 5
-#define PWM2B_NUM 6
-#define PWM3A_NUM 7
-#define PWM3B_NUM 8
-#define PWM3C_NUM 9
-#define PWM_TOTAL_NUM 10
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE3_NUM 1
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 2
-
-
-/* UEBCHX */
-#define UEBCHX_0_REG UEBCHX
-#define UEBCHX_1_REG UEBCHX
-#define UEBCHX_2_REG UEBCHX
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* UDIEN */
-#define SUSPE_REG UDIEN
-#define SOFE_REG UDIEN
-#define EORSTE_REG UDIEN
-#define WAKEUPE_REG UDIEN
-#define EORSME_REG UDIEN
-#define UPRSME_REG UDIEN
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* OCR0B */
-#define OCR0B_0_REG OCR0B
-#define OCR0B_1_REG OCR0B
-#define OCR0B_2_REG OCR0B
-#define OCR0B_3_REG OCR0B
-#define OCR0B_4_REG OCR0B
-#define OCR0B_5_REG OCR0B
-#define OCR0B_6_REG OCR0B
-#define OCR0B_7_REG OCR0B
-
-/* UDINT */
-#define SUSPI_REG UDINT
-#define SOFI_REG UDINT
-#define EORSTI_REG UDINT
-#define WAKEUPI_REG UDINT
-#define EORSMI_REG UDINT
-#define UPRSMI_REG UDINT
-
-/* UERST */
-#define EPRST0_REG UERST
-#define EPRST1_REG UERST
-#define EPRST2_REG UERST
-#define EPRST3_REG UERST
-#define EPRST4_REG UERST
-#define EPRST5_REG UERST
-#define EPRST6_REG UERST
-
-/* RAMPZ */
-#define RAMPZ0_REG RAMPZ
-
-/* UECFG1X */
-#define ALLOC_REG UECFG1X
-#define EPBK0_REG UECFG1X
-#define EPBK1_REG UECFG1X
-#define EPSIZE0_REG UECFG1X
-#define EPSIZE1_REG UECFG1X
-#define EPSIZE2_REG UECFG1X
-
-/* OCR2B */
-#define OCR2B_0_REG OCR2B
-#define OCR2B_1_REG OCR2B
-#define OCR2B_2_REG OCR2B
-#define OCR2B_3_REG OCR2B
-#define OCR2B_4_REG OCR2B
-#define OCR2B_5_REG OCR2B
-#define OCR2B_6_REG OCR2B
-#define OCR2B_7_REG OCR2B
-
-/* OCR2A */
-#define OCR2A_0_REG OCR2A
-#define OCR2A_1_REG OCR2A
-#define OCR2A_2_REG OCR2A
-#define OCR2A_3_REG OCR2A
-#define OCR2A_4_REG OCR2A
-#define OCR2A_5_REG OCR2A
-#define OCR2A_6_REG OCR2A
-#define OCR2A_7_REG OCR2A
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* UEINT */
-#define EPINT0_REG UEINT
-#define EPINT1_REG UEINT
-#define EPINT2_REG UEINT
-#define EPINT3_REG UEINT
-#define EPINT4_REG UEINT
-#define EPINT5_REG UEINT
-#define EPINT6_REG UEINT
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-#define PORTE3_REG PORTE
-#define PORTE4_REG PORTE
-#define PORTE5_REG PORTE
-#define PORTE6_REG PORTE
-#define PORTE7_REG PORTE
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-#define INT3_REG EIMSK
-#define INT4_REG EIMSK
-#define INT5_REG EIMSK
-#define INT6_REG EIMSK
-#define INT7_REG EIMSK
-
-/* UDR1 */
-#define UDR1_0_REG UDR1
-#define UDR1_1_REG UDR1
-#define UDR1_2_REG UDR1
-#define UDR1_3_REG UDR1
-#define UDR1_4_REG UDR1
-#define UDR1_5_REG UDR1
-#define UDR1_6_REG UDR1
-#define UDR1_7_REG UDR1
-
-/* EICRB */
-#define ISC40_REG EICRB
-#define ISC41_REG EICRB
-#define ISC50_REG EICRB
-#define ISC51_REG EICRB
-#define ISC60_REG EICRB
-#define ISC61_REG EICRB
-#define ISC70_REG EICRB
-#define ISC71_REG EICRB
-
-/* UEDATX */
-#define UEDATX_0_REG UEDATX
-#define UEDATX_1_REG UEDATX
-#define UEDATX_2_REG UEDATX
-#define UEDATX_3_REG UEDATX
-#define UEDATX_4_REG UEDATX
-#define UEDATX_5_REG UEDATX
-#define UEDATX_6_REG UEDATX
-#define UEDATX_7_REG UEDATX
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-#define ISC20_REG EICRA
-#define ISC21_REG EICRA
-#define ISC30_REG EICRA
-#define ISC31_REG EICRA
-
-/* UECFG0X */
-#define EPDIR_REG UECFG0X
-#define EPTYPE0_REG UECFG0X
-#define EPTYPE1_REG UECFG0X
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* DDRF */
-#define DDF0_REG DDRF
-#define DDF1_REG DDRF
-#define DDF2_REG DDRF
-#define DDF3_REG DDRF
-#define DDF4_REG DDRF
-#define DDF5_REG DDRF
-#define DDF6_REG DDRF
-#define DDF7_REG DDRF
-
-/* ASSR */
-#define TCR2BUB_REG ASSR
-#define TCR2AUB_REG ASSR
-#define OCR2BUB_REG ASSR
-#define OCR2AUB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* UENUM */
-#define UENUM_0_REG UENUM
-#define UENUM_1_REG UENUM
-#define UENUM_2_REG UENUM
-
-/* UBRR1L */
-#define UBRR_0_REG UBRR1L
-#define UBRR_1_REG UBRR1L
-#define UBRR_2_REG UBRR1L
-#define UBRR_3_REG UBRR1L
-#define UBRR_4_REG UBRR1L
-#define UBRR_5_REG UBRR1L
-#define UBRR_6_REG UBRR1L
-#define UBRR_7_REG UBRR1L
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* OCR3AL */
-#define OCR3AL0_REG OCR3AL
-#define OCR3AL1_REG OCR3AL
-#define OCR3AL2_REG OCR3AL
-#define OCR3AL3_REG OCR3AL
-#define OCR3AL4_REG OCR3AL
-#define OCR3AL5_REG OCR3AL
-#define OCR3AL6_REG OCR3AL
-#define OCR3AL7_REG OCR3AL
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1C0_REG TCCR1A
-#define COM1C1_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* OCR3AH */
-#define OCR3AH0_REG OCR3AH
-#define OCR3AH1_REG OCR3AH
-#define OCR3AH2_REG OCR3AH
-#define OCR3AH3_REG OCR3AH
-#define OCR3AH4_REG OCR3AH
-#define OCR3AH5_REG OCR3AH
-#define OCR3AH6_REG OCR3AH
-#define OCR3AH7_REG OCR3AH
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* UDCON */
-#define DETACH_REG UDCON
-#define RMWKUP_REG UDCON
-#define LSM_REG UDCON
-
-/* PCICR */
-#define PCIE0_REG PCICR
-
-/* USBINT */
-#define VBUSTI_REG USBINT
-#define IDTI_REG USBINT
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* UHWCON */
-#define UVREGE_REG UHWCON
-#define UVCONE_REG UHWCON
-#define UIDE_REG UHWCON
-#define UIMOD_REG UHWCON
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* UDMFN */
-#define FNCERR_REG UDMFN
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-#define OCF2B_REG TIFR2
-
-/* TIFR3 */
-#define TOV3_REG TIFR3
-#define OCF3A_REG TIFR3
-#define OCF3B_REG TIFR3
-#define OCF3C_REG TIFR3
-#define ICF3_REG TIFR3
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define OCF1C_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-#define EEAR10_REG EEARH
-#define EEAR11_REG EEARH
-
-/* UEBCLX */
-#define UEBCLX_0_REG UEBCLX
-#define UEBCLX_1_REG UEBCLX
-#define UEBCLX_2_REG UEBCLX
-#define UEBCLX_3_REG UEBCLX
-#define UEBCLX_4_REG UEBCLX
-#define UEBCLX_5_REG UEBCLX
-#define UEBCLX_6_REG UEBCLX
-#define UEBCLX_7_REG UEBCLX
-
-/* OCR3CH */
-#define OCR3CH0_REG OCR3CH
-#define OCR3CH1_REG OCR3CH
-#define OCR3CH2_REG OCR3CH
-#define OCR3CH3_REG OCR3CH
-#define OCR3CH4_REG OCR3CH
-#define OCR3CH5_REG OCR3CH
-#define OCR3CH6_REG OCR3CH
-#define OCR3CH7_REG OCR3CH
-
-/* UESTA1X */
-#define CURRBK0_REG UESTA1X
-#define CURRBK1_REG UESTA1X
-#define CTRLDIR_REG UESTA1X
-
-/* OCR3CL */
-#define OCR3CL0_REG OCR3CL
-#define OCR3CL1_REG OCR3CL
-#define OCR3CL2_REG OCR3CL
-#define OCR3CL3_REG OCR3CL
-#define OCR3CL4_REG OCR3CL
-#define OCR3CL5_REG OCR3CL
-#define OCR3CL6_REG OCR3CL
-#define OCR3CL7_REG OCR3CL
-
-/* GTCCR */
-#define PSRSYNC_REG GTCCR
-#define TSM_REG GTCCR
-#define PSRASY_REG GTCCR
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* TCCR3C */
-#define FOC3C_REG TCCR3C
-#define FOC3B_REG TCCR3C
-#define FOC3A_REG TCCR3C
-
-/* TCCR3B */
-#define CS30_REG TCCR3B
-#define CS31_REG TCCR3B
-#define CS32_REG TCCR3B
-#define WGM32_REG TCCR3B
-#define WGM33_REG TCCR3B
-#define ICES3_REG TCCR3B
-#define ICNC3_REG TCCR3B
-
-/* TCCR3A */
-#define WGM30_REG TCCR3A
-#define WGM31_REG TCCR3A
-#define COM3C0_REG TCCR3A
-#define COM3C1_REG TCCR3A
-#define COM3B0_REG TCCR3A
-#define COM3B1_REG TCCR3A
-#define COM3A0_REG TCCR3A
-#define COM3A1_REG TCCR3A
-
-/* UEINTX */
-#define TXINI_REG UEINTX
-#define STALLEDI_REG UEINTX
-#define RXOUTI_REG UEINTX
-#define RXSTPI_REG UEINTX
-#define NAKOUTI_REG UEINTX
-#define RWAL_REG UEINTX
-#define NAKINI_REG UEINTX
-#define FIFOCON_REG UEINTX
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* TCNT3H */
-#define TCNT3H0_REG TCNT3H
-#define TCNT3H1_REG TCNT3H
-#define TCNT3H2_REG TCNT3H
-#define TCNT3H3_REG TCNT3H
-#define TCNT3H4_REG TCNT3H
-#define TCNT3H5_REG TCNT3H
-#define TCNT3H6_REG TCNT3H
-#define TCNT3H7_REG TCNT3H
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* TCNT3L */
-#define TCNT3L0_REG TCNT3L
-#define TCNT3L1_REG TCNT3L
-#define TCNT3L2_REG TCNT3L
-#define TCNT3L3_REG TCNT3L
-#define TCNT3L4_REG TCNT3L
-#define TCNT3L5_REG TCNT3L
-#define TCNT3L6_REG TCNT3L
-#define TCNT3L7_REG TCNT3L
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* USBCON */
-#define VBUSTE_REG USBCON
-#define IDTE_REG USBCON
-#define OTGPADE_REG USBCON
-#define FRZCLK_REG USBCON
-#define HOST_REG USBCON
-#define USBE_REG USBCON
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-#define JTRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* PCIFR */
-#define PCIF0_REG PCIFR
-
-/* TCCR2A */
-#define WGM20_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2B0_REG TCCR2A
-#define COM2B1_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-
-/* TCCR2B */
-#define CS20_REG TCCR2B
-#define CS21_REG TCCR2B
-#define CS22_REG TCCR2B
-#define WGM22_REG TCCR2B
-#define FOC2B_REG TCCR2B
-#define FOC2A_REG TCCR2B
-
-/* UECONX */
-#define EPEN_REG UECONX
-#define RSTDT_REG UECONX
-#define STALLRQC_REG UECONX
-#define STALLRQ_REG UECONX
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* MCUCR */
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-#define JTD_REG MCUCR
-
-/* OCR1CL */
-#define OCR1CL0_REG OCR1CL
-#define OCR1CL1_REG OCR1CL
-#define OCR1CL2_REG OCR1CL
-#define OCR1CL3_REG OCR1CL
-#define OCR1CL4_REG OCR1CL
-#define OCR1CL5_REG OCR1CL
-#define OCR1CL6_REG OCR1CL
-#define OCR1CL7_REG OCR1CL
-
-/* OCR1CH */
-#define OCR1CH0_REG OCR1CH
-#define OCR1CH1_REG OCR1CH
-#define OCR1CH2_REG OCR1CH
-#define OCR1CH3_REG OCR1CH
-#define OCR1CH4_REG OCR1CH
-#define OCR1CH5_REG OCR1CH
-#define OCR1CH6_REG OCR1CH
-#define OCR1CH7_REG OCR1CH
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* USBSTA */
-#define VBUS_REG USBSTA
-#define ID_REG USBSTA
-#define SPEED_REG USBSTA
-
-/* UEIENX */
-#define TXINE_REG UEIENX
-#define STALLEDE_REG UEIENX
-#define RXOUTE_REG UEIENX
-#define RXSTPE_REG UEIENX
-#define NAKOUTE_REG UEIENX
-#define NAKINE_REG UEIENX
-#define FLERRE_REG UEIENX
-
-/* UCSR1B */
-#define TXB81_REG UCSR1B
-#define RXB81_REG UCSR1B
-#define UCSZ12_REG UCSR1B
-#define TXEN1_REG UCSR1B
-#define RXEN1_REG UCSR1B
-#define UDRIE1_REG UCSR1B
-#define TXCIE1_REG UCSR1B
-#define RXCIE1_REG UCSR1B
-
-/* UCSR1C */
-#define UCPOL1_REG UCSR1C
-#define UCSZ10_REG UCSR1C
-#define UCSZ11_REG UCSR1C
-#define USBS1_REG UCSR1C
-#define UPM10_REG UCSR1C
-#define UPM11_REG UCSR1C
-#define UMSEL10_REG UCSR1C
-#define UMSEL11_REG UCSR1C
-
-/* UCSR1A */
-#define MPCM1_REG UCSR1A
-#define U2X1_REG UCSR1A
-#define UPE1_REG UCSR1A
-#define DOR1_REG UCSR1A
-#define FE1_REG UCSR1A
-#define UDRE1_REG UCSR1A
-#define TXC1_REG UCSR1A
-#define RXC1_REG UCSR1A
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* EIND */
-#define EIND0_REG EIND
-
-/* UDFNUML */
-#define UDFNUML_0_REG UDFNUML
-#define UDFNUML_1_REG UDFNUML
-#define UDFNUML_2_REG UDFNUML
-#define UDFNUML_3_REG UDFNUML
-#define UDFNUML_4_REG UDFNUML
-#define UDFNUML_5_REG UDFNUML
-#define UDFNUML_6_REG UDFNUML
-#define UDFNUML_7_REG UDFNUML
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* UDFNUMH */
-#define UDFNUMH_0_REG UDFNUMH
-#define UDFNUMH_1_REG UDFNUMH
-#define UDFNUMH_2_REG UDFNUMH
-
-/* TWAMR */
-#define TWAM0_REG TWAMR
-#define TWAM1_REG TWAMR
-#define TWAM2_REG TWAMR
-#define TWAM3_REG TWAMR
-#define TWAM4_REG TWAMR
-#define TWAM5_REG TWAMR
-#define TWAM6_REG TWAMR
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ADHSM_REG ADCSRB
-#define ACME_REG ADCSRB
-
-/* PRR0 */
-#define PRADC_REG PRR0
-#define PRSPI_REG PRR0
-#define PRTIM1_REG PRR0
-#define PRTIM0_REG PRR0
-#define PRTIM2_REG PRR0
-#define PRTWI_REG PRR0
-
-/* UBRR1H */
-#define UBRR_8_REG UBRR1H
-#define UBRR_9_REG UBRR1H
-#define UBRR_10_REG UBRR1H
-#define UBRR_11_REG UBRR1H
-
-/* OCR0A */
-#define OCROA_0_REG OCR0A
-#define OCROA_1_REG OCR0A
-#define OCROA_2_REG OCR0A
-#define OCROA_3_REG OCR0A
-#define OCROA_4_REG OCR0A
-#define OCROA_5_REG OCR0A
-#define OCROA_6_REG OCR0A
-#define OCROA_7_REG OCR0A
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* PORTF */
-#define PORTF0_REG PORTF
-#define PORTF1_REG PORTF
-#define PORTF2_REG PORTF
-#define PORTF3_REG PORTF
-#define PORTF4_REG PORTF
-#define PORTF5_REG PORTF
-#define PORTF6_REG PORTF
-#define PORTF7_REG PORTF
-
-/* TCCR1C */
-#define FOC1C_REG TCCR1C
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* ICR3H */
-#define ICR3H0_REG ICR3H
-#define ICR3H1_REG ICR3H
-#define ICR3H2_REG ICR3H
-#define ICR3H3_REG ICR3H
-#define ICR3H4_REG ICR3H
-#define ICR3H5_REG ICR3H
-#define ICR3H6_REG ICR3H
-#define ICR3H7_REG ICR3H
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-#define DDE3_REG DDRE
-#define DDE4_REG DDRE
-#define DDE5_REG DDRE
-#define DDE6_REG DDRE
-#define DDE7_REG DDRE
-
-/* UDADDR */
-#define UADD0_REG UDADDR
-#define UADD1_REG UDADDR
-#define UADD2_REG UDADDR
-#define UADD3_REG UDADDR
-#define UADD4_REG UDADDR
-#define UADD5_REG UDADDR
-#define UADD6_REG UDADDR
-#define ADDEN_REG UDADDR
-
-/* ICR3L */
-#define ICR3L0_REG ICR3L
-#define ICR3L1_REG ICR3L
-#define ICR3L2_REG ICR3L
-#define ICR3L3_REG ICR3L
-#define ICR3L4_REG ICR3L
-#define ICR3L5_REG ICR3L
-#define ICR3L6_REG ICR3L
-#define ICR3L7_REG ICR3L
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define SIGRD_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* UESTA0X */
-#define NBUSYBK0_REG UESTA0X
-#define NBUSYBK1_REG UESTA0X
-#define DTSEQ0_REG UESTA0X
-#define DTSEQ1_REG UESTA0X
-#define UNDERFI_REG UESTA0X
-#define OVERFI_REG UESTA0X
-#define CFGOK_REG UESTA0X
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* OCR3BL */
-#define OCR3BL0_REG OCR3BL
-#define OCR3BL1_REG OCR3BL
-#define OCR3BL2_REG OCR3BL
-#define OCR3BL3_REG OCR3BL
-#define OCR3BL4_REG OCR3BL
-#define OCR3BL5_REG OCR3BL
-#define OCR3BL6_REG OCR3BL
-#define OCR3BL7_REG OCR3BL
-
-/* OCR3BH */
-#define OCR3BH0_REG OCR3BH
-#define OCR3BH1_REG OCR3BH
-#define OCR3BH2_REG OCR3BH
-#define OCR3BH3_REG OCR3BH
-#define OCR3BH4_REG OCR3BH
-#define OCR3BH5_REG OCR3BH
-#define OCR3BH6_REG OCR3BH
-#define OCR3BH7_REG OCR3BH
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-#define OCIE2B_REG TIMSK2
-
-/* TIMSK3 */
-#define TOIE3_REG TIMSK3
-#define OCIE3A_REG TIMSK3
-#define OCIE3B_REG TIMSK3
-#define OCIE3C_REG TIMSK3
-#define ICIE3_REG TIMSK3
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define OCIE1C_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* PLLCSR */
-#define PLOCK_REG PLLCSR
-#define PLLE_REG PLLCSR
-#define PLLP0_REG PLLCSR
-#define PLLP1_REG PLLCSR
-#define PLLP2_REG PLLCSR
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* XMCRB */
-#define XMM0_REG XMCRB
-#define XMM1_REG XMCRB
-#define XMM2_REG XMCRB
-#define XMBK_REG XMCRB
-
-/* XMCRA */
-#define SRW00_REG XMCRA
-#define SRW01_REG XMCRA
-#define SRW10_REG XMCRA
-#define SRW11_REG XMCRA
-#define SRL0_REG XMCRA
-#define SRL1_REG XMCRA
-#define SRL2_REG XMCRA
-#define SRE_REG XMCRA
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-#define INTF2_REG EIFR
-#define INTF3_REG EIFR
-#define INTF4_REG EIFR
-#define INTF5_REG EIFR
-#define INTF6_REG EIFR
-#define INTF7_REG EIFR
-
-/* PINF */
-#define PINF0_REG PINF
-#define PINF1_REG PINF
-#define PINF2_REG PINF
-#define PINF3_REG PINF
-#define PINF4_REG PINF
-#define PINF5_REG PINF
-#define PINF6_REG PINF
-#define PINF7_REG PINF
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-#define PINE3_REG PINE
-#define PINE4_REG PINE
-#define PINE5_REG PINE
-#define PINE6_REG PINE
-#define PINE7_REG PINE
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* PRR1 */
-#define PRUSART1_REG PRR1
-#define PRTIM3_REG PRR1
-#define PRUSB_REG PRR1
-
-/* pins mapping */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-/* prescalers timer 3 */
-#define TIMER3_PRESCALER_DIV_0 0
-#define TIMER3_PRESCALER_DIV_1 1
-#define TIMER3_PRESCALER_DIV_8 2
-#define TIMER3_PRESCALER_DIV_64 3
-#define TIMER3_PRESCALER_DIV_256 4
-#define TIMER3_PRESCALER_DIV_1024 5
-#define TIMER3_PRESCALER_DIV_FALL 6
-#define TIMER3_PRESCALER_DIV_RISE 7
-
-#define TIMER3_PRESCALER_REG_0 0
-#define TIMER3_PRESCALER_REG_1 1
-#define TIMER3_PRESCALER_REG_2 8
-#define TIMER3_PRESCALER_REG_3 64
-#define TIMER3_PRESCALER_REG_4 256
-#define TIMER3_PRESCALER_REG_5 1024
-#define TIMER3_PRESCALER_REG_6 -1
-#define TIMER3_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER1C_AVAILABLE
-#define TIMER2_AVAILABLE
-#define TIMER2A_AVAILABLE
-#define TIMER2B_AVAILABLE
-#define TIMER3_AVAILABLE
-#define TIMER3A_AVAILABLE
-#define TIMER3B_AVAILABLE
-#define TIMER3C_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW3_NUM 3
-#define SIG_OVERFLOW_TOTAL_NUM 4
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE1C_NUM 4
-#define SIG_OUTPUT_COMPARE2A_NUM 5
-#define SIG_OUTPUT_COMPARE2B_NUM 6
-#define SIG_OUTPUT_COMPARE3A_NUM 7
-#define SIG_OUTPUT_COMPARE3B_NUM 8
-#define SIG_OUTPUT_COMPARE3C_NUM 9
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 10
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM1C_NUM 4
-#define PWM2A_NUM 5
-#define PWM2B_NUM 6
-#define PWM3A_NUM 7
-#define PWM3B_NUM 8
-#define PWM3C_NUM 9
-#define PWM_TOTAL_NUM 10
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE3_NUM 1
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 2
-
-
-/* UEBCHX */
-#define UEBCHX_0_REG UEBCHX
-#define UEBCHX_1_REG UEBCHX
-#define UEBCHX_2_REG UEBCHX
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* UDIEN */
-#define SUSPE_REG UDIEN
-#define SOFE_REG UDIEN
-#define EORSTE_REG UDIEN
-#define WAKEUPE_REG UDIEN
-#define EORSME_REG UDIEN
-#define UPRSME_REG UDIEN
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* OCR0B */
-#define OCR0B_0_REG OCR0B
-#define OCR0B_1_REG OCR0B
-#define OCR0B_2_REG OCR0B
-#define OCR0B_3_REG OCR0B
-#define OCR0B_4_REG OCR0B
-#define OCR0B_5_REG OCR0B
-#define OCR0B_6_REG OCR0B
-#define OCR0B_7_REG OCR0B
-
-/* UPIENX */
-#define RXINE_REG UPIENX
-#define RXSTALLE_REG UPIENX
-#define TXOUTE_REG UPIENX
-#define TXSTPE_REG UPIENX
-#define PERRE_REG UPIENX
-#define NAKEDE_REG UPIENX
-/* #define FLERRE_REG UPIENX */ /* dup in UEIENX */
-
-/* UDINT */
-#define SUSPI_REG UDINT
-#define SOFI_REG UDINT
-#define EORSTI_REG UDINT
-#define WAKEUPI_REG UDINT
-#define EORSMI_REG UDINT
-#define UPRSMI_REG UDINT
-
-/* UERST */
-#define EPRST0_REG UERST
-#define EPRST1_REG UERST
-#define EPRST2_REG UERST
-#define EPRST3_REG UERST
-#define EPRST4_REG UERST
-#define EPRST5_REG UERST
-#define EPRST6_REG UERST
-
-/* RAMPZ */
-#define RAMPZ0_REG RAMPZ
-
-/* UECFG1X */
-/* #define ALLOC_REG UECFG1X */ /* dup in UPCFG1X */
-#define EPBK0_REG UECFG1X
-#define EPBK1_REG UECFG1X
-#define EPSIZE0_REG UECFG1X
-#define EPSIZE1_REG UECFG1X
-#define EPSIZE2_REG UECFG1X
-
-/* UECONX */
-#define EPEN_REG UECONX
-/* #define RSTDT_REG UECONX */ /* dup in UPCONX */
-#define STALLRQC_REG UECONX
-#define STALLRQ_REG UECONX
-
-/* OCR2A */
-#define OCR2A_0_REG OCR2A
-#define OCR2A_1_REG OCR2A
-#define OCR2A_2_REG OCR2A
-#define OCR2A_3_REG OCR2A
-#define OCR2A_4_REG OCR2A
-#define OCR2A_5_REG OCR2A
-#define OCR2A_6_REG OCR2A
-#define OCR2A_7_REG OCR2A
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* OTGIEN */
-#define SRPE_REG OTGIEN
-#define VBERRE_REG OTGIEN
-#define BCERRE_REG OTGIEN
-#define ROLEEXE_REG OTGIEN
-#define HNPERRE_REG OTGIEN
-#define STOE_REG OTGIEN
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* UEINT */
-#define EPINT0_REG UEINT
-#define EPINT1_REG UEINT
-#define EPINT2_REG UEINT
-#define EPINT3_REG UEINT
-#define EPINT4_REG UEINT
-#define EPINT5_REG UEINT
-#define EPINT6_REG UEINT
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* OTGTCON */
-#define VALUE_20_REG OTGTCON
-#define VALUE_21_REG OTGTCON
-#define VALUE_22_REG OTGTCON
-#define PAGE0_REG OTGTCON
-#define PAGE1_REG OTGTCON
-#define OTGTCON_7_REG OTGTCON
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* UPBCHX */
-#define PBYCT8_REG UPBCHX
-#define PBYCT9_REG UPBCHX
-#define PBYCT10_REG UPBCHX
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-#define INT3_REG EIMSK
-#define INT4_REG EIMSK
-#define INT5_REG EIMSK
-#define INT6_REG EIMSK
-#define INT7_REG EIMSK
-
-/* UDR1 */
-#define UDR1_0_REG UDR1
-#define UDR1_1_REG UDR1
-#define UDR1_2_REG UDR1
-#define UDR1_3_REG UDR1
-#define UDR1_4_REG UDR1
-#define UDR1_5_REG UDR1
-#define UDR1_6_REG UDR1
-#define UDR1_7_REG UDR1
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* EICRB */
-#define ISC40_REG EICRB
-#define ISC41_REG EICRB
-#define ISC50_REG EICRB
-#define ISC51_REG EICRB
-#define ISC60_REG EICRB
-#define ISC61_REG EICRB
-#define ISC70_REG EICRB
-#define ISC71_REG EICRB
-
-/* UEDATX */
-#define UEDATX_0_REG UEDATX
-#define UEDATX_1_REG UEDATX
-#define UEDATX_2_REG UEDATX
-#define UEDATX_3_REG UEDATX
-#define UEDATX_4_REG UEDATX
-#define UEDATX_5_REG UEDATX
-#define UEDATX_6_REG UEDATX
-#define UEDATX_7_REG UEDATX
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-#define ISC20_REG EICRA
-#define ISC21_REG EICRA
-#define ISC30_REG EICRA
-#define ISC31_REG EICRA
-
-/* OTGINT */
-#define SRPI_REG OTGINT
-#define VBERRI_REG OTGINT
-#define BCERRI_REG OTGINT
-#define ROLEEXI_REG OTGINT
-#define HNPERRI_REG OTGINT
-#define STOI_REG OTGINT
-
-/* UECFG0X */
-#define EPDIR_REG UECFG0X
-#define EPTYPE0_REG UECFG0X
-#define EPTYPE1_REG UECFG0X
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* DDRF */
-#define DDF0_REG DDRF
-#define DDF1_REG DDRF
-#define DDF2_REG DDRF
-#define DDF3_REG DDRF
-#define DDF4_REG DDRF
-#define DDF5_REG DDRF
-#define DDF6_REG DDRF
-#define DDF7_REG DDRF
-
-/* ASSR */
-#define TCR2BUB_REG ASSR
-#define TCR2AUB_REG ASSR
-#define OCR2BUB_REG ASSR
-#define OCR2AUB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* UHIEN */
-#define DCONNE_REG UHIEN
-#define DDISCE_REG UHIEN
-#define RSTE_REG UHIEN
-#define RSMEDE_REG UHIEN
-#define RXRSME_REG UHIEN
-#define HSOFE_REG UHIEN
-#define HWUPE_REG UHIEN
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* UENUM */
-#define UENUM_0_REG UENUM
-#define UENUM_1_REG UENUM
-#define UENUM_2_REG UENUM
-
-/* UBRR1L */
-#define UBRR_0_REG UBRR1L
-#define UBRR_1_REG UBRR1L
-#define UBRR_2_REG UBRR1L
-#define UBRR_3_REG UBRR1L
-#define UBRR_4_REG UBRR1L
-#define UBRR_5_REG UBRR1L
-#define UBRR_6_REG UBRR1L
-#define UBRR_7_REG UBRR1L
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* OCR3AL */
-#define OCR3AL0_REG OCR3AL
-#define OCR3AL1_REG OCR3AL
-#define OCR3AL2_REG OCR3AL
-#define OCR3AL3_REG OCR3AL
-#define OCR3AL4_REG OCR3AL
-#define OCR3AL5_REG OCR3AL
-#define OCR3AL6_REG OCR3AL
-#define OCR3AL7_REG OCR3AL
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* UBRR1H */
-#define UBRR_8_REG UBRR1H
-#define UBRR_9_REG UBRR1H
-#define UBRR_10_REG UBRR1H
-#define UBRR_11_REG UBRR1H
-
-/* OCR3AH */
-#define OCR3AH0_REG OCR3AH
-#define OCR3AH1_REG OCR3AH
-#define OCR3AH2_REG OCR3AH
-#define OCR3AH3_REG OCR3AH
-#define OCR3AH4_REG OCR3AH
-#define OCR3AH5_REG OCR3AH
-#define OCR3AH6_REG OCR3AH
-#define OCR3AH7_REG OCR3AH
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* UHADDR */
-#define UHADDR_0_REG UHADDR
-#define UHADDR_1_REG UHADDR
-#define UHADDR_2_REG UHADDR
-#define UHADDR_3_REG UHADDR
-#define UHADDR_4_REG UHADDR
-#define UHADDR_5_REG UHADDR
-#define UHADDR_6_REG UHADDR
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* UDCON */
-#define DETACH_REG UDCON
-#define RMWKUP_REG UDCON
-#define LSM_REG UDCON
-
-/* UHFLEN */
-#define UHFLEN_0_REG UHFLEN
-#define UHFLEN_1_REG UHFLEN
-#define UHFLEN_2_REG UHFLEN
-#define UHFLEN_3_REG UHFLEN
-#define UHFLEN_4_REG UHFLEN
-#define UHFLEN_5_REG UHFLEN
-#define UHFLEN_6_REG UHFLEN
-#define UHFLEN_7_REG UHFLEN
-
-/* UHFNUMH */
-#define UHFNUMH_0_REG UHFNUMH
-#define UHFNUMH_1_REG UHFNUMH
-#define UHFNUMH_2_REG UHFNUMH
-
-/* UHFNUML */
-#define UHFNUML_0_REG UHFNUML
-#define UHFNUML_1_REG UHFNUML
-#define UHFNUML_2_REG UHFNUML
-#define UHFNUML_3_REG UHFNUML
-#define UHFNUML_4_REG UHFNUML
-#define UHFNUML_5_REG UHFNUML
-#define UHFNUML_6_REG UHFNUML
-#define UHFNUML_7_REG UHFNUML
-
-/* PCICR */
-#define PCIE0_REG PCICR
-
-/* USBINT */
-#define VBUSTI_REG USBINT
-#define IDTI_REG USBINT
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* UHWCON */
-#define UVREGE_REG UHWCON
-#define UVCONE_REG UHWCON
-#define UIDE_REG UHWCON
-#define UIMOD_REG UHWCON
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* UDMFN */
-#define FNCERR_REG UDMFN
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* UPDATX */
-#define PDAT0_REG UPDATX
-#define PDAT1_REG UPDATX
-#define PDAT2_REG UPDATX
-#define PDAT3_REG UPDATX
-#define PDAT4_REG UPDATX
-#define PDAT5_REG UPDATX
-#define PDAT6_REG UPDATX
-#define PDAT7_REG UPDATX
-
-/* OCR2B */
-#define OCR2B_0_REG OCR2B
-#define OCR2B_1_REG OCR2B
-#define OCR2B_2_REG OCR2B
-#define OCR2B_3_REG OCR2B
-#define OCR2B_4_REG OCR2B
-#define OCR2B_5_REG OCR2B
-#define OCR2B_6_REG OCR2B
-#define OCR2B_7_REG OCR2B
-
-/* UHCON */
-#define SOFEN_REG UHCON
-#define RESET_REG UHCON
-#define RESUME_REG UHCON
-
-/* TIFR3 */
-#define TOV3_REG TIFR3
-#define OCF3A_REG TIFR3
-#define OCF3B_REG TIFR3
-#define OCF3C_REG TIFR3
-#define ICF3_REG TIFR3
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define OCF1C_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-#define EEAR10_REG EEARH
-#define EEAR11_REG EEARH
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* UPINT */
-#define PINT0_REG UPINT
-#define PINT1_REG UPINT
-#define PINT2_REG UPINT
-#define PINT3_REG UPINT
-#define PINT4_REG UPINT
-#define PINT5_REG UPINT
-#define PINT6_REG UPINT
-
-/* UEBCLX */
-#define UEBCLX_0_REG UEBCLX
-#define UEBCLX_1_REG UEBCLX
-#define UEBCLX_2_REG UEBCLX
-#define UEBCLX_3_REG UEBCLX
-#define UEBCLX_4_REG UEBCLX
-#define UEBCLX_5_REG UEBCLX
-#define UEBCLX_6_REG UEBCLX
-#define UEBCLX_7_REG UEBCLX
-
-/* OCR3CH */
-#define OCR3CH0_REG OCR3CH
-#define OCR3CH1_REG OCR3CH
-#define OCR3CH2_REG OCR3CH
-#define OCR3CH3_REG OCR3CH
-#define OCR3CH4_REG OCR3CH
-#define OCR3CH5_REG OCR3CH
-#define OCR3CH6_REG OCR3CH
-#define OCR3CH7_REG OCR3CH
-
-/* UESTA1X */
-#define CURRBK0_REG UESTA1X
-#define CURRBK1_REG UESTA1X
-#define CTRLDIR_REG UESTA1X
-
-/* OCR3CL */
-#define OCR3CL0_REG OCR3CL
-#define OCR3CL1_REG OCR3CL
-#define OCR3CL2_REG OCR3CL
-#define OCR3CL3_REG OCR3CL
-#define OCR3CL4_REG OCR3CL
-#define OCR3CL5_REG OCR3CL
-#define OCR3CL6_REG OCR3CL
-#define OCR3CL7_REG OCR3CL
-
-/* GTCCR */
-#define PSRSYNC_REG GTCCR
-#define TSM_REG GTCCR
-#define PSRASY_REG GTCCR
-
-/* UPSTAX */
-#define NBUSYK0_REG UPSTAX
-#define NBUSYK1_REG UPSTAX
-/* #define DTSEQ0_REG UPSTAX */ /* dup in UESTA0X */
-/* #define DTSEQ1_REG UPSTAX */ /* dup in UESTA0X */
-/* #define UNDERFI_REG UPSTAX */ /* dup in UESTA0X */
-/* #define OVERFI_REG UPSTAX */ /* dup in UESTA0X */
-/* #define CFGOK_REG UPSTAX */ /* dup in UESTA0X */
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* TCCR3C */
-#define FOC3C_REG TCCR3C
-#define FOC3B_REG TCCR3C
-#define FOC3A_REG TCCR3C
-
-/* TCCR3B */
-#define CS30_REG TCCR3B
-#define CS31_REG TCCR3B
-#define CS32_REG TCCR3B
-#define WGM32_REG TCCR3B
-#define WGM33_REG TCCR3B
-#define ICES3_REG TCCR3B
-#define ICNC3_REG TCCR3B
-
-/* TCCR3A */
-#define WGM30_REG TCCR3A
-#define WGM31_REG TCCR3A
-#define COM3C0_REG TCCR3A
-#define COM3C1_REG TCCR3A
-#define COM3B0_REG TCCR3A
-#define COM3B1_REG TCCR3A
-#define COM3A0_REG TCCR3A
-#define COM3A1_REG TCCR3A
-
-/* UEINTX */
-#define TXINI_REG UEINTX
-#define STALLEDI_REG UEINTX
-#define RXOUTI_REG UEINTX
-#define RXSTPI_REG UEINTX
-#define NAKOUTI_REG UEINTX
-/* #define RWAL_REG UEINTX */ /* dup in UPINTX */
-#define NAKINI_REG UEINTX
-/* #define FIFOCON_REG UEINTX */ /* dup in UPINTX */
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* TCNT3H */
-#define TCNT3H0_REG TCNT3H
-#define TCNT3H1_REG TCNT3H
-#define TCNT3H2_REG TCNT3H
-#define TCNT3H3_REG TCNT3H
-#define TCNT3H4_REG TCNT3H
-#define TCNT3H5_REG TCNT3H
-#define TCNT3H6_REG TCNT3H
-#define TCNT3H7_REG TCNT3H
-
-/* UPCFG0X */
-#define PEPNUM0_REG UPCFG0X
-#define PEPNUM1_REG UPCFG0X
-#define PEPNUM2_REG UPCFG0X
-#define PEPNUM3_REG UPCFG0X
-#define PTOKEN0_REG UPCFG0X
-#define PTOKEN1_REG UPCFG0X
-#define PTYPE0_REG UPCFG0X
-#define PTYPE1_REG UPCFG0X
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* TCNT3L */
-#define TCNT3L0_REG TCNT3L
-#define TCNT3L1_REG TCNT3L
-#define TCNT3L2_REG TCNT3L
-#define TCNT3L3_REG TCNT3L
-#define TCNT3L4_REG TCNT3L
-#define TCNT3L5_REG TCNT3L
-#define TCNT3L6_REG TCNT3L
-#define TCNT3L7_REG TCNT3L
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* UPERRX */
-#define DATATGL_REG UPERRX
-#define DATAPID_REG UPERRX
-#define PID_REG UPERRX
-#define TIMEOUT_REG UPERRX
-#define CRC16_REG UPERRX
-#define COUNTER0_REG UPERRX
-#define COUNTER1_REG UPERRX
-
-/* USBCON */
-#define VBUSTE_REG USBCON
-#define IDTE_REG USBCON
-#define OTGPADE_REG USBCON
-#define FRZCLK_REG USBCON
-#define HOST_REG USBCON
-#define USBE_REG USBCON
-
-/* UPCONX */
-#define PEN_REG UPCONX
-/* #define RSTDT_REG UPCONX */ /* dup in UECONX */
-#define INMODE_REG UPCONX
-#define PFREEZE_REG UPCONX
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-#define JTRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* UPBCLX */
-#define PBYCT0_REG UPBCLX
-#define PBYCT1_REG UPBCLX
-#define PBYCT2_REG UPBCLX
-#define PBYCT3_REG UPBCLX
-#define PBYCT4_REG UPBCLX
-#define PBYCT5_REG UPBCLX
-#define PBYCT6_REG UPBCLX
-#define PBYCT7_REG UPBCLX
-
-/* UHINT */
-#define DCONNI_REG UHINT
-#define DDISCI_REG UHINT
-#define RSTI_REG UHINT
-#define RSMEDI_REG UHINT
-#define RXRSMI_REG UHINT
-#define HSOFI_REG UHINT
-#define UHUPI_REG UHINT
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* PCIFR */
-#define PCIF0_REG PCIFR
-
-/* TCCR2A */
-#define WGM20_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2B0_REG TCCR2A
-#define COM2B1_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-
-/* TCCR2B */
-#define CS20_REG TCCR2B
-#define CS21_REG TCCR2B
-#define CS22_REG TCCR2B
-#define WGM22_REG TCCR2B
-#define FOC2B_REG TCCR2B
-#define FOC2A_REG TCCR2B
-
-/* UPNUM */
-#define PNUM0_REG UPNUM
-#define PNUM1_REG UPNUM
-#define PNUM2_REG UPNUM
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* MCUCR */
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-#define JTD_REG MCUCR
-
-/* OCR1CL */
-#define OCR1CL0_REG OCR1CL
-#define OCR1CL1_REG OCR1CL
-#define OCR1CL2_REG OCR1CL
-#define OCR1CL3_REG OCR1CL
-#define OCR1CL4_REG OCR1CL
-#define OCR1CL5_REG OCR1CL
-#define OCR1CL6_REG OCR1CL
-#define OCR1CL7_REG OCR1CL
-
-/* OCR1CH */
-#define OCR1CH0_REG OCR1CH
-#define OCR1CH1_REG OCR1CH
-#define OCR1CH2_REG OCR1CH
-#define OCR1CH3_REG OCR1CH
-#define OCR1CH4_REG OCR1CH
-#define OCR1CH5_REG OCR1CH
-#define OCR1CH6_REG OCR1CH
-#define OCR1CH7_REG OCR1CH
-
-/* UPCFG1X */
-/* #define ALLOC_REG UPCFG1X */ /* dup in UECFG1X */
-#define PBK0_REG UPCFG1X
-#define PBK1_REG UPCFG1X
-#define PSIZE0_REG UPCFG1X
-#define PSIZE1_REG UPCFG1X
-#define PSIZE2_REG UPCFG1X
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* USBSTA */
-#define VBUS_REG USBSTA
-#define ID_REG USBSTA
-#define SPEED_REG USBSTA
-
-/* UEIENX */
-#define TXINE_REG UEIENX
-#define STALLEDE_REG UEIENX
-#define RXOUTE_REG UEIENX
-#define RXSTPE_REG UEIENX
-#define NAKOUTE_REG UEIENX
-#define NAKINE_REG UEIENX
-/* #define FLERRE_REG UEIENX */ /* dup in UPIENX */
-
-/* OTGCON */
-#define VBUSRQC_REG OTGCON
-#define VBUSREQ_REG OTGCON
-#define VBUSHWC_REG OTGCON
-#define SRPSEL_REG OTGCON
-#define SRPREQ_REG OTGCON
-#define HNPREQ_REG OTGCON
-
-/* UCSR1B */
-#define TXB81_REG UCSR1B
-#define RXB81_REG UCSR1B
-#define UCSZ12_REG UCSR1B
-#define TXEN1_REG UCSR1B
-#define RXEN1_REG UCSR1B
-#define UDRIE1_REG UCSR1B
-#define TXCIE1_REG UCSR1B
-#define RXCIE1_REG UCSR1B
-
-/* UCSR1C */
-#define UCPOL1_REG UCSR1C
-#define UCSZ10_REG UCSR1C
-#define UCSZ11_REG UCSR1C
-#define USBS1_REG UCSR1C
-#define UPM10_REG UCSR1C
-#define UPM11_REG UCSR1C
-#define UMSEL10_REG UCSR1C
-#define UMSEL11_REG UCSR1C
-
-/* UCSR1A */
-#define MPCM1_REG UCSR1A
-#define U2X1_REG UCSR1A
-#define UPE1_REG UCSR1A
-#define DOR1_REG UCSR1A
-#define FE1_REG UCSR1A
-#define UDRE1_REG UCSR1A
-#define TXC1_REG UCSR1A
-#define RXC1_REG UCSR1A
-
-/* UPINRQX */
-#define INRQ0_REG UPINRQX
-#define INRQ1_REG UPINRQX
-#define INRQ2_REG UPINRQX
-#define INRQ3_REG UPINRQX
-#define INRQ4_REG UPINRQX
-#define INRQ5_REG UPINRQX
-#define INRQ6_REG UPINRQX
-#define INRQ7_REG UPINRQX
-
-/* EIND */
-#define EIND0_REG EIND
-
-/* UDFNUML */
-#define UDFNUML_0_REG UDFNUML
-#define UDFNUML_1_REG UDFNUML
-#define UDFNUML_2_REG UDFNUML
-#define UDFNUML_3_REG UDFNUML
-#define UDFNUML_4_REG UDFNUML
-#define UDFNUML_5_REG UDFNUML
-#define UDFNUML_6_REG UDFNUML
-#define UDFNUML_7_REG UDFNUML
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* UDFNUMH */
-#define UDFNUMH_0_REG UDFNUMH
-#define UDFNUMH_1_REG UDFNUMH
-#define UDFNUMH_2_REG UDFNUMH
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ADHSM_REG ADCSRB
-#define ACME_REG ADCSRB
-
-/* UPINTX */
-#define RXINI_REG UPINTX
-#define RXSTALLI_REG UPINTX
-#define TXOUTI_REG UPINTX
-#define TXSTPI_REG UPINTX
-#define PERRI_REG UPINTX
-/* #define RWAL_REG UPINTX */ /* dup in UEINTX */
-#define NAKEDI_REG UPINTX
-/* #define FIFOCON_REG UPINTX */ /* dup in UEINTX */
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1C0_REG TCCR1A
-#define COM1C1_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* OCR0A */
-#define OCROA_0_REG OCR0A
-#define OCROA_1_REG OCR0A
-#define OCROA_2_REG OCR0A
-#define OCROA_3_REG OCR0A
-#define OCROA_4_REG OCR0A
-#define OCROA_5_REG OCR0A
-#define OCROA_6_REG OCR0A
-#define OCROA_7_REG OCR0A
-
-/* UPCFG2X */
-#define UPCFG2X_0_REG UPCFG2X
-#define UPCFG2X_1_REG UPCFG2X
-#define UPCFG2X_2_REG UPCFG2X
-#define UPCFG2X_3_REG UPCFG2X
-#define UPCFG2X_4_REG UPCFG2X
-#define UPCFG2X_5_REG UPCFG2X
-#define UPCFG2X_6_REG UPCFG2X
-#define UPCFG2X_7_REG UPCFG2X
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* PORTF */
-#define PORTF0_REG PORTF
-#define PORTF1_REG PORTF
-#define PORTF2_REG PORTF
-#define PORTF3_REG PORTF
-#define PORTF4_REG PORTF
-#define PORTF5_REG PORTF
-#define PORTF6_REG PORTF
-#define PORTF7_REG PORTF
-
-/* TCCR1C */
-#define FOC1C_REG TCCR1C
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* ICR3H */
-#define ICR3H0_REG ICR3H
-#define ICR3H1_REG ICR3H
-#define ICR3H2_REG ICR3H
-#define ICR3H3_REG ICR3H
-#define ICR3H4_REG ICR3H
-#define ICR3H5_REG ICR3H
-#define ICR3H6_REG ICR3H
-#define ICR3H7_REG ICR3H
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-#define DDE3_REG DDRE
-#define DDE4_REG DDRE
-#define DDE5_REG DDRE
-#define DDE6_REG DDRE
-#define DDE7_REG DDRE
-
-/* UDADDR */
-#define UADD0_REG UDADDR
-#define UADD1_REG UDADDR
-#define UADD2_REG UDADDR
-#define UADD3_REG UDADDR
-#define UADD4_REG UDADDR
-#define UADD5_REG UDADDR
-#define UADD6_REG UDADDR
-#define ADDEN_REG UDADDR
-
-/* ICR3L */
-#define ICR3L0_REG ICR3L
-#define ICR3L1_REG ICR3L
-#define ICR3L2_REG ICR3L
-#define ICR3L3_REG ICR3L
-#define ICR3L4_REG ICR3L
-#define ICR3L5_REG ICR3L
-#define ICR3L6_REG ICR3L
-#define ICR3L7_REG ICR3L
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-#define PORTE3_REG PORTE
-#define PORTE4_REG PORTE
-#define PORTE5_REG PORTE
-#define PORTE6_REG PORTE
-#define PORTE7_REG PORTE
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define SIGRD_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* UESTA0X */
-#define NBUSYBK0_REG UESTA0X
-#define NBUSYBK1_REG UESTA0X
-/* #define DTSEQ0_REG UESTA0X */ /* dup in UPSTAX */
-/* #define DTSEQ1_REG UESTA0X */ /* dup in UPSTAX */
-/* #define UNDERFI_REG UESTA0X */ /* dup in UPSTAX */
-/* #define OVERFI_REG UESTA0X */ /* dup in UPSTAX */
-/* #define CFGOK_REG UESTA0X */ /* dup in UPSTAX */
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* OCR3BL */
-#define OCR3BL0_REG OCR3BL
-#define OCR3BL1_REG OCR3BL
-#define OCR3BL2_REG OCR3BL
-#define OCR3BL3_REG OCR3BL
-#define OCR3BL4_REG OCR3BL
-#define OCR3BL5_REG OCR3BL
-#define OCR3BL6_REG OCR3BL
-#define OCR3BL7_REG OCR3BL
-
-/* OCR3BH */
-#define OCR3BH0_REG OCR3BH
-#define OCR3BH1_REG OCR3BH
-#define OCR3BH2_REG OCR3BH
-#define OCR3BH3_REG OCR3BH
-#define OCR3BH4_REG OCR3BH
-#define OCR3BH5_REG OCR3BH
-#define OCR3BH6_REG OCR3BH
-#define OCR3BH7_REG OCR3BH
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-#define OCIE2B_REG TIMSK2
-
-/* TIMSK3 */
-#define TOIE3_REG TIMSK3
-#define OCIE3A_REG TIMSK3
-#define OCIE3B_REG TIMSK3
-#define OCIE3C_REG TIMSK3
-#define ICIE3_REG TIMSK3
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define OCIE1C_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* PLLCSR */
-#define PLOCK_REG PLLCSR
-#define PLLE_REG PLLCSR
-#define PLLP0_REG PLLCSR
-#define PLLP1_REG PLLCSR
-#define PLLP2_REG PLLCSR
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* XMCRB */
-#define XMM0_REG XMCRB
-#define XMM1_REG XMCRB
-#define XMM2_REG XMCRB
-#define XMBK_REG XMCRB
-
-/* XMCRA */
-#define SRW00_REG XMCRA
-#define SRW01_REG XMCRA
-#define SRW10_REG XMCRA
-#define SRW11_REG XMCRA
-#define SRL0_REG XMCRA
-#define SRL1_REG XMCRA
-#define SRL2_REG XMCRA
-#define SRE_REG XMCRA
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-#define OCF2B_REG TIFR2
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-#define INTF2_REG EIFR
-#define INTF3_REG EIFR
-#define INTF4_REG EIFR
-#define INTF5_REG EIFR
-#define INTF6_REG EIFR
-#define INTF7_REG EIFR
-
-/* PINF */
-#define PINF0_REG PINF
-#define PINF1_REG PINF
-#define PINF2_REG PINF
-#define PINF3_REG PINF
-#define PINF4_REG PINF
-#define PINF5_REG PINF
-#define PINF6_REG PINF
-#define PINF7_REG PINF
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-#define PINE3_REG PINE
-#define PINE4_REG PINE
-#define PINE5_REG PINE
-#define PINE6_REG PINE
-#define PINE7_REG PINE
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* TWAMR */
-#define TWAM0_REG TWAMR
-#define TWAM1_REG TWAMR
-#define TWAM2_REG TWAMR
-#define TWAM3_REG TWAMR
-#define TWAM4_REG TWAMR
-#define TWAM5_REG TWAMR
-#define TWAM6_REG TWAMR
-
-/* PRR0 */
-#define PRADC_REG PRR0
-#define PRSPI_REG PRR0
-#define PRTIM1_REG PRR0
-#define PRTIM0_REG PRR0
-#define PRTIM2_REG PRR0
-#define PRTWI_REG PRR0
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* PRR1 */
-#define PRUSART1_REG PRR1
-#define PRTIM3_REG PRR1
-#define PRUSB_REG PRR1
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* UPRST */
-#define PRST0_REG UPRST
-#define PRST1_REG UPRST
-#define PRST2_REG UPRST
-#define PRST3_REG UPRST
-#define PRST4_REG UPRST
-#define PRST5_REG UPRST
-#define PRST6_REG UPRST
-
-/* pins mapping */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-/* prescalers timer 3 */
-#define TIMER3_PRESCALER_DIV_0 0
-#define TIMER3_PRESCALER_DIV_1 1
-#define TIMER3_PRESCALER_DIV_8 2
-#define TIMER3_PRESCALER_DIV_64 3
-#define TIMER3_PRESCALER_DIV_256 4
-#define TIMER3_PRESCALER_DIV_1024 5
-#define TIMER3_PRESCALER_DIV_FALL 6
-#define TIMER3_PRESCALER_DIV_RISE 7
-
-#define TIMER3_PRESCALER_REG_0 0
-#define TIMER3_PRESCALER_REG_1 1
-#define TIMER3_PRESCALER_REG_2 8
-#define TIMER3_PRESCALER_REG_3 64
-#define TIMER3_PRESCALER_REG_4 256
-#define TIMER3_PRESCALER_REG_5 1024
-#define TIMER3_PRESCALER_REG_6 -1
-#define TIMER3_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER1C_AVAILABLE
-#define TIMER2_AVAILABLE
-#define TIMER2A_AVAILABLE
-#define TIMER2B_AVAILABLE
-#define TIMER3_AVAILABLE
-#define TIMER3A_AVAILABLE
-#define TIMER3B_AVAILABLE
-#define TIMER3C_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW3_NUM 3
-#define SIG_OVERFLOW_TOTAL_NUM 4
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE1C_NUM 4
-#define SIG_OUTPUT_COMPARE2A_NUM 5
-#define SIG_OUTPUT_COMPARE2B_NUM 6
-#define SIG_OUTPUT_COMPARE3A_NUM 7
-#define SIG_OUTPUT_COMPARE3B_NUM 8
-#define SIG_OUTPUT_COMPARE3C_NUM 9
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 10
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM1C_NUM 4
-#define PWM2A_NUM 5
-#define PWM2B_NUM 6
-#define PWM3A_NUM 7
-#define PWM3B_NUM 8
-#define PWM3C_NUM 9
-#define PWM_TOTAL_NUM 10
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE3_NUM 1
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 2
-
-
-/* UEBCHX */
-#define UEBCHX_0_REG UEBCHX
-#define UEBCHX_1_REG UEBCHX
-#define UEBCHX_2_REG UEBCHX
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* UDIEN */
-#define SUSPE_REG UDIEN
-#define SOFE_REG UDIEN
-#define EORSTE_REG UDIEN
-#define WAKEUPE_REG UDIEN
-#define EORSME_REG UDIEN
-#define UPRSME_REG UDIEN
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* OCR0B */
-#define OCR0B_0_REG OCR0B
-#define OCR0B_1_REG OCR0B
-#define OCR0B_2_REG OCR0B
-#define OCR0B_3_REG OCR0B
-#define OCR0B_4_REG OCR0B
-#define OCR0B_5_REG OCR0B
-#define OCR0B_6_REG OCR0B
-#define OCR0B_7_REG OCR0B
-
-/* UPIENX */
-#define RXINE_REG UPIENX
-#define RXSTALLE_REG UPIENX
-#define TXOUTE_REG UPIENX
-#define TXSTPE_REG UPIENX
-#define PERRE_REG UPIENX
-#define NAKEDE_REG UPIENX
-/* #define FLERRE_REG UPIENX */ /* dup in UEIENX */
-
-/* UDINT */
-#define SUSPI_REG UDINT
-#define SOFI_REG UDINT
-#define EORSTI_REG UDINT
-#define WAKEUPI_REG UDINT
-#define EORSMI_REG UDINT
-#define UPRSMI_REG UDINT
-
-/* UERST */
-#define EPRST0_REG UERST
-#define EPRST1_REG UERST
-#define EPRST2_REG UERST
-#define EPRST3_REG UERST
-#define EPRST4_REG UERST
-#define EPRST5_REG UERST
-#define EPRST6_REG UERST
-
-/* RAMPZ */
-#define RAMPZ0_REG RAMPZ
-
-/* UECFG1X */
-/* #define ALLOC_REG UECFG1X */ /* dup in UPCFG1X */
-#define EPBK0_REG UECFG1X
-#define EPBK1_REG UECFG1X
-#define EPSIZE0_REG UECFG1X
-#define EPSIZE1_REG UECFG1X
-#define EPSIZE2_REG UECFG1X
-
-/* UECONX */
-#define EPEN_REG UECONX
-/* #define RSTDT_REG UECONX */ /* dup in UPCONX */
-#define STALLRQC_REG UECONX
-#define STALLRQ_REG UECONX
-
-/* OCR2A */
-#define OCR2A_0_REG OCR2A
-#define OCR2A_1_REG OCR2A
-#define OCR2A_2_REG OCR2A
-#define OCR2A_3_REG OCR2A
-#define OCR2A_4_REG OCR2A
-#define OCR2A_5_REG OCR2A
-#define OCR2A_6_REG OCR2A
-#define OCR2A_7_REG OCR2A
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* OTGIEN */
-#define SRPE_REG OTGIEN
-#define VBERRE_REG OTGIEN
-#define BCERRE_REG OTGIEN
-#define ROLEEXE_REG OTGIEN
-#define HNPERRE_REG OTGIEN
-#define STOE_REG OTGIEN
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* UEINT */
-#define EPINT0_REG UEINT
-#define EPINT1_REG UEINT
-#define EPINT2_REG UEINT
-#define EPINT3_REG UEINT
-#define EPINT4_REG UEINT
-#define EPINT5_REG UEINT
-#define EPINT6_REG UEINT
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* OTGTCON */
-#define VALUE_20_REG OTGTCON
-#define VALUE_21_REG OTGTCON
-#define VALUE_22_REG OTGTCON
-#define PAGE0_REG OTGTCON
-#define PAGE1_REG OTGTCON
-#define OTGTCON_7_REG OTGTCON
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* UPBCHX */
-#define PBYCT8_REG UPBCHX
-#define PBYCT9_REG UPBCHX
-#define PBYCT10_REG UPBCHX
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-#define INT3_REG EIMSK
-#define INT4_REG EIMSK
-#define INT5_REG EIMSK
-#define INT6_REG EIMSK
-#define INT7_REG EIMSK
-
-/* UDR1 */
-#define UDR1_0_REG UDR1
-#define UDR1_1_REG UDR1
-#define UDR1_2_REG UDR1
-#define UDR1_3_REG UDR1
-#define UDR1_4_REG UDR1
-#define UDR1_5_REG UDR1
-#define UDR1_6_REG UDR1
-#define UDR1_7_REG UDR1
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* EICRB */
-#define ISC40_REG EICRB
-#define ISC41_REG EICRB
-#define ISC50_REG EICRB
-#define ISC51_REG EICRB
-#define ISC60_REG EICRB
-#define ISC61_REG EICRB
-#define ISC70_REG EICRB
-#define ISC71_REG EICRB
-
-/* UEDATX */
-#define UEDATX_0_REG UEDATX
-#define UEDATX_1_REG UEDATX
-#define UEDATX_2_REG UEDATX
-#define UEDATX_3_REG UEDATX
-#define UEDATX_4_REG UEDATX
-#define UEDATX_5_REG UEDATX
-#define UEDATX_6_REG UEDATX
-#define UEDATX_7_REG UEDATX
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-#define ISC20_REG EICRA
-#define ISC21_REG EICRA
-#define ISC30_REG EICRA
-#define ISC31_REG EICRA
-
-/* OTGINT */
-#define SRPI_REG OTGINT
-#define VBERRI_REG OTGINT
-#define BCERRI_REG OTGINT
-#define ROLEEXI_REG OTGINT
-#define HNPERRI_REG OTGINT
-#define STOI_REG OTGINT
-
-/* UECFG0X */
-#define EPDIR_REG UECFG0X
-#define EPTYPE0_REG UECFG0X
-#define EPTYPE1_REG UECFG0X
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* DDRF */
-#define DDF0_REG DDRF
-#define DDF1_REG DDRF
-#define DDF2_REG DDRF
-#define DDF3_REG DDRF
-#define DDF4_REG DDRF
-#define DDF5_REG DDRF
-#define DDF6_REG DDRF
-#define DDF7_REG DDRF
-
-/* ASSR */
-#define TCR2BUB_REG ASSR
-#define TCR2AUB_REG ASSR
-#define OCR2BUB_REG ASSR
-#define OCR2AUB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* UHIEN */
-#define DCONNE_REG UHIEN
-#define DDISCE_REG UHIEN
-#define RSTE_REG UHIEN
-#define RSMEDE_REG UHIEN
-#define RXRSME_REG UHIEN
-#define HSOFE_REG UHIEN
-#define HWUPE_REG UHIEN
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* UENUM */
-#define UENUM_0_REG UENUM
-#define UENUM_1_REG UENUM
-#define UENUM_2_REG UENUM
-
-/* UBRR1L */
-#define UBRR_0_REG UBRR1L
-#define UBRR_1_REG UBRR1L
-#define UBRR_2_REG UBRR1L
-#define UBRR_3_REG UBRR1L
-#define UBRR_4_REG UBRR1L
-#define UBRR_5_REG UBRR1L
-#define UBRR_6_REG UBRR1L
-#define UBRR_7_REG UBRR1L
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* OCR3AL */
-#define OCR3AL0_REG OCR3AL
-#define OCR3AL1_REG OCR3AL
-#define OCR3AL2_REG OCR3AL
-#define OCR3AL3_REG OCR3AL
-#define OCR3AL4_REG OCR3AL
-#define OCR3AL5_REG OCR3AL
-#define OCR3AL6_REG OCR3AL
-#define OCR3AL7_REG OCR3AL
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* UBRR1H */
-#define UBRR_8_REG UBRR1H
-#define UBRR_9_REG UBRR1H
-#define UBRR_10_REG UBRR1H
-#define UBRR_11_REG UBRR1H
-
-/* OCR3AH */
-#define OCR3AH0_REG OCR3AH
-#define OCR3AH1_REG OCR3AH
-#define OCR3AH2_REG OCR3AH
-#define OCR3AH3_REG OCR3AH
-#define OCR3AH4_REG OCR3AH
-#define OCR3AH5_REG OCR3AH
-#define OCR3AH6_REG OCR3AH
-#define OCR3AH7_REG OCR3AH
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* UHADDR */
-#define UHADDR_0_REG UHADDR
-#define UHADDR_1_REG UHADDR
-#define UHADDR_2_REG UHADDR
-#define UHADDR_3_REG UHADDR
-#define UHADDR_4_REG UHADDR
-#define UHADDR_5_REG UHADDR
-#define UHADDR_6_REG UHADDR
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* UDCON */
-#define DETACH_REG UDCON
-#define RMWKUP_REG UDCON
-#define LSM_REG UDCON
-
-/* UHFLEN */
-#define UHFLEN_0_REG UHFLEN
-#define UHFLEN_1_REG UHFLEN
-#define UHFLEN_2_REG UHFLEN
-#define UHFLEN_3_REG UHFLEN
-#define UHFLEN_4_REG UHFLEN
-#define UHFLEN_5_REG UHFLEN
-#define UHFLEN_6_REG UHFLEN
-#define UHFLEN_7_REG UHFLEN
-
-/* UHFNUMH */
-#define UHFNUMH_0_REG UHFNUMH
-#define UHFNUMH_1_REG UHFNUMH
-#define UHFNUMH_2_REG UHFNUMH
-
-/* UHFNUML */
-#define UHFNUML_0_REG UHFNUML
-#define UHFNUML_1_REG UHFNUML
-#define UHFNUML_2_REG UHFNUML
-#define UHFNUML_3_REG UHFNUML
-#define UHFNUML_4_REG UHFNUML
-#define UHFNUML_5_REG UHFNUML
-#define UHFNUML_6_REG UHFNUML
-#define UHFNUML_7_REG UHFNUML
-
-/* PCICR */
-#define PCIE0_REG PCICR
-
-/* USBINT */
-#define VBUSTI_REG USBINT
-#define IDTI_REG USBINT
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* UHWCON */
-#define UVREGE_REG UHWCON
-#define UVCONE_REG UHWCON
-#define UIDE_REG UHWCON
-#define UIMOD_REG UHWCON
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* UDMFN */
-#define FNCERR_REG UDMFN
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* UPDATX */
-#define PDAT0_REG UPDATX
-#define PDAT1_REG UPDATX
-#define PDAT2_REG UPDATX
-#define PDAT3_REG UPDATX
-#define PDAT4_REG UPDATX
-#define PDAT5_REG UPDATX
-#define PDAT6_REG UPDATX
-#define PDAT7_REG UPDATX
-
-/* OCR2B */
-#define OCR2B_0_REG OCR2B
-#define OCR2B_1_REG OCR2B
-#define OCR2B_2_REG OCR2B
-#define OCR2B_3_REG OCR2B
-#define OCR2B_4_REG OCR2B
-#define OCR2B_5_REG OCR2B
-#define OCR2B_6_REG OCR2B
-#define OCR2B_7_REG OCR2B
-
-/* UHCON */
-#define SOFEN_REG UHCON
-#define RESET_REG UHCON
-#define RESUME_REG UHCON
-
-/* TIFR3 */
-#define TOV3_REG TIFR3
-#define OCF3A_REG TIFR3
-#define OCF3B_REG TIFR3
-#define OCF3C_REG TIFR3
-#define ICF3_REG TIFR3
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define OCF1C_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-#define EEAR10_REG EEARH
-#define EEAR11_REG EEARH
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* UPINT */
-#define PINT0_REG UPINT
-#define PINT1_REG UPINT
-#define PINT2_REG UPINT
-#define PINT3_REG UPINT
-#define PINT4_REG UPINT
-#define PINT5_REG UPINT
-#define PINT6_REG UPINT
-
-/* UEBCLX */
-#define UEBCLX_0_REG UEBCLX
-#define UEBCLX_1_REG UEBCLX
-#define UEBCLX_2_REG UEBCLX
-#define UEBCLX_3_REG UEBCLX
-#define UEBCLX_4_REG UEBCLX
-#define UEBCLX_5_REG UEBCLX
-#define UEBCLX_6_REG UEBCLX
-#define UEBCLX_7_REG UEBCLX
-
-/* OCR3CH */
-#define OCR3CH0_REG OCR3CH
-#define OCR3CH1_REG OCR3CH
-#define OCR3CH2_REG OCR3CH
-#define OCR3CH3_REG OCR3CH
-#define OCR3CH4_REG OCR3CH
-#define OCR3CH5_REG OCR3CH
-#define OCR3CH6_REG OCR3CH
-#define OCR3CH7_REG OCR3CH
-
-/* UESTA1X */
-#define CURRBK0_REG UESTA1X
-#define CURRBK1_REG UESTA1X
-#define CTRLDIR_REG UESTA1X
-
-/* OCR3CL */
-#define OCR3CL0_REG OCR3CL
-#define OCR3CL1_REG OCR3CL
-#define OCR3CL2_REG OCR3CL
-#define OCR3CL3_REG OCR3CL
-#define OCR3CL4_REG OCR3CL
-#define OCR3CL5_REG OCR3CL
-#define OCR3CL6_REG OCR3CL
-#define OCR3CL7_REG OCR3CL
-
-/* GTCCR */
-#define PSRSYNC_REG GTCCR
-#define TSM_REG GTCCR
-#define PSRASY_REG GTCCR
-
-/* UPSTAX */
-#define NBUSYK0_REG UPSTAX
-#define NBUSYK1_REG UPSTAX
-/* #define DTSEQ0_REG UPSTAX */ /* dup in UESTA0X */
-/* #define DTSEQ1_REG UPSTAX */ /* dup in UESTA0X */
-/* #define UNDERFI_REG UPSTAX */ /* dup in UESTA0X */
-/* #define OVERFI_REG UPSTAX */ /* dup in UESTA0X */
-/* #define CFGOK_REG UPSTAX */ /* dup in UESTA0X */
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* TCCR3C */
-#define FOC3C_REG TCCR3C
-#define FOC3B_REG TCCR3C
-#define FOC3A_REG TCCR3C
-
-/* TCCR3B */
-#define CS30_REG TCCR3B
-#define CS31_REG TCCR3B
-#define CS32_REG TCCR3B
-#define WGM32_REG TCCR3B
-#define WGM33_REG TCCR3B
-#define ICES3_REG TCCR3B
-#define ICNC3_REG TCCR3B
-
-/* TCCR3A */
-#define WGM30_REG TCCR3A
-#define WGM31_REG TCCR3A
-#define COM3C0_REG TCCR3A
-#define COM3C1_REG TCCR3A
-#define COM3B0_REG TCCR3A
-#define COM3B1_REG TCCR3A
-#define COM3A0_REG TCCR3A
-#define COM3A1_REG TCCR3A
-
-/* UEINTX */
-#define TXINI_REG UEINTX
-#define STALLEDI_REG UEINTX
-#define RXOUTI_REG UEINTX
-#define RXSTPI_REG UEINTX
-#define NAKOUTI_REG UEINTX
-/* #define RWAL_REG UEINTX */ /* dup in UPINTX */
-#define NAKINI_REG UEINTX
-/* #define FIFOCON_REG UEINTX */ /* dup in UPINTX */
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* TCNT3H */
-#define TCNT3H0_REG TCNT3H
-#define TCNT3H1_REG TCNT3H
-#define TCNT3H2_REG TCNT3H
-#define TCNT3H3_REG TCNT3H
-#define TCNT3H4_REG TCNT3H
-#define TCNT3H5_REG TCNT3H
-#define TCNT3H6_REG TCNT3H
-#define TCNT3H7_REG TCNT3H
-
-/* UPCFG0X */
-#define PEPNUM0_REG UPCFG0X
-#define PEPNUM1_REG UPCFG0X
-#define PEPNUM2_REG UPCFG0X
-#define PEPNUM3_REG UPCFG0X
-#define PTOKEN0_REG UPCFG0X
-#define PTOKEN1_REG UPCFG0X
-#define PTYPE0_REG UPCFG0X
-#define PTYPE1_REG UPCFG0X
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* TCNT3L */
-#define TCNT3L0_REG TCNT3L
-#define TCNT3L1_REG TCNT3L
-#define TCNT3L2_REG TCNT3L
-#define TCNT3L3_REG TCNT3L
-#define TCNT3L4_REG TCNT3L
-#define TCNT3L5_REG TCNT3L
-#define TCNT3L6_REG TCNT3L
-#define TCNT3L7_REG TCNT3L
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* UPERRX */
-#define DATATGL_REG UPERRX
-#define DATAPID_REG UPERRX
-#define PID_REG UPERRX
-#define TIMEOUT_REG UPERRX
-#define CRC16_REG UPERRX
-#define COUNTER0_REG UPERRX
-#define COUNTER1_REG UPERRX
-
-/* USBCON */
-#define VBUSTE_REG USBCON
-#define IDTE_REG USBCON
-#define OTGPADE_REG USBCON
-#define FRZCLK_REG USBCON
-#define HOST_REG USBCON
-#define USBE_REG USBCON
-
-/* UPCONX */
-#define PEN_REG UPCONX
-/* #define RSTDT_REG UPCONX */ /* dup in UECONX */
-#define INMODE_REG UPCONX
-#define PFREEZE_REG UPCONX
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-#define JTRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* UPBCLX */
-#define PBYCT0_REG UPBCLX
-#define PBYCT1_REG UPBCLX
-#define PBYCT2_REG UPBCLX
-#define PBYCT3_REG UPBCLX
-#define PBYCT4_REG UPBCLX
-#define PBYCT5_REG UPBCLX
-#define PBYCT6_REG UPBCLX
-#define PBYCT7_REG UPBCLX
-
-/* UHINT */
-#define DCONNI_REG UHINT
-#define DDISCI_REG UHINT
-#define RSTI_REG UHINT
-#define RSMEDI_REG UHINT
-#define RXRSMI_REG UHINT
-#define HSOFI_REG UHINT
-#define UHUPI_REG UHINT
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* PCIFR */
-#define PCIF0_REG PCIFR
-
-/* TCCR2A */
-#define WGM20_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2B0_REG TCCR2A
-#define COM2B1_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-
-/* TCCR2B */
-#define CS20_REG TCCR2B
-#define CS21_REG TCCR2B
-#define CS22_REG TCCR2B
-#define WGM22_REG TCCR2B
-#define FOC2B_REG TCCR2B
-#define FOC2A_REG TCCR2B
-
-/* UPNUM */
-#define PNUM0_REG UPNUM
-#define PNUM1_REG UPNUM
-#define PNUM2_REG UPNUM
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* MCUCR */
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-#define JTD_REG MCUCR
-
-/* OCR1CL */
-#define OCR1CL0_REG OCR1CL
-#define OCR1CL1_REG OCR1CL
-#define OCR1CL2_REG OCR1CL
-#define OCR1CL3_REG OCR1CL
-#define OCR1CL4_REG OCR1CL
-#define OCR1CL5_REG OCR1CL
-#define OCR1CL6_REG OCR1CL
-#define OCR1CL7_REG OCR1CL
-
-/* OCR1CH */
-#define OCR1CH0_REG OCR1CH
-#define OCR1CH1_REG OCR1CH
-#define OCR1CH2_REG OCR1CH
-#define OCR1CH3_REG OCR1CH
-#define OCR1CH4_REG OCR1CH
-#define OCR1CH5_REG OCR1CH
-#define OCR1CH6_REG OCR1CH
-#define OCR1CH7_REG OCR1CH
-
-/* UPCFG1X */
-/* #define ALLOC_REG UPCFG1X */ /* dup in UECFG1X */
-#define PBK0_REG UPCFG1X
-#define PBK1_REG UPCFG1X
-#define PSIZE0_REG UPCFG1X
-#define PSIZE1_REG UPCFG1X
-#define PSIZE2_REG UPCFG1X
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* USBSTA */
-#define VBUS_REG USBSTA
-#define ID_REG USBSTA
-#define SPEED_REG USBSTA
-
-/* UEIENX */
-#define TXINE_REG UEIENX
-#define STALLEDE_REG UEIENX
-#define RXOUTE_REG UEIENX
-#define RXSTPE_REG UEIENX
-#define NAKOUTE_REG UEIENX
-#define NAKINE_REG UEIENX
-/* #define FLERRE_REG UEIENX */ /* dup in UPIENX */
-
-/* OTGCON */
-#define VBUSRQC_REG OTGCON
-#define VBUSREQ_REG OTGCON
-#define VBUSHWC_REG OTGCON
-#define SRPSEL_REG OTGCON
-#define SRPREQ_REG OTGCON
-#define HNPREQ_REG OTGCON
-
-/* UCSR1B */
-#define TXB81_REG UCSR1B
-#define RXB81_REG UCSR1B
-#define UCSZ12_REG UCSR1B
-#define TXEN1_REG UCSR1B
-#define RXEN1_REG UCSR1B
-#define UDRIE1_REG UCSR1B
-#define TXCIE1_REG UCSR1B
-#define RXCIE1_REG UCSR1B
-
-/* UCSR1C */
-#define UCPOL1_REG UCSR1C
-#define UCSZ10_REG UCSR1C
-#define UCSZ11_REG UCSR1C
-#define USBS1_REG UCSR1C
-#define UPM10_REG UCSR1C
-#define UPM11_REG UCSR1C
-#define UMSEL10_REG UCSR1C
-#define UMSEL11_REG UCSR1C
-
-/* UCSR1A */
-#define MPCM1_REG UCSR1A
-#define U2X1_REG UCSR1A
-#define UPE1_REG UCSR1A
-#define DOR1_REG UCSR1A
-#define FE1_REG UCSR1A
-#define UDRE1_REG UCSR1A
-#define TXC1_REG UCSR1A
-#define RXC1_REG UCSR1A
-
-/* UPINRQX */
-#define INRQ0_REG UPINRQX
-#define INRQ1_REG UPINRQX
-#define INRQ2_REG UPINRQX
-#define INRQ3_REG UPINRQX
-#define INRQ4_REG UPINRQX
-#define INRQ5_REG UPINRQX
-#define INRQ6_REG UPINRQX
-#define INRQ7_REG UPINRQX
-
-/* EIND */
-#define EIND0_REG EIND
-
-/* UDFNUML */
-#define UDFNUML_0_REG UDFNUML
-#define UDFNUML_1_REG UDFNUML
-#define UDFNUML_2_REG UDFNUML
-#define UDFNUML_3_REG UDFNUML
-#define UDFNUML_4_REG UDFNUML
-#define UDFNUML_5_REG UDFNUML
-#define UDFNUML_6_REG UDFNUML
-#define UDFNUML_7_REG UDFNUML
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* UDFNUMH */
-#define UDFNUMH_0_REG UDFNUMH
-#define UDFNUMH_1_REG UDFNUMH
-#define UDFNUMH_2_REG UDFNUMH
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ADHSM_REG ADCSRB
-#define ACME_REG ADCSRB
-
-/* UPINTX */
-#define RXINI_REG UPINTX
-#define RXSTALLI_REG UPINTX
-#define TXOUTI_REG UPINTX
-#define TXSTPI_REG UPINTX
-#define PERRI_REG UPINTX
-/* #define RWAL_REG UPINTX */ /* dup in UEINTX */
-#define NAKEDI_REG UPINTX
-/* #define FIFOCON_REG UPINTX */ /* dup in UEINTX */
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1C0_REG TCCR1A
-#define COM1C1_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* OCR0A */
-#define OCROA_0_REG OCR0A
-#define OCROA_1_REG OCR0A
-#define OCROA_2_REG OCR0A
-#define OCROA_3_REG OCR0A
-#define OCROA_4_REG OCR0A
-#define OCROA_5_REG OCR0A
-#define OCROA_6_REG OCR0A
-#define OCROA_7_REG OCR0A
-
-/* UPCFG2X */
-#define UPCFG2X_0_REG UPCFG2X
-#define UPCFG2X_1_REG UPCFG2X
-#define UPCFG2X_2_REG UPCFG2X
-#define UPCFG2X_3_REG UPCFG2X
-#define UPCFG2X_4_REG UPCFG2X
-#define UPCFG2X_5_REG UPCFG2X
-#define UPCFG2X_6_REG UPCFG2X
-#define UPCFG2X_7_REG UPCFG2X
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* PORTF */
-#define PORTF0_REG PORTF
-#define PORTF1_REG PORTF
-#define PORTF2_REG PORTF
-#define PORTF3_REG PORTF
-#define PORTF4_REG PORTF
-#define PORTF5_REG PORTF
-#define PORTF6_REG PORTF
-#define PORTF7_REG PORTF
-
-/* TCCR1C */
-#define FOC1C_REG TCCR1C
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* ICR3H */
-#define ICR3H0_REG ICR3H
-#define ICR3H1_REG ICR3H
-#define ICR3H2_REG ICR3H
-#define ICR3H3_REG ICR3H
-#define ICR3H4_REG ICR3H
-#define ICR3H5_REG ICR3H
-#define ICR3H6_REG ICR3H
-#define ICR3H7_REG ICR3H
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-#define DDE3_REG DDRE
-#define DDE4_REG DDRE
-#define DDE5_REG DDRE
-#define DDE6_REG DDRE
-#define DDE7_REG DDRE
-
-/* UDADDR */
-#define UADD0_REG UDADDR
-#define UADD1_REG UDADDR
-#define UADD2_REG UDADDR
-#define UADD3_REG UDADDR
-#define UADD4_REG UDADDR
-#define UADD5_REG UDADDR
-#define UADD6_REG UDADDR
-#define ADDEN_REG UDADDR
-
-/* ICR3L */
-#define ICR3L0_REG ICR3L
-#define ICR3L1_REG ICR3L
-#define ICR3L2_REG ICR3L
-#define ICR3L3_REG ICR3L
-#define ICR3L4_REG ICR3L
-#define ICR3L5_REG ICR3L
-#define ICR3L6_REG ICR3L
-#define ICR3L7_REG ICR3L
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-#define PORTE3_REG PORTE
-#define PORTE4_REG PORTE
-#define PORTE5_REG PORTE
-#define PORTE6_REG PORTE
-#define PORTE7_REG PORTE
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define SIGRD_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* UESTA0X */
-#define NBUSYBK0_REG UESTA0X
-#define NBUSYBK1_REG UESTA0X
-/* #define DTSEQ0_REG UESTA0X */ /* dup in UPSTAX */
-/* #define DTSEQ1_REG UESTA0X */ /* dup in UPSTAX */
-/* #define UNDERFI_REG UESTA0X */ /* dup in UPSTAX */
-/* #define OVERFI_REG UESTA0X */ /* dup in UPSTAX */
-/* #define CFGOK_REG UESTA0X */ /* dup in UPSTAX */
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* OCR3BL */
-#define OCR3BL0_REG OCR3BL
-#define OCR3BL1_REG OCR3BL
-#define OCR3BL2_REG OCR3BL
-#define OCR3BL3_REG OCR3BL
-#define OCR3BL4_REG OCR3BL
-#define OCR3BL5_REG OCR3BL
-#define OCR3BL6_REG OCR3BL
-#define OCR3BL7_REG OCR3BL
-
-/* OCR3BH */
-#define OCR3BH0_REG OCR3BH
-#define OCR3BH1_REG OCR3BH
-#define OCR3BH2_REG OCR3BH
-#define OCR3BH3_REG OCR3BH
-#define OCR3BH4_REG OCR3BH
-#define OCR3BH5_REG OCR3BH
-#define OCR3BH6_REG OCR3BH
-#define OCR3BH7_REG OCR3BH
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-#define OCIE2B_REG TIMSK2
-
-/* TIMSK3 */
-#define TOIE3_REG TIMSK3
-#define OCIE3A_REG TIMSK3
-#define OCIE3B_REG TIMSK3
-#define OCIE3C_REG TIMSK3
-#define ICIE3_REG TIMSK3
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define OCIE1C_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* PLLCSR */
-#define PLOCK_REG PLLCSR
-#define PLLE_REG PLLCSR
-#define PLLP0_REG PLLCSR
-#define PLLP1_REG PLLCSR
-#define PLLP2_REG PLLCSR
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* XMCRB */
-#define XMM0_REG XMCRB
-#define XMM1_REG XMCRB
-#define XMM2_REG XMCRB
-#define XMBK_REG XMCRB
-
-/* XMCRA */
-#define SRW00_REG XMCRA
-#define SRW01_REG XMCRA
-#define SRW10_REG XMCRA
-#define SRW11_REG XMCRA
-#define SRL0_REG XMCRA
-#define SRL1_REG XMCRA
-#define SRL2_REG XMCRA
-#define SRE_REG XMCRA
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-#define OCF2B_REG TIFR2
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-#define INTF2_REG EIFR
-#define INTF3_REG EIFR
-#define INTF4_REG EIFR
-#define INTF5_REG EIFR
-#define INTF6_REG EIFR
-#define INTF7_REG EIFR
-
-/* PINF */
-#define PINF0_REG PINF
-#define PINF1_REG PINF
-#define PINF2_REG PINF
-#define PINF3_REG PINF
-#define PINF4_REG PINF
-#define PINF5_REG PINF
-#define PINF6_REG PINF
-#define PINF7_REG PINF
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-#define PINE3_REG PINE
-#define PINE4_REG PINE
-#define PINE5_REG PINE
-#define PINE6_REG PINE
-#define PINE7_REG PINE
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* TWAMR */
-#define TWAM0_REG TWAMR
-#define TWAM1_REG TWAMR
-#define TWAM2_REG TWAMR
-#define TWAM3_REG TWAMR
-#define TWAM4_REG TWAMR
-#define TWAM5_REG TWAMR
-#define TWAM6_REG TWAMR
-
-/* PRR0 */
-#define PRADC_REG PRR0
-#define PRSPI_REG PRR0
-#define PRTIM1_REG PRR0
-#define PRTIM0_REG PRR0
-#define PRTIM2_REG PRR0
-#define PRTWI_REG PRR0
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* PRR1 */
-#define PRUSART1_REG PRR1
-#define PRTIM3_REG PRR1
-#define PRUSB_REG PRR1
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* UPRST */
-#define PRST0_REG UPRST
-#define PRST1_REG UPRST
-#define PRST2_REG UPRST
-#define PRST3_REG UPRST
-#define PRST4_REG UPRST
-#define PRST5_REG UPRST
-#define PRST6_REG UPRST
-
-/* pins mapping */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER1C_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW_TOTAL_NUM 2
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE1C_NUM 4
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 5
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM1C_NUM 4
-#define PWM_TOTAL_NUM 5
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* UDIEN */
-#define SUSPE_REG UDIEN
-#define SOFE_REG UDIEN
-#define EORSTE_REG UDIEN
-#define WAKEUPE_REG UDIEN
-#define EORSME_REG UDIEN
-#define UPRSME_REG UDIEN
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* PS2CON */
-#define PS2EN_REG PS2CON
-
-/* UERST */
-#define EPRST0_REG UERST
-#define EPRST1_REG UERST
-#define EPRST2_REG UERST
-#define EPRST3_REG UERST
-#define EPRST4_REG UERST
-
-/* UECFG1X */
-#define ALLOC_REG UECFG1X
-#define EPBK0_REG UECFG1X
-#define EPBK1_REG UECFG1X
-#define EPSIZE0_REG UECFG1X
-#define EPSIZE1_REG UECFG1X
-#define EPSIZE2_REG UECFG1X
-
-/* UDR1 */
-#define UDR1_0_REG UDR1
-#define UDR1_1_REG UDR1
-#define UDR1_2_REG UDR1
-#define UDR1_3_REG UDR1
-#define UDR1_4_REG UDR1
-#define UDR1_5_REG UDR1
-#define UDR1_6_REG UDR1
-#define UDR1_7_REG UDR1
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* UEINT */
-#define EPINT0_REG UEINT
-#define EPINT1_REG UEINT
-#define EPINT2_REG UEINT
-#define EPINT3_REG UEINT
-#define EPINT4_REG UEINT
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* REGCR */
-#define REGDIS_REG REGCR
-
-/* EICRB */
-#define ISC40_REG EICRB
-#define ISC41_REG EICRB
-#define ISC50_REG EICRB
-#define ISC51_REG EICRB
-#define ISC60_REG EICRB
-#define ISC61_REG EICRB
-#define ISC70_REG EICRB
-#define ISC71_REG EICRB
-
-/* UEDATX */
-#define DAT0_REG UEDATX
-#define DAT1_REG UEDATX
-#define DAT2_REG UEDATX
-#define DAT3_REG UEDATX
-#define DAT4_REG UEDATX
-#define DAT5_REG UEDATX
-#define DAT6_REG UEDATX
-#define DAT7_REG UEDATX
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-#define ISC20_REG EICRA
-#define ISC21_REG EICRA
-#define ISC30_REG EICRA
-#define ISC31_REG EICRA
-
-/* UECFG0X */
-#define EPDIR_REG UECFG0X
-#define EPTYPE0_REG UECFG0X
-#define EPTYPE1_REG UECFG0X
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* CLKSEL1 */
-#define EXCKSEL0_REG CLKSEL1
-#define EXCKSEL1_REG CLKSEL1
-#define EXCKSEL2_REG CLKSEL1
-#define EXCKSEL3_REG CLKSEL1
-#define RCCKSEL0_REG CLKSEL1
-#define RCCKSEL1_REG CLKSEL1
-#define RCCKSEL2_REG CLKSEL1
-#define RCCKSEL3_REG CLKSEL1
-
-/* CLKSEL0 */
-#define CLKS_REG CLKSEL0
-#define EXTE_REG CLKSEL0
-#define RCE_REG CLKSEL0
-#define EXSUT0_REG CLKSEL0
-#define EXSUT1_REG CLKSEL0
-#define RCSUT0_REG CLKSEL0
-#define RCSUT1_REG CLKSEL0
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* UPOE */
-#define DMI_REG UPOE
-#define DPI_REG UPOE
-#define DATAI_REG UPOE
-#define SCKI_REG UPOE
-#define UPDRV0_REG UPOE
-#define UPDRV1_REG UPOE
-#define UPWE0_REG UPOE
-#define UPWE1_REG UPOE
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* UENUM */
-#define EPNUM0_REG UENUM
-#define EPNUM1_REG UENUM
-#define EPNUM2_REG UENUM
-
-/* UBRR1L */
-#define UBRR1_0_REG UBRR1L
-#define UBRR1_1_REG UBRR1L
-#define UBRR1_2_REG UBRR1L
-#define UBRR1_3_REG UBRR1L
-#define UBRR1_4_REG UBRR1L
-#define UBRR1_5_REG UBRR1L
-#define UBRR1_6_REG UBRR1L
-#define UBRR1_7_REG UBRR1L
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1C0_REG TCCR1A
-#define COM1C1_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* TCCR1C */
-#define FOC1C_REG TCCR1C
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* UDCON */
-#define DETACH_REG UDCON
-#define RMWKUP_REG UDCON
-#define RSTCPU_REG UDCON
-
-/* WDTCKD */
-#define WCLKD0_REG WDTCKD
-#define WCLKD1_REG WDTCKD
-#define WDEWIE_REG WDTCKD
-#define WDEWIF_REG WDTCKD
-
-/* PCICR */
-#define PCIE0_REG PCICR
-#define PCIE1_REG PCICR
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* UDINT */
-#define SUSPI_REG UDINT
-#define SOFI_REG UDINT
-#define EORSTI_REG UDINT
-#define WAKEUPI_REG UDINT
-#define EORSMI_REG UDINT
-#define UPRSMI_REG UDINT
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* UDMFN */
-#define FNCERR_REG UDMFN
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* DWDR */
-#define DWDR0_REG DWDR
-#define DWDR1_REG DWDR
-#define DWDR2_REG DWDR
-#define DWDR3_REG DWDR
-#define DWDR4_REG DWDR
-#define DWDR5_REG DWDR
-#define DWDR6_REG DWDR
-#define DWDR7_REG DWDR
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define OCF1C_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* UEBCLX */
-#define BYCT0_REG UEBCLX
-#define BYCT1_REG UEBCLX
-#define BYCT2_REG UEBCLX
-#define BYCT3_REG UEBCLX
-#define BYCT4_REG UEBCLX
-#define BYCT5_REG UEBCLX
-#define BYCT6_REG UEBCLX
-#define BYCT7_REG UEBCLX
-
-/* UESTA1X */
-#define CURRBK0_REG UESTA1X
-#define CURRBK1_REG UESTA1X
-#define CTRLDIR_REG UESTA1X
-
-/* GTCCR */
-#define PSRSYNC_REG GTCCR
-#define TSM_REG GTCCR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* UEINTX */
-#define TXINI_REG UEINTX
-#define STALLEDI_REG UEINTX
-#define RXOUTI_REG UEINTX
-#define RXSTPI_REG UEINTX
-#define NAKOUTI_REG UEINTX
-#define RWAL_REG UEINTX
-#define NAKINI_REG UEINTX
-#define FIFOCON_REG UEINTX
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* USBCON */
-#define FRZCLK_REG USBCON
-#define USBE_REG USBCON
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-#define USBRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* PCIFR */
-#define PCIF0_REG PCIFR
-#define PCIF1_REG PCIFR
-
-/* UECONX */
-#define EPEN_REG UECONX
-#define RSTDT_REG UECONX
-#define STALLRQC_REG UECONX
-#define STALLRQ_REG UECONX
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-#define EEAR10_REG EEARH
-#define EEAR11_REG EEARH
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* MCUCR */
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-
-/* OCR1CL */
-#define OCR1CL0_REG OCR1CL
-#define OCR1CL1_REG OCR1CL
-#define OCR1CL2_REG OCR1CL
-#define OCR1CL3_REG OCR1CL
-#define OCR1CL4_REG OCR1CL
-#define OCR1CL5_REG OCR1CL
-#define OCR1CL6_REG OCR1CL
-#define OCR1CL7_REG OCR1CL
-
-/* OCR1CH */
-#define OCR1CH0_REG OCR1CH
-#define OCR1CH1_REG OCR1CH
-#define OCR1CH2_REG OCR1CH
-#define OCR1CH3_REG OCR1CH
-#define OCR1CH4_REG OCR1CH
-#define OCR1CH5_REG OCR1CH
-#define OCR1CH6_REG OCR1CH
-#define OCR1CH7_REG OCR1CH
-
-/* UEIENX */
-#define TXINE_REG UEIENX
-#define STALLEDE_REG UEIENX
-#define RXOUTE_REG UEIENX
-#define RXSTPE_REG UEIENX
-#define NAKOUTE_REG UEIENX
-#define NAKINE_REG UEIENX
-#define FLERRE_REG UEIENX
-
-/* UCSR1B */
-#define TXB81_REG UCSR1B
-#define RXB81_REG UCSR1B
-#define UCSZ12_REG UCSR1B
-#define TXEN1_REG UCSR1B
-#define RXEN1_REG UCSR1B
-#define UDRIE1_REG UCSR1B
-#define TXCIE1_REG UCSR1B
-#define RXCIE1_REG UCSR1B
-
-/* UCSR1C */
-#define UCPOL1_REG UCSR1C
-#define UCSZ10_REG UCSR1C
-#define UCSZ11_REG UCSR1C
-#define USBS1_REG UCSR1C
-#define UPM10_REG UCSR1C
-#define UPM11_REG UCSR1C
-#define UMSEL10_REG UCSR1C
-#define UMSEL11_REG UCSR1C
-
-/* UCSR1A */
-#define MPCM1_REG UCSR1A
-#define U2X1_REG UCSR1A
-#define UPE1_REG UCSR1A
-#define DOR1_REG UCSR1A
-#define FE1_REG UCSR1A
-#define UDRE1_REG UCSR1A
-#define TXC1_REG UCSR1A
-#define RXC1_REG UCSR1A
-
-/* UCSR1D */
-#define RTSEN_REG UCSR1D
-#define CTSEN_REG UCSR1D
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* EIND */
-#define EIND0_REG EIND
-
-/* UDFNUML */
-#define FNUM0_REG UDFNUML
-#define FNUM1_REG UDFNUML
-#define FNUM2_REG UDFNUML
-#define FNUM3_REG UDFNUML
-#define FNUM4_REG UDFNUML
-#define FNUM5_REG UDFNUML
-#define FNUM6_REG UDFNUML
-#define FNUM7_REG UDFNUML
-
-/* UDFNUMH */
-#define FNUM8_REG UDFNUMH
-#define FNUM9_REG UDFNUMH
-#define FNUM10_REG UDFNUMH
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-#define INT3_REG EIMSK
-#define INT4_REG EIMSK
-#define INT5_REG EIMSK
-#define INT6_REG EIMSK
-#define INT7_REG EIMSK
-
-/* PRR0 */
-#define PRSPI_REG PRR0
-#define PRTIM1_REG PRR0
-#define PRTIM0_REG PRR0
-
-/* UBRR1H */
-#define UBRR1_8_REG UBRR1H
-#define UBRR1_9_REG UBRR1H
-#define UBRR1_10_REG UBRR1H
-#define UBRR1_11_REG UBRR1H
-
-/* OCR0A */
-#define OCROA_0_REG OCR0A
-#define OCROA_1_REG OCR0A
-#define OCROA_2_REG OCR0A
-#define OCROA_3_REG OCR0A
-#define OCROA_4_REG OCR0A
-#define OCROA_5_REG OCR0A
-#define OCROA_6_REG OCR0A
-#define OCROA_7_REG OCR0A
-
-/* OCR0B */
-#define OCR0B_0_REG OCR0B
-#define OCR0B_1_REG OCR0B
-#define OCR0B_2_REG OCR0B
-#define OCR0B_3_REG OCR0B
-#define OCR0B_4_REG OCR0B
-#define OCR0B_5_REG OCR0B
-#define OCR0B_6_REG OCR0B
-#define OCR0B_7_REG OCR0B
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* UDADDR */
-#define UADD0_REG UDADDR
-#define UADD1_REG UDADDR
-#define UADD2_REG UDADDR
-#define UADD3_REG UDADDR
-#define UADD4_REG UDADDR
-#define UADD5_REG UDADDR
-#define UADD6_REG UDADDR
-#define ADDEN_REG UDADDR
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define SIGRD_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* UESTA0X */
-#define NBUSYBK0_REG UESTA0X
-#define NBUSYBK1_REG UESTA0X
-#define DTSEQ0_REG UESTA0X
-#define DTSEQ1_REG UESTA0X
-#define UNDERFI_REG UESTA0X
-#define OVERFI_REG UESTA0X
-#define CFGOK_REG UESTA0X
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define OCIE1C_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* CLKSTA */
-#define EXTON_REG CLKSTA
-#define RCON_REG CLKSTA
-
-/* PLLCSR */
-#define PLOCK_REG PLLCSR
-#define PLLE_REG PLLCSR
-#define PLLP0_REG PLLCSR
-#define PLLP1_REG PLLCSR
-#define PLLP2_REG PLLCSR
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-#define INTF2_REG EIFR
-#define INTF3_REG EIFR
-#define INTF4_REG EIFR
-#define INTF5_REG EIFR
-#define INTF6_REG EIFR
-#define INTF7_REG EIFR
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* PRR1 */
-#define PRUSART1_REG PRR1
-#define PRUSB_REG PRR1
-
-/* pins mapping */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-/* prescalers timer 3 */
-#define TIMER3_PRESCALER_DIV_0 0
-#define TIMER3_PRESCALER_DIV_1 1
-#define TIMER3_PRESCALER_DIV_8 2
-#define TIMER3_PRESCALER_DIV_64 3
-#define TIMER3_PRESCALER_DIV_256 4
-#define TIMER3_PRESCALER_DIV_1024 5
-#define TIMER3_PRESCALER_DIV_FALL 6
-#define TIMER3_PRESCALER_DIV_RISE 7
-
-#define TIMER3_PRESCALER_REG_0 0
-#define TIMER3_PRESCALER_REG_1 1
-#define TIMER3_PRESCALER_REG_2 8
-#define TIMER3_PRESCALER_REG_3 64
-#define TIMER3_PRESCALER_REG_4 256
-#define TIMER3_PRESCALER_REG_5 1024
-#define TIMER3_PRESCALER_REG_6 -1
-#define TIMER3_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER1C_AVAILABLE
-#define TIMER2_AVAILABLE
-#define TIMER2A_AVAILABLE
-#define TIMER2B_AVAILABLE
-#define TIMER3_AVAILABLE
-#define TIMER3A_AVAILABLE
-#define TIMER3B_AVAILABLE
-#define TIMER3C_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW3_NUM 3
-#define SIG_OVERFLOW_TOTAL_NUM 4
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE1C_NUM 4
-#define SIG_OUTPUT_COMPARE2A_NUM 5
-#define SIG_OUTPUT_COMPARE2B_NUM 6
-#define SIG_OUTPUT_COMPARE3A_NUM 7
-#define SIG_OUTPUT_COMPARE3B_NUM 8
-#define SIG_OUTPUT_COMPARE3C_NUM 9
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 10
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM1C_NUM 4
-#define PWM2A_NUM 5
-#define PWM2B_NUM 6
-#define PWM3A_NUM 7
-#define PWM3B_NUM 8
-#define PWM3C_NUM 9
-#define PWM_TOTAL_NUM 10
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE3_NUM 1
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 2
-
-
-/* UEBCHX */
-#define UEBCHX_0_REG UEBCHX
-#define UEBCHX_1_REG UEBCHX
-#define UEBCHX_2_REG UEBCHX
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* UDIEN */
-#define SUSPE_REG UDIEN
-#define SOFE_REG UDIEN
-#define EORSTE_REG UDIEN
-#define WAKEUPE_REG UDIEN
-#define EORSME_REG UDIEN
-#define UPRSME_REG UDIEN
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* OCR0B */
-#define OCR0B_0_REG OCR0B
-#define OCR0B_1_REG OCR0B
-#define OCR0B_2_REG OCR0B
-#define OCR0B_3_REG OCR0B
-#define OCR0B_4_REG OCR0B
-#define OCR0B_5_REG OCR0B
-#define OCR0B_6_REG OCR0B
-#define OCR0B_7_REG OCR0B
-
-/* UPIENX */
-#define RXINE_REG UPIENX
-#define RXSTALLE_REG UPIENX
-#define TXOUTE_REG UPIENX
-#define TXSTPE_REG UPIENX
-#define PERRE_REG UPIENX
-#define NAKEDE_REG UPIENX
-/* #define FLERRE_REG UPIENX */ /* dup in UEIENX */
-
-/* UDINT */
-#define SUSPI_REG UDINT
-#define SOFI_REG UDINT
-#define EORSTI_REG UDINT
-#define WAKEUPI_REG UDINT
-#define EORSMI_REG UDINT
-#define UPRSMI_REG UDINT
-
-/* UERST */
-#define EPRST0_REG UERST
-#define EPRST1_REG UERST
-#define EPRST2_REG UERST
-#define EPRST3_REG UERST
-#define EPRST4_REG UERST
-#define EPRST5_REG UERST
-#define EPRST6_REG UERST
-
-/* RAMPZ */
-#define RAMPZ0_REG RAMPZ
-
-/* UECFG1X */
-/* #define ALLOC_REG UECFG1X */ /* dup in UPCFG1X */
-#define EPBK0_REG UECFG1X
-#define EPBK1_REG UECFG1X
-#define EPSIZE0_REG UECFG1X
-#define EPSIZE1_REG UECFG1X
-#define EPSIZE2_REG UECFG1X
-
-/* UECONX */
-#define EPEN_REG UECONX
-/* #define RSTDT_REG UECONX */ /* dup in UPCONX */
-#define STALLRQC_REG UECONX
-#define STALLRQ_REG UECONX
-
-/* OCR2A */
-#define OCR2A_0_REG OCR2A
-#define OCR2A_1_REG OCR2A
-#define OCR2A_2_REG OCR2A
-#define OCR2A_3_REG OCR2A
-#define OCR2A_4_REG OCR2A
-#define OCR2A_5_REG OCR2A
-#define OCR2A_6_REG OCR2A
-#define OCR2A_7_REG OCR2A
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* OTGIEN */
-#define SRPE_REG OTGIEN
-#define VBERRE_REG OTGIEN
-#define BCERRE_REG OTGIEN
-#define ROLEEXE_REG OTGIEN
-#define HNPERRE_REG OTGIEN
-#define STOE_REG OTGIEN
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* UEINT */
-#define EPINT0_REG UEINT
-#define EPINT1_REG UEINT
-#define EPINT2_REG UEINT
-#define EPINT3_REG UEINT
-#define EPINT4_REG UEINT
-#define EPINT5_REG UEINT
-#define EPINT6_REG UEINT
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* OTGTCON */
-#define VALUE_20_REG OTGTCON
-#define VALUE_21_REG OTGTCON
-#define VALUE_22_REG OTGTCON
-#define PAGE0_REG OTGTCON
-#define PAGE1_REG OTGTCON
-#define OTGTCON_7_REG OTGTCON
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* UPBCHX */
-#define PBYCT8_REG UPBCHX
-#define PBYCT9_REG UPBCHX
-#define PBYCT10_REG UPBCHX
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-#define INT3_REG EIMSK
-#define INT4_REG EIMSK
-#define INT5_REG EIMSK
-#define INT6_REG EIMSK
-#define INT7_REG EIMSK
-
-/* UDR1 */
-#define UDR1_0_REG UDR1
-#define UDR1_1_REG UDR1
-#define UDR1_2_REG UDR1
-#define UDR1_3_REG UDR1
-#define UDR1_4_REG UDR1
-#define UDR1_5_REG UDR1
-#define UDR1_6_REG UDR1
-#define UDR1_7_REG UDR1
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* EICRB */
-#define ISC40_REG EICRB
-#define ISC41_REG EICRB
-#define ISC50_REG EICRB
-#define ISC51_REG EICRB
-#define ISC60_REG EICRB
-#define ISC61_REG EICRB
-#define ISC70_REG EICRB
-#define ISC71_REG EICRB
-
-/* UEDATX */
-#define UEDATX_0_REG UEDATX
-#define UEDATX_1_REG UEDATX
-#define UEDATX_2_REG UEDATX
-#define UEDATX_3_REG UEDATX
-#define UEDATX_4_REG UEDATX
-#define UEDATX_5_REG UEDATX
-#define UEDATX_6_REG UEDATX
-#define UEDATX_7_REG UEDATX
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-#define ISC20_REG EICRA
-#define ISC21_REG EICRA
-#define ISC30_REG EICRA
-#define ISC31_REG EICRA
-
-/* OTGINT */
-#define SRPI_REG OTGINT
-#define VBERRI_REG OTGINT
-#define BCERRI_REG OTGINT
-#define ROLEEXI_REG OTGINT
-#define HNPERRI_REG OTGINT
-#define STOI_REG OTGINT
-
-/* UECFG0X */
-#define EPDIR_REG UECFG0X
-#define EPTYPE0_REG UECFG0X
-#define EPTYPE1_REG UECFG0X
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* DDRF */
-#define DDF0_REG DDRF
-#define DDF1_REG DDRF
-#define DDF2_REG DDRF
-#define DDF3_REG DDRF
-#define DDF4_REG DDRF
-#define DDF5_REG DDRF
-#define DDF6_REG DDRF
-#define DDF7_REG DDRF
-
-/* ASSR */
-#define TCR2BUB_REG ASSR
-#define TCR2AUB_REG ASSR
-#define OCR2BUB_REG ASSR
-#define OCR2AUB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* UHIEN */
-#define DCONNE_REG UHIEN
-#define DDISCE_REG UHIEN
-#define RSTE_REG UHIEN
-#define RSMEDE_REG UHIEN
-#define RXRSME_REG UHIEN
-#define HSOFE_REG UHIEN
-#define HWUPE_REG UHIEN
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* UENUM */
-#define UENUM_0_REG UENUM
-#define UENUM_1_REG UENUM
-#define UENUM_2_REG UENUM
-
-/* UBRR1L */
-#define UBRR_0_REG UBRR1L
-#define UBRR_1_REG UBRR1L
-#define UBRR_2_REG UBRR1L
-#define UBRR_3_REG UBRR1L
-#define UBRR_4_REG UBRR1L
-#define UBRR_5_REG UBRR1L
-#define UBRR_6_REG UBRR1L
-#define UBRR_7_REG UBRR1L
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* OCR3AL */
-#define OCR3AL0_REG OCR3AL
-#define OCR3AL1_REG OCR3AL
-#define OCR3AL2_REG OCR3AL
-#define OCR3AL3_REG OCR3AL
-#define OCR3AL4_REG OCR3AL
-#define OCR3AL5_REG OCR3AL
-#define OCR3AL6_REG OCR3AL
-#define OCR3AL7_REG OCR3AL
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* UBRR1H */
-#define UBRR_8_REG UBRR1H
-#define UBRR_9_REG UBRR1H
-#define UBRR_10_REG UBRR1H
-#define UBRR_11_REG UBRR1H
-
-/* OCR3AH */
-#define OCR3AH0_REG OCR3AH
-#define OCR3AH1_REG OCR3AH
-#define OCR3AH2_REG OCR3AH
-#define OCR3AH3_REG OCR3AH
-#define OCR3AH4_REG OCR3AH
-#define OCR3AH5_REG OCR3AH
-#define OCR3AH6_REG OCR3AH
-#define OCR3AH7_REG OCR3AH
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* UHADDR */
-#define UHADDR_0_REG UHADDR
-#define UHADDR_1_REG UHADDR
-#define UHADDR_2_REG UHADDR
-#define UHADDR_3_REG UHADDR
-#define UHADDR_4_REG UHADDR
-#define UHADDR_5_REG UHADDR
-#define UHADDR_6_REG UHADDR
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* UDCON */
-#define DETACH_REG UDCON
-#define RMWKUP_REG UDCON
-#define LSM_REG UDCON
-
-/* UHFLEN */
-#define UHFLEN_0_REG UHFLEN
-#define UHFLEN_1_REG UHFLEN
-#define UHFLEN_2_REG UHFLEN
-#define UHFLEN_3_REG UHFLEN
-#define UHFLEN_4_REG UHFLEN
-#define UHFLEN_5_REG UHFLEN
-#define UHFLEN_6_REG UHFLEN
-#define UHFLEN_7_REG UHFLEN
-
-/* UHFNUMH */
-#define UHFNUMH_0_REG UHFNUMH
-#define UHFNUMH_1_REG UHFNUMH
-#define UHFNUMH_2_REG UHFNUMH
-
-/* UHFNUML */
-#define UHFNUML_0_REG UHFNUML
-#define UHFNUML_1_REG UHFNUML
-#define UHFNUML_2_REG UHFNUML
-#define UHFNUML_3_REG UHFNUML
-#define UHFNUML_4_REG UHFNUML
-#define UHFNUML_5_REG UHFNUML
-#define UHFNUML_6_REG UHFNUML
-#define UHFNUML_7_REG UHFNUML
-
-/* PCICR */
-#define PCIE0_REG PCICR
-
-/* USBINT */
-#define VBUSTI_REG USBINT
-#define IDTI_REG USBINT
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* UHWCON */
-#define UVREGE_REG UHWCON
-#define UVCONE_REG UHWCON
-#define UIDE_REG UHWCON
-#define UIMOD_REG UHWCON
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* UDMFN */
-#define FNCERR_REG UDMFN
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* UPDATX */
-#define PDAT0_REG UPDATX
-#define PDAT1_REG UPDATX
-#define PDAT2_REG UPDATX
-#define PDAT3_REG UPDATX
-#define PDAT4_REG UPDATX
-#define PDAT5_REG UPDATX
-#define PDAT6_REG UPDATX
-#define PDAT7_REG UPDATX
-
-/* OCR2B */
-#define OCR2B_0_REG OCR2B
-#define OCR2B_1_REG OCR2B
-#define OCR2B_2_REG OCR2B
-#define OCR2B_3_REG OCR2B
-#define OCR2B_4_REG OCR2B
-#define OCR2B_5_REG OCR2B
-#define OCR2B_6_REG OCR2B
-#define OCR2B_7_REG OCR2B
-
-/* UHCON */
-#define SOFEN_REG UHCON
-#define RESET_REG UHCON
-#define RESUME_REG UHCON
-
-/* TIFR3 */
-#define TOV3_REG TIFR3
-#define OCF3A_REG TIFR3
-#define OCF3B_REG TIFR3
-#define OCF3C_REG TIFR3
-#define ICF3_REG TIFR3
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define OCF1C_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-#define EEAR10_REG EEARH
-#define EEAR11_REG EEARH
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* UPINT */
-#define PINT0_REG UPINT
-#define PINT1_REG UPINT
-#define PINT2_REG UPINT
-#define PINT3_REG UPINT
-#define PINT4_REG UPINT
-#define PINT5_REG UPINT
-#define PINT6_REG UPINT
-
-/* UEBCLX */
-#define UEBCLX_0_REG UEBCLX
-#define UEBCLX_1_REG UEBCLX
-#define UEBCLX_2_REG UEBCLX
-#define UEBCLX_3_REG UEBCLX
-#define UEBCLX_4_REG UEBCLX
-#define UEBCLX_5_REG UEBCLX
-#define UEBCLX_6_REG UEBCLX
-#define UEBCLX_7_REG UEBCLX
-
-/* OCR3CH */
-#define OCR3CH0_REG OCR3CH
-#define OCR3CH1_REG OCR3CH
-#define OCR3CH2_REG OCR3CH
-#define OCR3CH3_REG OCR3CH
-#define OCR3CH4_REG OCR3CH
-#define OCR3CH5_REG OCR3CH
-#define OCR3CH6_REG OCR3CH
-#define OCR3CH7_REG OCR3CH
-
-/* UESTA1X */
-#define CURRBK0_REG UESTA1X
-#define CURRBK1_REG UESTA1X
-#define CTRLDIR_REG UESTA1X
-
-/* OCR3CL */
-#define OCR3CL0_REG OCR3CL
-#define OCR3CL1_REG OCR3CL
-#define OCR3CL2_REG OCR3CL
-#define OCR3CL3_REG OCR3CL
-#define OCR3CL4_REG OCR3CL
-#define OCR3CL5_REG OCR3CL
-#define OCR3CL6_REG OCR3CL
-#define OCR3CL7_REG OCR3CL
-
-/* GTCCR */
-#define PSRSYNC_REG GTCCR
-#define TSM_REG GTCCR
-#define PSRASY_REG GTCCR
-
-/* UPSTAX */
-#define NBUSYK0_REG UPSTAX
-#define NBUSYK1_REG UPSTAX
-/* #define DTSEQ0_REG UPSTAX */ /* dup in UESTA0X */
-/* #define DTSEQ1_REG UPSTAX */ /* dup in UESTA0X */
-/* #define UNDERFI_REG UPSTAX */ /* dup in UESTA0X */
-/* #define OVERFI_REG UPSTAX */ /* dup in UESTA0X */
-/* #define CFGOK_REG UPSTAX */ /* dup in UESTA0X */
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* TCCR3C */
-#define FOC3C_REG TCCR3C
-#define FOC3B_REG TCCR3C
-#define FOC3A_REG TCCR3C
-
-/* TCCR3B */
-#define CS30_REG TCCR3B
-#define CS31_REG TCCR3B
-#define CS32_REG TCCR3B
-#define WGM32_REG TCCR3B
-#define WGM33_REG TCCR3B
-#define ICES3_REG TCCR3B
-#define ICNC3_REG TCCR3B
-
-/* TCCR3A */
-#define WGM30_REG TCCR3A
-#define WGM31_REG TCCR3A
-#define COM3C0_REG TCCR3A
-#define COM3C1_REG TCCR3A
-#define COM3B0_REG TCCR3A
-#define COM3B1_REG TCCR3A
-#define COM3A0_REG TCCR3A
-#define COM3A1_REG TCCR3A
-
-/* UEINTX */
-#define TXINI_REG UEINTX
-#define STALLEDI_REG UEINTX
-#define RXOUTI_REG UEINTX
-#define RXSTPI_REG UEINTX
-#define NAKOUTI_REG UEINTX
-/* #define RWAL_REG UEINTX */ /* dup in UPINTX */
-#define NAKINI_REG UEINTX
-/* #define FIFOCON_REG UEINTX */ /* dup in UPINTX */
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* TCNT3H */
-#define TCNT3H0_REG TCNT3H
-#define TCNT3H1_REG TCNT3H
-#define TCNT3H2_REG TCNT3H
-#define TCNT3H3_REG TCNT3H
-#define TCNT3H4_REG TCNT3H
-#define TCNT3H5_REG TCNT3H
-#define TCNT3H6_REG TCNT3H
-#define TCNT3H7_REG TCNT3H
-
-/* UPCFG0X */
-#define PEPNUM0_REG UPCFG0X
-#define PEPNUM1_REG UPCFG0X
-#define PEPNUM2_REG UPCFG0X
-#define PEPNUM3_REG UPCFG0X
-#define PTOKEN0_REG UPCFG0X
-#define PTOKEN1_REG UPCFG0X
-#define PTYPE0_REG UPCFG0X
-#define PTYPE1_REG UPCFG0X
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* TCNT3L */
-#define TCNT3L0_REG TCNT3L
-#define TCNT3L1_REG TCNT3L
-#define TCNT3L2_REG TCNT3L
-#define TCNT3L3_REG TCNT3L
-#define TCNT3L4_REG TCNT3L
-#define TCNT3L5_REG TCNT3L
-#define TCNT3L6_REG TCNT3L
-#define TCNT3L7_REG TCNT3L
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* UPERRX */
-#define DATATGL_REG UPERRX
-#define DATAPID_REG UPERRX
-#define PID_REG UPERRX
-#define TIMEOUT_REG UPERRX
-#define CRC16_REG UPERRX
-#define COUNTER0_REG UPERRX
-#define COUNTER1_REG UPERRX
-
-/* USBCON */
-#define VBUSTE_REG USBCON
-#define IDTE_REG USBCON
-#define OTGPADE_REG USBCON
-#define FRZCLK_REG USBCON
-#define HOST_REG USBCON
-#define USBE_REG USBCON
-
-/* UPCONX */
-#define PEN_REG UPCONX
-/* #define RSTDT_REG UPCONX */ /* dup in UECONX */
-#define INMODE_REG UPCONX
-#define PFREEZE_REG UPCONX
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-#define JTRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* UPBCLX */
-#define PBYCT0_REG UPBCLX
-#define PBYCT1_REG UPBCLX
-#define PBYCT2_REG UPBCLX
-#define PBYCT3_REG UPBCLX
-#define PBYCT4_REG UPBCLX
-#define PBYCT5_REG UPBCLX
-#define PBYCT6_REG UPBCLX
-#define PBYCT7_REG UPBCLX
-
-/* UHINT */
-#define DCONNI_REG UHINT
-#define DDISCI_REG UHINT
-#define RSTI_REG UHINT
-#define RSMEDI_REG UHINT
-#define RXRSMI_REG UHINT
-#define HSOFI_REG UHINT
-#define UHUPI_REG UHINT
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* PCIFR */
-#define PCIF0_REG PCIFR
-
-/* TCCR2A */
-#define WGM20_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2B0_REG TCCR2A
-#define COM2B1_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-
-/* TCCR2B */
-#define CS20_REG TCCR2B
-#define CS21_REG TCCR2B
-#define CS22_REG TCCR2B
-#define WGM22_REG TCCR2B
-#define FOC2B_REG TCCR2B
-#define FOC2A_REG TCCR2B
-
-/* UPNUM */
-#define PNUM0_REG UPNUM
-#define PNUM1_REG UPNUM
-#define PNUM2_REG UPNUM
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* MCUCR */
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-#define JTD_REG MCUCR
-
-/* OCR1CL */
-#define OCR1CL0_REG OCR1CL
-#define OCR1CL1_REG OCR1CL
-#define OCR1CL2_REG OCR1CL
-#define OCR1CL3_REG OCR1CL
-#define OCR1CL4_REG OCR1CL
-#define OCR1CL5_REG OCR1CL
-#define OCR1CL6_REG OCR1CL
-#define OCR1CL7_REG OCR1CL
-
-/* OCR1CH */
-#define OCR1CH0_REG OCR1CH
-#define OCR1CH1_REG OCR1CH
-#define OCR1CH2_REG OCR1CH
-#define OCR1CH3_REG OCR1CH
-#define OCR1CH4_REG OCR1CH
-#define OCR1CH5_REG OCR1CH
-#define OCR1CH6_REG OCR1CH
-#define OCR1CH7_REG OCR1CH
-
-/* UPCFG1X */
-/* #define ALLOC_REG UPCFG1X */ /* dup in UECFG1X */
-#define PBK0_REG UPCFG1X
-#define PBK1_REG UPCFG1X
-#define PSIZE0_REG UPCFG1X
-#define PSIZE1_REG UPCFG1X
-#define PSIZE2_REG UPCFG1X
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* USBSTA */
-#define VBUS_REG USBSTA
-#define ID_REG USBSTA
-#define SPEED_REG USBSTA
-
-/* UEIENX */
-#define TXINE_REG UEIENX
-#define STALLEDE_REG UEIENX
-#define RXOUTE_REG UEIENX
-#define RXSTPE_REG UEIENX
-#define NAKOUTE_REG UEIENX
-#define NAKINE_REG UEIENX
-/* #define FLERRE_REG UEIENX */ /* dup in UPIENX */
-
-/* OTGCON */
-#define VBUSRQC_REG OTGCON
-#define VBUSREQ_REG OTGCON
-#define VBUSHWC_REG OTGCON
-#define SRPSEL_REG OTGCON
-#define SRPREQ_REG OTGCON
-#define HNPREQ_REG OTGCON
-
-/* UCSR1B */
-#define TXB81_REG UCSR1B
-#define RXB81_REG UCSR1B
-#define UCSZ12_REG UCSR1B
-#define TXEN1_REG UCSR1B
-#define RXEN1_REG UCSR1B
-#define UDRIE1_REG UCSR1B
-#define TXCIE1_REG UCSR1B
-#define RXCIE1_REG UCSR1B
-
-/* UCSR1C */
-#define UCPOL1_REG UCSR1C
-#define UCSZ10_REG UCSR1C
-#define UCSZ11_REG UCSR1C
-#define USBS1_REG UCSR1C
-#define UPM10_REG UCSR1C
-#define UPM11_REG UCSR1C
-#define UMSEL10_REG UCSR1C
-#define UMSEL11_REG UCSR1C
-
-/* UCSR1A */
-#define MPCM1_REG UCSR1A
-#define U2X1_REG UCSR1A
-#define UPE1_REG UCSR1A
-#define DOR1_REG UCSR1A
-#define FE1_REG UCSR1A
-#define UDRE1_REG UCSR1A
-#define TXC1_REG UCSR1A
-#define RXC1_REG UCSR1A
-
-/* UPINRQX */
-#define INRQ0_REG UPINRQX
-#define INRQ1_REG UPINRQX
-#define INRQ2_REG UPINRQX
-#define INRQ3_REG UPINRQX
-#define INRQ4_REG UPINRQX
-#define INRQ5_REG UPINRQX
-#define INRQ6_REG UPINRQX
-#define INRQ7_REG UPINRQX
-
-/* EIND */
-#define EIND0_REG EIND
-
-/* UDFNUML */
-#define UDFNUML_0_REG UDFNUML
-#define UDFNUML_1_REG UDFNUML
-#define UDFNUML_2_REG UDFNUML
-#define UDFNUML_3_REG UDFNUML
-#define UDFNUML_4_REG UDFNUML
-#define UDFNUML_5_REG UDFNUML
-#define UDFNUML_6_REG UDFNUML
-#define UDFNUML_7_REG UDFNUML
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* UDFNUMH */
-#define UDFNUMH_0_REG UDFNUMH
-#define UDFNUMH_1_REG UDFNUMH
-#define UDFNUMH_2_REG UDFNUMH
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ADHSM_REG ADCSRB
-#define ACME_REG ADCSRB
-
-/* UPINTX */
-#define RXINI_REG UPINTX
-#define RXSTALLI_REG UPINTX
-#define TXOUTI_REG UPINTX
-#define TXSTPI_REG UPINTX
-#define PERRI_REG UPINTX
-/* #define RWAL_REG UPINTX */ /* dup in UEINTX */
-#define NAKEDI_REG UPINTX
-/* #define FIFOCON_REG UPINTX */ /* dup in UEINTX */
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1C0_REG TCCR1A
-#define COM1C1_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* OCR0A */
-#define OCROA_0_REG OCR0A
-#define OCROA_1_REG OCR0A
-#define OCROA_2_REG OCR0A
-#define OCROA_3_REG OCR0A
-#define OCROA_4_REG OCR0A
-#define OCROA_5_REG OCR0A
-#define OCROA_6_REG OCR0A
-#define OCROA_7_REG OCR0A
-
-/* UPCFG2X */
-#define UPCFG2X_0_REG UPCFG2X
-#define UPCFG2X_1_REG UPCFG2X
-#define UPCFG2X_2_REG UPCFG2X
-#define UPCFG2X_3_REG UPCFG2X
-#define UPCFG2X_4_REG UPCFG2X
-#define UPCFG2X_5_REG UPCFG2X
-#define UPCFG2X_6_REG UPCFG2X
-#define UPCFG2X_7_REG UPCFG2X
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* PORTF */
-#define PORTF0_REG PORTF
-#define PORTF1_REG PORTF
-#define PORTF2_REG PORTF
-#define PORTF3_REG PORTF
-#define PORTF4_REG PORTF
-#define PORTF5_REG PORTF
-#define PORTF6_REG PORTF
-#define PORTF7_REG PORTF
-
-/* TCCR1C */
-#define FOC1C_REG TCCR1C
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* ICR3H */
-#define ICR3H0_REG ICR3H
-#define ICR3H1_REG ICR3H
-#define ICR3H2_REG ICR3H
-#define ICR3H3_REG ICR3H
-#define ICR3H4_REG ICR3H
-#define ICR3H5_REG ICR3H
-#define ICR3H6_REG ICR3H
-#define ICR3H7_REG ICR3H
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-#define DDE3_REG DDRE
-#define DDE4_REG DDRE
-#define DDE5_REG DDRE
-#define DDE6_REG DDRE
-#define DDE7_REG DDRE
-
-/* UDADDR */
-#define UADD0_REG UDADDR
-#define UADD1_REG UDADDR
-#define UADD2_REG UDADDR
-#define UADD3_REG UDADDR
-#define UADD4_REG UDADDR
-#define UADD5_REG UDADDR
-#define UADD6_REG UDADDR
-#define ADDEN_REG UDADDR
-
-/* ICR3L */
-#define ICR3L0_REG ICR3L
-#define ICR3L1_REG ICR3L
-#define ICR3L2_REG ICR3L
-#define ICR3L3_REG ICR3L
-#define ICR3L4_REG ICR3L
-#define ICR3L5_REG ICR3L
-#define ICR3L6_REG ICR3L
-#define ICR3L7_REG ICR3L
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-#define PORTE3_REG PORTE
-#define PORTE4_REG PORTE
-#define PORTE5_REG PORTE
-#define PORTE6_REG PORTE
-#define PORTE7_REG PORTE
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define SIGRD_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* UESTA0X */
-#define NBUSYBK0_REG UESTA0X
-#define NBUSYBK1_REG UESTA0X
-/* #define DTSEQ0_REG UESTA0X */ /* dup in UPSTAX */
-/* #define DTSEQ1_REG UESTA0X */ /* dup in UPSTAX */
-/* #define UNDERFI_REG UESTA0X */ /* dup in UPSTAX */
-/* #define OVERFI_REG UESTA0X */ /* dup in UPSTAX */
-/* #define CFGOK_REG UESTA0X */ /* dup in UPSTAX */
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* OCR3BL */
-#define OCR3BL0_REG OCR3BL
-#define OCR3BL1_REG OCR3BL
-#define OCR3BL2_REG OCR3BL
-#define OCR3BL3_REG OCR3BL
-#define OCR3BL4_REG OCR3BL
-#define OCR3BL5_REG OCR3BL
-#define OCR3BL6_REG OCR3BL
-#define OCR3BL7_REG OCR3BL
-
-/* OCR3BH */
-#define OCR3BH0_REG OCR3BH
-#define OCR3BH1_REG OCR3BH
-#define OCR3BH2_REG OCR3BH
-#define OCR3BH3_REG OCR3BH
-#define OCR3BH4_REG OCR3BH
-#define OCR3BH5_REG OCR3BH
-#define OCR3BH6_REG OCR3BH
-#define OCR3BH7_REG OCR3BH
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-#define OCIE2B_REG TIMSK2
-
-/* TIMSK3 */
-#define TOIE3_REG TIMSK3
-#define OCIE3A_REG TIMSK3
-#define OCIE3B_REG TIMSK3
-#define OCIE3C_REG TIMSK3
-#define ICIE3_REG TIMSK3
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define OCIE1C_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* PLLCSR */
-#define PLOCK_REG PLLCSR
-#define PLLE_REG PLLCSR
-#define PLLP0_REG PLLCSR
-#define PLLP1_REG PLLCSR
-#define PLLP2_REG PLLCSR
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* XMCRB */
-#define XMM0_REG XMCRB
-#define XMM1_REG XMCRB
-#define XMM2_REG XMCRB
-#define XMBK_REG XMCRB
-
-/* XMCRA */
-#define SRW00_REG XMCRA
-#define SRW01_REG XMCRA
-#define SRW10_REG XMCRA
-#define SRW11_REG XMCRA
-#define SRL0_REG XMCRA
-#define SRL1_REG XMCRA
-#define SRL2_REG XMCRA
-#define SRE_REG XMCRA
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-#define OCF2B_REG TIFR2
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-#define INTF2_REG EIFR
-#define INTF3_REG EIFR
-#define INTF4_REG EIFR
-#define INTF5_REG EIFR
-#define INTF6_REG EIFR
-#define INTF7_REG EIFR
-
-/* PINF */
-#define PINF0_REG PINF
-#define PINF1_REG PINF
-#define PINF2_REG PINF
-#define PINF3_REG PINF
-#define PINF4_REG PINF
-#define PINF5_REG PINF
-#define PINF6_REG PINF
-#define PINF7_REG PINF
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-#define PINE3_REG PINE
-#define PINE4_REG PINE
-#define PINE5_REG PINE
-#define PINE6_REG PINE
-#define PINE7_REG PINE
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* TWAMR */
-#define TWAM0_REG TWAMR
-#define TWAM1_REG TWAMR
-#define TWAM2_REG TWAMR
-#define TWAM3_REG TWAMR
-#define TWAM4_REG TWAMR
-#define TWAM5_REG TWAMR
-#define TWAM6_REG TWAMR
-
-/* PRR0 */
-#define PRADC_REG PRR0
-#define PRSPI_REG PRR0
-#define PRTIM1_REG PRR0
-#define PRTIM0_REG PRR0
-#define PRTIM2_REG PRR0
-#define PRTWI_REG PRR0
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* PRR1 */
-#define PRUSART1_REG PRR1
-#define PRTIM3_REG PRR1
-#define PRUSB_REG PRR1
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* UPRST */
-#define PRST0_REG UPRST
-#define PRST1_REG UPRST
-#define PRST2_REG UPRST
-#define PRST3_REG UPRST
-#define PRST4_REG UPRST
-#define PRST5_REG UPRST
-#define PRST6_REG UPRST
-
-/* pins mapping */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-/* prescalers timer 3 */
-#define TIMER3_PRESCALER_DIV_0 0
-#define TIMER3_PRESCALER_DIV_1 1
-#define TIMER3_PRESCALER_DIV_8 2
-#define TIMER3_PRESCALER_DIV_64 3
-#define TIMER3_PRESCALER_DIV_256 4
-#define TIMER3_PRESCALER_DIV_1024 5
-#define TIMER3_PRESCALER_DIV_FALL 6
-#define TIMER3_PRESCALER_DIV_RISE 7
-
-#define TIMER3_PRESCALER_REG_0 0
-#define TIMER3_PRESCALER_REG_1 1
-#define TIMER3_PRESCALER_REG_2 8
-#define TIMER3_PRESCALER_REG_3 64
-#define TIMER3_PRESCALER_REG_4 256
-#define TIMER3_PRESCALER_REG_5 1024
-#define TIMER3_PRESCALER_REG_6 -1
-#define TIMER3_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER1C_AVAILABLE
-#define TIMER2_AVAILABLE
-#define TIMER2A_AVAILABLE
-#define TIMER2B_AVAILABLE
-#define TIMER3_AVAILABLE
-#define TIMER3A_AVAILABLE
-#define TIMER3B_AVAILABLE
-#define TIMER3C_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW3_NUM 3
-#define SIG_OVERFLOW_TOTAL_NUM 4
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE1C_NUM 4
-#define SIG_OUTPUT_COMPARE2A_NUM 5
-#define SIG_OUTPUT_COMPARE2B_NUM 6
-#define SIG_OUTPUT_COMPARE3A_NUM 7
-#define SIG_OUTPUT_COMPARE3B_NUM 8
-#define SIG_OUTPUT_COMPARE3C_NUM 9
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 10
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM1C_NUM 4
-#define PWM2A_NUM 5
-#define PWM2B_NUM 6
-#define PWM3A_NUM 7
-#define PWM3B_NUM 8
-#define PWM3C_NUM 9
-#define PWM_TOTAL_NUM 10
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE3_NUM 1
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 2
-
-
-/* UEBCHX */
-#define UEBCHX_0_REG UEBCHX
-#define UEBCHX_1_REG UEBCHX
-#define UEBCHX_2_REG UEBCHX
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* UDIEN */
-#define SUSPE_REG UDIEN
-#define SOFE_REG UDIEN
-#define EORSTE_REG UDIEN
-#define WAKEUPE_REG UDIEN
-#define EORSME_REG UDIEN
-#define UPRSME_REG UDIEN
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* OCR0B */
-#define OCR0B_0_REG OCR0B
-#define OCR0B_1_REG OCR0B
-#define OCR0B_2_REG OCR0B
-#define OCR0B_3_REG OCR0B
-#define OCR0B_4_REG OCR0B
-#define OCR0B_5_REG OCR0B
-#define OCR0B_6_REG OCR0B
-#define OCR0B_7_REG OCR0B
-
-/* UPIENX */
-#define RXINE_REG UPIENX
-#define RXSTALLE_REG UPIENX
-#define TXOUTE_REG UPIENX
-#define TXSTPE_REG UPIENX
-#define PERRE_REG UPIENX
-#define NAKEDE_REG UPIENX
-/* #define FLERRE_REG UPIENX */ /* dup in UEIENX */
-
-/* UDINT */
-#define SUSPI_REG UDINT
-#define SOFI_REG UDINT
-#define EORSTI_REG UDINT
-#define WAKEUPI_REG UDINT
-#define EORSMI_REG UDINT
-#define UPRSMI_REG UDINT
-
-/* UERST */
-#define EPRST0_REG UERST
-#define EPRST1_REG UERST
-#define EPRST2_REG UERST
-#define EPRST3_REG UERST
-#define EPRST4_REG UERST
-#define EPRST5_REG UERST
-#define EPRST6_REG UERST
-
-/* RAMPZ */
-#define RAMPZ0_REG RAMPZ
-
-/* UECFG1X */
-/* #define ALLOC_REG UECFG1X */ /* dup in UPCFG1X */
-#define EPBK0_REG UECFG1X
-#define EPBK1_REG UECFG1X
-#define EPSIZE0_REG UECFG1X
-#define EPSIZE1_REG UECFG1X
-#define EPSIZE2_REG UECFG1X
-
-/* UECONX */
-#define EPEN_REG UECONX
-/* #define RSTDT_REG UECONX */ /* dup in UPCONX */
-#define STALLRQC_REG UECONX
-#define STALLRQ_REG UECONX
-
-/* OCR2A */
-#define OCR2A_0_REG OCR2A
-#define OCR2A_1_REG OCR2A
-#define OCR2A_2_REG OCR2A
-#define OCR2A_3_REG OCR2A
-#define OCR2A_4_REG OCR2A
-#define OCR2A_5_REG OCR2A
-#define OCR2A_6_REG OCR2A
-#define OCR2A_7_REG OCR2A
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* OTGIEN */
-#define SRPE_REG OTGIEN
-#define VBERRE_REG OTGIEN
-#define BCERRE_REG OTGIEN
-#define ROLEEXE_REG OTGIEN
-#define HNPERRE_REG OTGIEN
-#define STOE_REG OTGIEN
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* UEINT */
-#define EPINT0_REG UEINT
-#define EPINT1_REG UEINT
-#define EPINT2_REG UEINT
-#define EPINT3_REG UEINT
-#define EPINT4_REG UEINT
-#define EPINT5_REG UEINT
-#define EPINT6_REG UEINT
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* OTGTCON */
-#define VALUE_20_REG OTGTCON
-#define VALUE_21_REG OTGTCON
-#define VALUE_22_REG OTGTCON
-#define PAGE0_REG OTGTCON
-#define PAGE1_REG OTGTCON
-#define OTGTCON_7_REG OTGTCON
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* UPBCHX */
-#define PBYCT8_REG UPBCHX
-#define PBYCT9_REG UPBCHX
-#define PBYCT10_REG UPBCHX
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-#define INT3_REG EIMSK
-#define INT4_REG EIMSK
-#define INT5_REG EIMSK
-#define INT6_REG EIMSK
-#define INT7_REG EIMSK
-
-/* UDR1 */
-#define UDR1_0_REG UDR1
-#define UDR1_1_REG UDR1
-#define UDR1_2_REG UDR1
-#define UDR1_3_REG UDR1
-#define UDR1_4_REG UDR1
-#define UDR1_5_REG UDR1
-#define UDR1_6_REG UDR1
-#define UDR1_7_REG UDR1
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* EICRB */
-#define ISC40_REG EICRB
-#define ISC41_REG EICRB
-#define ISC50_REG EICRB
-#define ISC51_REG EICRB
-#define ISC60_REG EICRB
-#define ISC61_REG EICRB
-#define ISC70_REG EICRB
-#define ISC71_REG EICRB
-
-/* UEDATX */
-#define UEDATX_0_REG UEDATX
-#define UEDATX_1_REG UEDATX
-#define UEDATX_2_REG UEDATX
-#define UEDATX_3_REG UEDATX
-#define UEDATX_4_REG UEDATX
-#define UEDATX_5_REG UEDATX
-#define UEDATX_6_REG UEDATX
-#define UEDATX_7_REG UEDATX
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-#define ISC20_REG EICRA
-#define ISC21_REG EICRA
-#define ISC30_REG EICRA
-#define ISC31_REG EICRA
-
-/* OTGINT */
-#define SRPI_REG OTGINT
-#define VBERRI_REG OTGINT
-#define BCERRI_REG OTGINT
-#define ROLEEXI_REG OTGINT
-#define HNPERRI_REG OTGINT
-#define STOI_REG OTGINT
-
-/* UECFG0X */
-#define EPDIR_REG UECFG0X
-#define EPTYPE0_REG UECFG0X
-#define EPTYPE1_REG UECFG0X
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* DDRF */
-#define DDF0_REG DDRF
-#define DDF1_REG DDRF
-#define DDF2_REG DDRF
-#define DDF3_REG DDRF
-#define DDF4_REG DDRF
-#define DDF5_REG DDRF
-#define DDF6_REG DDRF
-#define DDF7_REG DDRF
-
-/* ASSR */
-#define TCR2BUB_REG ASSR
-#define TCR2AUB_REG ASSR
-#define OCR2BUB_REG ASSR
-#define OCR2AUB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* UHIEN */
-#define DCONNE_REG UHIEN
-#define DDISCE_REG UHIEN
-#define RSTE_REG UHIEN
-#define RSMEDE_REG UHIEN
-#define RXRSME_REG UHIEN
-#define HSOFE_REG UHIEN
-#define HWUPE_REG UHIEN
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* UENUM */
-#define UENUM_0_REG UENUM
-#define UENUM_1_REG UENUM
-#define UENUM_2_REG UENUM
-
-/* UBRR1L */
-#define UBRR_0_REG UBRR1L
-#define UBRR_1_REG UBRR1L
-#define UBRR_2_REG UBRR1L
-#define UBRR_3_REG UBRR1L
-#define UBRR_4_REG UBRR1L
-#define UBRR_5_REG UBRR1L
-#define UBRR_6_REG UBRR1L
-#define UBRR_7_REG UBRR1L
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* OCR3AL */
-#define OCR3AL0_REG OCR3AL
-#define OCR3AL1_REG OCR3AL
-#define OCR3AL2_REG OCR3AL
-#define OCR3AL3_REG OCR3AL
-#define OCR3AL4_REG OCR3AL
-#define OCR3AL5_REG OCR3AL
-#define OCR3AL6_REG OCR3AL
-#define OCR3AL7_REG OCR3AL
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* UBRR1H */
-#define UBRR_8_REG UBRR1H
-#define UBRR_9_REG UBRR1H
-#define UBRR_10_REG UBRR1H
-#define UBRR_11_REG UBRR1H
-
-/* OCR3AH */
-#define OCR3AH0_REG OCR3AH
-#define OCR3AH1_REG OCR3AH
-#define OCR3AH2_REG OCR3AH
-#define OCR3AH3_REG OCR3AH
-#define OCR3AH4_REG OCR3AH
-#define OCR3AH5_REG OCR3AH
-#define OCR3AH6_REG OCR3AH
-#define OCR3AH7_REG OCR3AH
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* UHADDR */
-#define UHADDR_0_REG UHADDR
-#define UHADDR_1_REG UHADDR
-#define UHADDR_2_REG UHADDR
-#define UHADDR_3_REG UHADDR
-#define UHADDR_4_REG UHADDR
-#define UHADDR_5_REG UHADDR
-#define UHADDR_6_REG UHADDR
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* UDCON */
-#define DETACH_REG UDCON
-#define RMWKUP_REG UDCON
-#define LSM_REG UDCON
-
-/* UHFLEN */
-#define UHFLEN_0_REG UHFLEN
-#define UHFLEN_1_REG UHFLEN
-#define UHFLEN_2_REG UHFLEN
-#define UHFLEN_3_REG UHFLEN
-#define UHFLEN_4_REG UHFLEN
-#define UHFLEN_5_REG UHFLEN
-#define UHFLEN_6_REG UHFLEN
-#define UHFLEN_7_REG UHFLEN
-
-/* UHFNUMH */
-#define UHFNUMH_0_REG UHFNUMH
-#define UHFNUMH_1_REG UHFNUMH
-#define UHFNUMH_2_REG UHFNUMH
-
-/* UHFNUML */
-#define UHFNUML_0_REG UHFNUML
-#define UHFNUML_1_REG UHFNUML
-#define UHFNUML_2_REG UHFNUML
-#define UHFNUML_3_REG UHFNUML
-#define UHFNUML_4_REG UHFNUML
-#define UHFNUML_5_REG UHFNUML
-#define UHFNUML_6_REG UHFNUML
-#define UHFNUML_7_REG UHFNUML
-
-/* PCICR */
-#define PCIE0_REG PCICR
-
-/* USBINT */
-#define VBUSTI_REG USBINT
-#define IDTI_REG USBINT
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* UHWCON */
-#define UVREGE_REG UHWCON
-#define UVCONE_REG UHWCON
-#define UIDE_REG UHWCON
-#define UIMOD_REG UHWCON
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* UDMFN */
-#define FNCERR_REG UDMFN
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* UPDATX */
-#define PDAT0_REG UPDATX
-#define PDAT1_REG UPDATX
-#define PDAT2_REG UPDATX
-#define PDAT3_REG UPDATX
-#define PDAT4_REG UPDATX
-#define PDAT5_REG UPDATX
-#define PDAT6_REG UPDATX
-#define PDAT7_REG UPDATX
-
-/* OCR2B */
-#define OCR2B_0_REG OCR2B
-#define OCR2B_1_REG OCR2B
-#define OCR2B_2_REG OCR2B
-#define OCR2B_3_REG OCR2B
-#define OCR2B_4_REG OCR2B
-#define OCR2B_5_REG OCR2B
-#define OCR2B_6_REG OCR2B
-#define OCR2B_7_REG OCR2B
-
-/* UHCON */
-#define SOFEN_REG UHCON
-#define RESET_REG UHCON
-#define RESUME_REG UHCON
-
-/* TIFR3 */
-#define TOV3_REG TIFR3
-#define OCF3A_REG TIFR3
-#define OCF3B_REG TIFR3
-#define OCF3C_REG TIFR3
-#define ICF3_REG TIFR3
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define OCF1C_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-#define EEAR10_REG EEARH
-#define EEAR11_REG EEARH
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* UPINT */
-#define PINT0_REG UPINT
-#define PINT1_REG UPINT
-#define PINT2_REG UPINT
-#define PINT3_REG UPINT
-#define PINT4_REG UPINT
-#define PINT5_REG UPINT
-#define PINT6_REG UPINT
-
-/* UEBCLX */
-#define UEBCLX_0_REG UEBCLX
-#define UEBCLX_1_REG UEBCLX
-#define UEBCLX_2_REG UEBCLX
-#define UEBCLX_3_REG UEBCLX
-#define UEBCLX_4_REG UEBCLX
-#define UEBCLX_5_REG UEBCLX
-#define UEBCLX_6_REG UEBCLX
-#define UEBCLX_7_REG UEBCLX
-
-/* OCR3CH */
-#define OCR3CH0_REG OCR3CH
-#define OCR3CH1_REG OCR3CH
-#define OCR3CH2_REG OCR3CH
-#define OCR3CH3_REG OCR3CH
-#define OCR3CH4_REG OCR3CH
-#define OCR3CH5_REG OCR3CH
-#define OCR3CH6_REG OCR3CH
-#define OCR3CH7_REG OCR3CH
-
-/* UESTA1X */
-#define CURRBK0_REG UESTA1X
-#define CURRBK1_REG UESTA1X
-#define CTRLDIR_REG UESTA1X
-
-/* OCR3CL */
-#define OCR3CL0_REG OCR3CL
-#define OCR3CL1_REG OCR3CL
-#define OCR3CL2_REG OCR3CL
-#define OCR3CL3_REG OCR3CL
-#define OCR3CL4_REG OCR3CL
-#define OCR3CL5_REG OCR3CL
-#define OCR3CL6_REG OCR3CL
-#define OCR3CL7_REG OCR3CL
-
-/* GTCCR */
-#define PSRSYNC_REG GTCCR
-#define TSM_REG GTCCR
-#define PSRASY_REG GTCCR
-
-/* UPSTAX */
-#define NBUSYK0_REG UPSTAX
-#define NBUSYK1_REG UPSTAX
-/* #define DTSEQ0_REG UPSTAX */ /* dup in UESTA0X */
-/* #define DTSEQ1_REG UPSTAX */ /* dup in UESTA0X */
-/* #define UNDERFI_REG UPSTAX */ /* dup in UESTA0X */
-/* #define OVERFI_REG UPSTAX */ /* dup in UESTA0X */
-/* #define CFGOK_REG UPSTAX */ /* dup in UESTA0X */
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* TCCR3C */
-#define FOC3C_REG TCCR3C
-#define FOC3B_REG TCCR3C
-#define FOC3A_REG TCCR3C
-
-/* TCCR3B */
-#define CS30_REG TCCR3B
-#define CS31_REG TCCR3B
-#define CS32_REG TCCR3B
-#define WGM32_REG TCCR3B
-#define WGM33_REG TCCR3B
-#define ICES3_REG TCCR3B
-#define ICNC3_REG TCCR3B
-
-/* TCCR3A */
-#define WGM30_REG TCCR3A
-#define WGM31_REG TCCR3A
-#define COM3C0_REG TCCR3A
-#define COM3C1_REG TCCR3A
-#define COM3B0_REG TCCR3A
-#define COM3B1_REG TCCR3A
-#define COM3A0_REG TCCR3A
-#define COM3A1_REG TCCR3A
-
-/* UEINTX */
-#define TXINI_REG UEINTX
-#define STALLEDI_REG UEINTX
-#define RXOUTI_REG UEINTX
-#define RXSTPI_REG UEINTX
-#define NAKOUTI_REG UEINTX
-/* #define RWAL_REG UEINTX */ /* dup in UPINTX */
-#define NAKINI_REG UEINTX
-/* #define FIFOCON_REG UEINTX */ /* dup in UPINTX */
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* TCNT3H */
-#define TCNT3H0_REG TCNT3H
-#define TCNT3H1_REG TCNT3H
-#define TCNT3H2_REG TCNT3H
-#define TCNT3H3_REG TCNT3H
-#define TCNT3H4_REG TCNT3H
-#define TCNT3H5_REG TCNT3H
-#define TCNT3H6_REG TCNT3H
-#define TCNT3H7_REG TCNT3H
-
-/* UPCFG0X */
-#define PEPNUM0_REG UPCFG0X
-#define PEPNUM1_REG UPCFG0X
-#define PEPNUM2_REG UPCFG0X
-#define PEPNUM3_REG UPCFG0X
-#define PTOKEN0_REG UPCFG0X
-#define PTOKEN1_REG UPCFG0X
-#define PTYPE0_REG UPCFG0X
-#define PTYPE1_REG UPCFG0X
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* TCNT3L */
-#define TCNT3L0_REG TCNT3L
-#define TCNT3L1_REG TCNT3L
-#define TCNT3L2_REG TCNT3L
-#define TCNT3L3_REG TCNT3L
-#define TCNT3L4_REG TCNT3L
-#define TCNT3L5_REG TCNT3L
-#define TCNT3L6_REG TCNT3L
-#define TCNT3L7_REG TCNT3L
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* UPERRX */
-#define DATATGL_REG UPERRX
-#define DATAPID_REG UPERRX
-#define PID_REG UPERRX
-#define TIMEOUT_REG UPERRX
-#define CRC16_REG UPERRX
-#define COUNTER0_REG UPERRX
-#define COUNTER1_REG UPERRX
-
-/* USBCON */
-#define VBUSTE_REG USBCON
-#define IDTE_REG USBCON
-#define OTGPADE_REG USBCON
-#define FRZCLK_REG USBCON
-#define HOST_REG USBCON
-#define USBE_REG USBCON
-
-/* UPCONX */
-#define PEN_REG UPCONX
-/* #define RSTDT_REG UPCONX */ /* dup in UECONX */
-#define INMODE_REG UPCONX
-#define PFREEZE_REG UPCONX
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-#define JTRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* UPBCLX */
-#define PBYCT0_REG UPBCLX
-#define PBYCT1_REG UPBCLX
-#define PBYCT2_REG UPBCLX
-#define PBYCT3_REG UPBCLX
-#define PBYCT4_REG UPBCLX
-#define PBYCT5_REG UPBCLX
-#define PBYCT6_REG UPBCLX
-#define PBYCT7_REG UPBCLX
-
-/* UHINT */
-#define DCONNI_REG UHINT
-#define DDISCI_REG UHINT
-#define RSTI_REG UHINT
-#define RSMEDI_REG UHINT
-#define RXRSMI_REG UHINT
-#define HSOFI_REG UHINT
-#define UHUPI_REG UHINT
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* PCIFR */
-#define PCIF0_REG PCIFR
-
-/* TCCR2A */
-#define WGM20_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2B0_REG TCCR2A
-#define COM2B1_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-
-/* TCCR2B */
-#define CS20_REG TCCR2B
-#define CS21_REG TCCR2B
-#define CS22_REG TCCR2B
-#define WGM22_REG TCCR2B
-#define FOC2B_REG TCCR2B
-#define FOC2A_REG TCCR2B
-
-/* UPNUM */
-#define PNUM0_REG UPNUM
-#define PNUM1_REG UPNUM
-#define PNUM2_REG UPNUM
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* MCUCR */
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-#define JTD_REG MCUCR
-
-/* OCR1CL */
-#define OCR1CL0_REG OCR1CL
-#define OCR1CL1_REG OCR1CL
-#define OCR1CL2_REG OCR1CL
-#define OCR1CL3_REG OCR1CL
-#define OCR1CL4_REG OCR1CL
-#define OCR1CL5_REG OCR1CL
-#define OCR1CL6_REG OCR1CL
-#define OCR1CL7_REG OCR1CL
-
-/* OCR1CH */
-#define OCR1CH0_REG OCR1CH
-#define OCR1CH1_REG OCR1CH
-#define OCR1CH2_REG OCR1CH
-#define OCR1CH3_REG OCR1CH
-#define OCR1CH4_REG OCR1CH
-#define OCR1CH5_REG OCR1CH
-#define OCR1CH6_REG OCR1CH
-#define OCR1CH7_REG OCR1CH
-
-/* UPCFG1X */
-/* #define ALLOC_REG UPCFG1X */ /* dup in UECFG1X */
-#define PBK0_REG UPCFG1X
-#define PBK1_REG UPCFG1X
-#define PSIZE0_REG UPCFG1X
-#define PSIZE1_REG UPCFG1X
-#define PSIZE2_REG UPCFG1X
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* USBSTA */
-#define VBUS_REG USBSTA
-#define ID_REG USBSTA
-#define SPEED_REG USBSTA
-
-/* UEIENX */
-#define TXINE_REG UEIENX
-#define STALLEDE_REG UEIENX
-#define RXOUTE_REG UEIENX
-#define RXSTPE_REG UEIENX
-#define NAKOUTE_REG UEIENX
-#define NAKINE_REG UEIENX
-/* #define FLERRE_REG UEIENX */ /* dup in UPIENX */
-
-/* OTGCON */
-#define VBUSRQC_REG OTGCON
-#define VBUSREQ_REG OTGCON
-#define VBUSHWC_REG OTGCON
-#define SRPSEL_REG OTGCON
-#define SRPREQ_REG OTGCON
-#define HNPREQ_REG OTGCON
-
-/* UCSR1B */
-#define TXB81_REG UCSR1B
-#define RXB81_REG UCSR1B
-#define UCSZ12_REG UCSR1B
-#define TXEN1_REG UCSR1B
-#define RXEN1_REG UCSR1B
-#define UDRIE1_REG UCSR1B
-#define TXCIE1_REG UCSR1B
-#define RXCIE1_REG UCSR1B
-
-/* UCSR1C */
-#define UCPOL1_REG UCSR1C
-#define UCSZ10_REG UCSR1C
-#define UCSZ11_REG UCSR1C
-#define USBS1_REG UCSR1C
-#define UPM10_REG UCSR1C
-#define UPM11_REG UCSR1C
-#define UMSEL10_REG UCSR1C
-#define UMSEL11_REG UCSR1C
-
-/* UCSR1A */
-#define MPCM1_REG UCSR1A
-#define U2X1_REG UCSR1A
-#define UPE1_REG UCSR1A
-#define DOR1_REG UCSR1A
-#define FE1_REG UCSR1A
-#define UDRE1_REG UCSR1A
-#define TXC1_REG UCSR1A
-#define RXC1_REG UCSR1A
-
-/* UPINRQX */
-#define INRQ0_REG UPINRQX
-#define INRQ1_REG UPINRQX
-#define INRQ2_REG UPINRQX
-#define INRQ3_REG UPINRQX
-#define INRQ4_REG UPINRQX
-#define INRQ5_REG UPINRQX
-#define INRQ6_REG UPINRQX
-#define INRQ7_REG UPINRQX
-
-/* EIND */
-#define EIND0_REG EIND
-
-/* UDFNUML */
-#define UDFNUML_0_REG UDFNUML
-#define UDFNUML_1_REG UDFNUML
-#define UDFNUML_2_REG UDFNUML
-#define UDFNUML_3_REG UDFNUML
-#define UDFNUML_4_REG UDFNUML
-#define UDFNUML_5_REG UDFNUML
-#define UDFNUML_6_REG UDFNUML
-#define UDFNUML_7_REG UDFNUML
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* UDFNUMH */
-#define UDFNUMH_0_REG UDFNUMH
-#define UDFNUMH_1_REG UDFNUMH
-#define UDFNUMH_2_REG UDFNUMH
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ADHSM_REG ADCSRB
-#define ACME_REG ADCSRB
-
-/* UPINTX */
-#define RXINI_REG UPINTX
-#define RXSTALLI_REG UPINTX
-#define TXOUTI_REG UPINTX
-#define TXSTPI_REG UPINTX
-#define PERRI_REG UPINTX
-/* #define RWAL_REG UPINTX */ /* dup in UEINTX */
-#define NAKEDI_REG UPINTX
-/* #define FIFOCON_REG UPINTX */ /* dup in UEINTX */
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1C0_REG TCCR1A
-#define COM1C1_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* OCR0A */
-#define OCROA_0_REG OCR0A
-#define OCROA_1_REG OCR0A
-#define OCROA_2_REG OCR0A
-#define OCROA_3_REG OCR0A
-#define OCROA_4_REG OCR0A
-#define OCROA_5_REG OCR0A
-#define OCROA_6_REG OCR0A
-#define OCROA_7_REG OCR0A
-
-/* UPCFG2X */
-#define UPCFG2X_0_REG UPCFG2X
-#define UPCFG2X_1_REG UPCFG2X
-#define UPCFG2X_2_REG UPCFG2X
-#define UPCFG2X_3_REG UPCFG2X
-#define UPCFG2X_4_REG UPCFG2X
-#define UPCFG2X_5_REG UPCFG2X
-#define UPCFG2X_6_REG UPCFG2X
-#define UPCFG2X_7_REG UPCFG2X
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* PORTF */
-#define PORTF0_REG PORTF
-#define PORTF1_REG PORTF
-#define PORTF2_REG PORTF
-#define PORTF3_REG PORTF
-#define PORTF4_REG PORTF
-#define PORTF5_REG PORTF
-#define PORTF6_REG PORTF
-#define PORTF7_REG PORTF
-
-/* TCCR1C */
-#define FOC1C_REG TCCR1C
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* ICR3H */
-#define ICR3H0_REG ICR3H
-#define ICR3H1_REG ICR3H
-#define ICR3H2_REG ICR3H
-#define ICR3H3_REG ICR3H
-#define ICR3H4_REG ICR3H
-#define ICR3H5_REG ICR3H
-#define ICR3H6_REG ICR3H
-#define ICR3H7_REG ICR3H
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-#define DDE3_REG DDRE
-#define DDE4_REG DDRE
-#define DDE5_REG DDRE
-#define DDE6_REG DDRE
-#define DDE7_REG DDRE
-
-/* UDADDR */
-#define UADD0_REG UDADDR
-#define UADD1_REG UDADDR
-#define UADD2_REG UDADDR
-#define UADD3_REG UDADDR
-#define UADD4_REG UDADDR
-#define UADD5_REG UDADDR
-#define UADD6_REG UDADDR
-#define ADDEN_REG UDADDR
-
-/* ICR3L */
-#define ICR3L0_REG ICR3L
-#define ICR3L1_REG ICR3L
-#define ICR3L2_REG ICR3L
-#define ICR3L3_REG ICR3L
-#define ICR3L4_REG ICR3L
-#define ICR3L5_REG ICR3L
-#define ICR3L6_REG ICR3L
-#define ICR3L7_REG ICR3L
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-#define PORTE3_REG PORTE
-#define PORTE4_REG PORTE
-#define PORTE5_REG PORTE
-#define PORTE6_REG PORTE
-#define PORTE7_REG PORTE
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define SIGRD_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* UESTA0X */
-#define NBUSYBK0_REG UESTA0X
-#define NBUSYBK1_REG UESTA0X
-/* #define DTSEQ0_REG UESTA0X */ /* dup in UPSTAX */
-/* #define DTSEQ1_REG UESTA0X */ /* dup in UPSTAX */
-/* #define UNDERFI_REG UESTA0X */ /* dup in UPSTAX */
-/* #define OVERFI_REG UESTA0X */ /* dup in UPSTAX */
-/* #define CFGOK_REG UESTA0X */ /* dup in UPSTAX */
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* OCR3BL */
-#define OCR3BL0_REG OCR3BL
-#define OCR3BL1_REG OCR3BL
-#define OCR3BL2_REG OCR3BL
-#define OCR3BL3_REG OCR3BL
-#define OCR3BL4_REG OCR3BL
-#define OCR3BL5_REG OCR3BL
-#define OCR3BL6_REG OCR3BL
-#define OCR3BL7_REG OCR3BL
-
-/* OCR3BH */
-#define OCR3BH0_REG OCR3BH
-#define OCR3BH1_REG OCR3BH
-#define OCR3BH2_REG OCR3BH
-#define OCR3BH3_REG OCR3BH
-#define OCR3BH4_REG OCR3BH
-#define OCR3BH5_REG OCR3BH
-#define OCR3BH6_REG OCR3BH
-#define OCR3BH7_REG OCR3BH
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-#define OCIE2B_REG TIMSK2
-
-/* TIMSK3 */
-#define TOIE3_REG TIMSK3
-#define OCIE3A_REG TIMSK3
-#define OCIE3B_REG TIMSK3
-#define OCIE3C_REG TIMSK3
-#define ICIE3_REG TIMSK3
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define OCIE1C_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* PLLCSR */
-#define PLOCK_REG PLLCSR
-#define PLLE_REG PLLCSR
-#define PLLP0_REG PLLCSR
-#define PLLP1_REG PLLCSR
-#define PLLP2_REG PLLCSR
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* XMCRB */
-#define XMM0_REG XMCRB
-#define XMM1_REG XMCRB
-#define XMM2_REG XMCRB
-#define XMBK_REG XMCRB
-
-/* XMCRA */
-#define SRW00_REG XMCRA
-#define SRW01_REG XMCRA
-#define SRW10_REG XMCRA
-#define SRW11_REG XMCRA
-#define SRL0_REG XMCRA
-#define SRL1_REG XMCRA
-#define SRL2_REG XMCRA
-#define SRE_REG XMCRA
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-#define OCF2B_REG TIFR2
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-#define INTF2_REG EIFR
-#define INTF3_REG EIFR
-#define INTF4_REG EIFR
-#define INTF5_REG EIFR
-#define INTF6_REG EIFR
-#define INTF7_REG EIFR
-
-/* PINF */
-#define PINF0_REG PINF
-#define PINF1_REG PINF
-#define PINF2_REG PINF
-#define PINF3_REG PINF
-#define PINF4_REG PINF
-#define PINF5_REG PINF
-#define PINF6_REG PINF
-#define PINF7_REG PINF
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-#define PINE3_REG PINE
-#define PINE4_REG PINE
-#define PINE5_REG PINE
-#define PINE6_REG PINE
-#define PINE7_REG PINE
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* TWAMR */
-#define TWAM0_REG TWAMR
-#define TWAM1_REG TWAMR
-#define TWAM2_REG TWAMR
-#define TWAM3_REG TWAMR
-#define TWAM4_REG TWAMR
-#define TWAM5_REG TWAMR
-#define TWAM6_REG TWAMR
-
-/* PRR0 */
-#define PRADC_REG PRR0
-#define PRSPI_REG PRR0
-#define PRTIM1_REG PRR0
-#define PRTIM0_REG PRR0
-#define PRTIM2_REG PRR0
-#define PRTWI_REG PRR0
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* PRR1 */
-#define PRUSART1_REG PRR1
-#define PRTIM3_REG PRR1
-#define PRUSB_REG PRR1
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* UPRST */
-#define PRST0_REG UPRST
-#define PRST1_REG UPRST
-#define PRST2_REG UPRST
-#define PRST3_REG UPRST
-#define PRST4_REG UPRST
-#define PRST5_REG UPRST
-#define PRST6_REG UPRST
-
-/* pins mapping */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER1C_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW_TOTAL_NUM 2
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE1C_NUM 4
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 5
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM1C_NUM 4
-#define PWM_TOTAL_NUM 5
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* UDIEN */
-#define SUSPE_REG UDIEN
-#define SOFE_REG UDIEN
-#define EORSTE_REG UDIEN
-#define WAKEUPE_REG UDIEN
-#define EORSME_REG UDIEN
-#define UPRSME_REG UDIEN
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* PS2CON */
-#define PS2EN_REG PS2CON
-
-/* UERST */
-#define EPRST0_REG UERST
-#define EPRST1_REG UERST
-#define EPRST2_REG UERST
-#define EPRST3_REG UERST
-#define EPRST4_REG UERST
-
-/* UECFG1X */
-#define ALLOC_REG UECFG1X
-#define EPBK0_REG UECFG1X
-#define EPBK1_REG UECFG1X
-#define EPSIZE0_REG UECFG1X
-#define EPSIZE1_REG UECFG1X
-#define EPSIZE2_REG UECFG1X
-
-/* UDR1 */
-#define UDR1_0_REG UDR1
-#define UDR1_1_REG UDR1
-#define UDR1_2_REG UDR1
-#define UDR1_3_REG UDR1
-#define UDR1_4_REG UDR1
-#define UDR1_5_REG UDR1
-#define UDR1_6_REG UDR1
-#define UDR1_7_REG UDR1
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* UEINT */
-#define EPINT0_REG UEINT
-#define EPINT1_REG UEINT
-#define EPINT2_REG UEINT
-#define EPINT3_REG UEINT
-#define EPINT4_REG UEINT
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* REGCR */
-#define REGDIS_REG REGCR
-
-/* EICRB */
-#define ISC40_REG EICRB
-#define ISC41_REG EICRB
-#define ISC50_REG EICRB
-#define ISC51_REG EICRB
-#define ISC60_REG EICRB
-#define ISC61_REG EICRB
-#define ISC70_REG EICRB
-#define ISC71_REG EICRB
-
-/* UEDATX */
-#define DAT0_REG UEDATX
-#define DAT1_REG UEDATX
-#define DAT2_REG UEDATX
-#define DAT3_REG UEDATX
-#define DAT4_REG UEDATX
-#define DAT5_REG UEDATX
-#define DAT6_REG UEDATX
-#define DAT7_REG UEDATX
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-#define ISC20_REG EICRA
-#define ISC21_REG EICRA
-#define ISC30_REG EICRA
-#define ISC31_REG EICRA
-
-/* UECFG0X */
-#define EPDIR_REG UECFG0X
-#define EPTYPE0_REG UECFG0X
-#define EPTYPE1_REG UECFG0X
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* CLKSEL1 */
-#define EXCKSEL0_REG CLKSEL1
-#define EXCKSEL1_REG CLKSEL1
-#define EXCKSEL2_REG CLKSEL1
-#define EXCKSEL3_REG CLKSEL1
-#define RCCKSEL0_REG CLKSEL1
-#define RCCKSEL1_REG CLKSEL1
-#define RCCKSEL2_REG CLKSEL1
-#define RCCKSEL3_REG CLKSEL1
-
-/* CLKSEL0 */
-#define CLKS_REG CLKSEL0
-#define EXTE_REG CLKSEL0
-#define RCE_REG CLKSEL0
-#define EXSUT0_REG CLKSEL0
-#define EXSUT1_REG CLKSEL0
-#define RCSUT0_REG CLKSEL0
-#define RCSUT1_REG CLKSEL0
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* UPOE */
-#define DMI_REG UPOE
-#define DPI_REG UPOE
-#define DATAI_REG UPOE
-#define SCKI_REG UPOE
-#define UPDRV0_REG UPOE
-#define UPDRV1_REG UPOE
-#define UPWE0_REG UPOE
-#define UPWE1_REG UPOE
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* UENUM */
-#define EPNUM0_REG UENUM
-#define EPNUM1_REG UENUM
-#define EPNUM2_REG UENUM
-
-/* UBRR1L */
-#define UBRR1_0_REG UBRR1L
-#define UBRR1_1_REG UBRR1L
-#define UBRR1_2_REG UBRR1L
-#define UBRR1_3_REG UBRR1L
-#define UBRR1_4_REG UBRR1L
-#define UBRR1_5_REG UBRR1L
-#define UBRR1_6_REG UBRR1L
-#define UBRR1_7_REG UBRR1L
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1C0_REG TCCR1A
-#define COM1C1_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* TCCR1C */
-#define FOC1C_REG TCCR1C
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* UDCON */
-#define DETACH_REG UDCON
-#define RMWKUP_REG UDCON
-#define RSTCPU_REG UDCON
-
-/* WDTCKD */
-#define WCLKD0_REG WDTCKD
-#define WCLKD1_REG WDTCKD
-#define WDEWIE_REG WDTCKD
-#define WDEWIF_REG WDTCKD
-
-/* PCICR */
-#define PCIE0_REG PCICR
-#define PCIE1_REG PCICR
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* UDINT */
-#define SUSPI_REG UDINT
-#define SOFI_REG UDINT
-#define EORSTI_REG UDINT
-#define WAKEUPI_REG UDINT
-#define EORSMI_REG UDINT
-#define UPRSMI_REG UDINT
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* UDMFN */
-#define FNCERR_REG UDMFN
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* DWDR */
-#define DWDR0_REG DWDR
-#define DWDR1_REG DWDR
-#define DWDR2_REG DWDR
-#define DWDR3_REG DWDR
-#define DWDR4_REG DWDR
-#define DWDR5_REG DWDR
-#define DWDR6_REG DWDR
-#define DWDR7_REG DWDR
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define OCF1C_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* UEBCLX */
-#define BYCT0_REG UEBCLX
-#define BYCT1_REG UEBCLX
-#define BYCT2_REG UEBCLX
-#define BYCT3_REG UEBCLX
-#define BYCT4_REG UEBCLX
-#define BYCT5_REG UEBCLX
-#define BYCT6_REG UEBCLX
-#define BYCT7_REG UEBCLX
-
-/* UESTA1X */
-#define CURRBK0_REG UESTA1X
-#define CURRBK1_REG UESTA1X
-#define CTRLDIR_REG UESTA1X
-
-/* GTCCR */
-#define PSRSYNC_REG GTCCR
-#define TSM_REG GTCCR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* UEINTX */
-#define TXINI_REG UEINTX
-#define STALLEDI_REG UEINTX
-#define RXOUTI_REG UEINTX
-#define RXSTPI_REG UEINTX
-#define NAKOUTI_REG UEINTX
-#define RWAL_REG UEINTX
-#define NAKINI_REG UEINTX
-#define FIFOCON_REG UEINTX
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* USBCON */
-#define FRZCLK_REG USBCON
-#define USBE_REG USBCON
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-#define USBRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* PCIFR */
-#define PCIF0_REG PCIFR
-#define PCIF1_REG PCIFR
-
-/* UECONX */
-#define EPEN_REG UECONX
-#define RSTDT_REG UECONX
-#define STALLRQC_REG UECONX
-#define STALLRQ_REG UECONX
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-#define EEAR10_REG EEARH
-#define EEAR11_REG EEARH
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* MCUCR */
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-
-/* OCR1CL */
-#define OCR1CL0_REG OCR1CL
-#define OCR1CL1_REG OCR1CL
-#define OCR1CL2_REG OCR1CL
-#define OCR1CL3_REG OCR1CL
-#define OCR1CL4_REG OCR1CL
-#define OCR1CL5_REG OCR1CL
-#define OCR1CL6_REG OCR1CL
-#define OCR1CL7_REG OCR1CL
-
-/* OCR1CH */
-#define OCR1CH0_REG OCR1CH
-#define OCR1CH1_REG OCR1CH
-#define OCR1CH2_REG OCR1CH
-#define OCR1CH3_REG OCR1CH
-#define OCR1CH4_REG OCR1CH
-#define OCR1CH5_REG OCR1CH
-#define OCR1CH6_REG OCR1CH
-#define OCR1CH7_REG OCR1CH
-
-/* UEIENX */
-#define TXINE_REG UEIENX
-#define STALLEDE_REG UEIENX
-#define RXOUTE_REG UEIENX
-#define RXSTPE_REG UEIENX
-#define NAKOUTE_REG UEIENX
-#define NAKINE_REG UEIENX
-#define FLERRE_REG UEIENX
-
-/* UCSR1B */
-#define TXB81_REG UCSR1B
-#define RXB81_REG UCSR1B
-#define UCSZ12_REG UCSR1B
-#define TXEN1_REG UCSR1B
-#define RXEN1_REG UCSR1B
-#define UDRIE1_REG UCSR1B
-#define TXCIE1_REG UCSR1B
-#define RXCIE1_REG UCSR1B
-
-/* UCSR1C */
-#define UCPOL1_REG UCSR1C
-#define UCSZ10_REG UCSR1C
-#define UCSZ11_REG UCSR1C
-#define USBS1_REG UCSR1C
-#define UPM10_REG UCSR1C
-#define UPM11_REG UCSR1C
-#define UMSEL10_REG UCSR1C
-#define UMSEL11_REG UCSR1C
-
-/* UCSR1A */
-#define MPCM1_REG UCSR1A
-#define U2X1_REG UCSR1A
-#define UPE1_REG UCSR1A
-#define DOR1_REG UCSR1A
-#define FE1_REG UCSR1A
-#define UDRE1_REG UCSR1A
-#define TXC1_REG UCSR1A
-#define RXC1_REG UCSR1A
-
-/* UCSR1D */
-#define RTSEN_REG UCSR1D
-#define CTSEN_REG UCSR1D
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* EIND */
-#define EIND0_REG EIND
-
-/* UDFNUML */
-#define FNUM0_REG UDFNUML
-#define FNUM1_REG UDFNUML
-#define FNUM2_REG UDFNUML
-#define FNUM3_REG UDFNUML
-#define FNUM4_REG UDFNUML
-#define FNUM5_REG UDFNUML
-#define FNUM6_REG UDFNUML
-#define FNUM7_REG UDFNUML
-
-/* UDFNUMH */
-#define FNUM8_REG UDFNUMH
-#define FNUM9_REG UDFNUMH
-#define FNUM10_REG UDFNUMH
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-#define INT3_REG EIMSK
-#define INT4_REG EIMSK
-#define INT5_REG EIMSK
-#define INT6_REG EIMSK
-#define INT7_REG EIMSK
-
-/* PRR0 */
-#define PRSPI_REG PRR0
-#define PRTIM1_REG PRR0
-#define PRTIM0_REG PRR0
-
-/* UBRR1H */
-#define UBRR1_8_REG UBRR1H
-#define UBRR1_9_REG UBRR1H
-#define UBRR1_10_REG UBRR1H
-#define UBRR1_11_REG UBRR1H
-
-/* OCR0A */
-#define OCROA_0_REG OCR0A
-#define OCROA_1_REG OCR0A
-#define OCROA_2_REG OCR0A
-#define OCROA_3_REG OCR0A
-#define OCROA_4_REG OCR0A
-#define OCROA_5_REG OCR0A
-#define OCROA_6_REG OCR0A
-#define OCROA_7_REG OCR0A
-
-/* OCR0B */
-#define OCR0B_0_REG OCR0B
-#define OCR0B_1_REG OCR0B
-#define OCR0B_2_REG OCR0B
-#define OCR0B_3_REG OCR0B
-#define OCR0B_4_REG OCR0B
-#define OCR0B_5_REG OCR0B
-#define OCR0B_6_REG OCR0B
-#define OCR0B_7_REG OCR0B
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* UDADDR */
-#define UADD0_REG UDADDR
-#define UADD1_REG UDADDR
-#define UADD2_REG UDADDR
-#define UADD3_REG UDADDR
-#define UADD4_REG UDADDR
-#define UADD5_REG UDADDR
-#define UADD6_REG UDADDR
-#define ADDEN_REG UDADDR
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define SIGRD_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* UESTA0X */
-#define NBUSYBK0_REG UESTA0X
-#define NBUSYBK1_REG UESTA0X
-#define DTSEQ0_REG UESTA0X
-#define DTSEQ1_REG UESTA0X
-#define UNDERFI_REG UESTA0X
-#define OVERFI_REG UESTA0X
-#define CFGOK_REG UESTA0X
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define OCIE1C_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* CLKSTA */
-#define EXTON_REG CLKSTA
-#define RCON_REG CLKSTA
-
-/* PLLCSR */
-#define PLOCK_REG PLLCSR
-#define PLLE_REG PLLCSR
-#define PLLP0_REG PLLCSR
-#define PLLP1_REG PLLCSR
-#define PLLP2_REG PLLCSR
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-#define INTF2_REG EIFR
-#define INTF3_REG EIFR
-#define INTF4_REG EIFR
-#define INTF5_REG EIFR
-#define INTF6_REG EIFR
-#define INTF7_REG EIFR
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* PRR1 */
-#define PRUSART1_REG PRR1
-#define PRUSB_REG PRR1
-
-/* pins mapping */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_32 3
-#define TIMER0_PRESCALER_DIV_64 4
-#define TIMER0_PRESCALER_DIV_128 5
-#define TIMER0_PRESCALER_DIV_256 6
-#define TIMER0_PRESCALER_DIV_1024 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 32
-#define TIMER0_PRESCALER_REG_4 64
-#define TIMER0_PRESCALER_REG_5 128
-#define TIMER0_PRESCALER_REG_6 256
-#define TIMER0_PRESCALER_REG_7 1024
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_64 3
-#define TIMER2_PRESCALER_DIV_256 4
-#define TIMER2_PRESCALER_DIV_1024 5
-#define TIMER2_PRESCALER_DIV_FALL 6
-#define TIMER2_PRESCALER_DIV_RISE 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 64
-#define TIMER2_PRESCALER_REG_4 256
-#define TIMER2_PRESCALER_REG_5 1024
-#define TIMER2_PRESCALER_REG_6 -1
-#define TIMER2_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE1A_NUM 1
-#define SIG_OUTPUT_COMPARE1B_NUM 2
-#define SIG_OUTPUT_COMPARE2_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM1A_NUM 1
-#define PWM1B_NUM 2
-#define PWM2_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDTOE_REG WDTCR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-
-/* TCCR0 */
-#define CS00_REG TCCR0
-#define CS01_REG TCCR0
-#define CS02_REG TCCR0
-#define CTC0_REG TCCR0
-#define COM00_REG TCCR0
-#define COM01_REG TCCR0
-#define PWM0_REG TCCR0
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* XDIV */
-#define XDIV0_REG XDIV
-#define XDIV1_REG XDIV
-#define XDIV2_REG XDIV
-#define XDIV3_REG XDIV
-#define XDIV4_REG XDIV
-#define XDIV5_REG XDIV
-#define XDIV6_REG XDIV
-#define XDIVEN_REG XDIV
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* TCCR1A */
-#define PWM10_REG TCCR1A
-#define PWM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define CTC1_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* TIMSK */
-#define TOIE2_REG TIMSK
-#define OCIE2_REG TIMSK
-#define TOIE0_REG TIMSK
-#define OCIE0_REG TIMSK
-#define TOIE1_REG TIMSK
-#define OCIE1B_REG TIMSK
-#define OCIE1A_REG TIMSK
-#define TICIE1_REG TIMSK
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-#define INT3_REG EIMSK
-#define INT4_REG EIMSK
-#define INT5_REG EIMSK
-#define INT6_REG EIMSK
-#define INT7_REG EIMSK
-
-/* EICR */
-#define ISC40_REG EICR
-#define ISC41_REG EICR
-#define ISC50_REG EICR
-#define ISC51_REG EICR
-#define ISC60_REG EICR
-#define ISC61_REG EICR
-#define ISC70_REG EICR
-#define ISC71_REG EICR
-
-/* RAMPZ */
-#define RAMPZ0_REG RAMPZ
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACD_REG ACSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-#define DDE3_REG DDRE
-#define DDE4_REG DDRE
-#define DDE5_REG DDRE
-#define DDE6_REG DDRE
-#define DDE7_REG DDRE
-
-/* ADCL */
-#define ADC0_REG ADCL
-#define ADC1_REG ADCL
-#define ADC2_REG ADCL
-#define ADC3_REG ADCL
-#define ADC4_REG ADCL
-#define ADC5_REG ADCL
-#define ADC6_REG ADCL
-#define ADC7_REG ADCL
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-#define PORTE3_REG PORTE
-#define PORTE4_REG PORTE
-#define PORTE5_REG PORTE
-#define PORTE6_REG PORTE
-#define PORTE7_REG PORTE
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* ADCH */
-#define ADC8_REG ADCH
-#define ADC9_REG ADCH
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* UDR */
-#define UDR0_REG UDR
-#define UDR1_REG UDR
-#define UDR2_REG UDR
-#define UDR3_REG UDR
-#define UDR4_REG UDR
-#define UDR5_REG UDR
-#define UDR6_REG UDR
-#define UDR7_REG UDR
-
-/* UBRR */
-#define UBRR0_REG UBRR
-#define UBRR1_REG UBRR
-#define UBRR2_REG UBRR
-#define UBRR3_REG UBRR
-#define UBRR4_REG UBRR
-#define UBRR5_REG UBRR
-#define UBRR6_REG UBRR
-#define UBRR7_REG UBRR
-
-/* ADCSR */
-#define ADPS0_REG ADCSR
-#define ADPS1_REG ADCSR
-#define ADPS2_REG ADCSR
-#define ADIE_REG ADCSR
-#define ADIF_REG ADCSR
-#define ADSC_REG ADCSR
-#define ADEN_REG ADCSR
-
-/* TCCR2 */
-#define CS20_REG TCCR2
-#define CS21_REG TCCR2
-#define CS22_REG TCCR2
-#define CTC2_REG TCCR2
-#define COM20_REG TCCR2
-#define COM21_REG TCCR2
-#define PWM2_REG TCCR2
-
-/* TIFR */
-#define TOV2_REG TIFR
-#define OCF2_REG TIFR
-#define TOV0_REG TIFR
-#define OCF0_REG TIFR
-#define TOV1_REG TIFR
-#define OCF1B_REG TIFR
-#define OCF1A_REG TIFR
-#define ICF1_REG TIFR
-
-/* UCR */
-#define TXB8_REG UCR
-#define RXB8_REG UCR
-#define CHR9_REG UCR
-#define TXEN_REG UCR
-#define RXEN_REG UCR
-#define UDRIE_REG UCR
-#define TXCIE_REG UCR
-#define RXCIE_REG UCR
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-#define EEAR10_REG EEARH
-#define EEAR11_REG EEARH
-
-/* EEARL */
-#define EEARL0_REG EEARL
-#define EEARL1_REG EEARL
-#define EEARL2_REG EEARL
-#define EEARL3_REG EEARL
-#define EEARL4_REG EEARL
-#define EEARL5_REG EEARL
-#define EEARL6_REG EEARL
-#define EEARL7_REG EEARL
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF4_REG EIFR
-#define INTF5_REG EIFR
-#define INTF6_REG EIFR
-#define INTF7_REG EIFR
-
-/* PINF */
-#define PINF0_REG PINF
-#define PINF1_REG PINF
-#define PINF2_REG PINF
-#define PINF3_REG PINF
-#define PINF4_REG PINF
-#define PINF5_REG PINF
-#define PINF6_REG PINF
-#define PINF7_REG PINF
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-#define PINE3_REG PINE
-#define PINE4_REG PINE
-#define PINE5_REG PINE
-#define PINE6_REG PINE
-#define PINE7_REG PINE
-
-/* MCUCR */
-#define SM0_REG MCUCR
-#define SM1_REG MCUCR
-#define SE_REG MCUCR
-#define SRW_REG MCUCR
-#define SRE_REG MCUCR
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* USR */
-#define OR_REG USR
-#define FE_REG USR
-#define UDRE_REG USR
-#define TXC_REG USR
-#define RXC_REG USR
-
-/* OCR0 */
-#define OCR0_0_REG OCR0
-#define OCR0_1_REG OCR0
-#define OCR0_2_REG OCR0
-#define OCR0_3_REG OCR0
-#define OCR0_4_REG OCR0
-#define OCR0_5_REG OCR0
-#define OCR0_6_REG OCR0
-#define OCR0_7_REG OCR0
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* OCR2 */
-#define OCR2_0_REG OCR2
-#define OCR2_1_REG OCR2
-#define OCR2_2_REG OCR2
-#define OCR2_3_REG OCR2
-#define OCR2_4_REG OCR2
-#define OCR2_5_REG OCR2
-#define OCR2_6_REG OCR2
-#define OCR2_7_REG OCR2
-
-/* ASSR */
-#define TCR0UB_REG ASSR
-#define OCR0UB_REG ASSR
-#define TCN0UB_REG ASSR
-#define AS0_REG ASSR
-
-/* pins mapping */
-#define AD0_PORT PORTA
-#define AD0_BIT 0
-
-#define AD1_PORT PORTA
-#define AD1_BIT 1
-
-#define AD2_PORT PORTA
-#define AD2_BIT 2
-
-#define AD3_PORT PORTA
-#define AD3_BIT 3
-
-#define AD4_PORT PORTA
-#define AD4_BIT 4
-
-#define AD5_PORT PORTA
-#define AD5_BIT 5
-
-#define AD6_PORT PORTA
-#define AD6_BIT 6
-
-#define AD7_PORT PORTA
-#define AD7_BIT 7
-
-#define SS_PORT PORTB
-#define SS_BIT 0
-
-#define SCK_PORT PORTB
-#define SCK_BIT 1
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 2
-
-#define MISO_PORT PORTB
-#define MISO_BIT 3
-
-#define OC0_PORT PORTB
-#define OC0_BIT 4
-#define PWM0_PORT PORTB
-#define PWM0_BIT 4
-
-#define OC1A_PORT PORTB
-#define OC1A_BIT 5
-#define PWM1A_PORT PORTB
-#define PWM1A_BIT 5
-
-#define OC1B_PORT PORTB
-#define OC1B_BIT 6
-#define PWM1B_PORT PORTB
-#define PWM1B_BIT 6
-
-#define OC2_PORT PORTB
-#define OC2_BIT 7
-#define PWM2_PORT PORTB
-#define PWM2_BIT 7
-#define OC1C_PORT PORTB
-#define OC1C_BIT 7
-
-#define A8_PORT PORTC
-#define A8_BIT 0
-
-#define A9_PORT PORTC
-#define A9_BIT 1
-
-#define A10_PORT PORTC
-#define A10_BIT 2
-
-#define A11_PORT PORTC
-#define A11_BIT 3
-
-#define A12_PORT PORTC
-#define A12_BIT 4
-
-#define A13_PORT PORTC
-#define A13_BIT 5
-
-#define A14_PORT PORTC
-#define A14_BIT 6
-
-#define A15_PORT PORTC
-#define A15_BIT 7
-
-#define INT0_PORT PORTD
-#define INT0_BIT 0
-
-#define INT1_PORT PORTD
-#define INT1_BIT 1
-
-#define INT2_PORT PORTD
-#define INT2_BIT 2
-
-#define INT3_PORT PORTD
-#define INT3_BIT 3
-
-#define IC1_PORT PORTD
-#define IC1_BIT 4
-
-
-#define T1_PORT PORTD
-#define T1_BIT 6
-
-#define T2_PORT PORTD
-#define T2_BIT 7
-
-#define RXD0_PORT PORTE
-#define RXD0_BIT 0
-#define PDI_PORT PORTE
-#define PDI_BIT 0
-
-#define TXD0_PORT PORTE
-#define TXD0_BIT 1
-#define PDO_PORT PORTE
-#define PDO_BIT 1
-
-#define AC+_PORT PORTE
-#define AC+_BIT 2
-
-#define AC-_PORT PORTE
-#define AC-_BIT 3
-
-#define INT4_PORT PORTE
-#define INT4_BIT 4
-
-#define INT5_PORT PORTE
-#define INT5_BIT 5
-
-#define INT6_PORT PORTE
-#define INT6_BIT 6
-
-#define INT7_PORT PORTE
-#define INT7_BIT 7
-
-#define ADC0_PORT PORTF
-#define ADC0_BIT 0
-
-#define ADC1_PORT PORTF
-#define ADC1_BIT 1
-
-#define ADC2_PORT PORTF
-#define ADC2_BIT 2
-
-#define ADC3_PORT PORTF
-#define ADC3_BIT 3
-
-#define ADC4_PORT PORTF
-#define ADC4_BIT 4
-
-#define ADC5_PORT PORTF
-#define ADC5_BIT 5
-
-#define ADC6_PORT PORTF
-#define ADC6_BIT 6
-
-#define ADC7_PORT PORTF
-#define ADC7_BIT 7
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_32 3
-#define TIMER0_PRESCALER_DIV_64 4
-#define TIMER0_PRESCALER_DIV_128 5
-#define TIMER0_PRESCALER_DIV_256 6
-#define TIMER0_PRESCALER_DIV_1024 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 32
-#define TIMER0_PRESCALER_REG_4 64
-#define TIMER0_PRESCALER_REG_5 128
-#define TIMER0_PRESCALER_REG_6 256
-#define TIMER0_PRESCALER_REG_7 1024
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_64 3
-#define TIMER2_PRESCALER_DIV_256 4
-#define TIMER2_PRESCALER_DIV_1024 5
-#define TIMER2_PRESCALER_DIV_FALL 6
-#define TIMER2_PRESCALER_DIV_RISE 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 64
-#define TIMER2_PRESCALER_REG_4 256
-#define TIMER2_PRESCALER_REG_5 1024
-#define TIMER2_PRESCALER_REG_6 -1
-#define TIMER2_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER1C_AVAILABLE
-#define TIMER2_AVAILABLE
-#define TIMER3_AVAILABLE
-#define TIMER3A_AVAILABLE
-#define TIMER3B_AVAILABLE
-#define TIMER3C_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW3_NUM 3
-#define SIG_OVERFLOW_TOTAL_NUM 4
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE1A_NUM 1
-#define SIG_OUTPUT_COMPARE1B_NUM 2
-#define SIG_OUTPUT_COMPARE1C_NUM 3
-#define SIG_OUTPUT_COMPARE2_NUM 4
-#define SIG_OUTPUT_COMPARE3A_NUM 5
-#define SIG_OUTPUT_COMPARE3B_NUM 6
-#define SIG_OUTPUT_COMPARE3C_NUM 7
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 8
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM1A_NUM 1
-#define PWM1B_NUM 2
-#define PWM1C_NUM 3
-#define PWM2_NUM 4
-#define PWM3A_NUM 5
-#define PWM3B_NUM 6
-#define PWM3C_NUM 7
-#define PWM_TOTAL_NUM 8
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE3_NUM 1
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 2
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* TCCR0 */
-#define CS00_REG TCCR0
-#define CS01_REG TCCR0
-#define CS02_REG TCCR0
-#define CTC0_REG TCCR0
-#define COM00_REG TCCR0
-#define COM01_REG TCCR0
-#define PWM0_REG TCCR0
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* XDIV */
-#define XDIV0_REG XDIV
-#define XDIV1_REG XDIV
-#define XDIV2_REG XDIV
-#define XDIV3_REG XDIV
-#define XDIV4_REG XDIV
-#define XDIV5_REG XDIV
-#define XDIV6_REG XDIV
-#define XDIVEN_REG XDIV
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-#define DDE3_REG DDRE
-#define DDE4_REG DDRE
-#define DDE5_REG DDRE
-#define DDE6_REG DDRE
-#define DDE7_REG DDRE
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* TCCR1A */
-#define PWM10_REG TCCR1A
-#define PWM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define CTC1_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* TIMSK */
-#define TOIE2_REG TIMSK
-#define OCIE2_REG TIMSK
-#define TOIE0_REG TIMSK
-#define OCIE0_REG TIMSK
-#define TOIE1_REG TIMSK
-#define OCIE1B_REG TIMSK
-#define OCIE1A_REG TIMSK
-#define TICIE1_REG TIMSK
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-#define INT3_REG EIMSK
-#define INT4_REG EIMSK
-#define INT5_REG EIMSK
-#define INT6_REG EIMSK
-#define INT7_REG EIMSK
-
-/* RAMPZ */
-#define RAMPZ0_REG RAMPZ
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* ADCSR */
-#define ADPS0_REG ADCSR
-#define ADPS1_REG ADCSR
-#define ADPS2_REG ADCSR
-#define ADIE_REG ADCSR
-#define ADIF_REG ADCSR
-#define ADFR_REG ADCSR
-#define ADSC_REG ADCSR
-#define ADEN_REG ADCSR
-
-/* SFIOR */
-#define ACME_REG SFIOR
-#define PSR321_REG SFIOR
-#define PSR0_REG SFIOR
-#define PUD_REG SFIOR
-#define TSM_REG SFIOR
-
-/* UDR0 */
-#define UDR00_REG UDR0
-#define UDR01_REG UDR0
-#define UDR02_REG UDR0
-#define UDR03_REG UDR0
-#define UDR04_REG UDR0
-#define UDR05_REG UDR0
-#define UDR06_REG UDR0
-#define UDR07_REG UDR0
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-#define PORTE3_REG PORTE
-#define PORTE4_REG PORTE
-#define PORTE5_REG PORTE
-#define PORTE6_REG PORTE
-#define PORTE7_REG PORTE
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* MCUCSR */
-#define PORF_REG MCUCSR
-#define EXTRF_REG MCUCSR
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* EEARL */
-#define EEARL0_REG EEARL
-#define EEARL1_REG EEARL
-#define EEARL2_REG EEARL
-#define EEARL3_REG EEARL
-#define EEARL4_REG EEARL
-#define EEARL5_REG EEARL
-#define EEARL6_REG EEARL
-#define EEARL7_REG EEARL
-
-/* TCCR2 */
-#define CS20_REG TCCR2
-#define CS21_REG TCCR2
-#define CS22_REG TCCR2
-#define CTC2_REG TCCR2
-#define COM20_REG TCCR2
-#define COM21_REG TCCR2
-#define PWM2_REG TCCR2
-
-/* TIFR */
-#define TOV2_REG TIFR
-#define OCF2_REG TIFR
-#define TOV0_REG TIFR
-#define OCF0_REG TIFR
-#define TOV1_REG TIFR
-#define OCF1B_REG TIFR
-#define OCF1A_REG TIFR
-#define ICF1_REG TIFR
-
-/* UBRR0L */
-#define UBRR0_REG UBRR0L
-#define UBRR1_REG UBRR0L
-#define UBRR2_REG UBRR0L
-#define UBRR3_REG UBRR0L
-#define UBRR4_REG UBRR0L
-#define UBRR5_REG UBRR0L
-#define UBRR6_REG UBRR0L
-#define UBRR7_REG UBRR0L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-#define EEAR10_REG EEARH
-#define EEAR11_REG EEARH
-
-/* EICRB */
-#define ISC40_REG EICRB
-#define ISC41_REG EICRB
-#define ISC50_REG EICRB
-#define ISC51_REG EICRB
-#define ISC60_REG EICRB
-#define ISC61_REG EICRB
-#define ISC70_REG EICRB
-#define ISC71_REG EICRB
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-#define INTF2_REG EIFR
-#define INTF3_REG EIFR
-#define INTF4_REG EIFR
-#define INTF5_REG EIFR
-#define INTF6_REG EIFR
-#define INTF7_REG EIFR
-
-/* PINF */
-#define PINF0_REG PINF
-#define PINF1_REG PINF
-#define PINF2_REG PINF
-#define PINF3_REG PINF
-#define PINF4_REG PINF
-#define PINF5_REG PINF
-#define PINF6_REG PINF
-#define PINF7_REG PINF
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-#define PINE3_REG PINE
-#define PINE4_REG PINE
-#define PINE5_REG PINE
-#define PINE6_REG PINE
-#define PINE7_REG PINE
-
-/* MCUCR */
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define SM2_REG MCUCR
-#define SM0_REG MCUCR
-#define SM1_REG MCUCR
-#define SE_REG MCUCR
-#define SRW10_REG MCUCR
-#define SRE_REG MCUCR
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* OCR0 */
-#define OCR0_0_REG OCR0
-#define OCR0_1_REG OCR0
-#define OCR0_2_REG OCR0
-#define OCR0_3_REG OCR0
-#define OCR0_4_REG OCR0
-#define OCR0_5_REG OCR0
-#define OCR0_6_REG OCR0
-#define OCR0_7_REG OCR0
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* OCR2 */
-#define OCR2_0_REG OCR2
-#define OCR2_1_REG OCR2
-#define OCR2_2_REG OCR2
-#define OCR2_3_REG OCR2
-#define OCR2_4_REG OCR2
-#define OCR2_5_REG OCR2
-#define OCR2_6_REG OCR2
-#define OCR2_7_REG OCR2
-
-/* ASSR */
-#define TCR0UB_REG ASSR
-#define OCR0UB_REG ASSR
-#define TCN0UB_REG ASSR
-#define AS0_REG ASSR
-
-/* pins mapping */
-#define AD0_PORT PORTA
-#define AD0_BIT 0
-
-#define AD1_PORT PORTA
-#define AD1_BIT 1
-
-#define AD2_PORT PORTA
-#define AD2_BIT 2
-
-#define AD3_PORT PORTA
-#define AD3_BIT 3
-
-#define AD4_PORT PORTA
-#define AD4_BIT 4
-
-#define AD5_PORT PORTA
-#define AD5_BIT 5
-
-#define AD6_PORT PORTA
-#define AD6_BIT 6
-
-#define AD7_PORT PORTA
-#define AD7_BIT 7
-
-#define SS_PORT PORTB
-#define SS_BIT 0
-
-#define SCK_PORT PORTB
-#define SCK_BIT 1
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 2
-
-#define MISO_PORT PORTB
-#define MISO_BIT 3
-
-#define OC0_PORT PORTB
-#define OC0_BIT 4
-#define PWM0_PORT PORTB
-#define PWM0_BIT 4
-
-#define OC1A_PORT PORTB
-#define OC1A_BIT 5
-#define PWM1A_PORT PORTB
-#define PWM1A_BIT 5
-
-#define OC1B_PORT PORTB
-#define OC1B_BIT 6
-#define PWM1B_PORT PORTB
-#define PWM1B_BIT 6
-
-#define OC2_PORT PORTB
-#define OC2_BIT 7
-#define PWM2_PORT PORTB
-#define PWM2_BIT 7
-#define OC1C_PORT PORTB
-#define OC1C_BIT 7
-
-#define A8_PORT PORTC
-#define A8_BIT 0
-
-#define A9_PORT PORTC
-#define A9_BIT 1
-
-#define A10_PORT PORTC
-#define A10_BIT 2
-
-#define A11_PORT PORTC
-#define A11_BIT 3
-
-#define A12_PORT PORTC
-#define A12_BIT 4
-
-#define A13_PORT PORTC
-#define A13_BIT 5
-
-#define A14_PORT PORTC
-#define A14_BIT 6
-
-#define A15_PORT PORTC
-#define A15_BIT 7
-
-#define SCL_PORT PORTD
-#define SCL_BIT 0
-#define INT0_PORT PORTD
-#define INT0_BIT 0
-
-#define SDA_PORT PORTD
-#define SDA_BIT 1
-#define INT1_PORT PORTD
-#define INT1_BIT 1
-
-#define RXD1_PORT PORTD
-#define RXD1_BIT 2
-#define INT2_PORT PORTD
-#define INT2_BIT 2
-
-#define TXD1_PORT PORTD
-#define TXD1_BIT 3
-#define INT3_PORT PORTD
-#define INT3_BIT 3
-
-#define IC1_PORT PORTD
-#define IC1_BIT 4
-
-#define XCK1_PORT PORTD
-#define XCK1_BIT 5
-
-#define T1_PORT PORTD
-#define T1_BIT 6
-
-#define T2_PORT PORTD
-#define T2_BIT 7
-
-#define RXD0_PORT PORTE
-#define RXD0_BIT 0
-#define PDI_PORT PORTE
-#define PDI_BIT 0
-
-#define TXD0_PORT PORTE
-#define TXD0_BIT 1
-#define PDO_PORT PORTE
-#define PDO_BIT 1
-
-#define XCK0_PORT PORTE
-#define XCK0_BIT 2
-#define AIN0_PORT PORTE
-#define AIN0_BIT 2
-
-#define OC3A_PORT PORTE
-#define OC3A_BIT 3
-#define AIN1_PORT PORTE
-#define AIN1_BIT 3
-
-#define OC3B_PORT PORTE
-#define OC3B_BIT 4
-#define INT4_PORT PORTE
-#define INT4_BIT 4
-
-#define OC3C_PORT PORTE
-#define OC3C_BIT 5
-#define INT5_PORT PORTE
-#define INT5_BIT 5
-
-#define T3_PORT PORTE
-#define T3_BIT 6
-#define INT6_PORT PORTE
-#define INT6_BIT 6
-
-#define IC3_PORT PORTE
-#define IC3_BIT 7
-#define INT7_PORT PORTE
-#define INT7_BIT 7
-
-#define ADC0_PORT PORTF
-#define ADC0_BIT 0
-
-#define ADC1_PORT PORTF
-#define ADC1_BIT 1
-
-#define ADC2_PORT PORTF
-#define ADC2_BIT 2
-
-#define ADC3_PORT PORTF
-#define ADC3_BIT 3
-
-#define ADC4_PORT PORTF
-#define ADC4_BIT 4
-#define TCK_PORT PORTF
-#define TCK_BIT 4
-
-#define ADC5_PORT PORTF
-#define ADC5_BIT 5
-#define TMS_PORT PORTF
-#define TMS_BIT 5
-
-#define ADC6_PORT PORTF
-#define ADC6_BIT 6
-#define TD0_PORT PORTF
-#define TD0_BIT 6
-
-#define ADC7_PORT PORTF
-#define ADC7_BIT 7
-#define TDI_PORT PORTF
-#define TDI_BIT 7
-
-#define WR_PORT PORTG
-#define WR_BIT 0
-
-#define RD_PORT PORTG
-#define RD_BIT 1
-
-#define ALE_PORT PORTG
-#define ALE_BIT 2
-
-#define TOSC2_PORT PORTG
-#define TOSC2_BIT 3
-
-#define TOSC1_PORT PORTG
-#define TOSC1_BIT 4
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_32 3
-#define TIMER0_PRESCALER_DIV_64 4
-#define TIMER0_PRESCALER_DIV_128 5
-#define TIMER0_PRESCALER_DIV_256 6
-#define TIMER0_PRESCALER_DIV_1024 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 32
-#define TIMER0_PRESCALER_REG_4 64
-#define TIMER0_PRESCALER_REG_5 128
-#define TIMER0_PRESCALER_REG_6 256
-#define TIMER0_PRESCALER_REG_7 1024
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_64 3
-#define TIMER2_PRESCALER_DIV_256 4
-#define TIMER2_PRESCALER_DIV_1024 5
-#define TIMER2_PRESCALER_DIV_FALL 6
-#define TIMER2_PRESCALER_DIV_RISE 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 64
-#define TIMER2_PRESCALER_REG_4 256
-#define TIMER2_PRESCALER_REG_5 1024
-#define TIMER2_PRESCALER_REG_6 -1
-#define TIMER2_PRESCALER_REG_7 -2
-
-/* prescalers timer 3 */
-#define TIMER3_PRESCALER_DIV_0 0
-#define TIMER3_PRESCALER_DIV_1 1
-#define TIMER3_PRESCALER_DIV_8 2
-#define TIMER3_PRESCALER_DIV_64 3
-#define TIMER3_PRESCALER_DIV_256 4
-#define TIMER3_PRESCALER_DIV_1024 5
-#define TIMER3_PRESCALER_DIV_FALL 6
-#define TIMER3_PRESCALER_DIV_RISE 7
-
-#define TIMER3_PRESCALER_REG_0 0
-#define TIMER3_PRESCALER_REG_1 1
-#define TIMER3_PRESCALER_REG_2 8
-#define TIMER3_PRESCALER_REG_3 64
-#define TIMER3_PRESCALER_REG_4 256
-#define TIMER3_PRESCALER_REG_5 1024
-#define TIMER3_PRESCALER_REG_6 -1
-#define TIMER3_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER1C_AVAILABLE
-#define TIMER2_AVAILABLE
-#define TIMER3_AVAILABLE
-#define TIMER3A_AVAILABLE
-#define TIMER3B_AVAILABLE
-#define TIMER3C_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW3_NUM 3
-#define SIG_OVERFLOW_TOTAL_NUM 4
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE1A_NUM 1
-#define SIG_OUTPUT_COMPARE1B_NUM 2
-#define SIG_OUTPUT_COMPARE1C_NUM 3
-#define SIG_OUTPUT_COMPARE2_NUM 4
-#define SIG_OUTPUT_COMPARE3A_NUM 5
-#define SIG_OUTPUT_COMPARE3B_NUM 6
-#define SIG_OUTPUT_COMPARE3C_NUM 7
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 8
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM1A_NUM 1
-#define PWM1B_NUM 2
-#define PWM1C_NUM 3
-#define PWM2_NUM 4
-#define PWM3A_NUM 5
-#define PWM3B_NUM 6
-#define PWM3C_NUM 7
-#define PWM_TOTAL_NUM 8
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE3_NUM 1
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 2
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* RAMPZ */
-#define RAMPZ0_REG RAMPZ
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTG */
-#define PORTG0_REG PORTG
-#define PORTG1_REG PORTG
-#define PORTG2_REG PORTG
-#define PORTG3_REG PORTG
-#define PORTG4_REG PORTG
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL0_REG UCSR0C
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* UDR1 */
-#define UDR10_REG UDR1
-#define UDR11_REG UDR1
-#define UDR12_REG UDR1
-#define UDR13_REG UDR1
-#define UDR14_REG UDR1
-#define UDR15_REG UDR1
-#define UDR16_REG UDR1
-#define UDR17_REG UDR1
-
-/* UDR0 */
-#define UDR00_REG UDR0
-#define UDR01_REG UDR0
-#define UDR02_REG UDR0
-#define UDR03_REG UDR0
-#define UDR04_REG UDR0
-#define UDR05_REG UDR0
-#define UDR06_REG UDR0
-#define UDR07_REG UDR0
-
-/* EICRB */
-#define ISC40_REG EICRB
-#define ISC41_REG EICRB
-#define ISC50_REG EICRB
-#define ISC51_REG EICRB
-#define ISC60_REG EICRB
-#define ISC61_REG EICRB
-#define ISC70_REG EICRB
-#define ISC71_REG EICRB
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-#define ISC20_REG EICRA
-#define ISC21_REG EICRA
-#define ISC30_REG EICRA
-#define ISC31_REG EICRA
-
-/* ASSR */
-#define TCR0UB_REG ASSR
-#define OCR0UB_REG ASSR
-#define TCN0UB_REG ASSR
-#define AS0_REG ASSR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* UBRR1L */
-/* #define UBRR0_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR1_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR2_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR3_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR4_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR5_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR6_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR7_REG UBRR1L */ /* dup in UBRR0L */
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* OCR3AL */
-#define OCR3AL0_REG OCR3AL
-#define OCR3AL1_REG OCR3AL
-#define OCR3AL2_REG OCR3AL
-#define OCR3AL3_REG OCR3AL
-#define OCR3AL4_REG OCR3AL
-#define OCR3AL5_REG OCR3AL
-#define OCR3AL6_REG OCR3AL
-#define OCR3AL7_REG OCR3AL
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* DDRF */
-#define DDF0_REG DDRF
-#define DDF1_REG DDRF
-#define DDF2_REG DDRF
-#define DDF3_REG DDRF
-#define DDF4_REG DDRF
-#define DDF5_REG DDRF
-#define DDF6_REG DDRF
-#define DDF7_REG DDRF
-
-/* DDRG */
-#define DDG0_REG DDRG
-#define DDG1_REG DDRG
-#define DDG2_REG DDRG
-#define DDG3_REG DDRG
-#define DDG4_REG DDRG
-
-/* OCR3AH */
-#define OCR3AH0_REG OCR3AH
-#define OCR3AH1_REG OCR3AH
-#define OCR3AH2_REG OCR3AH
-#define OCR3AH3_REG OCR3AH
-#define OCR3AH4_REG OCR3AH
-#define OCR3AH5_REG OCR3AH
-#define OCR3AH6_REG OCR3AH
-#define OCR3AH7_REG OCR3AH
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* SFIOR */
-#define ACME_REG SFIOR
-#define PSR321_REG SFIOR
-#define PSR0_REG SFIOR
-#define PUD_REG SFIOR
-#define TSM_REG SFIOR
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* UBRR1H */
-/* #define UBRR8_REG UBRR1H */ /* dup in UBRR0H */
-/* #define UBRR9_REG UBRR1H */ /* dup in UBRR0H */
-/* #define UBRR10_REG UBRR1H */ /* dup in UBRR0H */
-/* #define UBRR11_REG UBRR1H */ /* dup in UBRR0H */
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* TIFR */
-#define TOV0_REG TIFR
-#define OCF0_REG TIFR
-#define TOV1_REG TIFR
-#define OCF1B_REG TIFR
-#define OCF1A_REG TIFR
-#define ICF1_REG TIFR
-#define TOV2_REG TIFR
-#define OCF2_REG TIFR
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* ETIFR */
-#define OCF1C_REG ETIFR
-#define OCF3C_REG ETIFR
-#define TOV3_REG ETIFR
-#define OCF3B_REG ETIFR
-#define OCF3A_REG ETIFR
-#define ICF3_REG ETIFR
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* XDIV */
-#define XDIV0_REG XDIV
-#define XDIV1_REG XDIV
-#define XDIV2_REG XDIV
-#define XDIV3_REG XDIV
-#define XDIV4_REG XDIV
-#define XDIV5_REG XDIV
-#define XDIV6_REG XDIV
-#define XDIVEN_REG XDIV
-
-/* OCR3CH */
-#define OCR3CH0_REG OCR3CH
-#define OCR3CH1_REG OCR3CH
-#define OCR3CH2_REG OCR3CH
-#define OCR3CH3_REG OCR3CH
-#define OCR3CH4_REG OCR3CH
-#define OCR3CH5_REG OCR3CH
-#define OCR3CH6_REG OCR3CH
-#define OCR3CH7_REG OCR3CH
-
-/* ETIMSK */
-#define OCIE1C_REG ETIMSK
-#define OCIE3C_REG ETIMSK
-#define TOIE3_REG ETIMSK
-#define OCIE3B_REG ETIMSK
-#define OCIE3A_REG ETIMSK
-#define TICIE3_REG ETIMSK
-
-/* OCR3CL */
-#define OCR3CL0_REG OCR3CL
-#define OCR3CL1_REG OCR3CL
-#define OCR3CL2_REG OCR3CL
-#define OCR3CL3_REG OCR3CL
-#define OCR3CL4_REG OCR3CL
-#define OCR3CL5_REG OCR3CL
-#define OCR3CL6_REG OCR3CL
-#define OCR3CL7_REG OCR3CL
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* TCCR3C */
-#define FOC3C_REG TCCR3C
-#define FOC3B_REG TCCR3C
-#define FOC3A_REG TCCR3C
-
-/* TCCR3B */
-#define CS30_REG TCCR3B
-#define CS31_REG TCCR3B
-#define CS32_REG TCCR3B
-#define WGM32_REG TCCR3B
-#define WGM33_REG TCCR3B
-#define ICES3_REG TCCR3B
-#define ICNC3_REG TCCR3B
-
-/* TCCR3A */
-#define WGM30_REG TCCR3A
-#define WGM31_REG TCCR3A
-#define COM3C0_REG TCCR3A
-#define COM3C1_REG TCCR3A
-#define COM3B0_REG TCCR3A
-#define COM3B1_REG TCCR3A
-#define COM3A0_REG TCCR3A
-#define COM3A1_REG TCCR3A
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* TCNT3H */
-#define TCNT3H0_REG TCNT3H
-#define TCNT3H1_REG TCNT3H
-#define TCNT3H2_REG TCNT3H
-#define TCNT3H3_REG TCNT3H
-#define TCNT3H4_REG TCNT3H
-#define TCNT3H5_REG TCNT3H
-#define TCNT3H6_REG TCNT3H
-#define TCNT3H7_REG TCNT3H
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* TCNT3L */
-#define TCN3L0_REG TCNT3L
-#define TCN3L1_REG TCNT3L
-#define TCN3L2_REG TCNT3L
-#define TCN3L3_REG TCNT3L
-#define TCN3L4_REG TCNT3L
-#define TCN3L5_REG TCNT3L
-#define TCN3L6_REG TCNT3L
-#define TCN3L7_REG TCNT3L
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* MCUCSR */
-#define PORF_REG MCUCSR
-#define EXTRF_REG MCUCSR
-#define BORF_REG MCUCSR
-#define WDRF_REG MCUCSR
-#define JTRF_REG MCUCSR
-#define JTD_REG MCUCSR
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* UBRR0H */
-/* #define UBRR8_REG UBRR0H */ /* dup in UBRR1H */
-/* #define UBRR9_REG UBRR0H */ /* dup in UBRR1H */
-/* #define UBRR10_REG UBRR0H */ /* dup in UBRR1H */
-/* #define UBRR11_REG UBRR0H */ /* dup in UBRR1H */
-
-/* UBRR0L */
-/* #define UBRR0_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR1_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR2_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR3_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR4_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR5_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR6_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR7_REG UBRR0L */ /* dup in UBRR1L */
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-#define EEAR10_REG EEARH
-#define EEAR11_REG EEARH
-
-/* EEARL */
-#define EEARL0_REG EEARL
-#define EEARL1_REG EEARL
-#define EEARL2_REG EEARL
-#define EEARL3_REG EEARL
-#define EEARL4_REG EEARL
-#define EEARL5_REG EEARL
-#define EEARL6_REG EEARL
-#define EEARL7_REG EEARL
-
-/* MCUCR */
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define SM2_REG MCUCR
-#define SM0_REG MCUCR
-#define SM1_REG MCUCR
-#define SE_REG MCUCR
-#define SRW10_REG MCUCR
-#define SRE_REG MCUCR
-
-/* OCR1CL */
-#define OCR1CL0_REG OCR1CL
-#define OCR1CL1_REG OCR1CL
-#define OCR1CL2_REG OCR1CL
-#define OCR1CL3_REG OCR1CL
-#define OCR1CL4_REG OCR1CL
-#define OCR1CL5_REG OCR1CL
-#define OCR1CL6_REG OCR1CL
-#define OCR1CL7_REG OCR1CL
-
-/* OCR1CH */
-#define OCR1CH0_REG OCR1CH
-#define OCR1CH1_REG OCR1CH
-#define OCR1CH2_REG OCR1CH
-#define OCR1CH3_REG OCR1CH
-#define OCR1CH4_REG OCR1CH
-#define OCR1CH5_REG OCR1CH
-#define OCR1CH6_REG OCR1CH
-#define OCR1CH7_REG OCR1CH
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-#define INTF2_REG EIFR
-#define INTF3_REG EIFR
-#define INTF4_REG EIFR
-#define INTF5_REG EIFR
-#define INTF6_REG EIFR
-#define INTF7_REG EIFR
-
-/* UCSR1B */
-#define TXB81_REG UCSR1B
-#define RXB81_REG UCSR1B
-#define UCSZ12_REG UCSR1B
-#define TXEN1_REG UCSR1B
-#define RXEN1_REG UCSR1B
-#define UDRIE1_REG UCSR1B
-#define TXCIE1_REG UCSR1B
-#define RXCIE1_REG UCSR1B
-
-/* UCSR1C */
-#define UCPOL1_REG UCSR1C
-#define UCSZ10_REG UCSR1C
-#define UCSZ11_REG UCSR1C
-#define USBS1_REG UCSR1C
-#define UPM10_REG UCSR1C
-#define UPM11_REG UCSR1C
-#define UMSEL1_REG UCSR1C
-
-/* UCSR1A */
-#define MPCM1_REG UCSR1A
-#define U2X1_REG UCSR1A
-#define UPE1_REG UCSR1A
-#define DOR1_REG UCSR1A
-#define FE1_REG UCSR1A
-#define UDRE1_REG UCSR1A
-#define TXC1_REG UCSR1A
-#define RXC1_REG UCSR1A
-
-/* TCCR0 */
-#define CS00_REG TCCR0
-#define CS01_REG TCCR0
-#define CS02_REG TCCR0
-#define WGM01_REG TCCR0
-#define COM00_REG TCCR0
-#define COM01_REG TCCR0
-#define WGM00_REG TCCR0
-#define FOC0_REG TCCR0
-
-/* TCCR2 */
-#define CS20_REG TCCR2
-#define CS21_REG TCCR2
-#define CS22_REG TCCR2
-#define WGM21_REG TCCR2
-#define COM20_REG TCCR2
-#define COM21_REG TCCR2
-#define WGM20_REG TCCR2
-#define FOC2_REG TCCR2
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* TIMSK */
-#define TOIE0_REG TIMSK
-#define OCIE0_REG TIMSK
-#define TOIE1_REG TIMSK
-#define OCIE1B_REG TIMSK
-#define OCIE1A_REG TIMSK
-#define TICIE1_REG TIMSK
-#define TOIE2_REG TIMSK
-#define OCIE2_REG TIMSK
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-#define INT3_REG EIMSK
-#define INT4_REG EIMSK
-#define INT5_REG EIMSK
-#define INT6_REG EIMSK
-#define INT7_REG EIMSK
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1C0_REG TCCR1A
-#define COM1C1_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* PORTF */
-#define PORTF0_REG PORTF
-#define PORTF1_REG PORTF
-#define PORTF2_REG PORTF
-#define PORTF3_REG PORTF
-#define PORTF4_REG PORTF
-#define PORTF5_REG PORTF
-#define PORTF6_REG PORTF
-#define PORTF7_REG PORTF
-
-/* TCCR1C */
-#define FOC1C_REG TCCR1C
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* ICR3H */
-#define ICR3H0_REG ICR3H
-#define ICR3H1_REG ICR3H
-#define ICR3H2_REG ICR3H
-#define ICR3H3_REG ICR3H
-#define ICR3H4_REG ICR3H
-#define ICR3H5_REG ICR3H
-#define ICR3H6_REG ICR3H
-#define ICR3H7_REG ICR3H
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-#define DDE3_REG DDRE
-#define DDE4_REG DDRE
-#define DDE5_REG DDRE
-#define DDE6_REG DDRE
-#define DDE7_REG DDRE
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* ICR3L */
-#define ICR3L0_REG ICR3L
-#define ICR3L1_REG ICR3L
-#define ICR3L2_REG ICR3L
-#define ICR3L3_REG ICR3L
-#define ICR3L4_REG ICR3L
-#define ICR3L5_REG ICR3L
-#define ICR3L6_REG ICR3L
-#define ICR3L7_REG ICR3L
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-#define PORTE3_REG PORTE
-#define PORTE4_REG PORTE
-#define PORTE5_REG PORTE
-#define PORTE6_REG PORTE
-#define PORTE7_REG PORTE
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* OCR3BL */
-#define OCR3BL0_REG OCR3BL
-#define OCR3BL1_REG OCR3BL
-#define OCR3BL2_REG OCR3BL
-#define OCR3BL3_REG OCR3BL
-#define OCR3BL4_REG OCR3BL
-#define OCR3BL5_REG OCR3BL
-#define OCR3BL6_REG OCR3BL
-#define OCR3BL7_REG OCR3BL
-
-/* OCR3BH */
-#define OCR3BH0_REG OCR3BH
-#define OCR3BH1_REG OCR3BH
-#define OCR3BH2_REG OCR3BH
-#define OCR3BH3_REG OCR3BH
-#define OCR3BH4_REG OCR3BH
-#define OCR3BH5_REG OCR3BH
-#define OCR3BH6_REG OCR3BH
-#define OCR3BH7_REG OCR3BH
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADFR_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* XMCRB */
-#define XMM0_REG XMCRB
-#define XMM1_REG XMCRB
-#define XMM2_REG XMCRB
-#define XMBK_REG XMCRB
-
-/* XMCRA */
-#define SRW11_REG XMCRA
-#define SRW00_REG XMCRA
-#define SRW01_REG XMCRA
-#define SRL0_REG XMCRA
-#define SRL1_REG XMCRA
-#define SRL2_REG XMCRA
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* PING */
-#define PING0_REG PING
-#define PING1_REG PING
-#define PING2_REG PING
-#define PING3_REG PING
-#define PING4_REG PING
-
-/* PINF */
-#define PINF0_REG PINF
-#define PINF1_REG PINF
-#define PINF2_REG PINF
-#define PINF3_REG PINF
-#define PINF4_REG PINF
-#define PINF5_REG PINF
-#define PINF6_REG PINF
-#define PINF7_REG PINF
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-#define PINE3_REG PINE
-#define PINE4_REG PINE
-#define PINE5_REG PINE
-#define PINE6_REG PINE
-#define PINE7_REG PINE
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* OCR0 */
-#define OCR0_0_REG OCR0
-#define OCR0_1_REG OCR0
-#define OCR0_2_REG OCR0
-#define OCR0_3_REG OCR0
-#define OCR0_4_REG OCR0
-#define OCR0_5_REG OCR0
-#define OCR0_6_REG OCR0
-#define OCR0_7_REG OCR0
-
-/* OCR2 */
-#define OCR2_0_REG OCR2
-#define OCR2_1_REG OCR2
-#define OCR2_2_REG OCR2
-#define OCR2_3_REG OCR2
-#define OCR2_4_REG OCR2
-#define OCR2_5_REG OCR2
-#define OCR2_6_REG OCR2
-#define OCR2_7_REG OCR2
-
-/* pins mapping */
-#define AD0_PORT PORTA
-#define AD0_BIT 0
-
-#define AD1_PORT PORTA
-#define AD1_BIT 1
-
-#define AD2_PORT PORTA
-#define AD2_BIT 2
-
-#define AD3_PORT PORTA
-#define AD3_BIT 3
-
-#define AD4_PORT PORTA
-#define AD4_BIT 4
-
-#define AD5_PORT PORTA
-#define AD5_BIT 5
-
-#define AD6_PORT PORTA
-#define AD6_BIT 6
-
-#define AD7_PORT PORTA
-#define AD7_BIT 7
-
-#define SS_PORT PORTB
-#define SS_BIT 0
-
-#define SCK_PORT PORTB
-#define SCK_BIT 1
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 2
-
-#define MISO_PORT PORTB
-#define MISO_BIT 3
-
-#define OC0_PORT PORTB
-#define OC0_BIT 4
-#define PWM0_PORT PORTB
-#define PWM0_BIT 4
-
-#define OC1A_PORT PORTB
-#define OC1A_BIT 5
-#define PWM1A_PORT PORTB
-#define PWM1A_BIT 5
-
-#define OC1B_PORT PORTB
-#define OC1B_BIT 6
-#define PWM1B_PORT PORTB
-#define PWM1B_BIT 6
-
-#define OC2_PORT PORTB
-#define OC2_BIT 7
-#define PWM2_PORT PORTB
-#define PWM2_BIT 7
-#define OC1C_PORT PORTB
-#define OC1C_BIT 7
-
-#define A8_PORT PORTC
-#define A8_BIT 0
-
-#define A9_PORT PORTC
-#define A9_BIT 1
-
-#define A10_PORT PORTC
-#define A10_BIT 2
-
-#define A11_PORT PORTC
-#define A11_BIT 3
-
-#define A12_PORT PORTC
-#define A12_BIT 4
-
-#define A13_PORT PORTC
-#define A13_BIT 5
-
-#define A14_PORT PORTC
-#define A14_BIT 6
-
-#define A15_PORT PORTC
-#define A15_BIT 7
-
-#define SCL_PORT PORTD
-#define SCL_BIT 0
-#define INT0_PORT PORTD
-#define INT0_BIT 0
-
-#define SDA_PORT PORTD
-#define SDA_BIT 1
-#define INT1_PORT PORTD
-#define INT1_BIT 1
-
-#define RXD1_PORT PORTD
-#define RXD1_BIT 2
-#define INT2_PORT PORTD
-#define INT2_BIT 2
-
-#define TXD1_PORT PORTD
-#define TXD1_BIT 3
-#define INT3_PORT PORTD
-#define INT3_BIT 3
-
-#define IC1_PORT PORTD
-#define IC1_BIT 4
-
-#define XCK1_PORT PORTD
-#define XCK1_BIT 5
-
-#define T1_PORT PORTD
-#define T1_BIT 6
-
-#define T2_PORT PORTD
-#define T2_BIT 7
-
-#define RXD0_PORT PORTE
-#define RXD0_BIT 0
-#define PDI_PORT PORTE
-#define PDI_BIT 0
-
-#define TXD0_PORT PORTE
-#define TXD0_BIT 1
-#define PDO_PORT PORTE
-#define PDO_BIT 1
-
-#define XCK0_PORT PORTE
-#define XCK0_BIT 2
-#define AIN0_PORT PORTE
-#define AIN0_BIT 2
-
-#define OC3A_PORT PORTE
-#define OC3A_BIT 3
-#define AIN1_PORT PORTE
-#define AIN1_BIT 3
-
-#define OC3B_PORT PORTE
-#define OC3B_BIT 4
-#define INT4_PORT PORTE
-#define INT4_BIT 4
-
-#define OC3C_PORT PORTE
-#define OC3C_BIT 5
-#define INT5_PORT PORTE
-#define INT5_BIT 5
-
-#define T3_PORT PORTE
-#define T3_BIT 6
-#define INT6_PORT PORTE
-#define INT6_BIT 6
-
-#define IC3_PORT PORTE
-#define IC3_BIT 7
-#define INT7_PORT PORTE
-#define INT7_BIT 7
-
-#define ADC0_PORT PORTF
-#define ADC0_BIT 0
-
-#define ADC1_PORT PORTF
-#define ADC1_BIT 1
-
-#define ADC2_PORT PORTF
-#define ADC2_BIT 2
-
-#define ADC3_PORT PORTF
-#define ADC3_BIT 3
-
-#define ADC4_PORT PORTF
-#define ADC4_BIT 4
-#define TCK_PORT PORTF
-#define TCK_BIT 4
-
-#define ADC5_PORT PORTF
-#define ADC5_BIT 5
-#define TMS_PORT PORTF
-#define TMS_BIT 5
-
-#define ADC6_PORT PORTF
-#define ADC6_BIT 6
-#define TD0_PORT PORTF
-#define TD0_BIT 6
-
-#define ADC7_PORT PORTF
-#define ADC7_BIT 7
-#define TDI_PORT PORTF
-#define TDI_BIT 7
-
-#define WR_PORT PORTG
-#define WR_BIT 0
-
-#define RD_PORT PORTG
-#define RD_BIT 1
-
-#define ALE_PORT PORTG
-#define ALE_BIT 2
-
-#define TOSC2_PORT PORTG
-#define TOSC2_BIT 3
-
-#define TOSC1_PORT PORTG
-#define TOSC1_BIT 4
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-/* prescalers timer 3 */
-#define TIMER3_PRESCALER_DIV_0 0
-#define TIMER3_PRESCALER_DIV_1 1
-#define TIMER3_PRESCALER_DIV_8 2
-#define TIMER3_PRESCALER_DIV_64 3
-#define TIMER3_PRESCALER_DIV_256 4
-#define TIMER3_PRESCALER_DIV_1024 5
-#define TIMER3_PRESCALER_DIV_FALL 6
-#define TIMER3_PRESCALER_DIV_RISE 7
-
-#define TIMER3_PRESCALER_REG_0 0
-#define TIMER3_PRESCALER_REG_1 1
-#define TIMER3_PRESCALER_REG_2 8
-#define TIMER3_PRESCALER_REG_3 64
-#define TIMER3_PRESCALER_REG_4 256
-#define TIMER3_PRESCALER_REG_5 1024
-#define TIMER3_PRESCALER_REG_6 -1
-#define TIMER3_PRESCALER_REG_7 -2
-
-/* prescalers timer 4 */
-#define TIMER4_PRESCALER_DIV_0 0
-#define TIMER4_PRESCALER_DIV_1 1
-#define TIMER4_PRESCALER_DIV_8 2
-#define TIMER4_PRESCALER_DIV_64 3
-#define TIMER4_PRESCALER_DIV_256 4
-#define TIMER4_PRESCALER_DIV_1024 5
-#define TIMER4_PRESCALER_DIV_FALL 6
-#define TIMER4_PRESCALER_DIV_RISE 7
-
-#define TIMER4_PRESCALER_REG_0 0
-#define TIMER4_PRESCALER_REG_1 1
-#define TIMER4_PRESCALER_REG_2 8
-#define TIMER4_PRESCALER_REG_3 64
-#define TIMER4_PRESCALER_REG_4 256
-#define TIMER4_PRESCALER_REG_5 1024
-#define TIMER4_PRESCALER_REG_6 -1
-#define TIMER4_PRESCALER_REG_7 -2
-
-/* prescalers timer 5 */
-#define TIMER5_PRESCALER_DIV_0 0
-#define TIMER5_PRESCALER_DIV_1 1
-#define TIMER5_PRESCALER_DIV_8 2
-#define TIMER5_PRESCALER_DIV_64 3
-#define TIMER5_PRESCALER_DIV_256 4
-#define TIMER5_PRESCALER_DIV_1024 5
-#define TIMER5_PRESCALER_DIV_FALL 6
-#define TIMER5_PRESCALER_DIV_RISE 7
-
-#define TIMER5_PRESCALER_REG_0 0
-#define TIMER5_PRESCALER_REG_1 1
-#define TIMER5_PRESCALER_REG_2 8
-#define TIMER5_PRESCALER_REG_3 64
-#define TIMER5_PRESCALER_REG_4 256
-#define TIMER5_PRESCALER_REG_5 1024
-#define TIMER5_PRESCALER_REG_6 -1
-#define TIMER5_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER1C_AVAILABLE
-#define TIMER2_AVAILABLE
-#define TIMER2A_AVAILABLE
-#define TIMER2B_AVAILABLE
-#define TIMER3_AVAILABLE
-#define TIMER3A_AVAILABLE
-#define TIMER3B_AVAILABLE
-#define TIMER3C_AVAILABLE
-#define TIMER4_AVAILABLE
-#define TIMER4A_AVAILABLE
-#define TIMER4B_AVAILABLE
-#define TIMER4C_AVAILABLE
-#define TIMER5_AVAILABLE
-#define TIMER5A_AVAILABLE
-#define TIMER5B_AVAILABLE
-#define TIMER5C_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW3_NUM 3
-#define SIG_OVERFLOW4_NUM 4
-#define SIG_OVERFLOW5_NUM 5
-#define SIG_OVERFLOW_TOTAL_NUM 6
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE1C_NUM 4
-#define SIG_OUTPUT_COMPARE2A_NUM 5
-#define SIG_OUTPUT_COMPARE2B_NUM 6
-#define SIG_OUTPUT_COMPARE3A_NUM 7
-#define SIG_OUTPUT_COMPARE3B_NUM 8
-#define SIG_OUTPUT_COMPARE3C_NUM 9
-#define SIG_OUTPUT_COMPARE4A_NUM 10
-#define SIG_OUTPUT_COMPARE4B_NUM 11
-#define SIG_OUTPUT_COMPARE4C_NUM 12
-#define SIG_OUTPUT_COMPARE5A_NUM 13
-#define SIG_OUTPUT_COMPARE5B_NUM 14
-#define SIG_OUTPUT_COMPARE5C_NUM 15
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 16
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM1C_NUM 4
-#define PWM2A_NUM 5
-#define PWM2B_NUM 6
-#define PWM3A_NUM 7
-#define PWM3B_NUM 8
-#define PWM3C_NUM 9
-#define PWM4A_NUM 10
-#define PWM4B_NUM 11
-#define PWM4C_NUM 12
-#define PWM5A_NUM 13
-#define PWM5B_NUM 14
-#define PWM5C_NUM 15
-#define PWM_TOTAL_NUM 16
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE3_NUM 1
-#define SIG_INPUT_CAPTURE4_NUM 2
-#define SIG_INPUT_CAPTURE5_NUM 3
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 4
-
-
-/* UBRR3H */
-/* #define UBRR8_REG UBRR3H */ /* dup in UBRR2H, UBRR0H */
-/* #define UBRR9_REG UBRR3H */ /* dup in UBRR2H, UBRR0H */
-/* #define UBRR10_REG UBRR3H */ /* dup in UBRR2H, UBRR0H */
-/* #define UBRR11_REG UBRR3H */ /* dup in UBRR2H, UBRR0H */
-
-/* UBRR3L */
-/* #define UBRR0_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */
-/* #define UBRR1_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */
-/* #define UBRR2_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */
-/* #define UBRR3_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */
-/* #define UBRR4_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */
-/* #define UBRR5_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */
-/* #define UBRR6_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */
-/* #define UBRR7_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */
-
-/* OCR0A */
-#define OCROA_0_REG OCR0A
-#define OCROA_1_REG OCR0A
-#define OCROA_2_REG OCR0A
-#define OCROA_3_REG OCR0A
-#define OCROA_4_REG OCR0A
-#define OCROA_5_REG OCR0A
-#define OCROA_6_REG OCR0A
-#define OCROA_7_REG OCR0A
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* UCSR3A */
-#define MPCM3_REG UCSR3A
-#define U2X3_REG UCSR3A
-#define UPE3_REG UCSR3A
-#define DOR3_REG UCSR3A
-#define FE3_REG UCSR3A
-#define UDRE3_REG UCSR3A
-#define TXC3_REG UCSR3A
-#define RXC3_REG UCSR3A
-
-/* UCSR3B */
-#define TXB83_REG UCSR3B
-#define RXB83_REG UCSR3B
-#define UCSZ32_REG UCSR3B
-#define TXEN3_REG UCSR3B
-#define RXEN3_REG UCSR3B
-#define UDRIE3_REG UCSR3B
-#define TXCIE3_REG UCSR3B
-#define RXCIE3_REG UCSR3B
-
-/* UCSR3C */
-#define UCPOL3_REG UCSR3C
-#define UCSZ30_REG UCSR3C
-#define UCSZ31_REG UCSR3C
-#define USBS3_REG UCSR3C
-#define UPM30_REG UCSR3C
-#define UPM31_REG UCSR3C
-#define UMSEL30_REG UCSR3C
-#define UMSEL31_REG UCSR3C
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* RAMPZ */
-#define RAMPZ0_REG RAMPZ
-#define RAMPZ1_REG RAMPZ
-
-/* OCR2B */
-#define OCR2B_0_REG OCR2B
-#define OCR2B_1_REG OCR2B
-#define OCR2B_2_REG OCR2B
-#define OCR2B_3_REG OCR2B
-#define OCR2B_4_REG OCR2B
-#define OCR2B_5_REG OCR2B
-#define OCR2B_6_REG OCR2B
-#define OCR2B_7_REG OCR2B
-
-/* OCR2A */
-#define OCR2A_0_REG OCR2A
-#define OCR2A_1_REG OCR2A
-#define OCR2A_2_REG OCR2A
-#define OCR2A_3_REG OCR2A
-#define OCR2A_4_REG OCR2A
-#define OCR2A_5_REG OCR2A
-#define OCR2A_6_REG OCR2A
-#define OCR2A_7_REG OCR2A
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-#define EEAR10_REG EEARH
-#define EEAR11_REG EEARH
-
-/* PORTL */
-#define PORTL0_REG PORTL
-#define PORTL1_REG PORTL
-#define PORTL2_REG PORTL
-#define PORTL3_REG PORTL
-#define PORTL4_REG PORTL
-#define PORTL5_REG PORTL
-#define PORTL6_REG PORTL
-#define PORTL7_REG PORTL
-
-/* PORTJ */
-#define PORTJ0_REG PORTJ
-#define PORTJ1_REG PORTJ
-#define PORTJ2_REG PORTJ
-#define PORTJ3_REG PORTJ
-#define PORTJ4_REG PORTJ
-#define PORTJ5_REG PORTJ
-#define PORTJ6_REG PORTJ
-#define PORTJ7_REG PORTJ
-
-/* PORTK */
-#define PORTK0_REG PORTK
-#define PORTK1_REG PORTK
-#define PORTK2_REG PORTK
-#define PORTK3_REG PORTK
-#define PORTK4_REG PORTK
-#define PORTK5_REG PORTK
-#define PORTK6_REG PORTK
-#define PORTK7_REG PORTK
-
-/* PORTH */
-#define PORTH0_REG PORTH
-#define PORTH1_REG PORTH
-#define PORTH2_REG PORTH
-#define PORTH3_REG PORTH
-#define PORTH4_REG PORTH
-#define PORTH5_REG PORTH
-#define PORTH6_REG PORTH
-#define PORTH7_REG PORTH
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* PORTG */
-#define PORTG0_REG PORTG
-#define PORTG1_REG PORTG
-#define PORTG2_REG PORTG
-#define PORTG3_REG PORTG
-#define PORTG4_REG PORTG
-#define PORTG5_REG PORTG
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL00_REG UCSR0C
-#define UMSEL01_REG UCSR0C
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-#define INT3_REG EIMSK
-#define INT4_REG EIMSK
-#define INT5_REG EIMSK
-#define INT6_REG EIMSK
-#define INT7_REG EIMSK
-
-/* UDR1 */
-#define UDR1_0_REG UDR1
-#define UDR1_1_REG UDR1
-#define UDR1_2_REG UDR1
-#define UDR1_3_REG UDR1
-#define UDR1_4_REG UDR1
-#define UDR1_5_REG UDR1
-#define UDR1_6_REG UDR1
-#define UDR1_7_REG UDR1
-
-/* UDR0 */
-#define UDR0_0_REG UDR0
-#define UDR0_1_REG UDR0
-#define UDR0_2_REG UDR0
-#define UDR0_3_REG UDR0
-#define UDR0_4_REG UDR0
-#define UDR0_5_REG UDR0
-#define UDR0_6_REG UDR0
-#define UDR0_7_REG UDR0
-
-/* UDR3 */
-#define UDR3_0_REG UDR3
-#define UDR3_1_REG UDR3
-#define UDR3_2_REG UDR3
-#define UDR3_3_REG UDR3
-#define UDR3_4_REG UDR3
-#define UDR3_5_REG UDR3
-#define UDR3_6_REG UDR3
-#define UDR3_7_REG UDR3
-
-/* UDR2 */
-#define UDR2_0_REG UDR2
-#define UDR2_1_REG UDR2
-#define UDR2_2_REG UDR2
-#define UDR2_3_REG UDR2
-#define UDR2_4_REG UDR2
-#define UDR2_5_REG UDR2
-#define UDR2_6_REG UDR2
-#define UDR2_7_REG UDR2
-
-/* EICRB */
-#define ISC40_REG EICRB
-#define ISC41_REG EICRB
-#define ISC50_REG EICRB
-#define ISC51_REG EICRB
-#define ISC60_REG EICRB
-#define ISC61_REG EICRB
-#define ISC70_REG EICRB
-#define ISC71_REG EICRB
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-#define ISC20_REG EICRA
-#define ISC21_REG EICRA
-#define ISC30_REG EICRA
-#define ISC31_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* DIDR2 */
-#define ADC8D_REG DIDR2
-#define ADC9D_REG DIDR2
-#define ADC10D_REG DIDR2
-#define ADC11D_REG DIDR2
-#define ADC12D_REG DIDR2
-#define ADC13D_REG DIDR2
-#define ADC14D_REG DIDR2
-#define ADC15D_REG DIDR2
-
-/* DDRF */
-#define DDF0_REG DDRF
-#define DDF1_REG DDRF
-#define DDF2_REG DDRF
-#define DDF3_REG DDRF
-#define DDF4_REG DDRF
-#define DDF5_REG DDRF
-#define DDF6_REG DDRF
-#define DDF7_REG DDRF
-
-/* ASSR */
-#define TCR2BUB_REG ASSR
-#define TCR2AUB_REG ASSR
-#define OCR2BUB_REG ASSR
-#define OCR2AUB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* OCR0B */
-#define OCR0B_0_REG OCR0B
-#define OCR0B_1_REG OCR0B
-#define OCR0B_2_REG OCR0B
-#define OCR0B_3_REG OCR0B
-#define OCR0B_4_REG OCR0B
-#define OCR0B_5_REG OCR0B
-#define OCR0B_6_REG OCR0B
-#define OCR0B_7_REG OCR0B
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRJ */
-#define DDJ0_REG DDRJ
-#define DDJ1_REG DDRJ
-#define DDJ2_REG DDRJ
-#define DDJ3_REG DDRJ
-#define DDJ4_REG DDRJ
-#define DDJ5_REG DDRJ
-#define DDJ6_REG DDRJ
-#define DDJ7_REG DDRJ
-
-/* DDRK */
-#define DDK0_REG DDRK
-#define DDK1_REG DDRK
-#define DDK2_REG DDRK
-#define DDK3_REG DDRK
-#define DDK4_REG DDRK
-#define DDK5_REG DDRK
-#define DDK6_REG DDRK
-#define DDK7_REG DDRK
-
-/* DDRH */
-#define DDH0_REG DDRH
-#define DDH1_REG DDRH
-#define DDH2_REG DDRH
-#define DDH3_REG DDRH
-#define DDH4_REG DDRH
-#define DDH5_REG DDRH
-#define DDH6_REG DDRH
-#define DDH7_REG DDRH
-
-/* DDRL */
-#define DDL0_REG DDRL
-#define DDL1_REG DDRL
-#define DDL2_REG DDRL
-#define DDL3_REG DDRL
-#define DDL4_REG DDRL
-#define DDL5_REG DDRL
-#define DDL6_REG DDRL
-#define DDL7_REG DDRL
-
-/* UBRR1L */
-#define UBRR_0_REG UBRR1L
-#define UBRR_1_REG UBRR1L
-#define UBRR_2_REG UBRR1L
-#define UBRR_3_REG UBRR1L
-#define UBRR_4_REG UBRR1L
-#define UBRR_5_REG UBRR1L
-#define UBRR_6_REG UBRR1L
-#define UBRR_7_REG UBRR1L
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* OCR3AL */
-#define OCR3AL0_REG OCR3AL
-#define OCR3AL1_REG OCR3AL
-#define OCR3AL2_REG OCR3AL
-#define OCR3AL3_REG OCR3AL
-#define OCR3AL4_REG OCR3AL
-#define OCR3AL5_REG OCR3AL
-#define OCR3AL6_REG OCR3AL
-#define OCR3AL7_REG OCR3AL
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* UBRR1H */
-#define UBRR_8_REG UBRR1H
-#define UBRR_9_REG UBRR1H
-#define UBRR_10_REG UBRR1H
-#define UBRR_11_REG UBRR1H
-
-/* DDRG */
-#define DDG0_REG DDRG
-#define DDG1_REG DDRG
-#define DDG2_REG DDRG
-#define DDG3_REG DDRG
-#define DDG4_REG DDRG
-#define DDG5_REG DDRG
-
-/* OCR3AH */
-#define OCR3AH0_REG OCR3AH
-#define OCR3AH1_REG OCR3AH
-#define OCR3AH2_REG OCR3AH
-#define OCR3AH3_REG OCR3AH
-#define OCR3AH4_REG OCR3AH
-#define OCR3AH5_REG OCR3AH
-#define OCR3AH6_REG OCR3AH
-#define OCR3AH7_REG OCR3AH
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* TCNT5H */
-#define TCNT5H0_REG TCNT5H
-#define TCNT5H1_REG TCNT5H
-#define TCNT5H2_REG TCNT5H
-#define TCNT5H3_REG TCNT5H
-#define TCNT5H4_REG TCNT5H
-#define TCNT5H5_REG TCNT5H
-#define TCNT5H6_REG TCNT5H
-#define TCNT5H7_REG TCNT5H
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* TCNT5L */
-#define TCNT5L0_REG TCNT5L
-#define TCNT5L1_REG TCNT5L
-#define TCNT5L2_REG TCNT5L
-#define TCNT5L3_REG TCNT5L
-#define TCNT5L4_REG TCNT5L
-#define TCNT5L5_REG TCNT5L
-#define TCNT5L6_REG TCNT5L
-#define TCNT5L7_REG TCNT5L
-
-/* UBRR2H */
-/* #define UBRR8_REG UBRR2H */ /* dup in UBRR3H, UBRR0H */
-/* #define UBRR9_REG UBRR2H */ /* dup in UBRR3H, UBRR0H */
-/* #define UBRR10_REG UBRR2H */ /* dup in UBRR3H, UBRR0H */
-/* #define UBRR11_REG UBRR2H */ /* dup in UBRR3H, UBRR0H */
-
-/* UBRR2L */
-/* #define UBRR0_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */
-/* #define UBRR1_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */
-/* #define UBRR2_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */
-/* #define UBRR3_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */
-/* #define UBRR4_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */
-/* #define UBRR5_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */
-/* #define UBRR6_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */
-/* #define UBRR7_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */
-
-/* PCICR */
-#define PCIE0_REG PCICR
-#define PCIE1_REG PCICR
-#define PCIE2_REG PCICR
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* UCSR2B */
-#define TXB82_REG UCSR2B
-#define RXB82_REG UCSR2B
-#define UCSZ22_REG UCSR2B
-#define TXEN2_REG UCSR2B
-#define RXEN2_REG UCSR2B
-#define UDRIE2_REG UCSR2B
-#define TXCIE2_REG UCSR2B
-#define RXCIE2_REG UCSR2B
-
-/* UCSR2A */
-#define MPCM2_REG UCSR2A
-#define U2X2_REG UCSR2A
-#define UPE2_REG UCSR2A
-#define DOR2_REG UCSR2A
-#define FE2_REG UCSR2A
-#define UDRE2_REG UCSR2A
-#define TXC2_REG UCSR2A
-#define RXC2_REG UCSR2A
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* UCSR2C */
-#define UCPOL2_REG UCSR2C
-#define UCSZ20_REG UCSR2C
-#define UCSZ21_REG UCSR2C
-#define USBS2_REG UCSR2C
-#define UPM20_REG UCSR2C
-#define UPM21_REG UCSR2C
-#define UMSEL20_REG UCSR2C
-#define UMSEL21_REG UCSR2C
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TIFR4 */
-#define TOV4_REG TIFR4
-#define OCF4A_REG TIFR4
-#define OCF4B_REG TIFR4
-#define OCF4C_REG TIFR4
-#define ICF4_REG TIFR4
-
-/* TIFR5 */
-#define TOV5_REG TIFR5
-#define OCF5A_REG TIFR5
-#define OCF5B_REG TIFR5
-#define OCF5C_REG TIFR5
-#define ICF5_REG TIFR5
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-#define OCF2B_REG TIFR2
-
-/* TIFR3 */
-#define TOV3_REG TIFR3
-#define OCF3A_REG TIFR3
-#define OCF3B_REG TIFR3
-#define OCF3C_REG TIFR3
-#define ICF3_REG TIFR3
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define OCF1C_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* OCR4AH */
-#define OCR4AH0_REG OCR4AH
-#define OCR4AH1_REG OCR4AH
-#define OCR4AH2_REG OCR4AH
-#define OCR4AH3_REG OCR4AH
-#define OCR4AH4_REG OCR4AH
-#define OCR4AH5_REG OCR4AH
-#define OCR4AH6_REG OCR4AH
-#define OCR4AH7_REG OCR4AH
-
-/* OCR5CH */
-#define OCR5CH0_REG OCR5CH
-#define OCR5CH1_REG OCR5CH
-#define OCR5CH2_REG OCR5CH
-#define OCR5CH3_REG OCR5CH
-#define OCR5CH4_REG OCR5CH
-#define OCR5CH5_REG OCR5CH
-#define OCR5CH6_REG OCR5CH
-#define OCR5CH7_REG OCR5CH
-
-/* OCR4AL */
-#define OCR4AL0_REG OCR4AL
-#define OCR4AL1_REG OCR4AL
-#define OCR4AL2_REG OCR4AL
-#define OCR4AL3_REG OCR4AL
-#define OCR4AL4_REG OCR4AL
-#define OCR4AL5_REG OCR4AL
-#define OCR4AL6_REG OCR4AL
-#define OCR4AL7_REG OCR4AL
-
-/* OCR5CL */
-#define OCR5CL0_REG OCR5CL
-#define OCR5CL1_REG OCR5CL
-#define OCR5CL2_REG OCR5CL
-#define OCR5CL3_REG OCR5CL
-#define OCR5CL4_REG OCR5CL
-#define OCR5CL5_REG OCR5CL
-#define OCR5CL6_REG OCR5CL
-#define OCR5CL7_REG OCR5CL
-
-/* OCR3CH */
-#define OCR3CH0_REG OCR3CH
-#define OCR3CH1_REG OCR3CH
-#define OCR3CH2_REG OCR3CH
-#define OCR3CH3_REG OCR3CH
-#define OCR3CH4_REG OCR3CH
-#define OCR3CH5_REG OCR3CH
-#define OCR3CH6_REG OCR3CH
-#define OCR3CH7_REG OCR3CH
-
-/* OCR3CL */
-#define OCR3CL0_REG OCR3CL
-#define OCR3CL1_REG OCR3CL
-#define OCR3CL2_REG OCR3CL
-#define OCR3CL3_REG OCR3CL
-#define OCR3CL4_REG OCR3CL
-#define OCR3CL5_REG OCR3CL
-#define OCR3CL6_REG OCR3CL
-#define OCR3CL7_REG OCR3CL
-
-/* GTCCR */
-#define PSRSYNC_REG GTCCR
-#define TSM_REG GTCCR
-#define PSRASY_REG GTCCR
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* TCCR3C */
-#define FOC3C_REG TCCR3C
-#define FOC3B_REG TCCR3C
-#define FOC3A_REG TCCR3C
-
-/* TCCR3B */
-#define CS30_REG TCCR3B
-#define CS31_REG TCCR3B
-#define CS32_REG TCCR3B
-#define WGM32_REG TCCR3B
-#define WGM33_REG TCCR3B
-#define ICES3_REG TCCR3B
-#define ICNC3_REG TCCR3B
-
-/* TCCR3A */
-#define WGM30_REG TCCR3A
-#define WGM31_REG TCCR3A
-#define COM3C0_REG TCCR3A
-#define COM3C1_REG TCCR3A
-#define COM3B0_REG TCCR3A
-#define COM3B1_REG TCCR3A
-#define COM3A0_REG TCCR3A
-#define COM3A1_REG TCCR3A
-
-/* PORTF */
-#define PORTF0_REG PORTF
-#define PORTF1_REG PORTF
-#define PORTF2_REG PORTF
-#define PORTF3_REG PORTF
-#define PORTF4_REG PORTF
-#define PORTF5_REG PORTF
-#define PORTF6_REG PORTF
-#define PORTF7_REG PORTF
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-#define PCINT15_REG PCMSK1
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* TCNT3H */
-#define TCNT3H0_REG TCNT3H
-#define TCNT3H1_REG TCNT3H
-#define TCNT3H2_REG TCNT3H
-#define TCNT3H3_REG TCNT3H
-#define TCNT3H4_REG TCNT3H
-#define TCNT3H5_REG TCNT3H
-#define TCNT3H6_REG TCNT3H
-#define TCNT3H7_REG TCNT3H
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* TCNT3L */
-#define TCNT3L0_REG TCNT3L
-#define TCNT3L1_REG TCNT3L
-#define TCNT3L2_REG TCNT3L
-#define TCNT3L3_REG TCNT3L
-#define TCNT3L4_REG TCNT3L
-#define TCNT3L5_REG TCNT3L
-#define TCNT3L6_REG TCNT3L
-#define TCNT3L7_REG TCNT3L
-
-/* ICR5L */
-#define ICR5L0_REG ICR5L
-#define ICR5L1_REG ICR5L
-#define ICR5L2_REG ICR5L
-#define ICR5L3_REG ICR5L
-#define ICR5L4_REG ICR5L
-#define ICR5L5_REG ICR5L
-#define ICR5L6_REG ICR5L
-#define ICR5L7_REG ICR5L
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* ICR5H */
-#define ICR5H0_REG ICR5H
-#define ICR5H1_REG ICR5H
-#define ICR5H2_REG ICR5H
-#define ICR5H3_REG ICR5H
-#define ICR5H4_REG ICR5H
-#define ICR5H5_REG ICR5H
-#define ICR5H6_REG ICR5H
-#define ICR5H7_REG ICR5H
-
-/* MCUSR */
-#define JTRF_REG MCUSR
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* PINK */
-#define PINK0_REG PINK
-#define PINK1_REG PINK
-#define PINK2_REG PINK
-#define PINK3_REG PINK
-#define PINK4_REG PINK
-#define PINK5_REG PINK
-#define PINK6_REG PINK
-#define PINK7_REG PINK
-
-/* PINJ */
-#define PINJ0_REG PINJ
-#define PINJ1_REG PINJ
-#define PINJ2_REG PINJ
-#define PINJ3_REG PINJ
-#define PINJ4_REG PINJ
-#define PINJ5_REG PINJ
-#define PINJ6_REG PINJ
-#define PINJ7_REG PINJ
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* PINH */
-#define PINH0_REG PINH
-#define PINH1_REG PINH
-#define PINH2_REG PINH
-#define PINH3_REG PINH
-#define PINH4_REG PINH
-#define PINH5_REG PINH
-#define PINH6_REG PINH
-#define PINH7_REG PINH
-
-/* PCIFR */
-#define PCIF0_REG PCIFR
-#define PCIF1_REG PCIFR
-#define PCIF2_REG PCIFR
-
-/* TCCR2A */
-#define WGM20_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2B0_REG TCCR2A
-#define COM2B1_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-
-/* TCCR2B */
-#define CS20_REG TCCR2B
-#define CS21_REG TCCR2B
-#define CS22_REG TCCR2B
-#define WGM22_REG TCCR2B
-#define FOC2B_REG TCCR2B
-#define FOC2A_REG TCCR2B
-
-/* UBRR0H */
-/* #define UBRR8_REG UBRR0H */ /* dup in UBRR3H, UBRR2H */
-/* #define UBRR9_REG UBRR0H */ /* dup in UBRR3H, UBRR2H */
-/* #define UBRR10_REG UBRR0H */ /* dup in UBRR3H, UBRR2H */
-/* #define UBRR11_REG UBRR0H */ /* dup in UBRR3H, UBRR2H */
-
-/* PING */
-#define PING0_REG PING
-#define PING1_REG PING
-#define PING2_REG PING
-#define PING3_REG PING
-#define PING4_REG PING
-#define PING5_REG PING
-
-/* UBRR0L */
-/* #define UBRR0_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */
-/* #define UBRR1_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */
-/* #define UBRR2_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */
-/* #define UBRR3_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */
-/* #define UBRR4_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */
-/* #define UBRR5_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */
-/* #define UBRR6_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */
-/* #define UBRR7_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* ICR4H */
-#define ICR4H0_REG ICR4H
-#define ICR4H1_REG ICR4H
-#define ICR4H2_REG ICR4H
-#define ICR4H3_REG ICR4H
-#define ICR4H4_REG ICR4H
-#define ICR4H5_REG ICR4H
-#define ICR4H6_REG ICR4H
-#define ICR4H7_REG ICR4H
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* PCMSK2 */
-#define PCINT16_REG PCMSK2
-#define PCINT17_REG PCMSK2
-#define PCINT18_REG PCMSK2
-#define PCINT19_REG PCMSK2
-#define PCINT20_REG PCMSK2
-#define PCINT21_REG PCMSK2
-#define PCINT22_REG PCMSK2
-#define PCINT23_REG PCMSK2
-
-/* ICR4L */
-#define ICR4L0_REG ICR4L
-#define ICR4L1_REG ICR4L
-#define ICR4L2_REG ICR4L
-#define ICR4L3_REG ICR4L
-#define ICR4L4_REG ICR4L
-#define ICR4L5_REG ICR4L
-#define ICR4L6_REG ICR4L
-#define ICR4L7_REG ICR4L
-
-/* MCUCR */
-#define JTD_REG MCUCR
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* OCR1CL */
-#define OCR1CL0_REG OCR1CL
-#define OCR1CL1_REG OCR1CL
-#define OCR1CL2_REG OCR1CL
-#define OCR1CL3_REG OCR1CL
-#define OCR1CL4_REG OCR1CL
-#define OCR1CL5_REG OCR1CL
-#define OCR1CL6_REG OCR1CL
-#define OCR1CL7_REG OCR1CL
-
-/* TCNT4L */
-#define TCNT4L0_REG TCNT4L
-#define TCNT4L1_REG TCNT4L
-#define TCNT4L2_REG TCNT4L
-#define TCNT4L3_REG TCNT4L
-#define TCNT4L4_REG TCNT4L
-#define TCNT4L5_REG TCNT4L
-#define TCNT4L6_REG TCNT4L
-#define TCNT4L7_REG TCNT4L
-
-/* OCR1CH */
-#define OCR1CH0_REG OCR1CH
-#define OCR1CH1_REG OCR1CH
-#define OCR1CH2_REG OCR1CH
-#define OCR1CH3_REG OCR1CH
-#define OCR1CH4_REG OCR1CH
-#define OCR1CH5_REG OCR1CH
-#define OCR1CH6_REG OCR1CH
-#define OCR1CH7_REG OCR1CH
-
-/* TCNT4H */
-#define TCNT4H0_REG TCNT4H
-#define TCNT4H1_REG TCNT4H
-#define TCNT4H2_REG TCNT4H
-#define TCNT4H3_REG TCNT4H
-#define TCNT4H4_REG TCNT4H
-#define TCNT4H5_REG TCNT4H
-#define TCNT4H6_REG TCNT4H
-#define TCNT4H7_REG TCNT4H
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* UCSR1B */
-#define TXB81_REG UCSR1B
-#define RXB81_REG UCSR1B
-#define UCSZ12_REG UCSR1B
-#define TXEN1_REG UCSR1B
-#define RXEN1_REG UCSR1B
-#define UDRIE1_REG UCSR1B
-#define TXCIE1_REG UCSR1B
-#define RXCIE1_REG UCSR1B
-
-/* UCSR1C */
-#define UCPOL1_REG UCSR1C
-#define UCSZ10_REG UCSR1C
-#define UCSZ11_REG UCSR1C
-#define USBS1_REG UCSR1C
-#define UPM10_REG UCSR1C
-#define UPM11_REG UCSR1C
-#define UMSEL10_REG UCSR1C
-#define UMSEL11_REG UCSR1C
-
-/* UCSR1A */
-#define MPCM1_REG UCSR1A
-#define U2X1_REG UCSR1A
-#define UPE1_REG UCSR1A
-#define DOR1_REG UCSR1A
-#define FE1_REG UCSR1A
-#define UDRE1_REG UCSR1A
-#define TXC1_REG UCSR1A
-#define RXC1_REG UCSR1A
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* EIND */
-#define EIND0_REG EIND
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* TCCR5A */
-#define WGM50_REG TCCR5A
-#define WGM51_REG TCCR5A
-#define COM5C0_REG TCCR5A
-#define COM5C1_REG TCCR5A
-#define COM5B0_REG TCCR5A
-#define COM5B1_REG TCCR5A
-#define COM5A0_REG TCCR5A
-#define COM5A1_REG TCCR5A
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* TCCR5C */
-#define FOC5C_REG TCCR5C
-#define FOC5B_REG TCCR5C
-#define FOC5A_REG TCCR5C
-
-/* TCCR5B */
-#define CS50_REG TCCR5B
-#define CS51_REG TCCR5B
-#define CS52_REG TCCR5B
-#define WGM52_REG TCCR5B
-#define WGM53_REG TCCR5B
-#define ICES5_REG TCCR5B
-#define ICNC5_REG TCCR5B
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ACME_REG ADCSRB
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define MUX5_REG ADCSRB
-
-/* OCR5AL */
-#define OCR5AL0_REG OCR5AL
-#define OCR5AL1_REG OCR5AL
-#define OCR5AL2_REG OCR5AL
-#define OCR5AL3_REG OCR5AL
-#define OCR5AL4_REG OCR5AL
-#define OCR5AL5_REG OCR5AL
-#define OCR5AL6_REG OCR5AL
-#define OCR5AL7_REG OCR5AL
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1C0_REG TCCR1A
-#define COM1C1_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* OCR4CH */
-#define OCR4CH0_REG OCR4CH
-#define OCR4CH1_REG OCR4CH
-#define OCR4CH2_REG OCR4CH
-#define OCR4CH3_REG OCR4CH
-#define OCR4CH4_REG OCR4CH
-#define OCR4CH5_REG OCR4CH
-#define OCR4CH6_REG OCR4CH
-#define OCR4CH7_REG OCR4CH
-
-/* OCR5AH */
-#define OCR5AH0_REG OCR5AH
-#define OCR5AH1_REG OCR5AH
-#define OCR5AH2_REG OCR5AH
-#define OCR5AH3_REG OCR5AH
-#define OCR5AH4_REG OCR5AH
-#define OCR5AH5_REG OCR5AH
-#define OCR5AH6_REG OCR5AH
-#define OCR5AH7_REG OCR5AH
-
-/* OCR4CL */
-#define OCR4CL0_REG OCR4CL
-#define OCR4CL1_REG OCR4CL
-#define OCR4CL2_REG OCR4CL
-#define OCR4CL3_REG OCR4CL
-#define OCR4CL4_REG OCR4CL
-#define OCR4CL5_REG OCR4CL
-#define OCR4CL6_REG OCR4CL
-#define OCR4CL7_REG OCR4CL
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* TCCR1C */
-#define FOC1C_REG TCCR1C
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* ICR3H */
-#define ICR3H0_REG ICR3H
-#define ICR3H1_REG ICR3H
-#define ICR3H2_REG ICR3H
-#define ICR3H3_REG ICR3H
-#define ICR3H4_REG ICR3H
-#define ICR3H5_REG ICR3H
-#define ICR3H6_REG ICR3H
-#define ICR3H7_REG ICR3H
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-#define DDE3_REG DDRE
-#define DDE4_REG DDRE
-#define DDE5_REG DDRE
-#define DDE6_REG DDRE
-#define DDE7_REG DDRE
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* ICR3L */
-#define ICR3L0_REG ICR3L
-#define ICR3L1_REG ICR3L
-#define ICR3L2_REG ICR3L
-#define ICR3L3_REG ICR3L
-#define ICR3L4_REG ICR3L
-#define ICR3L5_REG ICR3L
-#define ICR3L6_REG ICR3L
-#define ICR3L7_REG ICR3L
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-#define PORTE3_REG PORTE
-#define PORTE4_REG PORTE
-#define PORTE5_REG PORTE
-#define PORTE6_REG PORTE
-#define PORTE7_REG PORTE
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define SIGRD_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* OCR5BH */
-#define OCR5BH0_REG OCR5BH
-#define OCR5BH1_REG OCR5BH
-#define OCR5BH2_REG OCR5BH
-#define OCR5BH3_REG OCR5BH
-#define OCR5BH4_REG OCR5BH
-#define OCR5BH5_REG OCR5BH
-#define OCR5BH6_REG OCR5BH
-#define OCR5BH7_REG OCR5BH
-
-/* OCR3BL */
-#define OCR3BL0_REG OCR3BL
-#define OCR3BL1_REG OCR3BL
-#define OCR3BL2_REG OCR3BL
-#define OCR3BL3_REG OCR3BL
-#define OCR3BL4_REG OCR3BL
-#define OCR3BL5_REG OCR3BL
-#define OCR3BL6_REG OCR3BL
-#define OCR3BL7_REG OCR3BL
-
-/* OCR5BL */
-#define OCR5BL0_REG OCR5BL
-#define OCR5BL1_REG OCR5BL
-#define OCR5BL2_REG OCR5BL
-#define OCR5BL3_REG OCR5BL
-#define OCR5BL4_REG OCR5BL
-#define OCR5BL5_REG OCR5BL
-#define OCR5BL6_REG OCR5BL
-#define OCR5BL7_REG OCR5BL
-
-/* OCR3BH */
-#define OCR3BH0_REG OCR3BH
-#define OCR3BH1_REG OCR3BH
-#define OCR3BH2_REG OCR3BH
-#define OCR3BH3_REG OCR3BH
-#define OCR3BH4_REG OCR3BH
-#define OCR3BH5_REG OCR3BH
-#define OCR3BH6_REG OCR3BH
-#define OCR3BH7_REG OCR3BH
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-#define OCIE2B_REG TIMSK2
-
-/* TIMSK3 */
-#define TOIE3_REG TIMSK3
-#define OCIE3A_REG TIMSK3
-#define OCIE3B_REG TIMSK3
-#define OCIE3C_REG TIMSK3
-#define ICIE3_REG TIMSK3
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define OCIE1C_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* TIMSK4 */
-#define TOIE4_REG TIMSK4
-#define OCIE4A_REG TIMSK4
-#define OCIE4B_REG TIMSK4
-#define OCIE4C_REG TIMSK4
-#define ICIE4_REG TIMSK4
-
-/* TIMSK5 */
-#define TOIE5_REG TIMSK5
-#define OCIE5A_REG TIMSK5
-#define OCIE5B_REG TIMSK5
-#define OCIE5C_REG TIMSK5
-#define ICIE5_REG TIMSK5
-
-/* TCCR4B */
-#define CS40_REG TCCR4B
-#define CS41_REG TCCR4B
-#define CS42_REG TCCR4B
-#define WGM42_REG TCCR4B
-#define WGM43_REG TCCR4B
-#define ICES4_REG TCCR4B
-#define ICNC4_REG TCCR4B
-
-/* TCCR4C */
-#define FOC4C_REG TCCR4C
-#define FOC4B_REG TCCR4C
-#define FOC4A_REG TCCR4C
-
-/* TCCR4A */
-#define WGM40_REG TCCR4A
-#define WGM41_REG TCCR4A
-#define COM4C0_REG TCCR4A
-#define COM4C1_REG TCCR4A
-#define COM4B0_REG TCCR4A
-#define COM4B1_REG TCCR4A
-#define COM4A0_REG TCCR4A
-#define COM4A1_REG TCCR4A
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* XMCRB */
-#define XMM0_REG XMCRB
-#define XMM1_REG XMCRB
-#define XMM2_REG XMCRB
-#define XMBK_REG XMCRB
-
-/* XMCRA */
-#define SRW00_REG XMCRA
-#define SRW01_REG XMCRA
-#define SRW10_REG XMCRA
-#define SRW11_REG XMCRA
-#define SRL0_REG XMCRA
-#define SRL1_REG XMCRA
-#define SRL2_REG XMCRA
-#define SRE_REG XMCRA
-
-/* PINL */
-#define PINL0_REG PINL
-#define PINL1_REG PINL
-#define PINL2_REG PINL
-#define PINL3_REG PINL
-#define PINL4_REG PINL
-#define PINL5_REG PINL
-#define PINL6_REG PINL
-#define PINL7_REG PINL
-
-/* OCR4BL */
-#define OCR4BL0_REG OCR4BL
-#define OCR4BL1_REG OCR4BL
-#define OCR4BL2_REG OCR4BL
-#define OCR4BL3_REG OCR4BL
-#define OCR4BL4_REG OCR4BL
-#define OCR4BL5_REG OCR4BL
-#define OCR4BL6_REG OCR4BL
-#define OCR4BL7_REG OCR4BL
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-#define INTF2_REG EIFR
-#define INTF3_REG EIFR
-#define INTF4_REG EIFR
-#define INTF5_REG EIFR
-#define INTF6_REG EIFR
-#define INTF7_REG EIFR
-
-/* OCR4BH */
-#define OCR4BH0_REG OCR4BH
-#define OCR4BH1_REG OCR4BH
-#define OCR4BH2_REG OCR4BH
-#define OCR4BH3_REG OCR4BH
-#define OCR4BH4_REG OCR4BH
-#define OCR4BH5_REG OCR4BH
-#define OCR4BH6_REG OCR4BH
-#define OCR4BH7_REG OCR4BH
-
-/* PINF */
-#define PINF0_REG PINF
-#define PINF1_REG PINF
-#define PINF2_REG PINF
-#define PINF3_REG PINF
-#define PINF4_REG PINF
-#define PINF5_REG PINF
-#define PINF6_REG PINF
-#define PINF7_REG PINF
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-#define PINE3_REG PINE
-#define PINE4_REG PINE
-#define PINE5_REG PINE
-#define PINE6_REG PINE
-#define PINE7_REG PINE
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* TWAMR */
-#define TWAM0_REG TWAMR
-#define TWAM1_REG TWAMR
-#define TWAM2_REG TWAMR
-#define TWAM3_REG TWAMR
-#define TWAM4_REG TWAMR
-#define TWAM5_REG TWAMR
-#define TWAM6_REG TWAMR
-
-/* PRR0 */
-#define PRADC_REG PRR0
-#define PRUSART0_REG PRR0
-#define PRSPI_REG PRR0
-#define PRTIM1_REG PRR0
-#define PRTIM0_REG PRR0
-#define PRTIM2_REG PRR0
-#define PRTWI_REG PRR0
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* PRR1 */
-#define PRUSART1_REG PRR1
-#define PRUSART2_REG PRR1
-#define PRUSART3_REG PRR1
-#define PRTIM3_REG PRR1
-#define PRTIM4_REG PRR1
-#define PRTIM5_REG PRR1
-
-/* pins mapping */
-#define AD0_PORT PORTA
-#define AD0_BIT 0
-
-#define AD1_PORT PORTA
-#define AD1_BIT 1
-
-#define AD2_PORT PORTA
-#define AD2_BIT 2
-
-#define AD3_PORT PORTA
-#define AD3_BIT 3
-
-#define AD4_PORT PORTA
-#define AD4_BIT 4
-
-#define AD5_PORT PORTA
-#define AD5_BIT 5
-
-#define AD6_PORT PORTA
-#define AD6_BIT 6
-
-#define AD7_PORT PORTA
-#define AD7_BIT 7
-
-#define SS_PORT PORTB
-#define SS_BIT 0
-#define PCINT0_PORT PORTB
-#define PCINT0_BIT 0
-
-#define SCK_PORT PORTB
-#define SCK_BIT 1
-#define PCINT1_PORT PORTB
-#define PCINT1_BIT 1
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 2
-#define PCINT2_PORT PORTB
-#define PCINT2_BIT 2
-
-#define MISO_PORT PORTB
-#define MISO_BIT 3
-#define PCINT3_PORT PORTB
-#define PCINT3_BIT 3
-
-#define OC0A_PORT PORTB
-#define OC0A_BIT 4
-#define PCINT4_PORT PORTB
-#define PCINT4_BIT 4
-
-#define OC1B_PORT PORTB
-#define OC1B_BIT 6
-#define PCINT6_PORT PORTB
-#define PCINT6_BIT 6
-
-#define OC0A_PORT PORTB
-#define OC0A_BIT 7
-#define OC1C_PORT PORTB
-#define OC1C_BIT 7
-#define PCINT7_PORT PORTB
-#define PCINT7_BIT 7
-
-#define A8_PORT PORTC
-#define A8_BIT 0
-
-#define A9_PORT PORTC
-#define A9_BIT 1
-
-#define A10_PORT PORTC
-#define A10_BIT 2
-
-#define A11_PORT PORTC
-#define A11_BIT 3
-
-#define A12_PORT PORTC
-#define A12_BIT 4
-
-#define A13_PORT PORTC
-#define A13_BIT 5
-
-#define A14_PORT PORTC
-#define A14_BIT 6
-
-#define A15_PORT PORTC
-#define A15_BIT 7
-
-#define SCL_PORT PORTD
-#define SCL_BIT 0
-#define INT0_PORT PORTD
-#define INT0_BIT 0
-
-#define SDA_PORT PORTD
-#define SDA_BIT 1
-#define INT1_PORT PORTD
-#define INT1_BIT 1
-
-#define RXD1_PORT PORTD
-#define RXD1_BIT 2
-#define INT2_PORT PORTD
-#define INT2_BIT 2
-
-#define TXD1_PORT PORTD
-#define TXD1_BIT 3
-#define INT3_PORT PORTD
-#define INT3_BIT 3
-
-#define ICP1_PORT PORTD
-#define ICP1_BIT 4
-
-#define XCK1_PORT PORTD
-#define XCK1_BIT 5
-
-#define T1_PORT PORTD
-#define T1_BIT 6
-
-#define T0_PORT PORTD
-#define T0_BIT 7
-
-#define RXD_PORT PORTE
-#define RXD_BIT 0
-#define PCINT8_PORT PORTE
-#define PCINT8_BIT 0
-
-#define TXD0_PORT PORTE
-#define TXD0_BIT 1
-
-#define XCK_PORT PORTE
-#define XCK_BIT 2
-#define AIN0_PORT PORTE
-#define AIN0_BIT 2
-
-#define OC3A_PORT PORTE
-#define OC3A_BIT 3
-#define AIN1_PORT PORTE
-#define AIN1_BIT 3
-
-#define OC3B_PORT PORTE
-#define OC3B_BIT 4
-#define INT4_PORT PORTE
-#define INT4_BIT 4
-
-#define T3_PORT PORTE
-#define T3_BIT 6
-#define INT6_PORT PORTE
-#define INT6_BIT 6
-
-#define CLKO_PORT PORTE
-#define CLKO_BIT 7
-#define ICP3_PORT PORTE
-#define ICP3_BIT 7
-#define INT7_PORT PORTE
-#define INT7_BIT 7
-
-#define ADC0_PORT PORTF
-#define ADC0_BIT 0
-
-#define ADC1_PORT PORTF
-#define ADC1_BIT 1
-
-#define ADC2_PORT PORTF
-#define ADC2_BIT 2
-
-#define ADC3_PORT PORTF
-#define ADC3_BIT 3
-
-#define ADC4_PORT PORTF
-#define ADC4_BIT 4
-#define TCK_PORT PORTF
-#define TCK_BIT 4
-
-#define ADC6_PORT PORTF
-#define ADC6_BIT 6
-#define TDO_PORT PORTF
-#define TDO_BIT 6
-
-#define ADC7_PORT PORTF
-#define ADC7_BIT 7
-#define TDI_PORT PORTF
-#define TDI_BIT 7
-
-#define WR_PORT PORTG
-#define WR_BIT 0
-
-#define RD_PORT PORTG
-#define RD_BIT 1
-
-#define ALE_PORT PORTG
-#define ALE_BIT 2
-
-#define TOSC2_PORT PORTG
-#define TOSC2_BIT 3
-
-#define TOSC1_PORT PORTG
-#define TOSC1_BIT 4
-
-#define OC0B_PORT PORTG
-#define OC0B_BIT 5
-
-#define RXD2_PORT PORTH
-#define RXD2_BIT 0
-
-#define TXD2_PORT PORTH
-#define TXD2_BIT 1
-
-#define XCK2_PORT PORTH
-#define XCK2_BIT 2
-
-#define OC4A_PORT PORTH
-#define OC4A_BIT 3
-
-#define OC4B_PORT PORTH
-#define OC4B_BIT 4
-
-#define OC2B_PORT PORTH
-#define OC2B_BIT 6
-
-#define T4_PORT PORTH
-#define T4_BIT 7
-
-#define RXD3_PORT PORTJ
-#define RXD3_BIT 0
-#define PCINT9_PORT PORTJ
-#define PCINT9_BIT 0
-
-#define TXD3_PORT PORTJ
-#define TXD3_BIT 1
-#define PCINT10_PORT PORTJ
-#define PCINT10_BIT 1
-
-#define XCK3_PORT PORTJ
-#define XCK3_BIT 2
-#define PCINT11_PORT PORTJ
-#define PCINT11_BIT 2
-
-#define PCINT12_PORT PORTJ
-#define PCINT12_BIT 3
-
-#define PCINT13_PORT PORTJ
-#define PCINT13_BIT 4
-
-#define PCINT15_PORT PORTJ
-#define PCINT15_BIT 6
-
-#define ADC8_PORT PORTK
-#define ADC8_BIT 0
-#define PCINT16_PORT PORTK
-#define PCINT16_BIT 0
-
-#define ADC9_PORT PORTK
-#define ADC9_BIT 1
-#define PCINT17_PORT PORTK
-#define PCINT17_BIT 1
-
-#define ADC10_PORT PORTK
-#define ADC10_BIT 2
-#define PCINT18_PORT PORTK
-#define PCINT18_BIT 2
-
-#define ADC11_PORT PORTK
-#define ADC11_BIT 3
-#define PCINT19_PORT PORTK
-#define PCINT19_BIT 3
-
-#define ADC12_PORT PORTK
-#define ADC12_BIT 4
-#define PCINT20_PORT PORTK
-#define PCINT20_BIT 4
-
-#define ADC13_PORT PORTK
-#define ADC13_BIT 5
-#define PCINT21_PORT PORTK
-#define PCINT21_BIT 5
-
-#define ADC14_PORT PORTK
-#define ADC14_BIT 6
-#define PCINT22_PORT PORTK
-#define PCINT22_BIT 6
-
-#define ADC15_PORT PORTK
-#define ADC15_BIT 7
-#define PCINT23_PORT PORTK
-#define PCINT23_BIT 7
-
-#define ICP4_PORT PORTL
-#define ICP4_BIT 0
-
-#define ICP5_PORT PORTL
-#define ICP5_BIT 1
-
-#define T5_PORT PORTL
-#define T5_BIT 2
-
-#define OC5A_PORT PORTL
-#define OC5A_BIT 3
-
-#define OC5B_PORT PORTL
-#define OC5B_BIT 4
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-/* prescalers timer 3 */
-#define TIMER3_PRESCALER_DIV_0 0
-#define TIMER3_PRESCALER_DIV_1 1
-#define TIMER3_PRESCALER_DIV_8 2
-#define TIMER3_PRESCALER_DIV_64 3
-#define TIMER3_PRESCALER_DIV_256 4
-#define TIMER3_PRESCALER_DIV_1024 5
-#define TIMER3_PRESCALER_DIV_FALL 6
-#define TIMER3_PRESCALER_DIV_RISE 7
-
-#define TIMER3_PRESCALER_REG_0 0
-#define TIMER3_PRESCALER_REG_1 1
-#define TIMER3_PRESCALER_REG_2 8
-#define TIMER3_PRESCALER_REG_3 64
-#define TIMER3_PRESCALER_REG_4 256
-#define TIMER3_PRESCALER_REG_5 1024
-#define TIMER3_PRESCALER_REG_6 -1
-#define TIMER3_PRESCALER_REG_7 -2
-
-/* prescalers timer 4 */
-#define TIMER4_PRESCALER_DIV_0 0
-#define TIMER4_PRESCALER_DIV_1 1
-#define TIMER4_PRESCALER_DIV_8 2
-#define TIMER4_PRESCALER_DIV_64 3
-#define TIMER4_PRESCALER_DIV_256 4
-#define TIMER4_PRESCALER_DIV_1024 5
-#define TIMER4_PRESCALER_DIV_FALL 6
-#define TIMER4_PRESCALER_DIV_RISE 7
-
-#define TIMER4_PRESCALER_REG_0 0
-#define TIMER4_PRESCALER_REG_1 1
-#define TIMER4_PRESCALER_REG_2 8
-#define TIMER4_PRESCALER_REG_3 64
-#define TIMER4_PRESCALER_REG_4 256
-#define TIMER4_PRESCALER_REG_5 1024
-#define TIMER4_PRESCALER_REG_6 -1
-#define TIMER4_PRESCALER_REG_7 -2
-
-/* prescalers timer 5 */
-#define TIMER5_PRESCALER_DIV_0 0
-#define TIMER5_PRESCALER_DIV_1 1
-#define TIMER5_PRESCALER_DIV_8 2
-#define TIMER5_PRESCALER_DIV_64 3
-#define TIMER5_PRESCALER_DIV_256 4
-#define TIMER5_PRESCALER_DIV_1024 5
-#define TIMER5_PRESCALER_DIV_FALL 6
-#define TIMER5_PRESCALER_DIV_RISE 7
-
-#define TIMER5_PRESCALER_REG_0 0
-#define TIMER5_PRESCALER_REG_1 1
-#define TIMER5_PRESCALER_REG_2 8
-#define TIMER5_PRESCALER_REG_3 64
-#define TIMER5_PRESCALER_REG_4 256
-#define TIMER5_PRESCALER_REG_5 1024
-#define TIMER5_PRESCALER_REG_6 -1
-#define TIMER5_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER1C_AVAILABLE
-#define TIMER2_AVAILABLE
-#define TIMER2A_AVAILABLE
-#define TIMER2B_AVAILABLE
-#define TIMER3_AVAILABLE
-#define TIMER3A_AVAILABLE
-#define TIMER3B_AVAILABLE
-#define TIMER3C_AVAILABLE
-#define TIMER4_AVAILABLE
-#define TIMER4A_AVAILABLE
-#define TIMER4B_AVAILABLE
-#define TIMER4C_AVAILABLE
-#define TIMER5_AVAILABLE
-#define TIMER5A_AVAILABLE
-#define TIMER5B_AVAILABLE
-#define TIMER5C_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW3_NUM 3
-#define SIG_OVERFLOW4_NUM 4
-#define SIG_OVERFLOW5_NUM 5
-#define SIG_OVERFLOW_TOTAL_NUM 6
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE1C_NUM 4
-#define SIG_OUTPUT_COMPARE2A_NUM 5
-#define SIG_OUTPUT_COMPARE2B_NUM 6
-#define SIG_OUTPUT_COMPARE3A_NUM 7
-#define SIG_OUTPUT_COMPARE3B_NUM 8
-#define SIG_OUTPUT_COMPARE3C_NUM 9
-#define SIG_OUTPUT_COMPARE4A_NUM 10
-#define SIG_OUTPUT_COMPARE4B_NUM 11
-#define SIG_OUTPUT_COMPARE4C_NUM 12
-#define SIG_OUTPUT_COMPARE5A_NUM 13
-#define SIG_OUTPUT_COMPARE5B_NUM 14
-#define SIG_OUTPUT_COMPARE5C_NUM 15
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 16
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM1C_NUM 4
-#define PWM2A_NUM 5
-#define PWM2B_NUM 6
-#define PWM3A_NUM 7
-#define PWM3B_NUM 8
-#define PWM3C_NUM 9
-#define PWM4A_NUM 10
-#define PWM4B_NUM 11
-#define PWM4C_NUM 12
-#define PWM5A_NUM 13
-#define PWM5B_NUM 14
-#define PWM5C_NUM 15
-#define PWM_TOTAL_NUM 16
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE3_NUM 1
-#define SIG_INPUT_CAPTURE4_NUM 2
-#define SIG_INPUT_CAPTURE5_NUM 3
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 4
-
-
-/* OCR0A */
-#define OCROA_0_REG OCR0A
-#define OCROA_1_REG OCR0A
-#define OCROA_2_REG OCR0A
-#define OCROA_3_REG OCR0A
-#define OCROA_4_REG OCR0A
-#define OCROA_5_REG OCR0A
-#define OCROA_6_REG OCR0A
-#define OCROA_7_REG OCR0A
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* RAMPZ */
-#define RAMPZ0_REG RAMPZ
-#define RAMPZ1_REG RAMPZ
-
-/* OCR2B */
-#define OCR2B_0_REG OCR2B
-#define OCR2B_1_REG OCR2B
-#define OCR2B_2_REG OCR2B
-#define OCR2B_3_REG OCR2B
-#define OCR2B_4_REG OCR2B
-#define OCR2B_5_REG OCR2B
-#define OCR2B_6_REG OCR2B
-#define OCR2B_7_REG OCR2B
-
-/* OCR2A */
-#define OCR2A_0_REG OCR2A
-#define OCR2A_1_REG OCR2A
-#define OCR2A_2_REG OCR2A
-#define OCR2A_3_REG OCR2A
-#define OCR2A_4_REG OCR2A
-#define OCR2A_5_REG OCR2A
-#define OCR2A_6_REG OCR2A
-#define OCR2A_7_REG OCR2A
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-#define EEAR10_REG EEARH
-#define EEAR11_REG EEARH
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTG */
-#define PORTG0_REG PORTG
-#define PORTG1_REG PORTG
-#define PORTG2_REG PORTG
-#define PORTG3_REG PORTG
-#define PORTG4_REG PORTG
-#define PORTG5_REG PORTG
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL00_REG UCSR0C
-#define UMSEL01_REG UCSR0C
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-#define INT3_REG EIMSK
-#define INT4_REG EIMSK
-#define INT5_REG EIMSK
-#define INT6_REG EIMSK
-#define INT7_REG EIMSK
-
-/* UDR1 */
-#define UDR1_0_REG UDR1
-#define UDR1_1_REG UDR1
-#define UDR1_2_REG UDR1
-#define UDR1_3_REG UDR1
-#define UDR1_4_REG UDR1
-#define UDR1_5_REG UDR1
-#define UDR1_6_REG UDR1
-#define UDR1_7_REG UDR1
-
-/* UDR0 */
-#define UDR0_0_REG UDR0
-#define UDR0_1_REG UDR0
-#define UDR0_2_REG UDR0
-#define UDR0_3_REG UDR0
-#define UDR0_4_REG UDR0
-#define UDR0_5_REG UDR0
-#define UDR0_6_REG UDR0
-#define UDR0_7_REG UDR0
-
-/* EICRB */
-#define ISC40_REG EICRB
-#define ISC41_REG EICRB
-#define ISC50_REG EICRB
-#define ISC51_REG EICRB
-#define ISC60_REG EICRB
-#define ISC61_REG EICRB
-#define ISC70_REG EICRB
-#define ISC71_REG EICRB
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-#define ISC20_REG EICRA
-#define ISC21_REG EICRA
-#define ISC30_REG EICRA
-#define ISC31_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* DIDR2 */
-#define ADC8D_REG DIDR2
-#define ADC9D_REG DIDR2
-#define ADC10D_REG DIDR2
-#define ADC11D_REG DIDR2
-#define ADC12D_REG DIDR2
-#define ADC13D_REG DIDR2
-#define ADC14D_REG DIDR2
-#define ADC15D_REG DIDR2
-
-/* DDRF */
-#define DDF0_REG DDRF
-#define DDF1_REG DDRF
-#define DDF2_REG DDRF
-#define DDF3_REG DDRF
-#define DDF4_REG DDRF
-#define DDF5_REG DDRF
-#define DDF6_REG DDRF
-#define DDF7_REG DDRF
-
-/* ASSR */
-#define TCR2BUB_REG ASSR
-#define TCR2AUB_REG ASSR
-#define OCR2BUB_REG ASSR
-#define OCR2AUB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* OCR0B */
-#define OCR0B_0_REG OCR0B
-#define OCR0B_1_REG OCR0B
-#define OCR0B_2_REG OCR0B
-#define OCR0B_3_REG OCR0B
-#define OCR0B_4_REG OCR0B
-#define OCR0B_5_REG OCR0B
-#define OCR0B_6_REG OCR0B
-#define OCR0B_7_REG OCR0B
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* UBRR1L */
-#define UBRR_0_REG UBRR1L
-#define UBRR_1_REG UBRR1L
-#define UBRR_2_REG UBRR1L
-#define UBRR_3_REG UBRR1L
-#define UBRR_4_REG UBRR1L
-#define UBRR_5_REG UBRR1L
-#define UBRR_6_REG UBRR1L
-#define UBRR_7_REG UBRR1L
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* OCR3AL */
-#define OCR3AL0_REG OCR3AL
-#define OCR3AL1_REG OCR3AL
-#define OCR3AL2_REG OCR3AL
-#define OCR3AL3_REG OCR3AL
-#define OCR3AL4_REG OCR3AL
-#define OCR3AL5_REG OCR3AL
-#define OCR3AL6_REG OCR3AL
-#define OCR3AL7_REG OCR3AL
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* UBRR1H */
-#define UBRR_8_REG UBRR1H
-#define UBRR_9_REG UBRR1H
-#define UBRR_10_REG UBRR1H
-#define UBRR_11_REG UBRR1H
-
-/* DDRG */
-#define DDG0_REG DDRG
-#define DDG1_REG DDRG
-#define DDG2_REG DDRG
-#define DDG3_REG DDRG
-#define DDG4_REG DDRG
-#define DDG5_REG DDRG
-
-/* OCR3AH */
-#define OCR3AH0_REG OCR3AH
-#define OCR3AH1_REG OCR3AH
-#define OCR3AH2_REG OCR3AH
-#define OCR3AH3_REG OCR3AH
-#define OCR3AH4_REG OCR3AH
-#define OCR3AH5_REG OCR3AH
-#define OCR3AH6_REG OCR3AH
-#define OCR3AH7_REG OCR3AH
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* TCNT5H */
-#define TCNT5H0_REG TCNT5H
-#define TCNT5H1_REG TCNT5H
-#define TCNT5H2_REG TCNT5H
-#define TCNT5H3_REG TCNT5H
-#define TCNT5H4_REG TCNT5H
-#define TCNT5H5_REG TCNT5H
-#define TCNT5H6_REG TCNT5H
-#define TCNT5H7_REG TCNT5H
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* TCNT5L */
-#define TCNT5L0_REG TCNT5L
-#define TCNT5L1_REG TCNT5L
-#define TCNT5L2_REG TCNT5L
-#define TCNT5L3_REG TCNT5L
-#define TCNT5L4_REG TCNT5L
-#define TCNT5L5_REG TCNT5L
-#define TCNT5L6_REG TCNT5L
-#define TCNT5L7_REG TCNT5L
-
-/* PCICR */
-#define PCIE0_REG PCICR
-#define PCIE1_REG PCICR
-#define PCIE2_REG PCICR
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* TIFR4 */
-#define TOV4_REG TIFR4
-#define OCF4A_REG TIFR4
-#define OCF4B_REG TIFR4
-#define OCF4C_REG TIFR4
-#define ICF4_REG TIFR4
-
-/* TIFR5 */
-#define TOV5_REG TIFR5
-#define OCF5A_REG TIFR5
-#define OCF5B_REG TIFR5
-#define OCF5C_REG TIFR5
-#define ICF5_REG TIFR5
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-#define OCF2B_REG TIFR2
-
-/* TIFR3 */
-#define TOV3_REG TIFR3
-#define OCF3A_REG TIFR3
-#define OCF3B_REG TIFR3
-#define OCF3C_REG TIFR3
-#define ICF3_REG TIFR3
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define OCF1C_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* OCR4AH */
-#define OCR4AH0_REG OCR4AH
-#define OCR4AH1_REG OCR4AH
-#define OCR4AH2_REG OCR4AH
-#define OCR4AH3_REG OCR4AH
-#define OCR4AH4_REG OCR4AH
-#define OCR4AH5_REG OCR4AH
-#define OCR4AH6_REG OCR4AH
-#define OCR4AH7_REG OCR4AH
-
-/* OCR5CH */
-#define OCR5CH0_REG OCR5CH
-#define OCR5CH1_REG OCR5CH
-#define OCR5CH2_REG OCR5CH
-#define OCR5CH3_REG OCR5CH
-#define OCR5CH4_REG OCR5CH
-#define OCR5CH5_REG OCR5CH
-#define OCR5CH6_REG OCR5CH
-#define OCR5CH7_REG OCR5CH
-
-/* OCR4AL */
-#define OCR4AL0_REG OCR4AL
-#define OCR4AL1_REG OCR4AL
-#define OCR4AL2_REG OCR4AL
-#define OCR4AL3_REG OCR4AL
-#define OCR4AL4_REG OCR4AL
-#define OCR4AL5_REG OCR4AL
-#define OCR4AL6_REG OCR4AL
-#define OCR4AL7_REG OCR4AL
-
-/* OCR5CL */
-#define OCR5CL0_REG OCR5CL
-#define OCR5CL1_REG OCR5CL
-#define OCR5CL2_REG OCR5CL
-#define OCR5CL3_REG OCR5CL
-#define OCR5CL4_REG OCR5CL
-#define OCR5CL5_REG OCR5CL
-#define OCR5CL6_REG OCR5CL
-#define OCR5CL7_REG OCR5CL
-
-/* OCR3CH */
-#define OCR3CH0_REG OCR3CH
-#define OCR3CH1_REG OCR3CH
-#define OCR3CH2_REG OCR3CH
-#define OCR3CH3_REG OCR3CH
-#define OCR3CH4_REG OCR3CH
-#define OCR3CH5_REG OCR3CH
-#define OCR3CH6_REG OCR3CH
-#define OCR3CH7_REG OCR3CH
-
-/* OCR3CL */
-#define OCR3CL0_REG OCR3CL
-#define OCR3CL1_REG OCR3CL
-#define OCR3CL2_REG OCR3CL
-#define OCR3CL3_REG OCR3CL
-#define OCR3CL4_REG OCR3CL
-#define OCR3CL5_REG OCR3CL
-#define OCR3CL6_REG OCR3CL
-#define OCR3CL7_REG OCR3CL
-
-/* GTCCR */
-#define PSRSYNC_REG GTCCR
-#define TSM_REG GTCCR
-#define PSRASY_REG GTCCR
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* TCCR3C */
-#define FOC3C_REG TCCR3C
-#define FOC3B_REG TCCR3C
-#define FOC3A_REG TCCR3C
-
-/* TCCR3B */
-#define CS30_REG TCCR3B
-#define CS31_REG TCCR3B
-#define CS32_REG TCCR3B
-#define WGM32_REG TCCR3B
-#define WGM33_REG TCCR3B
-#define ICES3_REG TCCR3B
-#define ICNC3_REG TCCR3B
-
-/* TCCR3A */
-#define WGM30_REG TCCR3A
-#define WGM31_REG TCCR3A
-#define COM3C0_REG TCCR3A
-#define COM3C1_REG TCCR3A
-#define COM3B0_REG TCCR3A
-#define COM3B1_REG TCCR3A
-#define COM3A0_REG TCCR3A
-#define COM3A1_REG TCCR3A
-
-/* PORTF */
-#define PORTF0_REG PORTF
-#define PORTF1_REG PORTF
-#define PORTF2_REG PORTF
-#define PORTF3_REG PORTF
-#define PORTF4_REG PORTF
-#define PORTF5_REG PORTF
-#define PORTF6_REG PORTF
-#define PORTF7_REG PORTF
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-#define PCINT15_REG PCMSK1
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* TCNT3H */
-#define TCNT3H0_REG TCNT3H
-#define TCNT3H1_REG TCNT3H
-#define TCNT3H2_REG TCNT3H
-#define TCNT3H3_REG TCNT3H
-#define TCNT3H4_REG TCNT3H
-#define TCNT3H5_REG TCNT3H
-#define TCNT3H6_REG TCNT3H
-#define TCNT3H7_REG TCNT3H
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* TCNT3L */
-#define TCNT3L0_REG TCNT3L
-#define TCNT3L1_REG TCNT3L
-#define TCNT3L2_REG TCNT3L
-#define TCNT3L3_REG TCNT3L
-#define TCNT3L4_REG TCNT3L
-#define TCNT3L5_REG TCNT3L
-#define TCNT3L6_REG TCNT3L
-#define TCNT3L7_REG TCNT3L
-
-/* ICR5L */
-#define ICR5L0_REG ICR5L
-#define ICR5L1_REG ICR5L
-#define ICR5L2_REG ICR5L
-#define ICR5L3_REG ICR5L
-#define ICR5L4_REG ICR5L
-#define ICR5L5_REG ICR5L
-#define ICR5L6_REG ICR5L
-#define ICR5L7_REG ICR5L
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* ICR5H */
-#define ICR5H0_REG ICR5H
-#define ICR5H1_REG ICR5H
-#define ICR5H2_REG ICR5H
-#define ICR5H3_REG ICR5H
-#define ICR5H4_REG ICR5H
-#define ICR5H5_REG ICR5H
-#define ICR5H6_REG ICR5H
-#define ICR5H7_REG ICR5H
-
-/* MCUSR */
-#define JTRF_REG MCUSR
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* PCIFR */
-#define PCIF0_REG PCIFR
-#define PCIF1_REG PCIFR
-#define PCIF2_REG PCIFR
-
-/* TCCR2A */
-#define WGM20_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2B0_REG TCCR2A
-#define COM2B1_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-
-/* TCCR2B */
-#define CS20_REG TCCR2B
-#define CS21_REG TCCR2B
-#define CS22_REG TCCR2B
-#define WGM22_REG TCCR2B
-#define FOC2B_REG TCCR2B
-#define FOC2A_REG TCCR2B
-
-/* UBRR0H */
-#define UBRR8_REG UBRR0H
-#define UBRR9_REG UBRR0H
-#define UBRR10_REG UBRR0H
-#define UBRR11_REG UBRR0H
-
-/* PING */
-#define PING0_REG PING
-#define PING1_REG PING
-#define PING2_REG PING
-#define PING3_REG PING
-#define PING4_REG PING
-#define PING5_REG PING
-
-/* UBRR0L */
-#define UBRR0_REG UBRR0L
-#define UBRR1_REG UBRR0L
-#define UBRR2_REG UBRR0L
-#define UBRR3_REG UBRR0L
-#define UBRR4_REG UBRR0L
-#define UBRR5_REG UBRR0L
-#define UBRR6_REG UBRR0L
-#define UBRR7_REG UBRR0L
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* ICR4H */
-#define ICR4H0_REG ICR4H
-#define ICR4H1_REG ICR4H
-#define ICR4H2_REG ICR4H
-#define ICR4H3_REG ICR4H
-#define ICR4H4_REG ICR4H
-#define ICR4H5_REG ICR4H
-#define ICR4H6_REG ICR4H
-#define ICR4H7_REG ICR4H
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* PCMSK2 */
-#define PCINT16_REG PCMSK2
-#define PCINT17_REG PCMSK2
-#define PCINT18_REG PCMSK2
-#define PCINT19_REG PCMSK2
-#define PCINT20_REG PCMSK2
-#define PCINT21_REG PCMSK2
-#define PCINT22_REG PCMSK2
-#define PCINT23_REG PCMSK2
-
-/* ICR4L */
-#define ICR4L0_REG ICR4L
-#define ICR4L1_REG ICR4L
-#define ICR4L2_REG ICR4L
-#define ICR4L3_REG ICR4L
-#define ICR4L4_REG ICR4L
-#define ICR4L5_REG ICR4L
-#define ICR4L6_REG ICR4L
-#define ICR4L7_REG ICR4L
-
-/* MCUCR */
-#define JTD_REG MCUCR
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* OCR1CL */
-#define OCR1CL0_REG OCR1CL
-#define OCR1CL1_REG OCR1CL
-#define OCR1CL2_REG OCR1CL
-#define OCR1CL3_REG OCR1CL
-#define OCR1CL4_REG OCR1CL
-#define OCR1CL5_REG OCR1CL
-#define OCR1CL6_REG OCR1CL
-#define OCR1CL7_REG OCR1CL
-
-/* TCNT4L */
-#define TCNT4L0_REG TCNT4L
-#define TCNT4L1_REG TCNT4L
-#define TCNT4L2_REG TCNT4L
-#define TCNT4L3_REG TCNT4L
-#define TCNT4L4_REG TCNT4L
-#define TCNT4L5_REG TCNT4L
-#define TCNT4L6_REG TCNT4L
-#define TCNT4L7_REG TCNT4L
-
-/* OCR1CH */
-#define OCR1CH0_REG OCR1CH
-#define OCR1CH1_REG OCR1CH
-#define OCR1CH2_REG OCR1CH
-#define OCR1CH3_REG OCR1CH
-#define OCR1CH4_REG OCR1CH
-#define OCR1CH5_REG OCR1CH
-#define OCR1CH6_REG OCR1CH
-#define OCR1CH7_REG OCR1CH
-
-/* TCNT4H */
-#define TCNT4H0_REG TCNT4H
-#define TCNT4H1_REG TCNT4H
-#define TCNT4H2_REG TCNT4H
-#define TCNT4H3_REG TCNT4H
-#define TCNT4H4_REG TCNT4H
-#define TCNT4H5_REG TCNT4H
-#define TCNT4H6_REG TCNT4H
-#define TCNT4H7_REG TCNT4H
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* UCSR1B */
-#define TXB81_REG UCSR1B
-#define RXB81_REG UCSR1B
-#define UCSZ12_REG UCSR1B
-#define TXEN1_REG UCSR1B
-#define RXEN1_REG UCSR1B
-#define UDRIE1_REG UCSR1B
-#define TXCIE1_REG UCSR1B
-#define RXCIE1_REG UCSR1B
-
-/* UCSR1C */
-#define UCPOL1_REG UCSR1C
-#define UCSZ10_REG UCSR1C
-#define UCSZ11_REG UCSR1C
-#define USBS1_REG UCSR1C
-#define UPM10_REG UCSR1C
-#define UPM11_REG UCSR1C
-#define UMSEL10_REG UCSR1C
-#define UMSEL11_REG UCSR1C
-
-/* UCSR1A */
-#define MPCM1_REG UCSR1A
-#define U2X1_REG UCSR1A
-#define UPE1_REG UCSR1A
-#define DOR1_REG UCSR1A
-#define FE1_REG UCSR1A
-#define UDRE1_REG UCSR1A
-#define TXC1_REG UCSR1A
-#define RXC1_REG UCSR1A
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* TCCR5A */
-#define WGM50_REG TCCR5A
-#define WGM51_REG TCCR5A
-#define COM5C0_REG TCCR5A
-#define COM5C1_REG TCCR5A
-#define COM5B0_REG TCCR5A
-#define COM5B1_REG TCCR5A
-#define COM5A0_REG TCCR5A
-#define COM5A1_REG TCCR5A
-
-/* TWAMR */
-#define TWAM0_REG TWAMR
-#define TWAM1_REG TWAMR
-#define TWAM2_REG TWAMR
-#define TWAM3_REG TWAMR
-#define TWAM4_REG TWAMR
-#define TWAM5_REG TWAMR
-#define TWAM6_REG TWAMR
-
-/* TCCR5C */
-#define FOC5C_REG TCCR5C
-#define FOC5B_REG TCCR5C
-#define FOC5A_REG TCCR5C
-
-/* TCCR5B */
-#define CS50_REG TCCR5B
-#define CS51_REG TCCR5B
-#define CS52_REG TCCR5B
-#define WGM52_REG TCCR5B
-#define WGM53_REG TCCR5B
-#define ICES5_REG TCCR5B
-#define ICNC5_REG TCCR5B
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ACME_REG ADCSRB
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define MUX5_REG ADCSRB
-
-/* OCR5AL */
-#define OCR5AL0_REG OCR5AL
-#define OCR5AL1_REG OCR5AL
-#define OCR5AL2_REG OCR5AL
-#define OCR5AL3_REG OCR5AL
-#define OCR5AL4_REG OCR5AL
-#define OCR5AL5_REG OCR5AL
-#define OCR5AL6_REG OCR5AL
-#define OCR5AL7_REG OCR5AL
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1C0_REG TCCR1A
-#define COM1C1_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* OCR4CH */
-#define OCR4CH0_REG OCR4CH
-#define OCR4CH1_REG OCR4CH
-#define OCR4CH2_REG OCR4CH
-#define OCR4CH3_REG OCR4CH
-#define OCR4CH4_REG OCR4CH
-#define OCR4CH5_REG OCR4CH
-#define OCR4CH6_REG OCR4CH
-#define OCR4CH7_REG OCR4CH
-
-/* OCR5AH */
-#define OCR5AH0_REG OCR5AH
-#define OCR5AH1_REG OCR5AH
-#define OCR5AH2_REG OCR5AH
-#define OCR5AH3_REG OCR5AH
-#define OCR5AH4_REG OCR5AH
-#define OCR5AH5_REG OCR5AH
-#define OCR5AH6_REG OCR5AH
-#define OCR5AH7_REG OCR5AH
-
-/* OCR4CL */
-#define OCR4CL0_REG OCR4CL
-#define OCR4CL1_REG OCR4CL
-#define OCR4CL2_REG OCR4CL
-#define OCR4CL3_REG OCR4CL
-#define OCR4CL4_REG OCR4CL
-#define OCR4CL5_REG OCR4CL
-#define OCR4CL6_REG OCR4CL
-#define OCR4CL7_REG OCR4CL
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* TCCR1C */
-#define FOC1C_REG TCCR1C
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* ICR3H */
-#define ICR3H0_REG ICR3H
-#define ICR3H1_REG ICR3H
-#define ICR3H2_REG ICR3H
-#define ICR3H3_REG ICR3H
-#define ICR3H4_REG ICR3H
-#define ICR3H5_REG ICR3H
-#define ICR3H6_REG ICR3H
-#define ICR3H7_REG ICR3H
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-#define DDE3_REG DDRE
-#define DDE4_REG DDRE
-#define DDE5_REG DDRE
-#define DDE6_REG DDRE
-#define DDE7_REG DDRE
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* ICR3L */
-#define ICR3L0_REG ICR3L
-#define ICR3L1_REG ICR3L
-#define ICR3L2_REG ICR3L
-#define ICR3L3_REG ICR3L
-#define ICR3L4_REG ICR3L
-#define ICR3L5_REG ICR3L
-#define ICR3L6_REG ICR3L
-#define ICR3L7_REG ICR3L
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-#define PORTE3_REG PORTE
-#define PORTE4_REG PORTE
-#define PORTE5_REG PORTE
-#define PORTE6_REG PORTE
-#define PORTE7_REG PORTE
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define SIGRD_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* OCR5BH */
-#define OCR5BH0_REG OCR5BH
-#define OCR5BH1_REG OCR5BH
-#define OCR5BH2_REG OCR5BH
-#define OCR5BH3_REG OCR5BH
-#define OCR5BH4_REG OCR5BH
-#define OCR5BH5_REG OCR5BH
-#define OCR5BH6_REG OCR5BH
-#define OCR5BH7_REG OCR5BH
-
-/* OCR3BL */
-#define OCR3BL0_REG OCR3BL
-#define OCR3BL1_REG OCR3BL
-#define OCR3BL2_REG OCR3BL
-#define OCR3BL3_REG OCR3BL
-#define OCR3BL4_REG OCR3BL
-#define OCR3BL5_REG OCR3BL
-#define OCR3BL6_REG OCR3BL
-#define OCR3BL7_REG OCR3BL
-
-/* OCR5BL */
-#define OCR5BL0_REG OCR5BL
-#define OCR5BL1_REG OCR5BL
-#define OCR5BL2_REG OCR5BL
-#define OCR5BL3_REG OCR5BL
-#define OCR5BL4_REG OCR5BL
-#define OCR5BL5_REG OCR5BL
-#define OCR5BL6_REG OCR5BL
-#define OCR5BL7_REG OCR5BL
-
-/* OCR3BH */
-#define OCR3BH0_REG OCR3BH
-#define OCR3BH1_REG OCR3BH
-#define OCR3BH2_REG OCR3BH
-#define OCR3BH3_REG OCR3BH
-#define OCR3BH4_REG OCR3BH
-#define OCR3BH5_REG OCR3BH
-#define OCR3BH6_REG OCR3BH
-#define OCR3BH7_REG OCR3BH
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-#define OCIE2B_REG TIMSK2
-
-/* TIMSK3 */
-#define TOIE3_REG TIMSK3
-#define OCIE3A_REG TIMSK3
-#define OCIE3B_REG TIMSK3
-#define OCIE3C_REG TIMSK3
-#define ICIE3_REG TIMSK3
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define OCIE1C_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* TIMSK4 */
-#define TOIE4_REG TIMSK4
-#define OCIE4A_REG TIMSK4
-#define OCIE4B_REG TIMSK4
-#define OCIE4C_REG TIMSK4
-#define ICIE4_REG TIMSK4
-
-/* TIMSK5 */
-#define TOIE5_REG TIMSK5
-#define OCIE5A_REG TIMSK5
-#define OCIE5B_REG TIMSK5
-#define OCIE5C_REG TIMSK5
-#define ICIE5_REG TIMSK5
-
-/* TCCR4B */
-#define CS40_REG TCCR4B
-#define CS41_REG TCCR4B
-#define CS42_REG TCCR4B
-#define WGM42_REG TCCR4B
-#define WGM43_REG TCCR4B
-#define ICES4_REG TCCR4B
-#define ICNC4_REG TCCR4B
-
-/* TCCR4C */
-#define FOC4C_REG TCCR4C
-#define FOC4B_REG TCCR4C
-#define FOC4A_REG TCCR4C
-
-/* TCCR4A */
-#define WGM40_REG TCCR4A
-#define WGM41_REG TCCR4A
-#define COM4C0_REG TCCR4A
-#define COM4C1_REG TCCR4A
-#define COM4B0_REG TCCR4A
-#define COM4B1_REG TCCR4A
-#define COM4A0_REG TCCR4A
-#define COM4A1_REG TCCR4A
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* XMCRB */
-#define XMM0_REG XMCRB
-#define XMM1_REG XMCRB
-#define XMM2_REG XMCRB
-#define XMBK_REG XMCRB
-
-/* XMCRA */
-#define SRW00_REG XMCRA
-#define SRW01_REG XMCRA
-#define SRW10_REG XMCRA
-#define SRW11_REG XMCRA
-#define SRL0_REG XMCRA
-#define SRL1_REG XMCRA
-#define SRL2_REG XMCRA
-#define SRE_REG XMCRA
-
-/* OCR4BL */
-#define OCR4BL0_REG OCR4BL
-#define OCR4BL1_REG OCR4BL
-#define OCR4BL2_REG OCR4BL
-#define OCR4BL3_REG OCR4BL
-#define OCR4BL4_REG OCR4BL
-#define OCR4BL5_REG OCR4BL
-#define OCR4BL6_REG OCR4BL
-#define OCR4BL7_REG OCR4BL
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-#define INTF2_REG EIFR
-#define INTF3_REG EIFR
-#define INTF4_REG EIFR
-#define INTF5_REG EIFR
-#define INTF6_REG EIFR
-#define INTF7_REG EIFR
-
-/* OCR4BH */
-#define OCR4BH0_REG OCR4BH
-#define OCR4BH1_REG OCR4BH
-#define OCR4BH2_REG OCR4BH
-#define OCR4BH3_REG OCR4BH
-#define OCR4BH4_REG OCR4BH
-#define OCR4BH5_REG OCR4BH
-#define OCR4BH6_REG OCR4BH
-#define OCR4BH7_REG OCR4BH
-
-/* PINF */
-#define PINF0_REG PINF
-#define PINF1_REG PINF
-#define PINF2_REG PINF
-#define PINF3_REG PINF
-#define PINF4_REG PINF
-#define PINF5_REG PINF
-#define PINF6_REG PINF
-#define PINF7_REG PINF
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-#define PINE3_REG PINE
-#define PINE4_REG PINE
-#define PINE5_REG PINE
-#define PINE6_REG PINE
-#define PINE7_REG PINE
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* PRR0 */
-#define PRADC_REG PRR0
-#define PRUSART0_REG PRR0
-#define PRSPI_REG PRR0
-#define PRTIM1_REG PRR0
-#define PRTIM0_REG PRR0
-#define PRTIM2_REG PRR0
-#define PRTWI_REG PRR0
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* PRR1 */
-#define PRUSART1_REG PRR1
-#define PRUSART2_REG PRR1
-#define PRUSART3_REG PRR1
-#define PRTIM3_REG PRR1
-#define PRTIM4_REG PRR1
-#define PRTIM5_REG PRR1
-
-/* pins mapping */
-#define AD0_PORT PORTA
-#define AD0_BIT 0
-
-#define AD1_PORT PORTA
-#define AD1_BIT 1
-
-#define AD2_PORT PORTA
-#define AD2_BIT 2
-
-#define AD3_PORT PORTA
-#define AD3_BIT 3
-
-#define AD4_PORT PORTA
-#define AD4_BIT 4
-
-#define AD5_PORT PORTA
-#define AD5_BIT 5
-
-#define AD6_PORT PORTA
-#define AD6_BIT 6
-
-#define AD7_PORT PORTA
-#define AD7_BIT 7
-
-#define SS_PORT PORTB
-#define SS_BIT 0
-#define PCINT0_PORT PORTB
-#define PCINT0_BIT 0
-
-#define SCK_PORT PORTB
-#define SCK_BIT 1
-#define PCINT1_PORT PORTB
-#define PCINT1_BIT 1
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 2
-#define PCINT2_PORT PORTB
-#define PCINT2_BIT 2
-
-#define MISO_PORT PORTB
-#define MISO_BIT 3
-#define PCINT3_PORT PORTB
-#define PCINT3_BIT 3
-
-#define OC2_PORT PORTB
-#define OC2_BIT 4
-#define PCINT4_PORT PORTB
-#define PCINT4_BIT 4
-
-#define OC1A_PORT PORTB
-#define OC1A_BIT 5
-#define PCINT5_PORT PORTB
-#define PCINT5_BIT 5
-
-#define OC1B_PORT PORTB
-#define OC1B_BIT 6
-#define PCINT6_PORT PORTB
-#define PCINT6_BIT 6
-
-#define OC0A_PORT PORTB
-#define OC0A_BIT 7
-#define OC1C_PORT PORTB
-#define OC1C_BIT 7
-#define PCINT7_PORT PORTB
-#define PCINT7_BIT 7
-
-#define A8_PORT PORTC
-#define A8_BIT 0
-
-#define A9_PORT PORTC
-#define A9_BIT 1
-
-#define A10_PORT PORTC
-#define A10_BIT 2
-
-#define A11_PORT PORTC
-#define A11_BIT 3
-
-#define A12_PORT PORTC
-#define A12_BIT 4
-
-#define A13_PORT PORTC
-#define A13_BIT 5
-
-#define A14_PORT PORTC
-#define A14_BIT 6
-
-#define A15_PORT PORTC
-#define A15_BIT 7
-
-#define SCL_PORT PORTD
-#define SCL_BIT 0
-#define INT0_PORT PORTD
-#define INT0_BIT 0
-
-#define SDA_PORT PORTD
-#define SDA_BIT 1
-#define INT1_PORT PORTD
-#define INT1_BIT 1
-
-#define RXD1_PORT PORTD
-#define RXD1_BIT 2
-#define INT2_PORT PORTD
-#define INT2_BIT 2
-
-#define TXD1_PORT PORTD
-#define TXD1_BIT 3
-#define INT3_PORT PORTD
-#define INT3_BIT 3
-
-#define ICP1_PORT PORTD
-#define ICP1_BIT 4
-
-#define XCK1_PORT PORTD
-#define XCK1_BIT 5
-
-#define T1_PORT PORTD
-#define T1_BIT 6
-
-#define T0_PORT PORTD
-#define T0_BIT 7
-
-#define RXD0_PORT PORTE
-#define RXD0_BIT 0
-#define PDI_PORT PORTE
-#define PDI_BIT 0
-#define PCINT8_PORT PORTE
-#define PCINT8_BIT 0
-
-#define TXD0_PORT PORTE
-#define TXD0_BIT 1
-#define PDO_PORT PORTE
-#define PDO_BIT 1
-
-#define XCK0_PORT PORTE
-#define XCK0_BIT 2
-#define AIN0_PORT PORTE
-#define AIN0_BIT 2
-
-#define OC3A_PORT PORTE
-#define OC3A_BIT 3
-#define AIN1_PORT PORTE
-#define AIN1_BIT 3
-
-#define OC3B_PORT PORTE
-#define OC3B_BIT 4
-#define INT4_PORT PORTE
-#define INT4_BIT 4
-
-#define OC3C_PORT PORTE
-#define OC3C_BIT 5
-#define INT5_PORT PORTE
-#define INT5_BIT 5
-
-#define T3_PORT PORTE
-#define T3_BIT 6
-#define INT6_PORT PORTE
-#define INT6_BIT 6
-
-#define ICP3_PORT PORTE
-#define ICP3_BIT 7
-#define INT7_PORT PORTE
-#define INT7_BIT 7
-#define CLKO_PORT PORTE
-#define CLKO_BIT 7
-
-#define ADC0_PORT PORTF
-#define ADC0_BIT 0
-
-#define ADC1_PORT PORTF
-#define ADC1_BIT 1
-
-#define ADC2_PORT PORTF
-#define ADC2_BIT 2
-
-#define ADC3_PORT PORTF
-#define ADC3_BIT 3
-
-#define ADC4_PORT PORTF
-#define ADC4_BIT 4
-#define TCK_PORT PORTF
-#define TCK_BIT 4
-
-#define ADC5_PORT PORTF
-#define ADC5_BIT 5
-#define TMS_PORT PORTF
-#define TMS_BIT 5
-
-#define ADC6_PORT PORTF
-#define ADC6_BIT 6
-#define TD0_PORT PORTF
-#define TD0_BIT 6
-
-#define ADC7_PORT PORTF
-#define ADC7_BIT 7
-#define TDI_PORT PORTF
-#define TDI_BIT 7
-
-#define WR_PORT PORTG
-#define WR_BIT 0
-
-#define RD_PORT PORTG
-#define RD_BIT 1
-
-#define ALE_PORT PORTG
-#define ALE_BIT 2
-
-#define TOSC2_PORT PORTG
-#define TOSC2_BIT 3
-
-#define TOSC1_PORT PORTG
-#define TOSC1_BIT 4
-
-#define OC0B_PORT PORTG
-#define OC0B_BIT 5
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-/* prescalers timer 3 */
-#define TIMER3_PRESCALER_DIV_0 0
-#define TIMER3_PRESCALER_DIV_1 1
-#define TIMER3_PRESCALER_DIV_8 2
-#define TIMER3_PRESCALER_DIV_64 3
-#define TIMER3_PRESCALER_DIV_256 4
-#define TIMER3_PRESCALER_DIV_1024 5
-#define TIMER3_PRESCALER_DIV_FALL 6
-#define TIMER3_PRESCALER_DIV_RISE 7
-
-#define TIMER3_PRESCALER_REG_0 0
-#define TIMER3_PRESCALER_REG_1 1
-#define TIMER3_PRESCALER_REG_2 8
-#define TIMER3_PRESCALER_REG_3 64
-#define TIMER3_PRESCALER_REG_4 256
-#define TIMER3_PRESCALER_REG_5 1024
-#define TIMER3_PRESCALER_REG_6 -1
-#define TIMER3_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-#define TIMER2A_AVAILABLE
-#define TIMER2B_AVAILABLE
-#define TIMER3_AVAILABLE
-#define TIMER3A_AVAILABLE
-#define TIMER3B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW3_NUM 3
-#define SIG_OVERFLOW_TOTAL_NUM 4
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE2A_NUM 4
-#define SIG_OUTPUT_COMPARE2B_NUM 5
-#define SIG_OUTPUT_COMPARE3A_NUM 6
-#define SIG_OUTPUT_COMPARE3B_NUM 7
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 8
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM2A_NUM 4
-#define PWM2B_NUM 5
-#define PWM3A_NUM 6
-#define PWM3B_NUM 7
-#define PWM_TOTAL_NUM 8
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE3_NUM 1
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 2
-
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* RAMPZ */
-#define RAMPZ0_REG RAMPZ
-
-/* OCR2B */
-#define OCR2B_0_REG OCR2B
-#define OCR2B_1_REG OCR2B
-#define OCR2B_2_REG OCR2B
-#define OCR2B_3_REG OCR2B
-#define OCR2B_4_REG OCR2B
-#define OCR2B_5_REG OCR2B
-#define OCR2B_6_REG OCR2B
-#define OCR2B_7_REG OCR2B
-
-/* OCR2A */
-#define OCR2A_0_REG OCR2A
-#define OCR2A_1_REG OCR2A
-#define OCR2A_2_REG OCR2A
-#define OCR2A_3_REG OCR2A
-#define OCR2A_4_REG OCR2A
-#define OCR2A_5_REG OCR2A
-#define OCR2A_6_REG OCR2A
-#define OCR2A_7_REG OCR2A
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-#define EEAR10_REG EEARH
-#define EEAR11_REG EEARH
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL00_REG UCSR0C
-#define UMSEL01_REG UCSR0C
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-
-/* UDR1 */
-#define UDR1_0_REG UDR1
-#define UDR1_1_REG UDR1
-#define UDR1_2_REG UDR1
-#define UDR1_3_REG UDR1
-#define UDR1_4_REG UDR1
-#define UDR1_5_REG UDR1
-#define UDR1_6_REG UDR1
-#define UDR1_7_REG UDR1
-
-/* UDR0 */
-#define UDR0_0_REG UDR0
-#define UDR0_1_REG UDR0
-#define UDR0_2_REG UDR0
-#define UDR0_3_REG UDR0
-#define UDR0_4_REG UDR0
-#define UDR0_5_REG UDR0
-#define UDR0_6_REG UDR0
-#define UDR0_7_REG UDR0
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-#define ISC20_REG EICRA
-#define ISC21_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* ASSR */
-#define TCR2BUB_REG ASSR
-#define TCR2AUB_REG ASSR
-#define OCR2BUB_REG ASSR
-#define OCR2AUB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* UBRR1L */
-#define UBRR_0_REG UBRR1L
-#define UBRR_1_REG UBRR1L
-#define UBRR_2_REG UBRR1L
-#define UBRR_3_REG UBRR1L
-#define UBRR_4_REG UBRR1L
-#define UBRR_5_REG UBRR1L
-#define UBRR_6_REG UBRR1L
-#define UBRR_7_REG UBRR1L
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* OCR3AL */
-/* #define OCR3AL0_REG OCR3AL */ /* dup in OCR3BL */
-/* #define OCR3AL1_REG OCR3AL */ /* dup in OCR3BL */
-/* #define OCR3AL2_REG OCR3AL */ /* dup in OCR3BL */
-/* #define OCR3AL3_REG OCR3AL */ /* dup in OCR3BL */
-/* #define OCR3AL4_REG OCR3AL */ /* dup in OCR3BL */
-/* #define OCR3AL5_REG OCR3AL */ /* dup in OCR3BL */
-/* #define OCR3AL6_REG OCR3AL */ /* dup in OCR3BL */
-/* #define OCR3AL7_REG OCR3AL */ /* dup in OCR3BL */
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* UBRR1H */
-#define UBRR_8_REG UBRR1H
-#define UBRR_9_REG UBRR1H
-#define UBRR_10_REG UBRR1H
-#define UBRR_11_REG UBRR1H
-
-/* OCR3AH */
-/* #define OCR3AH0_REG OCR3AH */ /* dup in OCR3BH */
-/* #define OCR3AH1_REG OCR3AH */ /* dup in OCR3BH */
-/* #define OCR3AH2_REG OCR3AH */ /* dup in OCR3BH */
-/* #define OCR3AH3_REG OCR3AH */ /* dup in OCR3BH */
-/* #define OCR3AH4_REG OCR3AH */ /* dup in OCR3BH */
-/* #define OCR3AH5_REG OCR3AH */ /* dup in OCR3BH */
-/* #define OCR3AH6_REG OCR3AH */ /* dup in OCR3BH */
-/* #define OCR3AH7_REG OCR3AH */ /* dup in OCR3BH */
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* PCICR */
-#define PCIE0_REG PCICR
-#define PCIE1_REG PCICR
-#define PCIE2_REG PCICR
-#define PCIE3_REG PCICR
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-#define OCF2B_REG TIFR2
-
-/* TIFR3 */
-#define TOV3_REG TIFR3
-#define OCF3A_REG TIFR3
-#define OCF3B_REG TIFR3
-#define ICF3_REG TIFR3
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* GTCCR */
-#define PSRSYNC_REG GTCCR
-#define TSM_REG GTCCR
-#define PSRASY_REG GTCCR
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* TCCR3C */
-#define FOC3B_REG TCCR3C
-#define FOC3A_REG TCCR3C
-
-/* TCCR3B */
-#define CS30_REG TCCR3B
-#define CS31_REG TCCR3B
-#define CS32_REG TCCR3B
-#define WGM32_REG TCCR3B
-#define WGM33_REG TCCR3B
-#define ICES3_REG TCCR3B
-#define ICNC3_REG TCCR3B
-
-/* TCCR3A */
-#define WGM30_REG TCCR3A
-#define WGM31_REG TCCR3A
-#define COM3B0_REG TCCR3A
-#define COM3B1_REG TCCR3A
-#define COM3A0_REG TCCR3A
-#define COM3A1_REG TCCR3A
-
-/* OCR1BL */
-/* #define OCR1AL0_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL1_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL2_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL3_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL4_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL5_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL6_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL7_REG OCR1BL */ /* dup in OCR1AL */
-
-/* TCNT3H */
-#define TCNT3H0_REG TCNT3H
-#define TCNT3H1_REG TCNT3H
-#define TCNT3H2_REG TCNT3H
-#define TCNT3H3_REG TCNT3H
-#define TCNT3H4_REG TCNT3H
-#define TCNT3H5_REG TCNT3H
-#define TCNT3H6_REG TCNT3H
-#define TCNT3H7_REG TCNT3H
-
-/* OCR1BH */
-/* #define OCR1AH0_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH1_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH2_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH3_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH4_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH5_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH6_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH7_REG OCR1BH */ /* dup in OCR1AH */
-
-/* TCNT3L */
-#define TCNT3L0_REG TCNT3L
-#define TCNT3L1_REG TCNT3L
-#define TCNT3L2_REG TCNT3L
-#define TCNT3L3_REG TCNT3L
-#define TCNT3L4_REG TCNT3L
-#define TCNT3L5_REG TCNT3L
-#define TCNT3L6_REG TCNT3L
-#define TCNT3L7_REG TCNT3L
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* MCUSR */
-#define JTRF_REG MCUSR
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* PCIFR */
-#define PCIF0_REG PCIFR
-#define PCIF1_REG PCIFR
-#define PCIF2_REG PCIFR
-#define PCIF3_REG PCIFR
-
-/* TCCR2A */
-#define WGM20_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2B0_REG TCCR2A
-#define COM2B1_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-
-/* TCCR2B */
-#define CS20_REG TCCR2B
-#define CS21_REG TCCR2B
-#define CS22_REG TCCR2B
-#define WGM22_REG TCCR2B
-#define FOC2B_REG TCCR2B
-#define FOC2A_REG TCCR2B
-
-/* UBRR0H */
-#define UBRR8_REG UBRR0H
-#define UBRR9_REG UBRR0H
-#define UBRR10_REG UBRR0H
-#define UBRR11_REG UBRR0H
-
-/* UBRR0L */
-#define UBRR0_REG UBRR0L
-#define UBRR1_REG UBRR0L
-#define UBRR2_REG UBRR0L
-#define UBRR3_REG UBRR0L
-#define UBRR4_REG UBRR0L
-#define UBRR5_REG UBRR0L
-#define UBRR6_REG UBRR0L
-#define UBRR7_REG UBRR0L
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* MCUCR */
-#define JTD_REG MCUCR
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-#define BODSE_REG MCUCR
-#define BODS_REG MCUCR
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* UCSR1B */
-#define TXB81_REG UCSR1B
-#define RXB81_REG UCSR1B
-#define UCSZ12_REG UCSR1B
-#define TXEN1_REG UCSR1B
-#define RXEN1_REG UCSR1B
-#define UDRIE1_REG UCSR1B
-#define TXCIE1_REG UCSR1B
-#define RXCIE1_REG UCSR1B
-
-/* UCSR1C */
-#define UCPOL1_REG UCSR1C
-#define UCSZ10_REG UCSR1C
-#define UCSZ11_REG UCSR1C
-#define USBS1_REG UCSR1C
-#define UPM10_REG UCSR1C
-#define UPM11_REG UCSR1C
-#define UMSEL10_REG UCSR1C
-#define UMSEL11_REG UCSR1C
-
-/* UCSR1A */
-#define MPCM1_REG UCSR1A
-#define U2X1_REG UCSR1A
-#define UPE1_REG UCSR1A
-#define DOR1_REG UCSR1A
-#define FE1_REG UCSR1A
-#define UDRE1_REG UCSR1A
-#define TXC1_REG UCSR1A
-#define RXC1_REG UCSR1A
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* TWAMR */
-#define TWAM0_REG TWAMR
-#define TWAM1_REG TWAMR
-#define TWAM2_REG TWAMR
-#define TWAM3_REG TWAMR
-#define TWAM4_REG TWAMR
-#define TWAM5_REG TWAMR
-#define TWAM6_REG TWAMR
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ACME_REG ADCSRB
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-
-/* PRR0 */
-#define PRADC_REG PRR0
-#define PRUSART0_REG PRR0
-#define PRSPI_REG PRR0
-#define PRTIM1_REG PRR0
-#define PRUSART1_REG PRR0
-#define PRTIM0_REG PRR0
-#define PRTIM2_REG PRR0
-#define PRTWI_REG PRR0
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* OCR0A */
-#define OCROA_0_REG OCR0A
-#define OCROA_1_REG OCR0A
-#define OCROA_2_REG OCR0A
-#define OCROA_3_REG OCR0A
-#define OCROA_4_REG OCR0A
-#define OCROA_5_REG OCR0A
-#define OCROA_6_REG OCR0A
-#define OCROA_7_REG OCR0A
-
-/* OCR0B */
-#define OCR0B_0_REG OCR0B
-#define OCR0B_1_REG OCR0B
-#define OCR0B_2_REG OCR0B
-#define OCR0B_3_REG OCR0B
-#define OCR0B_4_REG OCR0B
-#define OCR0B_5_REG OCR0B
-#define OCR0B_6_REG OCR0B
-#define OCR0B_7_REG OCR0B
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* ICR3H */
-#define ICR3H0_REG ICR3H
-#define ICR3H1_REG ICR3H
-#define ICR3H2_REG ICR3H
-#define ICR3H3_REG ICR3H
-#define ICR3H4_REG ICR3H
-#define ICR3H5_REG ICR3H
-#define ICR3H6_REG ICR3H
-#define ICR3H7_REG ICR3H
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* ICR3L */
-#define ICR3L0_REG ICR3L
-#define ICR3L1_REG ICR3L
-#define ICR3L2_REG ICR3L
-#define ICR3L3_REG ICR3L
-#define ICR3L4_REG ICR3L
-#define ICR3L5_REG ICR3L
-#define ICR3L6_REG ICR3L
-#define ICR3L7_REG ICR3L
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define SIGRD_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* OCR3BL */
-/* #define OCR3AL0_REG OCR3BL */ /* dup in OCR3AL */
-/* #define OCR3AL1_REG OCR3BL */ /* dup in OCR3AL */
-/* #define OCR3AL2_REG OCR3BL */ /* dup in OCR3AL */
-/* #define OCR3AL3_REG OCR3BL */ /* dup in OCR3AL */
-/* #define OCR3AL4_REG OCR3BL */ /* dup in OCR3AL */
-/* #define OCR3AL5_REG OCR3BL */ /* dup in OCR3AL */
-/* #define OCR3AL6_REG OCR3BL */ /* dup in OCR3AL */
-/* #define OCR3AL7_REG OCR3BL */ /* dup in OCR3AL */
-
-/* OCR3BH */
-/* #define OCR3AH0_REG OCR3BH */ /* dup in OCR3AH */
-/* #define OCR3AH1_REG OCR3BH */ /* dup in OCR3AH */
-/* #define OCR3AH2_REG OCR3BH */ /* dup in OCR3AH */
-/* #define OCR3AH3_REG OCR3BH */ /* dup in OCR3AH */
-/* #define OCR3AH4_REG OCR3BH */ /* dup in OCR3AH */
-/* #define OCR3AH5_REG OCR3BH */ /* dup in OCR3AH */
-/* #define OCR3AH6_REG OCR3BH */ /* dup in OCR3AH */
-/* #define OCR3AH7_REG OCR3BH */ /* dup in OCR3AH */
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-#define OCIE2B_REG TIMSK2
-
-/* TIMSK3 */
-#define TOIE3_REG TIMSK3
-#define OCIE3A_REG TIMSK3
-#define OCIE3B_REG TIMSK3
-#define ICIE3_REG TIMSK3
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-#define PCINT15_REG PCMSK1
-
-/* PCMSK2 */
-#define PCINT16_REG PCMSK2
-#define PCINT17_REG PCMSK2
-#define PCINT18_REG PCMSK2
-#define PCINT19_REG PCMSK2
-#define PCINT20_REG PCMSK2
-#define PCINT21_REG PCMSK2
-#define PCINT22_REG PCMSK2
-#define PCINT23_REG PCMSK2
-
-/* PCMSK3 */
-#define PCINT24_REG PCMSK3
-#define PCINT25_REG PCMSK3
-#define PCINT26_REG PCMSK3
-#define PCINT27_REG PCMSK3
-#define PCINT28_REG PCMSK3
-#define PCINT29_REG PCMSK3
-#define PCINT30_REG PCMSK3
-#define PCINT31_REG PCMSK3
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-#define INTF2_REG EIFR
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-/* #define OCR1AH0_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH1_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH2_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH3_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH4_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH5_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH6_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH7_REG OCR1AH */ /* dup in OCR1BH */
-
-/* OCR1AL */
-/* #define OCR1AL0_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL1_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL2_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL3_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL4_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL5_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL6_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL7_REG OCR1AL */ /* dup in OCR1BL */
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* PRR1 */
-#define PRTIM3_REG PRR1
-
-/* pins mapping */
-#define ADC0_PORT PORTA
-#define ADC0_BIT 0
-#define PCINT0_PORT PORTA
-#define PCINT0_BIT 0
-
-#define ADC1_PORT PORTA
-#define ADC1_BIT 1
-#define PCINT1_PORT PORTA
-#define PCINT1_BIT 1
-
-#define ADC2_PORT PORTA
-#define ADC2_BIT 2
-#define PCINT2_PORT PORTA
-#define PCINT2_BIT 2
-
-#define ADC3_PORT PORTA
-#define ADC3_BIT 3
-#define PCINT3_PORT PORTA
-#define PCINT3_BIT 3
-
-#define ADC4_PORT PORTA
-#define ADC4_BIT 4
-#define PCINT4_PORT PORTA
-#define PCINT4_BIT 4
-
-#define ADC5_PORT PORTA
-#define ADC5_BIT 5
-#define PCINT5_PORT PORTA
-#define PCINT5_BIT 5
-
-#define ADC6_PORT PORTA
-#define ADC6_BIT 6
-#define PCINT6_PORT PORTA
-#define PCINT6_BIT 6
-
-#define ADC7_PORT PORTA
-#define ADC7_BIT 7
-#define PCINT7_PORT PORTA
-#define PCINT7_BIT 7
-
-#define XCK_PORT PORTB
-#define XCK_BIT 0
-#define T0_PORT PORTB
-#define T0_BIT 0
-#define PCINT9_PORT PORTB
-#define PCINT9_BIT 0
-
-#define T1_PORT PORTB
-#define T1_BIT 1
-#define CLKO_PORT PORTB
-#define CLKO_BIT 1
-#define PCINT9_PORT PORTB
-#define PCINT9_BIT 1
-
-#define AIN0_PORT PORTB
-#define AIN0_BIT 2
-#define INT2_PORT PORTB
-#define INT2_BIT 2
-#define PCINT10_PORT PORTB
-#define PCINT10_BIT 2
-
-#define AIN1_PORT PORTB
-#define AIN1_BIT 3
-#define OC0A_PORT PORTB
-#define OC0A_BIT 3
-#define PCINT11_PORT PORTB
-#define PCINT11_BIT 3
-
-#define SS_PORT PORTB
-#define SS_BIT 4
-#define OC0B_PORT PORTB
-#define OC0B_BIT 4
-#define PCINT12_PORT PORTB
-#define PCINT12_BIT 4
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 5
-#define PCINT13_PORT PORTB
-#define PCINT13_BIT 5
-
-#define MISO_PORT PORTB
-#define MISO_BIT 6
-#define PCINT14_PORT PORTB
-#define PCINT14_BIT 6
-
-#define SCK_PORT PORTB
-#define SCK_BIT 7
-#define PCINT15_PORT PORTB
-#define PCINT15_BIT 7
-
-#define SCL_PORT PORTC
-#define SCL_BIT 0
-#define PCINT16_PORT PORTC
-#define PCINT16_BIT 0
-
-#define SDA_PORT PORTC
-#define SDA_BIT 1
-#define PCINT17_PORT PORTC
-#define PCINT17_BIT 1
-
-#define TCK_PORT PORTC
-#define TCK_BIT 2
-#define PCINT18_PORT PORTC
-#define PCINT18_BIT 2
-
-#define TMS_PORT PORTC
-#define TMS_BIT 3
-#define PCINT19_PORT PORTC
-#define PCINT19_BIT 3
-
-#define TDO_PORT PORTC
-#define TDO_BIT 4
-#define PCINT20_PORT PORTC
-#define PCINT20_BIT 4
-
-#define TDI_PORT PORTC
-#define TDI_BIT 5
-#define PCINT21_PORT PORTC
-#define PCINT21_BIT 5
-
-#define TOSC1_PORT PORTC
-#define TOSC1_BIT 6
-#define PCINT22_PORT PORTC
-#define PCINT22_BIT 6
-
-#define TOSC2_PORT PORTC
-#define TOSC2_BIT 7
-#define PCINT23_PORT PORTC
-#define PCINT23_BIT 7
-
-#define RXD_PORT PORTD
-#define RXD_BIT 0
-#define PCINT24_PORT PORTD
-#define PCINT24_BIT 0
-
-#define TXD_PORT PORTD
-#define TXD_BIT 1
-#define PCINT25_PORT PORTD
-#define PCINT25_BIT 1
-
-#define INT0_PORT PORTD
-#define INT0_BIT 2
-#define RDX1_PORT PORTD
-#define RDX1_BIT 2
-#define PCINT26_PORT PORTD
-#define PCINT26_BIT 2
-
-#define INT1_PORT PORTD
-#define INT1_BIT 3
-#define TXD1_PORT PORTD
-#define TXD1_BIT 3
-#define PCINT27_PORT PORTD
-#define PCINT27_BIT 3
-
-#define OC1B_PORT PORTD
-#define OC1B_BIT 4
-#define XCK1_PORT PORTD
-#define XCK1_BIT 4
-#define PCINT28_PORT PORTD
-#define PCINT28_BIT 4
-
-#define OC1A_PORT PORTD
-#define OC1A_BIT 5
-#define PCINT29_PORT PORTD
-#define PCINT29_BIT 5
-
-#define ICP_PORT PORTD
-#define ICP_BIT 6
-#define OC2B_PORT PORTD
-#define OC2B_BIT 6
-#define PCINT30_PORT PORTD
-#define PCINT30_BIT 6
-
-#define OC2A_PORT PORTD
-#define OC2A_BIT 7
-#define PCINT31_PORT PORTD
-#define PCINT31_BIT 7
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_32 3
-#define TIMER0_PRESCALER_DIV_64 4
-#define TIMER0_PRESCALER_DIV_128 5
-#define TIMER0_PRESCALER_DIV_256 6
-#define TIMER0_PRESCALER_DIV_1024 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 32
-#define TIMER0_PRESCALER_REG_4 64
-#define TIMER0_PRESCALER_REG_5 128
-#define TIMER0_PRESCALER_REG_6 256
-#define TIMER0_PRESCALER_REG_7 1024
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_64 3
-#define TIMER2_PRESCALER_DIV_256 4
-#define TIMER2_PRESCALER_DIV_1024 5
-#define TIMER2_PRESCALER_DIV_FALL 6
-#define TIMER2_PRESCALER_DIV_RISE 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 64
-#define TIMER2_PRESCALER_REG_4 256
-#define TIMER2_PRESCALER_REG_5 1024
-#define TIMER2_PRESCALER_REG_6 -1
-#define TIMER2_PRESCALER_REG_7 -2
-
-/* prescalers timer 3 */
-#define TIMER3_PRESCALER_DIV_0 0
-#define TIMER3_PRESCALER_DIV_1 1
-#define TIMER3_PRESCALER_DIV_8 2
-#define TIMER3_PRESCALER_DIV_64 3
-#define TIMER3_PRESCALER_DIV_256 4
-#define TIMER3_PRESCALER_DIV_1024 5
-#define TIMER3_PRESCALER_DIV_FALL 6
-#define TIMER3_PRESCALER_DIV_RISE 7
-
-#define TIMER3_PRESCALER_REG_0 0
-#define TIMER3_PRESCALER_REG_1 1
-#define TIMER3_PRESCALER_REG_2 8
-#define TIMER3_PRESCALER_REG_3 64
-#define TIMER3_PRESCALER_REG_4 256
-#define TIMER3_PRESCALER_REG_5 1024
-#define TIMER3_PRESCALER_REG_6 -1
-#define TIMER3_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER1C_AVAILABLE
-#define TIMER2_AVAILABLE
-#define TIMER3_AVAILABLE
-#define TIMER3A_AVAILABLE
-#define TIMER3B_AVAILABLE
-#define TIMER3C_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW3_NUM 3
-#define SIG_OVERFLOW_TOTAL_NUM 4
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE1A_NUM 1
-#define SIG_OUTPUT_COMPARE1B_NUM 2
-#define SIG_OUTPUT_COMPARE1C_NUM 3
-#define SIG_OUTPUT_COMPARE2_NUM 4
-#define SIG_OUTPUT_COMPARE3A_NUM 5
-#define SIG_OUTPUT_COMPARE3B_NUM 6
-#define SIG_OUTPUT_COMPARE3C_NUM 7
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 8
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM1A_NUM 1
-#define PWM1B_NUM 2
-#define PWM1C_NUM 3
-#define PWM2_NUM 4
-#define PWM3A_NUM 5
-#define PWM3B_NUM 6
-#define PWM3C_NUM 7
-#define PWM_TOTAL_NUM 8
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE3_NUM 1
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 2
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* RAMPZ */
-#define RAMPZ0_REG RAMPZ
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTG */
-#define PORTG0_REG PORTG
-#define PORTG1_REG PORTG
-#define PORTG2_REG PORTG
-#define PORTG3_REG PORTG
-#define PORTG4_REG PORTG
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL0_REG UCSR0C
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* UDR1 */
-#define UDR10_REG UDR1
-#define UDR11_REG UDR1
-#define UDR12_REG UDR1
-#define UDR13_REG UDR1
-#define UDR14_REG UDR1
-#define UDR15_REG UDR1
-#define UDR16_REG UDR1
-#define UDR17_REG UDR1
-
-/* UDR0 */
-#define UDR00_REG UDR0
-#define UDR01_REG UDR0
-#define UDR02_REG UDR0
-#define UDR03_REG UDR0
-#define UDR04_REG UDR0
-#define UDR05_REG UDR0
-#define UDR06_REG UDR0
-#define UDR07_REG UDR0
-
-/* EICRB */
-#define ISC40_REG EICRB
-#define ISC41_REG EICRB
-#define ISC50_REG EICRB
-#define ISC51_REG EICRB
-#define ISC60_REG EICRB
-#define ISC61_REG EICRB
-#define ISC70_REG EICRB
-#define ISC71_REG EICRB
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-#define ISC20_REG EICRA
-#define ISC21_REG EICRA
-#define ISC30_REG EICRA
-#define ISC31_REG EICRA
-
-/* ASSR */
-#define TCR0UB_REG ASSR
-#define OCR0UB_REG ASSR
-#define TCN0UB_REG ASSR
-#define AS0_REG ASSR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* UBRR1L */
-/* #define UBRR0_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR1_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR2_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR3_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR4_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR5_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR6_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR7_REG UBRR1L */ /* dup in UBRR0L */
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* OCR3AL */
-#define OCR3AL0_REG OCR3AL
-#define OCR3AL1_REG OCR3AL
-#define OCR3AL2_REG OCR3AL
-#define OCR3AL3_REG OCR3AL
-#define OCR3AL4_REG OCR3AL
-#define OCR3AL5_REG OCR3AL
-#define OCR3AL6_REG OCR3AL
-#define OCR3AL7_REG OCR3AL
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* DDRF */
-#define DDF0_REG DDRF
-#define DDF1_REG DDRF
-#define DDF2_REG DDRF
-#define DDF3_REG DDRF
-#define DDF4_REG DDRF
-#define DDF5_REG DDRF
-#define DDF6_REG DDRF
-#define DDF7_REG DDRF
-
-/* DDRG */
-#define DDG0_REG DDRG
-#define DDG1_REG DDRG
-#define DDG2_REG DDRG
-#define DDG3_REG DDRG
-#define DDG4_REG DDRG
-
-/* OCR3AH */
-#define OCR3AH0_REG OCR3AH
-#define OCR3AH1_REG OCR3AH
-#define OCR3AH2_REG OCR3AH
-#define OCR3AH3_REG OCR3AH
-#define OCR3AH4_REG OCR3AH
-#define OCR3AH5_REG OCR3AH
-#define OCR3AH6_REG OCR3AH
-#define OCR3AH7_REG OCR3AH
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* SFIOR */
-#define ACME_REG SFIOR
-#define PSR321_REG SFIOR
-#define PSR0_REG SFIOR
-#define PUD_REG SFIOR
-#define TSM_REG SFIOR
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* UBRR1H */
-/* #define UBRR8_REG UBRR1H */ /* dup in UBRR0H */
-/* #define UBRR9_REG UBRR1H */ /* dup in UBRR0H */
-/* #define UBRR10_REG UBRR1H */ /* dup in UBRR0H */
-/* #define UBRR11_REG UBRR1H */ /* dup in UBRR0H */
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* TIFR */
-#define TOV0_REG TIFR
-#define OCF0_REG TIFR
-#define TOV1_REG TIFR
-#define OCF1B_REG TIFR
-#define OCF1A_REG TIFR
-#define ICF1_REG TIFR
-#define TOV2_REG TIFR
-#define OCF2_REG TIFR
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* ETIFR */
-#define OCF1C_REG ETIFR
-#define OCF3C_REG ETIFR
-#define TOV3_REG ETIFR
-#define OCF3B_REG ETIFR
-#define OCF3A_REG ETIFR
-#define ICF3_REG ETIFR
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* XDIV */
-#define XDIV0_REG XDIV
-#define XDIV1_REG XDIV
-#define XDIV2_REG XDIV
-#define XDIV3_REG XDIV
-#define XDIV4_REG XDIV
-#define XDIV5_REG XDIV
-#define XDIV6_REG XDIV
-#define XDIVEN_REG XDIV
-
-/* OCR3CH */
-#define OCR3CH0_REG OCR3CH
-#define OCR3CH1_REG OCR3CH
-#define OCR3CH2_REG OCR3CH
-#define OCR3CH3_REG OCR3CH
-#define OCR3CH4_REG OCR3CH
-#define OCR3CH5_REG OCR3CH
-#define OCR3CH6_REG OCR3CH
-#define OCR3CH7_REG OCR3CH
-
-/* ETIMSK */
-#define OCIE1C_REG ETIMSK
-#define OCIE3C_REG ETIMSK
-#define TOIE3_REG ETIMSK
-#define OCIE3B_REG ETIMSK
-#define OCIE3A_REG ETIMSK
-#define TICIE3_REG ETIMSK
-
-/* OCR3CL */
-#define OCR3CL0_REG OCR3CL
-#define OCR3CL1_REG OCR3CL
-#define OCR3CL2_REG OCR3CL
-#define OCR3CL3_REG OCR3CL
-#define OCR3CL4_REG OCR3CL
-#define OCR3CL5_REG OCR3CL
-#define OCR3CL6_REG OCR3CL
-#define OCR3CL7_REG OCR3CL
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* TCCR3C */
-#define FOC3C_REG TCCR3C
-#define FOC3B_REG TCCR3C
-#define FOC3A_REG TCCR3C
-
-/* TCCR3B */
-#define CS30_REG TCCR3B
-#define CS31_REG TCCR3B
-#define CS32_REG TCCR3B
-#define WGM32_REG TCCR3B
-#define WGM33_REG TCCR3B
-#define ICES3_REG TCCR3B
-#define ICNC3_REG TCCR3B
-
-/* TCCR3A */
-#define WGM30_REG TCCR3A
-#define WGM31_REG TCCR3A
-#define COM3C0_REG TCCR3A
-#define COM3C1_REG TCCR3A
-#define COM3B0_REG TCCR3A
-#define COM3B1_REG TCCR3A
-#define COM3A0_REG TCCR3A
-#define COM3A1_REG TCCR3A
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* TCNT3H */
-#define TCNT3H0_REG TCNT3H
-#define TCNT3H1_REG TCNT3H
-#define TCNT3H2_REG TCNT3H
-#define TCNT3H3_REG TCNT3H
-#define TCNT3H4_REG TCNT3H
-#define TCNT3H5_REG TCNT3H
-#define TCNT3H6_REG TCNT3H
-#define TCNT3H7_REG TCNT3H
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* TCNT3L */
-#define TCN3L0_REG TCNT3L
-#define TCN3L1_REG TCNT3L
-#define TCN3L2_REG TCNT3L
-#define TCN3L3_REG TCNT3L
-#define TCN3L4_REG TCNT3L
-#define TCN3L5_REG TCNT3L
-#define TCN3L6_REG TCNT3L
-#define TCN3L7_REG TCNT3L
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* MCUCSR */
-#define PORF_REG MCUCSR
-#define EXTRF_REG MCUCSR
-#define BORF_REG MCUCSR
-#define WDRF_REG MCUCSR
-#define JTRF_REG MCUCSR
-#define JTD_REG MCUCSR
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* UBRR0H */
-/* #define UBRR8_REG UBRR0H */ /* dup in UBRR1H */
-/* #define UBRR9_REG UBRR0H */ /* dup in UBRR1H */
-/* #define UBRR10_REG UBRR0H */ /* dup in UBRR1H */
-/* #define UBRR11_REG UBRR0H */ /* dup in UBRR1H */
-
-/* UBRR0L */
-/* #define UBRR0_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR1_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR2_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR3_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR4_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR5_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR6_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR7_REG UBRR0L */ /* dup in UBRR1L */
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-#define EEAR10_REG EEARH
-#define EEAR11_REG EEARH
-
-/* EEARL */
-#define EEARL0_REG EEARL
-#define EEARL1_REG EEARL
-#define EEARL2_REG EEARL
-#define EEARL3_REG EEARL
-#define EEARL4_REG EEARL
-#define EEARL5_REG EEARL
-#define EEARL6_REG EEARL
-#define EEARL7_REG EEARL
-
-/* MCUCR */
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define SM2_REG MCUCR
-#define SM0_REG MCUCR
-#define SM1_REG MCUCR
-#define SE_REG MCUCR
-#define SRW10_REG MCUCR
-#define SRE_REG MCUCR
-
-/* OCR1CL */
-#define OCR1CL0_REG OCR1CL
-#define OCR1CL1_REG OCR1CL
-#define OCR1CL2_REG OCR1CL
-#define OCR1CL3_REG OCR1CL
-#define OCR1CL4_REG OCR1CL
-#define OCR1CL5_REG OCR1CL
-#define OCR1CL6_REG OCR1CL
-#define OCR1CL7_REG OCR1CL
-
-/* OCR1CH */
-#define OCR1CH0_REG OCR1CH
-#define OCR1CH1_REG OCR1CH
-#define OCR1CH2_REG OCR1CH
-#define OCR1CH3_REG OCR1CH
-#define OCR1CH4_REG OCR1CH
-#define OCR1CH5_REG OCR1CH
-#define OCR1CH6_REG OCR1CH
-#define OCR1CH7_REG OCR1CH
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-#define INTF2_REG EIFR
-#define INTF3_REG EIFR
-#define INTF4_REG EIFR
-#define INTF5_REG EIFR
-#define INTF6_REG EIFR
-#define INTF7_REG EIFR
-
-/* UCSR1B */
-#define TXB81_REG UCSR1B
-#define RXB81_REG UCSR1B
-#define UCSZ12_REG UCSR1B
-#define TXEN1_REG UCSR1B
-#define RXEN1_REG UCSR1B
-#define UDRIE1_REG UCSR1B
-#define TXCIE1_REG UCSR1B
-#define RXCIE1_REG UCSR1B
-
-/* UCSR1C */
-#define UCPOL1_REG UCSR1C
-#define UCSZ10_REG UCSR1C
-#define UCSZ11_REG UCSR1C
-#define USBS1_REG UCSR1C
-#define UPM10_REG UCSR1C
-#define UPM11_REG UCSR1C
-#define UMSEL1_REG UCSR1C
-
-/* UCSR1A */
-#define MPCM1_REG UCSR1A
-#define U2X1_REG UCSR1A
-#define UPE1_REG UCSR1A
-#define DOR1_REG UCSR1A
-#define FE1_REG UCSR1A
-#define UDRE1_REG UCSR1A
-#define TXC1_REG UCSR1A
-#define RXC1_REG UCSR1A
-
-/* TCCR0 */
-#define CS00_REG TCCR0
-#define CS01_REG TCCR0
-#define CS02_REG TCCR0
-#define WGM01_REG TCCR0
-#define COM00_REG TCCR0
-#define COM01_REG TCCR0
-#define WGM00_REG TCCR0
-#define FOC0_REG TCCR0
-
-/* TCCR2 */
-#define CS20_REG TCCR2
-#define CS21_REG TCCR2
-#define CS22_REG TCCR2
-#define WGM21_REG TCCR2
-#define COM20_REG TCCR2
-#define COM21_REG TCCR2
-#define WGM20_REG TCCR2
-#define FOC2_REG TCCR2
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* TIMSK */
-#define TOIE0_REG TIMSK
-#define OCIE0_REG TIMSK
-#define TOIE1_REG TIMSK
-#define OCIE1B_REG TIMSK
-#define OCIE1A_REG TIMSK
-#define TICIE1_REG TIMSK
-#define TOIE2_REG TIMSK
-#define OCIE2_REG TIMSK
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-#define INT3_REG EIMSK
-#define INT4_REG EIMSK
-#define INT5_REG EIMSK
-#define INT6_REG EIMSK
-#define INT7_REG EIMSK
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1C0_REG TCCR1A
-#define COM1C1_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* PORTF */
-#define PORTF0_REG PORTF
-#define PORTF1_REG PORTF
-#define PORTF2_REG PORTF
-#define PORTF3_REG PORTF
-#define PORTF4_REG PORTF
-#define PORTF5_REG PORTF
-#define PORTF6_REG PORTF
-#define PORTF7_REG PORTF
-
-/* TCCR1C */
-#define FOC1C_REG TCCR1C
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* ICR3H */
-#define ICR3H0_REG ICR3H
-#define ICR3H1_REG ICR3H
-#define ICR3H2_REG ICR3H
-#define ICR3H3_REG ICR3H
-#define ICR3H4_REG ICR3H
-#define ICR3H5_REG ICR3H
-#define ICR3H6_REG ICR3H
-#define ICR3H7_REG ICR3H
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-#define DDE3_REG DDRE
-#define DDE4_REG DDRE
-#define DDE5_REG DDRE
-#define DDE6_REG DDRE
-#define DDE7_REG DDRE
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* ICR3L */
-#define ICR3L0_REG ICR3L
-#define ICR3L1_REG ICR3L
-#define ICR3L2_REG ICR3L
-#define ICR3L3_REG ICR3L
-#define ICR3L4_REG ICR3L
-#define ICR3L5_REG ICR3L
-#define ICR3L6_REG ICR3L
-#define ICR3L7_REG ICR3L
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-#define PORTE3_REG PORTE
-#define PORTE4_REG PORTE
-#define PORTE5_REG PORTE
-#define PORTE6_REG PORTE
-#define PORTE7_REG PORTE
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* OCR3BL */
-#define OCR3BL0_REG OCR3BL
-#define OCR3BL1_REG OCR3BL
-#define OCR3BL2_REG OCR3BL
-#define OCR3BL3_REG OCR3BL
-#define OCR3BL4_REG OCR3BL
-#define OCR3BL5_REG OCR3BL
-#define OCR3BL6_REG OCR3BL
-#define OCR3BL7_REG OCR3BL
-
-/* OCR3BH */
-#define OCR3BH0_REG OCR3BH
-#define OCR3BH1_REG OCR3BH
-#define OCR3BH2_REG OCR3BH
-#define OCR3BH3_REG OCR3BH
-#define OCR3BH4_REG OCR3BH
-#define OCR3BH5_REG OCR3BH
-#define OCR3BH6_REG OCR3BH
-#define OCR3BH7_REG OCR3BH
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADFR_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* XMCRB */
-#define XMM0_REG XMCRB
-#define XMM1_REG XMCRB
-#define XMM2_REG XMCRB
-#define XMBK_REG XMCRB
-
-/* XMCRA */
-#define SRW11_REG XMCRA
-#define SRW00_REG XMCRA
-#define SRW01_REG XMCRA
-#define SRL0_REG XMCRA
-#define SRL1_REG XMCRA
-#define SRL2_REG XMCRA
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* PING */
-#define PING0_REG PING
-#define PING1_REG PING
-#define PING2_REG PING
-#define PING3_REG PING
-#define PING4_REG PING
-
-/* PINF */
-#define PINF0_REG PINF
-#define PINF1_REG PINF
-#define PINF2_REG PINF
-#define PINF3_REG PINF
-#define PINF4_REG PINF
-#define PINF5_REG PINF
-#define PINF6_REG PINF
-#define PINF7_REG PINF
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-#define PINE3_REG PINE
-#define PINE4_REG PINE
-#define PINE5_REG PINE
-#define PINE6_REG PINE
-#define PINE7_REG PINE
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* OCR0 */
-#define OCR0_0_REG OCR0
-#define OCR0_1_REG OCR0
-#define OCR0_2_REG OCR0
-#define OCR0_3_REG OCR0
-#define OCR0_4_REG OCR0
-#define OCR0_5_REG OCR0
-#define OCR0_6_REG OCR0
-#define OCR0_7_REG OCR0
-
-/* OCR2 */
-#define OCR2_0_REG OCR2
-#define OCR2_1_REG OCR2
-#define OCR2_2_REG OCR2
-#define OCR2_3_REG OCR2
-#define OCR2_4_REG OCR2
-#define OCR2_5_REG OCR2
-#define OCR2_6_REG OCR2
-#define OCR2_7_REG OCR2
-
-/* pins mapping */
-#define AD0_PORT PORTA
-#define AD0_BIT 0
-
-#define AD1_PORT PORTA
-#define AD1_BIT 1
-
-#define AD2_PORT PORTA
-#define AD2_BIT 2
-
-#define AD3_PORT PORTA
-#define AD3_BIT 3
-
-#define AD4_PORT PORTA
-#define AD4_BIT 4
-
-#define AD5_PORT PORTA
-#define AD5_BIT 5
-
-#define AD6_PORT PORTA
-#define AD6_BIT 6
-
-#define AD7_PORT PORTA
-#define AD7_BIT 7
-
-#define SS_PORT PORTB
-#define SS_BIT 0
-
-#define SCK_PORT PORTB
-#define SCK_BIT 1
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 2
-
-#define MISO_PORT PORTB
-#define MISO_BIT 3
-
-#define OC0_PORT PORTB
-#define OC0_BIT 4
-#define PWM0_PORT PORTB
-#define PWM0_BIT 4
-
-#define OC1A_PORT PORTB
-#define OC1A_BIT 5
-#define PWM1A_PORT PORTB
-#define PWM1A_BIT 5
-
-#define OC1B_PORT PORTB
-#define OC1B_BIT 6
-#define PWM1B_PORT PORTB
-#define PWM1B_BIT 6
-
-#define OC2_PORT PORTB
-#define OC2_BIT 7
-#define PWM2_PORT PORTB
-#define PWM2_BIT 7
-#define OC1C_PORT PORTB
-#define OC1C_BIT 7
-
-#define A8_PORT PORTC
-#define A8_BIT 0
-
-#define A9_PORT PORTC
-#define A9_BIT 1
-
-#define A10_PORT PORTC
-#define A10_BIT 2
-
-#define A11_PORT PORTC
-#define A11_BIT 3
-
-#define A12_PORT PORTC
-#define A12_BIT 4
-
-#define A13_PORT PORTC
-#define A13_BIT 5
-
-#define A14_PORT PORTC
-#define A14_BIT 6
-
-#define A15_PORT PORTC
-#define A15_BIT 7
-
-#define SCL_PORT PORTD
-#define SCL_BIT 0
-#define INT0_PORT PORTD
-#define INT0_BIT 0
-
-#define SDA_PORT PORTD
-#define SDA_BIT 1
-#define INT1_PORT PORTD
-#define INT1_BIT 1
-
-#define RXD1_PORT PORTD
-#define RXD1_BIT 2
-#define INT2_PORT PORTD
-#define INT2_BIT 2
-
-#define TXD1_PORT PORTD
-#define TXD1_BIT 3
-#define INT3_PORT PORTD
-#define INT3_BIT 3
-
-#define IC1_PORT PORTD
-#define IC1_BIT 4
-
-#define XCK1_PORT PORTD
-#define XCK1_BIT 5
-
-#define T1_PORT PORTD
-#define T1_BIT 6
-
-#define T2_PORT PORTD
-#define T2_BIT 7
-
-#define RXD0_PORT PORTE
-#define RXD0_BIT 0
-#define PDI_PORT PORTE
-#define PDI_BIT 0
-
-#define TXD0_PORT PORTE
-#define TXD0_BIT 1
-#define PDO_PORT PORTE
-#define PDO_BIT 1
-
-#define XCK0_PORT PORTE
-#define XCK0_BIT 2
-#define AIN0_PORT PORTE
-#define AIN0_BIT 2
-
-#define OC3A_PORT PORTE
-#define OC3A_BIT 3
-#define AIN1_PORT PORTE
-#define AIN1_BIT 3
-
-#define OC3B_PORT PORTE
-#define OC3B_BIT 4
-#define INT4_PORT PORTE
-#define INT4_BIT 4
-
-#define OC3C_PORT PORTE
-#define OC3C_BIT 5
-#define INT5_PORT PORTE
-#define INT5_BIT 5
-
-#define T3_PORT PORTE
-#define T3_BIT 6
-#define INT6_PORT PORTE
-#define INT6_BIT 6
-
-#define IC3_PORT PORTE
-#define IC3_BIT 7
-#define INT7_PORT PORTE
-#define INT7_BIT 7
-
-#define ADC0_PORT PORTF
-#define ADC0_BIT 0
-
-#define ADC1_PORT PORTF
-#define ADC1_BIT 1
-
-#define ADC2_PORT PORTF
-#define ADC2_BIT 2
-
-#define ADC3_PORT PORTF
-#define ADC3_BIT 3
-
-#define ADC4_PORT PORTF
-#define ADC4_BIT 4
-#define TCK_PORT PORTF
-#define TCK_BIT 4
-
-#define ADC5_PORT PORTF
-#define ADC5_BIT 5
-#define TMS_PORT PORTF
-#define TMS_BIT 5
-
-#define ADC6_PORT PORTF
-#define ADC6_BIT 6
-#define TD0_PORT PORTF
-#define TD0_BIT 6
-
-#define ADC7_PORT PORTF
-#define ADC7_BIT 7
-#define TDI_PORT PORTF
-#define TDI_BIT 7
-
-#define WR_PORT PORTG
-#define WR_BIT 0
-
-#define RD_PORT PORTG
-#define RD_BIT 1
-
-#define ALE_PORT PORTG
-#define ALE_BIT 2
-
-#define TOSC2_PORT PORTG
-#define TOSC2_BIT 3
-
-#define TOSC1_PORT PORTG
-#define TOSC1_BIT 4
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE1A_NUM 1
-#define SIG_OUTPUT_COMPARE1B_NUM 2
-#define SIG_OUTPUT_COMPARE2_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM1A_NUM 1
-#define PWM1B_NUM 2
-#define PWM2_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDTOE_REG WDTCR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* TCCR0 */
-#define CS00_REG TCCR0
-#define CS01_REG TCCR0
-#define CS02_REG TCCR0
-#define WGM01_REG TCCR0
-#define COM00_REG TCCR0
-#define COM01_REG TCCR0
-#define WGM00_REG TCCR0
-#define FOC0_REG TCCR0
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* GICR */
-#define IVCE_REG GICR
-#define IVSEL_REG GICR
-#define INT2_REG GICR
-#define INT0_REG GICR
-#define INT1_REG GICR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define FOC1B_REG TCCR1A
-#define FOC1A_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* GIFR */
-#define INTF2_REG GIFR
-#define INTF0_REG GIFR
-#define INTF1_REG GIFR
-
-/* TIMSK */
-#define TOIE0_REG TIMSK
-#define OCIE0_REG TIMSK
-#define TOIE1_REG TIMSK
-#define OCIE1B_REG TIMSK
-#define OCIE1A_REG TIMSK
-#define TICIE1_REG TIMSK
-#define TOIE2_REG TIMSK
-#define OCIE2_REG TIMSK
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* UCSRA */
-#define MPCM_REG UCSRA
-#define U2X_REG UCSRA
-#define UPE_REG UCSRA
-#define DOR_REG UCSRA
-#define FE_REG UCSRA
-#define UDRE_REG UCSRA
-#define TXC_REG UCSRA
-#define RXC_REG UCSRA
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SFIOR */
-#define PSR10_REG SFIOR
-#define PSR2_REG SFIOR
-#define PUD_REG SFIOR
-#define ACME_REG SFIOR
-#define ADTS0_REG SFIOR
-#define ADTS1_REG SFIOR
-#define ADTS2_REG SFIOR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* UCSRB */
-#define TXB8_REG UCSRB
-#define RXB8_REG UCSRB
-#define UCSZ2_REG UCSRB
-#define TXEN_REG UCSRB
-#define RXEN_REG UCSRB
-#define UDRIE_REG UCSRB
-#define TXCIE_REG UCSRB
-#define RXCIE_REG UCSRB
-
-/* UCSRC */
-#define UCPOL_REG UCSRC
-#define UCSZ0_REG UCSRC
-#define UCSZ1_REG UCSRC
-#define USBS_REG UCSRC
-#define UPM0_REG UCSRC
-#define UPM1_REG UCSRC
-#define UMSEL_REG UCSRC
-#define URSEL_REG UCSRC
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* UDR */
-#define UDR0_REG UDR
-#define UDR1_REG UDR
-#define UDR2_REG UDR
-#define UDR3_REG UDR
-#define UDR4_REG UDR
-#define UDR5_REG UDR
-#define UDR6_REG UDR
-#define UDR7_REG UDR
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* UBRRH */
-#define UBRR8_REG UBRRH
-#define UBRR9_REG UBRRH
-#define UBRR10_REG UBRRH
-#define UBRR11_REG UBRRH
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* UBRRL */
-#define UBRR0_REG UBRRL
-#define UBRR1_REG UBRRL
-#define UBRR2_REG UBRRL
-#define UBRR3_REG UBRRL
-#define UBRR4_REG UBRRL
-#define UBRR5_REG UBRRL
-#define UBRR6_REG UBRRL
-#define UBRR7_REG UBRRL
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* MCUCSR */
-#define ISC2_REG MCUCSR
-#define PORF_REG MCUCSR
-#define EXTRF_REG MCUCSR
-#define BORF_REG MCUCSR
-#define WDRF_REG MCUCSR
-#define JTRF_REG MCUCSR
-#define JTD_REG MCUCSR
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* TCCR2 */
-#define CS20_REG TCCR2
-#define CS21_REG TCCR2
-#define CS22_REG TCCR2
-#define WGM21_REG TCCR2
-#define COM20_REG TCCR2
-#define COM21_REG TCCR2
-#define WGM20_REG TCCR2
-#define FOC2_REG TCCR2
-
-/* TIFR */
-#define TOV0_REG TIFR
-#define OCF0_REG TIFR
-#define TOV1_REG TIFR
-#define OCF1B_REG TIFR
-#define OCF1A_REG TIFR
-#define ICF1_REG TIFR
-#define TOV2_REG TIFR
-#define OCF2_REG TIFR
-
-/* EEARH */
-#define EEAR8_REG EEARH
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* OCR0 */
-#define OCR0_0_REG OCR0
-#define OCR0_1_REG OCR0
-#define OCR0_2_REG OCR0
-#define OCR0_3_REG OCR0
-#define OCR0_4_REG OCR0
-#define OCR0_5_REG OCR0
-#define OCR0_6_REG OCR0
-#define OCR0_7_REG OCR0
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define ISC10_REG MCUCR
-#define ISC11_REG MCUCR
-#define SM0_REG MCUCR
-#define SM1_REG MCUCR
-#define SE_REG MCUCR
-#define SM2_REG MCUCR
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* OCR2 */
-#define OCR2_0_REG OCR2
-#define OCR2_1_REG OCR2
-#define OCR2_2_REG OCR2
-#define OCR2_3_REG OCR2
-#define OCR2_4_REG OCR2
-#define OCR2_5_REG OCR2
-#define OCR2_6_REG OCR2
-#define OCR2_7_REG OCR2
-
-/* ASSR */
-#define TCR2UB_REG ASSR
-#define OCR2UB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-
-/* pins mapping */
-#define ADC0_PORT PORTA
-#define ADC0_BIT 0
-
-#define ADC1_PORT PORTA
-#define ADC1_BIT 1
-
-#define ADC2_PORT PORTA
-#define ADC2_BIT 2
-
-#define ADC3_PORT PORTA
-#define ADC3_BIT 3
-
-#define ADC4_PORT PORTA
-#define ADC4_BIT 4
-
-#define ADc5_PORT PORTA
-#define ADc5_BIT 5
-
-#define ADC6_PORT PORTA
-#define ADC6_BIT 6
-
-#define ADC7_PORT PORTA
-#define ADC7_BIT 7
-
-#define T0_PORT PORTB
-#define T0_BIT 0
-
-#define T1_PORT PORTB
-#define T1_BIT 1
-
-#define AIN0_PORT PORTB
-#define AIN0_BIT 2
-
-#define AIN1_PORT PORTB
-#define AIN1_BIT 3
-
-#define SS_PORT PORTB
-#define SS_BIT 4
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 5
-
-#define MISO_PORT PORTB
-#define MISO_BIT 6
-
-
-#define SCL_PORT PORTC
-#define SCL_BIT 0
-
-#define SDA_PORT PORTC
-#define SDA_BIT 1
-
-#define TMS_PORT PORTC
-#define TMS_BIT 2
-
-
-
-
-#define TOSC1_PORT PORTC
-#define TOSC1_BIT 6
-
-#define TOSC2_PORT PORTC
-#define TOSC2_BIT 7
-
-#define RXD_PORT PORTD
-#define RXD_BIT 0
-
-#define TXD_PORT PORTD
-#define TXD_BIT 1
-
-#define INT0_PORT PORTD
-#define INT0_BIT 2
-
-#define INT1_PORT PORTD
-#define INT1_BIT 3
-
-#define OC1B_PORT PORTD
-#define OC1B_BIT 4
-
-#define OC1A_PORT PORTD
-#define OC1A_BIT 5
-
-#define ICP_PORT PORTD
-#define ICP_BIT 6
-
-#define OC2_PORT PORTD
-#define OC2_BIT 7
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE1A_NUM 1
-#define SIG_OUTPUT_COMPARE1B_NUM 2
-#define SIG_OUTPUT_COMPARE2_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM1A_NUM 1
-#define PWM1B_NUM 2
-#define PWM2_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDTOE_REG WDTCR
-
-/* GIMSK */
-#define INT2_REG GIMSK
-#define INT0_REG GIMSK
-#define INT1_REG GIMSK
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* UCSR1B */
-#define TXB81_REG UCSR1B
-#define RXB81_REG UCSR1B
-#define CHR91_REG UCSR1B
-#define TXEN1_REG UCSR1B
-#define RXEN1_REG UCSR1B
-#define UDR1IE1_REG UCSR1B
-#define TXCIE1_REG UCSR1B
-#define RXCIE1_REG UCSR1B
-
-/* UCSR1A */
-#define MPCM1_REG UCSR1A
-#define U2X1_REG UCSR1A
-#define OR1_REG UCSR1A
-#define FE1_REG UCSR1A
-#define UDRE1_REG UCSR1A
-#define TXC1_REG UCSR1A
-#define RXC1_REG UCSR1A
-
-/* TCCR0 */
-#define CS00_REG TCCR0
-#define CS01_REG TCCR0
-#define CS02_REG TCCR0
-#define WGM01_REG TCCR0
-#define COM00_REG TCCR0
-#define COM01_REG TCCR0
-#define WGM00_REG TCCR0
-#define FOC0_REG TCCR0
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* UBRR1 */
-#define UBRR10_REG UBRR1
-#define UBRR11_REG UBRR1
-#define UBRR12_REG UBRR1
-#define UBRR13_REG UBRR1
-#define UBRR14_REG UBRR1
-#define UBRR15_REG UBRR1
-#define UBRR16_REG UBRR1
-#define UBRR17_REG UBRR1
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define FOC1B_REG TCCR1A
-#define FOC1A_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define CTC1_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* GIFR */
-#define INTF2_REG GIFR
-#define INTF0_REG GIFR
-#define INTF1_REG GIFR
-
-/* TIMSK */
-#define OCIE0_REG TIMSK
-#define TOIE0_REG TIMSK
-#define OCIE2_REG TIMSK
-#define TOIE2_REG TIMSK
-#define TICIE1_REG TIMSK
-#define OCIE1B_REG TIMSK
-#define OCIE1A_REG TIMSK
-#define TOIE1_REG TIMSK
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* SFIOR */
-#define PSR10_REG SFIOR
-#define PSR2_REG SFIOR
-
-/* UDR0 */
-#define UDR00_REG UDR0
-#define UDR01_REG UDR0
-#define UDR02_REG UDR0
-#define UDR03_REG UDR0
-#define UDR04_REG UDR0
-#define UDR05_REG UDR0
-#define UDR06_REG UDR0
-#define UDR07_REG UDR0
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* UBRRHI */
-#define UBRRHI00_REG UBRRHI
-#define UBRRHI01_REG UBRRHI
-#define UBRRHI02_REG UBRRHI
-#define UBRRHI03_REG UBRRHI
-#define UBRRHI10_REG UBRRHI
-#define UBRRHI11_REG UBRRHI
-#define UBRRHI12_REG UBRRHI
-#define UBRRHI13_REG UBRRHI
-
-/* EMCUCR */
-#define ISC2_REG EMCUCR
-#define SRW11_REG EMCUCR
-#define SRW00_REG EMCUCR
-#define SRW01_REG EMCUCR
-#define SRL0_REG EMCUCR
-#define SRL1_REG EMCUCR
-#define SRL2_REG EMCUCR
-#define SM0_REG EMCUCR
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* SPMCR */
-#define SPMEN_REG SPMCR
-#define PGERS_REG SPMCR
-#define PGWRT_REG SPMCR
-#define BLBSET_REG SPMCR
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define AINBG_REG ACSR
-#define ACD_REG ACSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* UBRR0 */
-#define UBRR00_REG UBRR0
-#define UBRR01_REG UBRR0
-#define UBRR02_REG UBRR0
-#define UBRR03_REG UBRR0
-#define UBRR04_REG UBRR0
-#define UBRR05_REG UBRR0
-#define UBRR06_REG UBRR0
-#define UBRR07_REG UBRR0
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define CHR90_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDR0IE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define OR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* TCCR2 */
-#define CS20_REG TCCR2
-#define CS21_REG TCCR2
-#define CS22_REG TCCR2
-#define CTC2_REG TCCR2
-#define COM20_REG TCCR2
-#define COM21_REG TCCR2
-#define PWM2_REG TCCR2
-#define FOC2_REG TCCR2
-
-/* UDR1 */
-#define UDR10_REG UDR1
-#define UDR11_REG UDR1
-#define UDR12_REG UDR1
-#define UDR13_REG UDR1
-#define UDR14_REG UDR1
-#define UDR15_REG UDR1
-#define UDR16_REG UDR1
-#define UDR17_REG UDR1
-
-/* TIFR */
-#define OCF0_REG TIFR
-#define TOV0_REG TIFR
-#define OCF2_REG TIFR
-#define TOV2_REG TIFR
-#define ICF1_REG TIFR
-#define OCF1B_REG TIFR
-#define OCF1A_REG TIFR
-#define TOV1_REG TIFR
-
-/* EEARH */
-#define EEAR8_REG EEARH
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define ISC10_REG MCUCR
-#define ISC11_REG MCUCR
-#define SM1_REG MCUCR
-#define SE_REG MCUCR
-#define SRW10_REG MCUCR
-#define SRE_REG MCUCR
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* OCR0 */
-#define OCR0_0_REG OCR0
-#define OCR0_1_REG OCR0
-#define OCR0_2_REG OCR0
-#define OCR0_3_REG OCR0
-#define OCR0_4_REG OCR0
-#define OCR0_5_REG OCR0
-#define OCR0_6_REG OCR0
-#define OCR0_7_REG OCR0
-
-/* OCR2 */
-#define OCR2_0_REG OCR2
-#define OCR2_1_REG OCR2
-#define OCR2_2_REG OCR2
-#define OCR2_3_REG OCR2
-#define OCR2_4_REG OCR2
-#define OCR2_5_REG OCR2
-#define OCR2_6_REG OCR2
-#define OCR2_7_REG OCR2
-
-/* ASSR */
-#define TCR2UB_REG ASSR
-#define OCR2UB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-
-/* pins mapping */
-#define AD0_PORT PORTA
-#define AD0_BIT 0
-
-#define AD1_PORT PORTA
-#define AD1_BIT 1
-
-#define AD2_PORT PORTA
-#define AD2_BIT 2
-
-#define AD3_PORT PORTA
-#define AD3_BIT 3
-
-#define AD4_PORT PORTA
-#define AD4_BIT 4
-
-#define AD5_PORT PORTA
-#define AD5_BIT 5
-
-#define AD6_PORT PORTA
-#define AD6_BIT 6
-
-#define AD7_PORT PORTA
-#define AD7_BIT 7
-
-#define OC0/T0_PORT PORTB
-#define OC0/T0_BIT 0
-
-#define OC2/T1_PORT PORTB
-#define OC2/T1_BIT 1
-
-#define RXD1_PORT PORTB
-#define RXD1_BIT 2
-#define AIN0_PORT PORTB
-#define AIN0_BIT 2
-
-#define TXD1_PORT PORTB
-#define TXD1_BIT 3
-#define AIN1_PORT PORTB
-#define AIN1_BIT 3
-
-#define SS_PORT PORTB
-#define SS_BIT 4
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 5
-
-#define MISO_PORT PORTB
-#define MISO_BIT 6
-
-#define SCK_PORT PORTB
-#define SCK_BIT 7
-
-#define A8_PORT PORTC
-#define A8_BIT 0
-
-#define A9_PORT PORTC
-#define A9_BIT 1
-
-#define A10_PORT PORTC
-#define A10_BIT 2
-
-#define A11_PORT PORTC
-#define A11_BIT 3
-
-#define A12_PORT PORTC
-#define A12_BIT 4
-
-#define A13_PORT PORTC
-#define A13_BIT 5
-
-#define A14_PORT PORTC
-#define A14_BIT 6
-
-#define A15_PORT PORTC
-#define A15_BIT 7
-
-#define RXD_PORT PORTD
-#define RXD_BIT 0
-
-#define TXD_PORT PORTD
-#define TXD_BIT 1
-
-#define INT0_PORT PORTD
-#define INT0_BIT 2
-
-#define INT1_PORT PORTD
-#define INT1_BIT 3
-
-
-#define OC1A_PORT PORTD
-#define OC1A_BIT 5
-#define TOSC2_PORT PORTD
-#define TOSC2_BIT 5
-
-#define WR_PORT PORTD
-#define WR_BIT 6
-
-#define RD_PORT PORTD
-#define RD_BIT 7
-
-#define ICP/INT2_PORT PORTE
-#define ICP/INT2_BIT 0
-
-#define ALE_PORT PORTE
-#define ALE_BIT 1
-
-#define OC1B_PORT PORTE
-#define OC1B_BIT 2
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE1A_NUM 1
-#define SIG_OUTPUT_COMPARE1B_NUM 2
-#define SIG_OUTPUT_COMPARE2_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM1A_NUM 1
-#define PWM1B_NUM 2
-#define PWM2_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDTOE_REG WDTCR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* UCSR1B */
-#define TXB81_REG UCSR1B
-#define RXB81_REG UCSR1B
-#define UCSZ12_REG UCSR1B
-#define TXEN1_REG UCSR1B
-#define RXEN1_REG UCSR1B
-#define UDRIE1_REG UCSR1B
-#define TXCIE1_REG UCSR1B
-#define RXCIE1_REG UCSR1B
-
-/* UCSR1C */
-#define UCPOL1_REG UCSR1C
-#define UCSZ10_REG UCSR1C
-#define UCSZ11_REG UCSR1C
-#define USBS1_REG UCSR1C
-#define UPM10_REG UCSR1C
-#define UPM11_REG UCSR1C
-#define UMSEL1_REG UCSR1C
-#define URSEL1_REG UCSR1C
-
-/* UCSR1A */
-#define MPCM1_REG UCSR1A
-#define U2X1_REG UCSR1A
-#define UPE1_REG UCSR1A
-#define DOR1_REG UCSR1A
-#define FE1_REG UCSR1A
-#define UDRE1_REG UCSR1A
-#define TXC1_REG UCSR1A
-#define RXC1_REG UCSR1A
-
-/* TCCR0 */
-#define CS00_REG TCCR0
-#define CS01_REG TCCR0
-#define CS02_REG TCCR0
-#define WGM01_REG TCCR0
-#define COM00_REG TCCR0
-#define COM01_REG TCCR0
-#define WGM00_REG TCCR0
-#define FOC0_REG TCCR0
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* GICR */
-#define IVCE_REG GICR
-#define IVSEL_REG GICR
-#define PCIE0_REG GICR
-#define PCIE1_REG GICR
-#define INT2_REG GICR
-#define INT0_REG GICR
-#define INT1_REG GICR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define FOC1B_REG TCCR1A
-#define FOC1A_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define CTC1_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* GIFR */
-#define PCIF0_REG GIFR
-#define PCIF1_REG GIFR
-#define INTF2_REG GIFR
-#define INTF0_REG GIFR
-#define INTF1_REG GIFR
-
-/* TIMSK */
-#define OCIE0_REG TIMSK
-#define TOIE0_REG TIMSK
-#define TICIE1_REG TIMSK
-#define OCIE1B_REG TIMSK
-#define OCIE1A_REG TIMSK
-#define TOIE1_REG TIMSK
-#define TOIE2_REG TIMSK
-#define OCIE2_REG TIMSK
-
-/* UBRR0H */
-/* #define UBRR8_REG UBRR0H */ /* dup in UBRR1H */
-/* #define UBRR9_REG UBRR0H */ /* dup in UBRR1H */
-/* #define UBRR10_REG UBRR0H */ /* dup in UBRR1H */
-/* #define UBRR11_REG UBRR0H */ /* dup in UBRR1H */
-/* #define URSEL0_REG UBRR0H */ /* dup in UCSR0C */
-
-/* UBRR1H */
-/* #define UBRR8_REG UBRR1H */ /* dup in UBRR0H */
-/* #define UBRR9_REG UBRR1H */ /* dup in UBRR0H */
-/* #define UBRR10_REG UBRR1H */ /* dup in UBRR0H */
-/* #define UBRR11_REG UBRR1H */ /* dup in UBRR0H */
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* SFIOR */
-#define PSR10_REG SFIOR
-#define PSR310_REG SFIOR
-#define PSR2_REG SFIOR
-#define PUD_REG SFIOR
-#define XMM0_REG SFIOR
-#define XMM1_REG SFIOR
-#define XMM2_REG SFIOR
-#define XMBK_REG SFIOR
-#define TSM_REG SFIOR
-
-/* UDR0 */
-#define UDR0_0_REG UDR0
-#define UDR0_1_REG UDR0
-#define UDR0_2_REG UDR0
-#define UDR0_3_REG UDR0
-#define UDR0_4_REG UDR0
-#define UDR0_5_REG UDR0
-#define UDR0_6_REG UDR0
-#define UDR0_7_REG UDR0
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* EMCUCR */
-#define ISC2_REG EMCUCR
-#define SRW11_REG EMCUCR
-#define SRW00_REG EMCUCR
-#define SRW01_REG EMCUCR
-#define SRL0_REG EMCUCR
-#define SRL1_REG EMCUCR
-#define SRL2_REG EMCUCR
-#define SM0_REG EMCUCR
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* SPMCR */
-#define SPMEN_REG SPMCR
-#define PGERS_REG SPMCR
-#define PGWRT_REG SPMCR
-#define BLBSET_REG SPMCR
-#define RWWSRE_REG SPMCR
-#define RWWSB_REG SPMCR
-#define SPMIE_REG SPMCR
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL0_REG UCSR0C
-/* #define URSEL0_REG UCSR0C */ /* dup in UBRR0H */
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* MCUCSR */
-#define PORF_REG MCUCSR
-#define EXTRF_REG MCUCSR
-#define BORF_REG MCUCSR
-#define WDRF_REG MCUCSR
-#define JTRF_REG MCUCSR
-#define SM2_REG MCUCSR
-#define JDT_REG MCUCSR
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* UBRR1L */
-#define UBRR1L0_REG UBRR1L
-#define UBRR1L1_REG UBRR1L
-#define UBRR1L2_REG UBRR1L
-#define UBRR1L3_REG UBRR1L
-#define UBRR1L4_REG UBRR1L
-#define UBRR1L5_REG UBRR1L
-#define UBRR1L6_REG UBRR1L
-#define UBRR1L7_REG UBRR1L
-
-/* TCCR2 */
-#define CS20_REG TCCR2
-#define CS21_REG TCCR2
-#define CS22_REG TCCR2
-#define WGM21_REG TCCR2
-#define COM20_REG TCCR2
-#define COM21_REG TCCR2
-#define WGM20_REG TCCR2
-#define FOC2_REG TCCR2
-
-/* UDR1 */
-#define UDR1_0_REG UDR1
-#define UDR1_1_REG UDR1
-#define UDR1_2_REG UDR1
-#define UDR1_3_REG UDR1
-#define UDR1_4_REG UDR1
-#define UDR1_5_REG UDR1
-#define UDR1_6_REG UDR1
-#define UDR1_7_REG UDR1
-
-/* TIFR */
-#define OCF0_REG TIFR
-#define TOV0_REG TIFR
-#define ICF1_REG TIFR
-#define OCF1B_REG TIFR
-#define OCF1A_REG TIFR
-#define TOV1_REG TIFR
-#define TOV2_REG TIFR
-#define OCF2_REG TIFR
-
-/* UBRR0L */
-#define UBRR0_REG UBRR0L
-#define UBRR1_REG UBRR0L
-#define UBRR2_REG UBRR0L
-#define UBRR3_REG UBRR0L
-#define UBRR4_REG UBRR0L
-#define UBRR5_REG UBRR0L
-#define UBRR6_REG UBRR0L
-#define UBRR7_REG UBRR0L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-#define PCINT15_REG PCMSK1
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define ISC10_REG MCUCR
-#define ISC11_REG MCUCR
-#define SM1_REG MCUCR
-#define SE_REG MCUCR
-#define SRW10_REG MCUCR
-#define SRE_REG MCUCR
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* OCR0 */
-#define OCR0_0_REG OCR0
-#define OCR0_1_REG OCR0
-#define OCR0_2_REG OCR0
-#define OCR0_3_REG OCR0
-#define OCR0_4_REG OCR0
-#define OCR0_5_REG OCR0
-#define OCR0_6_REG OCR0
-#define OCR0_7_REG OCR0
-
-/* OCR2 */
-#define OCR2_0_REG OCR2
-#define OCR2_1_REG OCR2
-#define OCR2_2_REG OCR2
-#define OCR2_3_REG OCR2
-#define OCR2_4_REG OCR2
-#define OCR2_5_REG OCR2
-#define OCR2_6_REG OCR2
-#define OCR2_7_REG OCR2
-
-/* ASSR */
-#define TCR2UB_REG ASSR
-#define OCR2UB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-
-/* pins mapping */
-#define AD0_PORT PORTA
-#define AD0_BIT 0
-
-#define AD1_PORT PORTA
-#define AD1_BIT 1
-
-#define AD2_PORT PORTA
-#define AD2_BIT 2
-
-#define AD3_PORT PORTA
-#define AD3_BIT 3
-
-#define AD4_PORT PORTA
-#define AD4_BIT 4
-
-#define AD5_PORT PORTA
-#define AD5_BIT 5
-
-#define AD6_PORT PORTA
-#define AD6_BIT 6
-
-#define AD7_PORT PORTA
-#define AD7_BIT 7
-
-#define OC0/T0_PORT PORTB
-#define OC0/T0_BIT 0
-
-#define OC2/T1_PORT PORTB
-#define OC2/T1_BIT 1
-
-#define RXD1_PORT PORTB
-#define RXD1_BIT 2
-#define AIN0_PORT PORTB
-#define AIN0_BIT 2
-
-#define TXD1_PORT PORTB
-#define TXD1_BIT 3
-#define AIN1_PORT PORTB
-#define AIN1_BIT 3
-
-#define SS_PORT PORTB
-#define SS_BIT 4
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 5
-
-#define MISO_PORT PORTB
-#define MISO_BIT 6
-
-#define SCK_PORT PORTB
-#define SCK_BIT 7
-
-#define A8_PORT PORTC
-#define A8_BIT 0
-
-#define A9_PORT PORTC
-#define A9_BIT 1
-
-#define A10_PORT PORTC
-#define A10_BIT 2
-
-#define A11_PORT PORTC
-#define A11_BIT 3
-
-#define A12_PORT PORTC
-#define A12_BIT 4
-
-#define A13_PORT PORTC
-#define A13_BIT 5
-
-#define A14_PORT PORTC
-#define A14_BIT 6
-
-#define A15_PORT PORTC
-#define A15_BIT 7
-
-#define RXD_PORT PORTD
-#define RXD_BIT 0
-
-#define TXD_PORT PORTD
-#define TXD_BIT 1
-
-#define INT0_PORT PORTD
-#define INT0_BIT 2
-
-#define INT1_PORT PORTD
-#define INT1_BIT 3
-
-
-#define OC1A_PORT PORTD
-#define OC1A_BIT 5
-#define TOSC2_PORT PORTD
-#define TOSC2_BIT 5
-
-#define WR_PORT PORTD
-#define WR_BIT 6
-
-#define RD_PORT PORTD
-#define RD_BIT 7
-
-#define ICP/INT2_PORT PORTE
-#define ICP/INT2_BIT 0
-
-#define ALE_PORT PORTE
-#define ALE_BIT 1
-
-#define OC1B_PORT PORTE
-#define OC1B_BIT 2
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-/* prescalers timer 3 */
-#define TIMER3_PRESCALER_DIV_0 0
-#define TIMER3_PRESCALER_DIV_1 1
-#define TIMER3_PRESCALER_DIV_8 2
-#define TIMER3_PRESCALER_DIV_64 3
-#define TIMER3_PRESCALER_DIV_256 4
-#define TIMER3_PRESCALER_DIV_1024 5
-#define TIMER3_PRESCALER_DIV_16 6
-#define TIMER3_PRESCALER_DIV_32 7
-
-#define TIMER3_PRESCALER_REG_0 0
-#define TIMER3_PRESCALER_REG_1 1
-#define TIMER3_PRESCALER_REG_2 8
-#define TIMER3_PRESCALER_REG_3 64
-#define TIMER3_PRESCALER_REG_4 256
-#define TIMER3_PRESCALER_REG_5 1024
-#define TIMER3_PRESCALER_REG_6 16
-#define TIMER3_PRESCALER_REG_7 32
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-#define TIMER3_AVAILABLE
-#define TIMER3A_AVAILABLE
-#define TIMER3B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW3_NUM 3
-#define SIG_OVERFLOW_TOTAL_NUM 4
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE1A_NUM 1
-#define SIG_OUTPUT_COMPARE1B_NUM 2
-#define SIG_OUTPUT_COMPARE2_NUM 3
-#define SIG_OUTPUT_COMPARE3A_NUM 4
-#define SIG_OUTPUT_COMPARE3B_NUM 5
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 6
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM1A_NUM 1
-#define PWM1B_NUM 2
-#define PWM2_NUM 3
-#define PWM3A_NUM 4
-#define PWM3B_NUM 5
-#define PWM_TOTAL_NUM 6
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE3_NUM 1
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 2
-
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* UCSR1B */
-#define TXB81_REG UCSR1B
-#define RXB81_REG UCSR1B
-#define UCSZ12_REG UCSR1B
-#define TXEN1_REG UCSR1B
-#define RXEN1_REG UCSR1B
-#define UDRIE1_REG UCSR1B
-#define TXCIE1_REG UCSR1B
-#define RXCIE1_REG UCSR1B
-
-/* UCSR1C */
-#define UCPOL1_REG UCSR1C
-#define UCSZ10_REG UCSR1C
-#define UCSZ11_REG UCSR1C
-#define USBS1_REG UCSR1C
-#define UPM10_REG UCSR1C
-#define UPM11_REG UCSR1C
-#define UMSEL1_REG UCSR1C
-#define URSEL1_REG UCSR1C
-
-/* UCSR1A */
-#define MPCM1_REG UCSR1A
-#define U2X1_REG UCSR1A
-#define UPE1_REG UCSR1A
-#define DOR1_REG UCSR1A
-#define FE1_REG UCSR1A
-#define UDRE1_REG UCSR1A
-#define TXC1_REG UCSR1A
-#define RXC1_REG UCSR1A
-
-/* TCCR0 */
-#define CS00_REG TCCR0
-#define CS01_REG TCCR0
-#define CS02_REG TCCR0
-#define WGM01_REG TCCR0
-#define COM00_REG TCCR0
-#define COM01_REG TCCR0
-#define WGM00_REG TCCR0
-#define FOC0_REG TCCR0
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* GICR */
-#define IVCE_REG GICR
-#define IVSEL_REG GICR
-#define PCIE0_REG GICR
-#define PCIE1_REG GICR
-#define INT2_REG GICR
-#define INT0_REG GICR
-#define INT1_REG GICR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* ETIMSK */
-#define TOIE3_REG ETIMSK
-#define OCIE3B_REG ETIMSK
-#define OCIE3A_REG ETIMSK
-#define TICIE3_REG ETIMSK
-
-/* OCR3AL */
-#define OCR3AL0_REG OCR3AL
-#define OCR3AL1_REG OCR3AL
-#define OCR3AL2_REG OCR3AL
-#define OCR3AL3_REG OCR3AL
-#define OCR3AL4_REG OCR3AL
-#define OCR3AL5_REG OCR3AL
-#define OCR3AL6_REG OCR3AL
-#define OCR3AL7_REG OCR3AL
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* UBRR1H */
-/* #define UBRR8_REG UBRR1H */ /* dup in UBRR0H */
-/* #define UBRR9_REG UBRR1H */ /* dup in UBRR0H */
-/* #define UBRR10_REG UBRR1H */ /* dup in UBRR0H */
-/* #define UBRR11_REG UBRR1H */ /* dup in UBRR0H */
-
-/* OCR3AH */
-#define OCR3AH0_REG OCR3AH
-#define OCR3AH1_REG OCR3AH
-#define OCR3AH2_REG OCR3AH
-#define OCR3AH3_REG OCR3AH
-#define OCR3AH4_REG OCR3AH
-#define OCR3AH5_REG OCR3AH
-#define OCR3AH6_REG OCR3AH
-#define OCR3AH7_REG OCR3AH
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* GIFR */
-#define PCIF0_REG GIFR
-#define PCIF1_REG GIFR
-#define INTF2_REG GIFR
-#define INTF0_REG GIFR
-#define INTF1_REG GIFR
-
-/* TIMSK */
-#define TICIE1_REG TIMSK
-#define OCIE1B_REG TIMSK
-#define OCIE1A_REG TIMSK
-#define TOIE1_REG TIMSK
-#define TOIE2_REG TIMSK
-#define OCIE2_REG TIMSK
-#define OCIE0_REG TIMSK
-#define TOIE0_REG TIMSK
-
-/* UBRR0H */
-/* #define UBRR8_REG UBRR0H */ /* dup in UBRR1H */
-/* #define UBRR9_REG UBRR0H */ /* dup in UBRR1H */
-/* #define UBRR10_REG UBRR0H */ /* dup in UBRR1H */
-/* #define UBRR11_REG UBRR0H */ /* dup in UBRR1H */
-/* #define URSEL0_REG UBRR0H */ /* dup in UCSR0C */
-
-/* TCCR3B */
-#define CS30_REG TCCR3B
-#define CS31_REG TCCR3B
-#define CS32_REG TCCR3B
-#define WGM32_REG TCCR3B
-#define WGM33_REG TCCR3B
-#define ICES3_REG TCCR3B
-#define ICNC3_REG TCCR3B
-
-/* TCCR3A */
-#define WGM30_REG TCCR3A
-#define WGM31_REG TCCR3A
-#define FOC3B_REG TCCR3A
-#define FOC3A_REG TCCR3A
-#define COM3B0_REG TCCR3A
-#define COM3B1_REG TCCR3A
-#define COM3A0_REG TCCR3A
-#define COM3A1_REG TCCR3A
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define FOC1B_REG TCCR1A
-#define FOC1A_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* SFIOR */
-#define PSR310_REG SFIOR
-#define PSR2_REG SFIOR
-#define PUD_REG SFIOR
-#define XMM0_REG SFIOR
-#define XMM1_REG SFIOR
-#define XMM2_REG SFIOR
-#define XMBK_REG SFIOR
-#define TSM_REG SFIOR
-
-/* UDR0 */
-#define UDR0_0_REG UDR0
-#define UDR0_1_REG UDR0
-#define UDR0_2_REG UDR0
-#define UDR0_3_REG UDR0
-#define UDR0_4_REG UDR0
-#define UDR0_5_REG UDR0
-#define UDR0_6_REG UDR0
-#define UDR0_7_REG UDR0
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* TCNT3H */
-#define TCNT3H0_REG TCNT3H
-#define TCNT3H1_REG TCNT3H
-#define TCNT3H2_REG TCNT3H
-#define TCNT3H3_REG TCNT3H
-#define TCNT3H4_REG TCNT3H
-#define TCNT3H5_REG TCNT3H
-#define TCNT3H6_REG TCNT3H
-#define TCNT3H7_REG TCNT3H
-
-/* EMCUCR */
-#define ISC2_REG EMCUCR
-#define SRW11_REG EMCUCR
-#define SRW00_REG EMCUCR
-#define SRW01_REG EMCUCR
-#define SRL0_REG EMCUCR
-#define SRL1_REG EMCUCR
-#define SRL2_REG EMCUCR
-#define SM0_REG EMCUCR
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* TCNT3L */
-#define TCNT3L0_REG TCNT3L
-#define TCNT3L1_REG TCNT3L
-#define TCNT3L2_REG TCNT3L
-#define TCNT3L3_REG TCNT3L
-#define TCNT3L4_REG TCNT3L
-#define TCNT3L5_REG TCNT3L
-#define TCNT3L6_REG TCNT3L
-#define TCNT3L7_REG TCNT3L
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* SPMCR */
-#define SPMEN_REG SPMCR
-#define PGERS_REG SPMCR
-#define PGWRT_REG SPMCR
-#define BLBSET_REG SPMCR
-#define RWWSRE_REG SPMCR
-#define RWWSB_REG SPMCR
-#define SPMIE_REG SPMCR
-
-/* ICR3H */
-#define ICR3H0_REG ICR3H
-#define ICR3H1_REG ICR3H
-#define ICR3H2_REG ICR3H
-#define ICR3H3_REG ICR3H
-#define ICR3H4_REG ICR3H
-#define ICR3H5_REG ICR3H
-#define ICR3H6_REG ICR3H
-#define ICR3H7_REG ICR3H
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* ICR3L */
-#define ICR3L0_REG ICR3L
-#define ICR3L1_REG ICR3L
-#define ICR3L2_REG ICR3L
-#define ICR3L3_REG ICR3L
-#define ICR3L4_REG ICR3L
-#define ICR3L5_REG ICR3L
-#define ICR3L6_REG ICR3L
-#define ICR3L7_REG ICR3L
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL0_REG UCSR0C
-/* #define URSEL0_REG UCSR0C */ /* dup in UBRR0H */
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* OCR3BL */
-#define OCR3BL0_REG OCR3BL
-#define OCR3BL1_REG OCR3BL
-#define OCR3BL2_REG OCR3BL
-#define OCR3BL3_REG OCR3BL
-#define OCR3BL4_REG OCR3BL
-#define OCR3BL5_REG OCR3BL
-#define OCR3BL6_REG OCR3BL
-#define OCR3BL7_REG OCR3BL
-
-/* MCUCSR */
-#define PORF_REG MCUCSR
-#define EXTRF_REG MCUCSR
-#define BORF_REG MCUCSR
-#define WDRF_REG MCUCSR
-#define JTRF_REG MCUCSR
-#define SM2_REG MCUCSR
-#define JDT_REG MCUCSR
-#define JTD_REG MCUCSR
-
-/* OCR3BH */
-#define OCR3BH0_REG OCR3BH
-#define OCR3BH1_REG OCR3BH
-#define OCR3BH2_REG OCR3BH
-#define OCR3BH3_REG OCR3BH
-#define OCR3BH4_REG OCR3BH
-#define OCR3BH5_REG OCR3BH
-#define OCR3BH6_REG OCR3BH
-#define OCR3BH7_REG OCR3BH
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* UBRR1L */
-#define UBRR1L0_REG UBRR1L
-#define UBRR1L1_REG UBRR1L
-#define UBRR1L2_REG UBRR1L
-#define UBRR1L3_REG UBRR1L
-#define UBRR1L4_REG UBRR1L
-#define UBRR1L5_REG UBRR1L
-#define UBRR1L6_REG UBRR1L
-#define UBRR1L7_REG UBRR1L
-
-/* TCCR2 */
-#define CS20_REG TCCR2
-#define CS21_REG TCCR2
-#define CS22_REG TCCR2
-#define WGM21_REG TCCR2
-#define COM20_REG TCCR2
-#define COM21_REG TCCR2
-#define WGM20_REG TCCR2
-#define FOC2_REG TCCR2
-
-/* UDR1 */
-#define UDR1_0_REG UDR1
-#define UDR1_1_REG UDR1
-#define UDR1_2_REG UDR1
-#define UDR1_3_REG UDR1
-#define UDR1_4_REG UDR1
-#define UDR1_5_REG UDR1
-#define UDR1_6_REG UDR1
-#define UDR1_7_REG UDR1
-
-/* TIFR */
-#define ICF1_REG TIFR
-#define OCF1B_REG TIFR
-#define OCF1A_REG TIFR
-#define TOV1_REG TIFR
-#define TOV2_REG TIFR
-#define OCF2_REG TIFR
-#define OCF0_REG TIFR
-#define TOV0_REG TIFR
-
-/* UBRR0L */
-#define UBRR0_REG UBRR0L
-#define UBRR1_REG UBRR0L
-#define UBRR2_REG UBRR0L
-#define UBRR3_REG UBRR0L
-#define UBRR4_REG UBRR0L
-#define UBRR5_REG UBRR0L
-#define UBRR6_REG UBRR0L
-#define UBRR7_REG UBRR0L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-#define PCINT15_REG PCMSK1
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-#define PINE3_REG PINE
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define ISC10_REG MCUCR
-#define ISC11_REG MCUCR
-#define SM1_REG MCUCR
-#define SE_REG MCUCR
-#define SRW10_REG MCUCR
-#define SRE_REG MCUCR
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* OCR0 */
-#define OCR0_0_REG OCR0
-#define OCR0_1_REG OCR0
-#define OCR0_2_REG OCR0
-#define OCR0_3_REG OCR0
-#define OCR0_4_REG OCR0
-#define OCR0_5_REG OCR0
-#define OCR0_6_REG OCR0
-#define OCR0_7_REG OCR0
-
-/* ETIFR */
-#define TOV3_REG ETIFR
-#define OCF3B_REG ETIFR
-#define OCF3A_REG ETIFR
-#define ICF3_REG ETIFR
-
-/* OCR2 */
-#define OCR2_0_REG OCR2
-#define OCR2_1_REG OCR2
-#define OCR2_2_REG OCR2
-#define OCR2_3_REG OCR2
-#define OCR2_4_REG OCR2
-#define OCR2_5_REG OCR2
-#define OCR2_6_REG OCR2
-#define OCR2_7_REG OCR2
-
-/* ASSR */
-#define TCR2UB_REG ASSR
-#define OCR2UB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-
-/* pins mapping */
-#define PCINT0_PORT PORTA
-#define PCINT0_BIT 0
-#define AD0_PORT PORTA
-#define AD0_BIT 0
-
-#define PCINT1_PORT PORTA
-#define PCINT1_BIT 1
-#define AD1_PORT PORTA
-#define AD1_BIT 1
-
-#define PCINT2_PORT PORTA
-#define PCINT2_BIT 2
-#define AD2_PORT PORTA
-#define AD2_BIT 2
-
-#define PCINT3_PORT PORTA
-#define PCINT3_BIT 3
-#define AD3_PORT PORTA
-#define AD3_BIT 3
-
-#define PCINT4_PORT PORTA
-#define PCINT4_BIT 4
-#define AD4_PORT PORTA
-#define AD4_BIT 4
-
-#define PCINT5_PORT PORTA
-#define PCINT5_BIT 5
-#define AD5_PORT PORTA
-#define AD5_BIT 5
-
-#define PCINT6_PORT PORTA
-#define PCINT6_BIT 6
-#define AD6_PORT PORTA
-#define AD6_BIT 6
-
-#define PCINT7_PORT PORTA
-#define PCINT7_BIT 7
-#define AD7_PORT PORTA
-#define AD7_BIT 7
-
-#define OC0_PORT PORTB
-#define OC0_BIT 0
-#define T0_PORT PORTB
-#define T0_BIT 0
-
-#define OC2_PORT PORTB
-#define OC2_BIT 1
-#define T1_PORT PORTB
-#define T1_BIT 1
-
-#define RXD1_PORT PORTB
-#define RXD1_BIT 2
-#define AIN0_PORT PORTB
-#define AIN0_BIT 2
-
-#define TXD1_PORT PORTB
-#define TXD1_BIT 3
-#define AIN1_PORT PORTB
-#define AIN1_BIT 3
-
-#define OC3B_PORT PORTB
-#define OC3B_BIT 4
-#define SS_PORT PORTB
-#define SS_BIT 4
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 5
-
-#define MISO_PORT PORTB
-#define MISO_BIT 6
-
-
-#define PCINT8_PORT PORTC
-#define PCINT8_BIT 0
-#define A8_PORT PORTC
-#define A8_BIT 0
-
-#define PCINT9_PORT PORTC
-#define PCINT9_BIT 1
-#define A9_PORT PORTC
-#define A9_BIT 1
-
-#define PCINT10_PORT PORTC
-#define PCINT10_BIT 2
-#define A10_PORT PORTC
-#define A10_BIT 2
-
-#define PCINT11_PORT PORTC
-#define PCINT11_BIT 3
-#define A11_PORT PORTC
-#define A11_BIT 3
-
-#define PCINT12_PORT PORTC
-#define PCINT12_BIT 4
-#define A12_PORT PORTC
-#define A12_BIT 4
-#define TCK_PORT PORTC
-#define TCK_BIT 4
-
-#define PCINT13_PORT PORTC
-#define PCINT13_BIT 5
-#define A13_PORT PORTC
-#define A13_BIT 5
-#define TMS_PORT PORTC
-#define TMS_BIT 5
-
-#define PCINT14_PORT PORTC
-#define PCINT14_BIT 6
-#define A14_PORT PORTC
-#define A14_BIT 6
-#define TDO_PORT PORTC
-#define TDO_BIT 6
-
-#define PCINT15_PORT PORTC
-#define PCINT15_BIT 7
-#define A15_PORT PORTC
-#define A15_BIT 7
-#define TDI_PORT PORTC
-#define TDI_BIT 7
-
-#define TXD0_PORT PORTD
-#define TXD0_BIT 1
-
-#define INT0_PORT PORTD
-#define INT0_BIT 2
-#define XCK1_PORT PORTD
-#define XCK1_BIT 2
-
-#define INT1_PORT PORTD
-#define INT1_BIT 3
-#define XCK1_PORT PORTD
-#define XCK1_BIT 3
-
-#define TOSC1_PORT PORTD
-#define TOSC1_BIT 4
-#define XCK0_PORT PORTD
-#define XCK0_BIT 4
-#define OC3A_PORT PORTD
-#define OC3A_BIT 4
-
-#define OC1A_PORT PORTD
-#define OC1A_BIT 5
-#define TOSC2_PORT PORTD
-#define TOSC2_BIT 5
-
-#define WR_PORT PORTD
-#define WR_BIT 6
-
-#define RD_PORT PORTD
-#define RD_BIT 7
-
-#define ICP1_PORT PORTE
-#define ICP1_BIT 0
-#define INT2_PORT PORTE
-#define INT2_BIT 0
-
-#define ALE_PORT PORTE
-#define ALE_BIT 1
-
-#define OC1B_PORT PORTE
-#define OC1B_BIT 2
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE1A_NUM 0
-#define SIG_OUTPUT_COMPARE1B_NUM 1
-#define SIG_OUTPUT_COMPARE2_NUM 2
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 3
-
-/* Pwm nums */
-#define PWM1A_NUM 0
-#define PWM1B_NUM 1
-#define PWM2_NUM 2
-#define PWM_TOTAL_NUM 3
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDTOE_REG WDTCR
-
-/* GIMSK */
-#define INT0_REG GIMSK
-#define INT1_REG GIMSK
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* TCCR0 */
-#define CS00_REG TCCR0
-#define CS01_REG TCCR0
-#define CS02_REG TCCR0
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* TCCR1A */
-#define PWM10_REG TCCR1A
-#define PWM11_REG TCCR1A
-#define FOC1B_REG TCCR1A
-#define FOC1A_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define CTC1_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* GIFR */
-#define INTF0_REG GIFR
-#define INTF1_REG GIFR
-
-/* TIMSK */
-#define TOIE0_REG TIMSK
-#define TOIE1_REG TIMSK
-#define OCIE1B_REG TIMSK
-#define OCIE1A_REG TIMSK
-#define TICIE1_REG TIMSK
-#define TOIE2_REG TIMSK
-#define OCIE2_REG TIMSK
-
-/* UCSRA */
-#define MPCM_REG UCSRA
-#define U2X_REG UCSRA
-#define OR_REG UCSRA
-#define FE_REG UCSRA
-#define UDRE_REG UCSRA
-#define TXC_REG UCSRA
-#define RXC_REG UCSRA
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* UCSRB */
-#define TXB8_REG UCSRB
-#define RXB8_REG UCSRB
-#define CHR9_REG UCSRB
-#define TXEN_REG UCSRB
-#define RXEN_REG UCSRB
-#define UDRIE_REG UCSRB
-#define TXCIE_REG UCSRB
-#define RXCIE_REG UCSRB
-
-/* SFIOR */
-#define PSR10_REG SFIOR
-#define PSR2_REG SFIOR
-#define PUD_REG SFIOR
-#define ACME_REG SFIOR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* UBRRHI */
-#define UBRRHI0_REG UBRRHI
-#define UBRRHI1_REG UBRRHI
-#define UBRRHI2_REG UBRRHI
-#define UBRRHI3_REG UBRRHI
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* SPMCR */
-#define SPMEN_REG SPMCR
-#define PGERS_REG SPMCR
-#define PGWRT_REG SPMCR
-#define BLBSET_REG SPMCR
-#define ASRE_REG SPMCR
-#define ASB_REG SPMCR
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* TCNT0 */
-#define TCNT00_REG TCNT0
-#define TCNT01_REG TCNT0
-#define TCNT02_REG TCNT0
-#define TCNT03_REG TCNT0
-#define TCNT04_REG TCNT0
-#define TCNT05_REG TCNT0
-#define TCNT06_REG TCNT0
-#define TCNT07_REG TCNT0
-
-/* UDR */
-#define UDR0_REG UDR
-#define UDR1_REG UDR
-#define UDR2_REG UDR
-#define UDR3_REG UDR
-#define UDR4_REG UDR
-#define UDR5_REG UDR
-#define UDR6_REG UDR
-#define UDR7_REG UDR
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* UBRR */
-#define UBRR0_REG UBRR
-#define UBRR1_REG UBRR
-#define UBRR2_REG UBRR
-#define UBRR3_REG UBRR
-#define UBRR4_REG UBRR
-#define UBRR5_REG UBRR
-#define UBRR6_REG UBRR
-#define UBRR7_REG UBRR
-
-/* ADCSR */
-#define ADPS0_REG ADCSR
-#define ADPS1_REG ADCSR
-#define ADPS2_REG ADCSR
-#define ADIE_REG ADCSR
-#define ADIF_REG ADCSR
-#define ADFR_REG ADCSR
-#define ADSC_REG ADCSR
-#define ADEN_REG ADCSR
-
-/* TCCR2 */
-#define CS20_REG TCCR2
-#define CS21_REG TCCR2
-#define CS22_REG TCCR2
-#define WGM21_REG TCCR2
-#define COM20_REG TCCR2
-#define COM21_REG TCCR2
-#define WGM20_REG TCCR2
-#define FOC2_REG TCCR2
-
-/* TIFR */
-#define TOV0_REG TIFR
-#define TOV1_REG TIFR
-#define OCF1B_REG TIFR
-#define OCF1A_REG TIFR
-#define ICF1_REG TIFR
-#define TOV2_REG TIFR
-#define OCF2_REG TIFR
-
-/* EEARH */
-#define EEAR8_REG EEARH
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* TWSR */
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define ISC10_REG MCUCR
-#define ISC11_REG MCUCR
-#define SM0_REG MCUCR
-#define SM1_REG MCUCR
-#define SE_REG MCUCR
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* ASSR */
-#define TCR2UB_REG ASSR
-#define OCR2UB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-
-/* OCR2 */
-#define OCR2_0_REG OCR2
-#define OCR2_1_REG OCR2
-#define OCR2_2_REG OCR2
-#define OCR2_3_REG OCR2
-#define OCR2_4_REG OCR2
-#define OCR2_5_REG OCR2
-#define OCR2_6_REG OCR2
-#define OCR2_7_REG OCR2
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* pins mapping */
-#define ADC0_PORT PORTA
-#define ADC0_BIT 0
-
-#define ADC1_PORT PORTA
-#define ADC1_BIT 1
-
-#define ADC2_PORT PORTA
-#define ADC2_BIT 2
-
-#define ADC3_PORT PORTA
-#define ADC3_BIT 3
-
-#define ADC4_PORT PORTA
-#define ADC4_BIT 4
-
-#define ADc5_PORT PORTA
-#define ADc5_BIT 5
-
-#define ADC6_PORT PORTA
-#define ADC6_BIT 6
-
-#define ADC7_PORT PORTA
-#define ADC7_BIT 7
-
-#define T0_PORT PORTB
-#define T0_BIT 0
-
-#define T1_PORT PORTB
-#define T1_BIT 1
-
-#define AIN0_PORT PORTB
-#define AIN0_BIT 2
-
-#define AIN1_PORT PORTB
-#define AIN1_BIT 3
-
-#define SS_PORT PORTB
-#define SS_BIT 4
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 5
-
-#define MISO_PORT PORTB
-#define MISO_BIT 6
-
-
-#define SCL_PORT PORTC
-#define SCL_BIT 0
-
-#define SDA_PORT PORTC
-#define SDA_BIT 1
-
-
-
-
-
-#define TOSC1_PORT PORTC
-#define TOSC1_BIT 6
-
-#define TOSC2_PORT PORTC
-#define TOSC2_BIT 7
-
-#define RXD_PORT PORTD
-#define RXD_BIT 0
-
-#define TXD_PORT PORTD
-#define TXD_BIT 1
-
-#define INT0_PORT PORTD
-#define INT0_BIT 2
-
-#define INT1_PORT PORTD
-#define INT1_BIT 3
-
-#define OC1B_PORT PORTD
-#define OC1B_BIT 4
-
-#define OC1A_PORT PORTD
-#define OC1A_BIT 5
-
-#define ICP_PORT PORTD
-#define ICP_BIT 6
-
-#define OC2_PORT PORTD
-#define OC2_BIT 7
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-#define TIMER2A_AVAILABLE
-#define TIMER2B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE2A_NUM 4
-#define SIG_OUTPUT_COMPARE2B_NUM 5
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 6
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM2A_NUM 4
-#define PWM2B_NUM 5
-#define PWM_TOTAL_NUM 6
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* SPCR0 */
-#define SPR00_REG SPCR0
-#define SPR10_REG SPCR0
-#define CPHA0_REG SPCR0
-#define CPOL0_REG SPCR0
-#define MSTR0_REG SPCR0
-#define DORD0_REG SPCR0
-#define SPE0_REG SPCR0
-#define SPIE0_REG SPCR0
-
-/* RAMPZ */
-#define RAMPZ0_REG RAMPZ
-
-/* OCR2B */
-#define OCR2B_0_REG OCR2B
-#define OCR2B_1_REG OCR2B
-#define OCR2B_2_REG OCR2B
-#define OCR2B_3_REG OCR2B
-#define OCR2B_4_REG OCR2B
-#define OCR2B_5_REG OCR2B
-#define OCR2B_6_REG OCR2B
-#define OCR2B_7_REG OCR2B
-
-/* OCR2A */
-#define OCR2A_0_REG OCR2A
-#define OCR2A_1_REG OCR2A
-#define OCR2A_2_REG OCR2A
-#define OCR2A_3_REG OCR2A
-#define OCR2A_4_REG OCR2A
-#define OCR2A_5_REG OCR2A
-#define OCR2A_6_REG OCR2A
-#define OCR2A_7_REG OCR2A
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL00_REG UCSR0C
-#define UMSEL01_REG UCSR0C
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* UDR1 */
-#define UDR1_0_REG UDR1
-#define UDR1_1_REG UDR1
-#define UDR1_2_REG UDR1
-#define UDR1_3_REG UDR1
-#define UDR1_4_REG UDR1
-#define UDR1_5_REG UDR1
-#define UDR1_6_REG UDR1
-#define UDR1_7_REG UDR1
-
-/* UDR0 */
-#define UDR0_0_REG UDR0
-#define UDR0_1_REG UDR0
-#define UDR0_2_REG UDR0
-#define UDR0_3_REG UDR0
-#define UDR0_4_REG UDR0
-#define UDR0_5_REG UDR0
-#define UDR0_6_REG UDR0
-#define UDR0_7_REG UDR0
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-#define ISC20_REG EICRA
-#define ISC21_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* SPDR0 */
-#define SPDRB0_REG SPDR0
-#define SPDRB1_REG SPDR0
-#define SPDRB2_REG SPDR0
-#define SPDRB3_REG SPDR0
-#define SPDRB4_REG SPDR0
-#define SPDRB5_REG SPDR0
-#define SPDRB6_REG SPDR0
-#define SPDRB7_REG SPDR0
-
-/* ASSR */
-#define TCR2BUB_REG ASSR
-#define TCR2AUB_REG ASSR
-#define OCR2BUB_REG ASSR
-#define OCR2AUB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* UBRR1L */
-#define UBRR_0_REG UBRR1L
-#define UBRR_1_REG UBRR1L
-#define UBRR_2_REG UBRR1L
-#define UBRR_3_REG UBRR1L
-#define UBRR_4_REG UBRR1L
-#define UBRR_5_REG UBRR1L
-#define UBRR_6_REG UBRR1L
-#define UBRR_7_REG UBRR1L
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* UBRR1H */
-#define UBRR_8_REG UBRR1H
-#define UBRR_9_REG UBRR1H
-#define UBRR_10_REG UBRR1H
-#define UBRR_11_REG UBRR1H
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* SPSR0 */
-#define SPI2X0_REG SPSR0
-#define WCOL0_REG SPSR0
-#define SPIF0_REG SPSR0
-
-/* PCICR */
-#define PCIE0_REG PCICR
-#define PCIE1_REG PCICR
-#define PCIE2_REG PCICR
-#define PCIE3_REG PCICR
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-#define OCF2B_REG TIFR2
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* GTCCR */
-#define PSRSYNC_REG GTCCR
-#define TSM_REG GTCCR
-#define PSRASY_REG GTCCR
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* OCR1BL */
-/* #define OCR1AL0_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL1_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL2_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL3_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL4_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL5_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL6_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL7_REG OCR1BL */ /* dup in OCR1AL */
-
-/* PCIFR */
-#define PCIF0_REG PCIFR
-#define PCIF1_REG PCIFR
-#define PCIF2_REG PCIFR
-#define PCIF3_REG PCIFR
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* OCR1BH */
-/* #define OCR1AH0_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH1_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH2_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH3_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH4_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH5_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH6_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH7_REG OCR1BH */ /* dup in OCR1AH */
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* TCCR2A */
-#define WGM20_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2B0_REG TCCR2A
-#define COM2B1_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-
-/* TCCR2B */
-#define CS20_REG TCCR2B
-#define CS21_REG TCCR2B
-#define CS22_REG TCCR2B
-#define WGM22_REG TCCR2B
-#define FOC2B_REG TCCR2B
-#define FOC2A_REG TCCR2B
-
-/* UBRR0H */
-#define UBRR8_REG UBRR0H
-#define UBRR9_REG UBRR0H
-#define UBRR10_REG UBRR0H
-#define UBRR11_REG UBRR0H
-
-/* UBRR0L */
-#define UBRR0_REG UBRR0L
-#define UBRR1_REG UBRR0L
-#define UBRR2_REG UBRR0L
-#define UBRR3_REG UBRR0L
-#define UBRR4_REG UBRR0L
-#define UBRR5_REG UBRR0L
-#define UBRR6_REG UBRR0L
-#define UBRR7_REG UBRR0L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-#define EEAR10_REG EEARH
-#define EEAR11_REG EEARH
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* MCUCR */
-#define JTD_REG MCUCR
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-#define BODSE_REG MCUCR
-#define BODS_REG MCUCR
-
-/* MCUSR */
-#define JTRF_REG MCUSR
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* UCSR1B */
-#define TXB81_REG UCSR1B
-#define RXB81_REG UCSR1B
-#define UCSZ12_REG UCSR1B
-#define TXEN1_REG UCSR1B
-#define RXEN1_REG UCSR1B
-#define UDRIE1_REG UCSR1B
-#define TXCIE1_REG UCSR1B
-#define RXCIE1_REG UCSR1B
-
-/* UCSR1C */
-#define UCPOL1_REG UCSR1C
-#define UCSZ10_REG UCSR1C
-#define UCSZ11_REG UCSR1C
-#define USBS1_REG UCSR1C
-#define UPM10_REG UCSR1C
-#define UPM11_REG UCSR1C
-#define UMSEL10_REG UCSR1C
-#define UMSEL11_REG UCSR1C
-
-/* UCSR1A */
-#define MPCM1_REG UCSR1A
-#define U2X1_REG UCSR1A
-#define UPE1_REG UCSR1A
-#define DOR1_REG UCSR1A
-#define FE1_REG UCSR1A
-#define UDRE1_REG UCSR1A
-#define TXC1_REG UCSR1A
-#define RXC1_REG UCSR1A
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* TWAMR */
-#define TWAM0_REG TWAMR
-#define TWAM1_REG TWAMR
-#define TWAM2_REG TWAMR
-#define TWAM3_REG TWAMR
-#define TWAM4_REG TWAMR
-#define TWAM5_REG TWAMR
-#define TWAM6_REG TWAMR
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ACME_REG ADCSRB
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-
-/* PRR0 */
-#define PRADC_REG PRR0
-#define PRUSART0_REG PRR0
-#define PRSPI_REG PRR0
-#define PRTIM1_REG PRR0
-#define PRUSART1_REG PRR0
-#define PRTIM0_REG PRR0
-#define PRTIM2_REG PRR0
-#define PRTWI_REG PRR0
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* OCR0A */
-#define OCROA_0_REG OCR0A
-#define OCROA_1_REG OCR0A
-#define OCROA_2_REG OCR0A
-#define OCROA_3_REG OCR0A
-#define OCROA_4_REG OCR0A
-#define OCROA_5_REG OCR0A
-#define OCROA_6_REG OCR0A
-#define OCROA_7_REG OCR0A
-
-/* OCR0B */
-#define OCR0B_0_REG OCR0B
-#define OCR0B_1_REG OCR0B
-#define OCR0B_2_REG OCR0B
-#define OCR0B_3_REG OCR0B
-#define OCR0B_4_REG OCR0B
-#define OCR0B_5_REG OCR0B
-#define OCR0B_6_REG OCR0B
-#define OCR0B_7_REG OCR0B
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define SIGRD_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-#define OCIE2B_REG TIMSK2
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-#define PCINT15_REG PCMSK1
-
-/* PCMSK2 */
-#define PCINT16_REG PCMSK2
-#define PCINT17_REG PCMSK2
-#define PCINT18_REG PCMSK2
-#define PCINT19_REG PCMSK2
-#define PCINT20_REG PCMSK2
-#define PCINT21_REG PCMSK2
-#define PCINT22_REG PCMSK2
-#define PCINT23_REG PCMSK2
-
-/* PCMSK3 */
-#define PCINT24_REG PCMSK3
-#define PCINT25_REG PCMSK3
-#define PCINT26_REG PCMSK3
-#define PCINT27_REG PCMSK3
-#define PCINT28_REG PCMSK3
-#define PCINT29_REG PCMSK3
-#define PCINT30_REG PCMSK3
-#define PCINT31_REG PCMSK3
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-#define INTF2_REG EIFR
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-/* #define OCR1AH0_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH1_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH2_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH3_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH4_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH5_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH6_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH7_REG OCR1AH */ /* dup in OCR1BH */
-
-/* OCR1AL */
-/* #define OCR1AL0_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL1_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL2_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL3_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL4_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL5_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL6_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL7_REG OCR1AL */ /* dup in OCR1BL */
-
-/* pins mapping */
-#define ADC0_PORT PORTA
-#define ADC0_BIT 0
-#define PCINT0_PORT PORTA
-#define PCINT0_BIT 0
-
-#define ADC1_PORT PORTA
-#define ADC1_BIT 1
-#define PCINT1_PORT PORTA
-#define PCINT1_BIT 1
-
-#define ADC2_PORT PORTA
-#define ADC2_BIT 2
-#define PCINT2_PORT PORTA
-#define PCINT2_BIT 2
-
-#define ADC3_PORT PORTA
-#define ADC3_BIT 3
-#define PCINT3_PORT PORTA
-#define PCINT3_BIT 3
-
-#define ADC4_PORT PORTA
-#define ADC4_BIT 4
-#define PCINT4_PORT PORTA
-#define PCINT4_BIT 4
-
-#define ADC5_PORT PORTA
-#define ADC5_BIT 5
-#define PCINT5_PORT PORTA
-#define PCINT5_BIT 5
-
-#define ADC6_PORT PORTA
-#define ADC6_BIT 6
-#define PCINT6_PORT PORTA
-#define PCINT6_BIT 6
-
-#define ADC7_PORT PORTA
-#define ADC7_BIT 7
-#define PCINT7_PORT PORTA
-#define PCINT7_BIT 7
-
-#define XCK_PORT PORTB
-#define XCK_BIT 0
-#define T0_PORT PORTB
-#define T0_BIT 0
-#define PCINT9_PORT PORTB
-#define PCINT9_BIT 0
-
-#define T1_PORT PORTB
-#define T1_BIT 1
-#define CLKO_PORT PORTB
-#define CLKO_BIT 1
-#define PCINT9_PORT PORTB
-#define PCINT9_BIT 1
-
-#define AIN0_PORT PORTB
-#define AIN0_BIT 2
-#define INT2_PORT PORTB
-#define INT2_BIT 2
-#define PCINT10_PORT PORTB
-#define PCINT10_BIT 2
-
-#define AIN1_PORT PORTB
-#define AIN1_BIT 3
-#define OC0A_PORT PORTB
-#define OC0A_BIT 3
-#define PCINT11_PORT PORTB
-#define PCINT11_BIT 3
-
-#define SS_PORT PORTB
-#define SS_BIT 4
-#define OC0B_PORT PORTB
-#define OC0B_BIT 4
-#define PCINT12_PORT PORTB
-#define PCINT12_BIT 4
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 5
-#define PCINT13_PORT PORTB
-#define PCINT13_BIT 5
-
-#define MISO_PORT PORTB
-#define MISO_BIT 6
-#define PCINT14_PORT PORTB
-#define PCINT14_BIT 6
-
-#define SCK_PORT PORTB
-#define SCK_BIT 7
-#define PCINT15_PORT PORTB
-#define PCINT15_BIT 7
-
-#define SCL_PORT PORTC
-#define SCL_BIT 0
-#define PCINT16_PORT PORTC
-#define PCINT16_BIT 0
-
-#define SDA_PORT PORTC
-#define SDA_BIT 1
-#define PCINT17_PORT PORTC
-#define PCINT17_BIT 1
-
-#define TCK_PORT PORTC
-#define TCK_BIT 2
-#define PCINT18_PORT PORTC
-#define PCINT18_BIT 2
-
-#define TMS_PORT PORTC
-#define TMS_BIT 3
-#define PCINT19_PORT PORTC
-#define PCINT19_BIT 3
-
-#define TDO_PORT PORTC
-#define TDO_BIT 4
-#define PCINT20_PORT PORTC
-#define PCINT20_BIT 4
-
-#define TDI_PORT PORTC
-#define TDI_BIT 5
-#define PCINT21_PORT PORTC
-#define PCINT21_BIT 5
-
-#define TOSC1_PORT PORTC
-#define TOSC1_BIT 6
-#define PCINT22_PORT PORTC
-#define PCINT22_BIT 6
-
-#define TOSC2_PORT PORTC
-#define TOSC2_BIT 7
-#define PCINT23_PORT PORTC
-#define PCINT23_BIT 7
-
-#define RXD_PORT PORTD
-#define RXD_BIT 0
-#define PCINT24_PORT PORTD
-#define PCINT24_BIT 0
-
-#define TXD_PORT PORTD
-#define TXD_BIT 1
-#define PCINT25_PORT PORTD
-#define PCINT25_BIT 1
-
-#define INT0_PORT PORTD
-#define INT0_BIT 2
-#define PCINT26_PORT PORTD
-#define PCINT26_BIT 2
-
-#define INT1_PORT PORTD
-#define INT1_BIT 3
-#define PCINT27_PORT PORTD
-#define PCINT27_BIT 3
-
-#define OC1B_PORT PORTD
-#define OC1B_BIT 4
-#define PCINT28_PORT PORTD
-#define PCINT28_BIT 4
-
-#define OC1A_PORT PORTD
-#define OC1A_BIT 5
-#define PCINT29_PORT PORTD
-#define PCINT29_BIT 5
-
-#define ICP_PORT PORTD
-#define ICP_BIT 6
-#define OC2B_PORT PORTD
-#define OC2B_BIT 6
-#define PCINT30_PORT PORTD
-#define PCINT30_BIT 6
-
-#define OC2A_PORT PORTD
-#define OC2A_BIT 7
-#define PCINT31_PORT PORTD
-#define PCINT31_BIT 7
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE1A_NUM 1
-#define SIG_OUTPUT_COMPARE1B_NUM 2
-#define SIG_OUTPUT_COMPARE2_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM1A_NUM 1
-#define PWM1B_NUM 2
-#define PWM2_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* OCR2A */
-#define OCR2A0_REG OCR2A
-#define OCR2A1_REG OCR2A
-#define OCR2A2_REG OCR2A
-#define OCR2A3_REG OCR2A
-#define OCR2A4_REG OCR2A
-#define OCR2A5_REG OCR2A
-#define OCR2A6_REG OCR2A
-#define OCR2A7_REG OCR2A
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSART0_REG PRR
-#define PRSPI_REG PRR
-#define PRTIM1_REG PRR
-
-/* PORTF */
-#define PORTF0_REG PORTF
-#define PORTF1_REG PORTF
-#define PORTF2_REG PORTF
-#define PORTF3_REG PORTF
-#define PORTF4_REG PORTF
-#define PORTF5_REG PORTF
-#define PORTF6_REG PORTF
-#define PORTF7_REG PORTF
-
-/* PORTG */
-#define PORTG0_REG PORTG
-#define PORTG1_REG PORTG
-#define PORTG2_REG PORTG
-#define PORTG3_REG PORTG
-#define PORTG4_REG PORTG
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-#define PORTE3_REG PORTE
-#define PORTE4_REG PORTE
-#define PORTE5_REG PORTE
-#define PORTE6_REG PORTE
-#define PORTE7_REG PORTE
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* UDR0 */
-#define UDR00_REG UDR0
-#define UDR01_REG UDR0
-#define UDR02_REG UDR0
-#define UDR03_REG UDR0
-#define UDR04_REG UDR0
-#define UDR05_REG UDR0
-#define UDR06_REG UDR0
-#define UDR07_REG UDR0
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* ASSR */
-#define TCR2UB_REG ASSR
-#define OCR2UB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* DDRG */
-#define DDG0_REG DDRG
-#define DDG1_REG DDRG
-#define DDG2_REG DDRG
-#define DDG3_REG DDRG
-#define DDG4_REG DDRG
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-#define DDE3_REG DDRE
-#define DDE4_REG DDRE
-#define DDE5_REG DDRE
-#define DDE6_REG DDRE
-#define DDE7_REG DDRE
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TCCR0A */
-#define CS00_REG TCCR0A
-#define CS01_REG TCCR0A
-#define CS02_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-#define WGM00_REG TCCR0A
-#define FOC0A_REG TCCR0A
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* GTCCR */
-#define PSR310_REG GTCCR
-#define TSM_REG GTCCR
-#define PSR2_REG GTCCR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* MCUSR */
-#define JTRF_REG MCUSR
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TCCR2A */
-#define CS20_REG TCCR2A
-#define CS21_REG TCCR2A
-#define CS22_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-#define WGM20_REG TCCR2A
-#define FOC2A_REG TCCR2A
-
-/* UBRR0H */
-#define UBRR8_REG UBRR0H
-#define UBRR9_REG UBRR0H
-#define UBRR10_REG UBRR0H
-#define UBRR11_REG UBRR0H
-
-/* UBRR0L */
-#define UBRR0_REG UBRR0L
-#define UBRR1_REG UBRR0L
-#define UBRR2_REG UBRR0L
-#define UBRR3_REG UBRR0L
-#define UBRR4_REG UBRR0L
-#define UBRR5_REG UBRR0L
-#define UBRR6_REG UBRR0L
-#define UBRR7_REG UBRR0L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* MCUCR */
-#define JTD_REG MCUCR
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* USISR */
-#define USICNT0_REG USISR
-#define USICNT1_REG USISR
-#define USICNT2_REG USISR
-#define USICNT3_REG USISR
-#define USIDC_REG USISR
-#define USIPF_REG USISR
-#define USIOIF_REG USISR
-#define USISIF_REG USISR
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ACME_REG ADCSRB
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-
-/* DDRF */
-#define DDF0_REG DDRF
-#define DDF1_REG DDRF
-#define DDF2_REG DDRF
-#define DDF3_REG DDRF
-#define DDF4_REG DDRF
-#define DDF5_REG DDRF
-#define DDF6_REG DDRF
-#define DDF7_REG DDRF
-
-/* OCR0A */
-#define OCR0A0_REG OCR0A
-#define OCR0A1_REG OCR0A
-#define OCR0A2_REG OCR0A
-#define OCR0A3_REG OCR0A
-#define OCR0A4_REG OCR0A
-#define OCR0A5_REG OCR0A
-#define OCR0A6_REG OCR0A
-#define OCR0A7_REG OCR0A
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* USICR */
-#define USITC_REG USICR
-#define USICLK_REG USICR
-#define USICS0_REG USICR
-#define USICS1_REG USICR
-#define USIWM0_REG USICR
-#define USIWM1_REG USICR
-#define USIOIE_REG USICR
-#define USISIE_REG USICR
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL0_REG UCSR0C
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define PCIE0_REG EIMSK
-#define PCIE1_REG EIMSK
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-#define PCINT15_REG PCMSK1
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define PCIF0_REG EIFR
-#define PCIF1_REG EIFR
-
-/* PING */
-#define PING0_REG PING
-#define PING1_REG PING
-#define PING2_REG PING
-#define PING3_REG PING
-#define PING4_REG PING
-#define PING5_REG PING
-
-/* PINF */
-#define PINF0_REG PINF
-#define PINF1_REG PINF
-#define PINF2_REG PINF
-#define PINF3_REG PINF
-#define PINF4_REG PINF
-#define PINF5_REG PINF
-#define PINF6_REG PINF
-#define PINF7_REG PINF
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-#define PINE3_REG PINE
-#define PINE4_REG PINE
-#define PINE5_REG PINE
-#define PINE6_REG PINE
-#define PINE7_REG PINE
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* USIDR */
-#define USIDR0_REG USIDR
-#define USIDR1_REG USIDR
-#define USIDR2_REG USIDR
-#define USIDR3_REG USIDR
-#define USIDR4_REG USIDR
-#define USIDR5_REG USIDR
-#define USIDR6_REG USIDR
-#define USIDR7_REG USIDR
-
-/* pins mapping */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE1A_NUM 1
-#define SIG_OUTPUT_COMPARE1B_NUM 2
-#define SIG_OUTPUT_COMPARE2_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM1A_NUM 1
-#define PWM1B_NUM 2
-#define PWM2_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* OCR2A */
-#define OCR2A0_REG OCR2A
-#define OCR2A1_REG OCR2A
-#define OCR2A2_REG OCR2A
-#define OCR2A3_REG OCR2A
-#define OCR2A4_REG OCR2A
-#define OCR2A5_REG OCR2A
-#define OCR2A6_REG OCR2A
-#define OCR2A7_REG OCR2A
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSART0_REG PRR
-#define PRSPI_REG PRR
-#define PRTIM1_REG PRR
-
-/* PORTF */
-#define PORTF0_REG PORTF
-#define PORTF1_REG PORTF
-#define PORTF2_REG PORTF
-#define PORTF3_REG PORTF
-#define PORTF4_REG PORTF
-#define PORTF5_REG PORTF
-#define PORTF6_REG PORTF
-#define PORTF7_REG PORTF
-
-/* PORTG */
-#define PORTG0_REG PORTG
-#define PORTG1_REG PORTG
-#define PORTG2_REG PORTG
-#define PORTG3_REG PORTG
-#define PORTG4_REG PORTG
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-#define PORTE3_REG PORTE
-#define PORTE4_REG PORTE
-#define PORTE5_REG PORTE
-#define PORTE6_REG PORTE
-#define PORTE7_REG PORTE
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* UDR0 */
-#define UDR00_REG UDR0
-#define UDR01_REG UDR0
-#define UDR02_REG UDR0
-#define UDR03_REG UDR0
-#define UDR04_REG UDR0
-#define UDR05_REG UDR0
-#define UDR06_REG UDR0
-#define UDR07_REG UDR0
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* ASSR */
-#define TCR2UB_REG ASSR
-#define OCR2UB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* DDRG */
-#define DDG0_REG DDRG
-#define DDG1_REG DDRG
-#define DDG2_REG DDRG
-#define DDG3_REG DDRG
-#define DDG4_REG DDRG
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-#define DDE3_REG DDRE
-#define DDE4_REG DDRE
-#define DDE5_REG DDRE
-#define DDE6_REG DDRE
-#define DDE7_REG DDRE
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TCCR0A */
-#define CS00_REG TCCR0A
-#define CS01_REG TCCR0A
-#define CS02_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-#define WGM00_REG TCCR0A
-#define FOC0A_REG TCCR0A
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* GTCCR */
-#define PSR310_REG GTCCR
-#define TSM_REG GTCCR
-#define PSR2_REG GTCCR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* MCUSR */
-#define JTRF_REG MCUSR
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TCCR2A */
-#define CS20_REG TCCR2A
-#define CS21_REG TCCR2A
-#define CS22_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-#define WGM20_REG TCCR2A
-#define FOC2A_REG TCCR2A
-
-/* UBRR0H */
-#define UBRR8_REG UBRR0H
-#define UBRR9_REG UBRR0H
-#define UBRR10_REG UBRR0H
-#define UBRR11_REG UBRR0H
-
-/* UBRR0L */
-#define UBRR0_REG UBRR0L
-#define UBRR1_REG UBRR0L
-#define UBRR2_REG UBRR0L
-#define UBRR3_REG UBRR0L
-#define UBRR4_REG UBRR0L
-#define UBRR5_REG UBRR0L
-#define UBRR6_REG UBRR0L
-#define UBRR7_REG UBRR0L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* MCUCR */
-#define JTD_REG MCUCR
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* USISR */
-#define USICNT0_REG USISR
-#define USICNT1_REG USISR
-#define USICNT2_REG USISR
-#define USICNT3_REG USISR
-#define USIDC_REG USISR
-#define USIPF_REG USISR
-#define USIOIF_REG USISR
-#define USISIF_REG USISR
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ACME_REG ADCSRB
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-
-/* DDRF */
-#define DDF0_REG DDRF
-#define DDF1_REG DDRF
-#define DDF2_REG DDRF
-#define DDF3_REG DDRF
-#define DDF4_REG DDRF
-#define DDF5_REG DDRF
-#define DDF6_REG DDRF
-#define DDF7_REG DDRF
-
-/* OCR0A */
-#define OCR0A0_REG OCR0A
-#define OCR0A1_REG OCR0A
-#define OCR0A2_REG OCR0A
-#define OCR0A3_REG OCR0A
-#define OCR0A4_REG OCR0A
-#define OCR0A5_REG OCR0A
-#define OCR0A6_REG OCR0A
-#define OCR0A7_REG OCR0A
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* USICR */
-#define USITC_REG USICR
-#define USICLK_REG USICR
-#define USICS0_REG USICR
-#define USICS1_REG USICR
-#define USIWM0_REG USICR
-#define USIWM1_REG USICR
-#define USIOIE_REG USICR
-#define USISIE_REG USICR
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL0_REG UCSR0C
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define PCIE0_REG EIMSK
-#define PCIE1_REG EIMSK
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-#define PCINT15_REG PCMSK1
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define PCIF0_REG EIFR
-#define PCIF1_REG EIFR
-
-/* PING */
-#define PING0_REG PING
-#define PING1_REG PING
-#define PING2_REG PING
-#define PING3_REG PING
-#define PING4_REG PING
-#define PING5_REG PING
-
-/* PINF */
-#define PINF0_REG PINF
-#define PINF1_REG PINF
-#define PINF2_REG PINF
-#define PINF3_REG PINF
-#define PINF4_REG PINF
-#define PINF5_REG PINF
-#define PINF6_REG PINF
-#define PINF7_REG PINF
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-#define PINE3_REG PINE
-#define PINE4_REG PINE
-#define PINE5_REG PINE
-#define PINE6_REG PINE
-#define PINE7_REG PINE
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* USIDR */
-#define USIDR0_REG USIDR
-#define USIDR1_REG USIDR
-#define USIDR2_REG USIDR
-#define USIDR3_REG USIDR
-#define USIDR4_REG USIDR
-#define USIDR5_REG USIDR
-#define USIDR6_REG USIDR
-#define USIDR7_REG USIDR
-
-/* pins mapping */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-#define TIMER2A_AVAILABLE
-#define TIMER2B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE2A_NUM 4
-#define SIG_OUTPUT_COMPARE2B_NUM 5
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 6
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM2A_NUM 4
-#define PWM2B_NUM 5
-#define PWM_TOTAL_NUM 6
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* OCR2B */
-#define OCR2B_0_REG OCR2B
-#define OCR2B_1_REG OCR2B
-#define OCR2B_2_REG OCR2B
-#define OCR2B_3_REG OCR2B
-#define OCR2B_4_REG OCR2B
-#define OCR2B_5_REG OCR2B
-#define OCR2B_6_REG OCR2B
-#define OCR2B_7_REG OCR2B
-
-/* OCR2A */
-#define OCR2A_0_REG OCR2A
-#define OCR2A_1_REG OCR2A
-#define OCR2A_2_REG OCR2A
-#define OCR2A_3_REG OCR2A
-#define OCR2A_4_REG OCR2A
-#define OCR2A_5_REG OCR2A
-#define OCR2A_6_REG OCR2A
-#define OCR2A_7_REG OCR2A
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSART0_REG PRR
-#define PRSPI_REG PRR
-#define PRTIM1_REG PRR
-#define PRTIM0_REG PRR
-#define PRTIM2_REG PRR
-#define PRTWI_REG PRR
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-
-/* UDR0 */
-#define UDR0_0_REG UDR0
-#define UDR0_1_REG UDR0
-#define UDR0_2_REG UDR0
-#define UDR0_3_REG UDR0
-#define UDR0_4_REG UDR0
-#define UDR0_5_REG UDR0
-#define UDR0_6_REG UDR0
-#define UDR0_7_REG UDR0
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* ASSR */
-#define TCR2BUB_REG ASSR
-#define TCR2AUB_REG ASSR
-#define OCR2BUB_REG ASSR
-#define OCR2AUB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* PCICR */
-#define PCIE0_REG PCICR
-#define PCIE1_REG PCICR
-#define PCIE2_REG PCICR
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-#define OCF2B_REG TIFR2
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* GTCCR */
-#define PSRSYNC_REG GTCCR
-#define TSM_REG GTCCR
-#define PSRASY_REG GTCCR
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* PCIFR */
-#define PCIF0_REG PCIFR
-#define PCIF1_REG PCIFR
-#define PCIF2_REG PCIFR
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* TCCR2A */
-#define WGM20_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2B0_REG TCCR2A
-#define COM2B1_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-
-/* TCCR2B */
-#define CS20_REG TCCR2B
-#define CS21_REG TCCR2B
-#define CS22_REG TCCR2B
-#define WGM22_REG TCCR2B
-#define FOC2B_REG TCCR2B
-#define FOC2A_REG TCCR2B
-
-/* UBRR0H */
-#define UBRR8_REG UBRR0H
-#define UBRR9_REG UBRR0H
-#define UBRR10_REG UBRR0H
-#define UBRR11_REG UBRR0H
-
-/* UBRR0L */
-#define UBRR0_REG UBRR0L
-#define UBRR1_REG UBRR0L
-#define UBRR2_REG UBRR0L
-#define UBRR3_REG UBRR0L
-#define UBRR4_REG UBRR0L
-#define UBRR5_REG UBRR0L
-#define UBRR6_REG UBRR0L
-#define UBRR7_REG UBRR0L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* MCUCR */
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ACME_REG ADCSRB
-
-/* OCR0A */
-#define OCROA_0_REG OCR0A
-#define OCROA_1_REG OCR0A
-#define OCROA_2_REG OCR0A
-#define OCROA_3_REG OCR0A
-#define OCROA_4_REG OCR0A
-#define OCROA_5_REG OCR0A
-#define OCROA_6_REG OCR0A
-#define OCROA_7_REG OCR0A
-
-/* OCR0B */
-#define OCR0B_0_REG OCR0B
-#define OCR0B_1_REG OCR0B
-#define OCR0B_2_REG OCR0B
-#define OCR0B_3_REG OCR0B
-#define OCR0B_4_REG OCR0B
-#define OCR0B_5_REG OCR0B
-#define OCR0B_6_REG OCR0B
-#define OCR0B_7_REG OCR0B
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL00_REG UCSR0C
-#define UMSEL01_REG UCSR0C
-
-/* SPMCSR */
-#define SELFPRGEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-#define OCIE2B_REG TIMSK2
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-
-/* PCMSK2 */
-#define PCINT16_REG PCMSK2
-#define PCINT17_REG PCMSK2
-#define PCINT18_REG PCMSK2
-#define PCINT19_REG PCMSK2
-#define PCINT20_REG PCMSK2
-#define PCINT21_REG PCMSK2
-#define PCINT22_REG PCMSK2
-#define PCINT23_REG PCMSK2
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* TWAMR */
-#define TWAM0_REG TWAMR
-#define TWAM1_REG TWAMR
-#define TWAM2_REG TWAMR
-#define TWAM3_REG TWAMR
-#define TWAM4_REG TWAMR
-#define TWAM5_REG TWAMR
-#define TWAM6_REG TWAMR
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* pins mapping */
-#define ICP1_PORT PORTB
-#define ICP1_BIT 0
-#define CLKO_PORT PORTB
-#define CLKO_BIT 0
-#define PCINT0_PORT PORTB
-#define PCINT0_BIT 0
-
-#define OC1A_PORT PORTB
-#define OC1A_BIT 1
-#define PCINT1_PORT PORTB
-#define PCINT1_BIT 1
-
-#define SS_PORT PORTB
-#define SS_BIT 2
-#define OC1B_PORT PORTB
-#define OC1B_BIT 2
-#define PCINT2_PORT PORTB
-#define PCINT2_BIT 2
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 3
-#define OC2A_PORT PORTB
-#define OC2A_BIT 3
-#define PCINT3_PORT PORTB
-#define PCINT3_BIT 3
-
-#define MISO_PORT PORTB
-#define MISO_BIT 4
-#define PCINT4_PORT PORTB
-#define PCINT4_BIT 4
-
-#define SCK_PORT PORTB
-#define SCK_BIT 5
-#define PCINT5_PORT PORTB
-#define PCINT5_BIT 5
-
-#define XTAL1_PORT PORTB
-#define XTAL1_BIT 6
-#define TOSC1_PORT PORTB
-#define TOSC1_BIT 6
-#define PCINT6_PORT PORTB
-#define PCINT6_BIT 6
-
-#define XTAL2_PORT PORTB
-#define XTAL2_BIT 7
-#define TOSC2_PORT PORTB
-#define TOSC2_BIT 7
-#define PCINT7_PORT PORTB
-#define PCINT7_BIT 7
-
-#define ADC0_PORT PORTC
-#define ADC0_BIT 0
-#define PCINT8_PORT PORTC
-#define PCINT8_BIT 0
-
-#define ADC1_PORT PORTC
-#define ADC1_BIT 1
-#define PCINT9_PORT PORTC
-#define PCINT9_BIT 1
-
-#define ADC2_PORT PORTC
-#define ADC2_BIT 2
-#define PCINT10_PORT PORTC
-#define PCINT10_BIT 2
-
-#define ADC3_PORT PORTC
-#define ADC3_BIT 3
-#define PCINT11_PORT PORTC
-#define PCINT11_BIT 3
-
-#define ADC4_PORT PORTC
-#define ADC4_BIT 4
-#define SDA_PORT PORTC
-#define SDA_BIT 4
-#define PCINT12_PORT PORTC
-#define PCINT12_BIT 4
-
-#define ADC5_PORT PORTC
-#define ADC5_BIT 5
-#define SCL_PORT PORTC
-#define SCL_BIT 5
-#define PCINT13_PORT PORTC
-#define PCINT13_BIT 5
-
-#define RESET_PORT PORTC
-#define RESET_BIT 6
-#define PCINT14_PORT PORTC
-#define PCINT14_BIT 6
-
-#define RXD_PORT PORTD
-#define RXD_BIT 0
-#define PCINT16_PORT PORTD
-#define PCINT16_BIT 0
-
-#define TXD_PORT PORTD
-#define TXD_BIT 1
-#define PCINT17_PORT PORTD
-#define PCINT17_BIT 1
-
-#define INT0_PORT PORTD
-#define INT0_BIT 2
-#define PCINT18_PORT PORTD
-#define PCINT18_BIT 2
-
-#define PCINT19_PORT PORTD
-#define PCINT19_BIT 3
-#define OC2B_PORT PORTD
-#define OC2B_BIT 3
-#define INT1_PORT PORTD
-#define INT1_BIT 3
-
-#define XCK_PORT PORTD
-#define XCK_BIT 4
-#define T0_PORT PORTD
-#define T0_BIT 4
-#define PCINT20_PORT PORTD
-#define PCINT20_BIT 4
-
-#define T1_PORT PORTD
-#define T1_BIT 5
-#define OC0B_PORT PORTD
-#define OC0B_BIT 5
-#define PCINT21_PORT PORTD
-#define PCINT21_BIT 5
-
-#define AIN0_PORT PORTD
-#define AIN0_BIT 6
-#define OC0A_PORT PORTD
-#define OC0A_BIT 6
-#define PCINT22_PORT PORTD
-#define PCINT22_BIT 6
-
-#define AIN1_PORT PORTD
-#define AIN1_BIT 7
-#define PCINT23_PORT PORTD
-#define PCINT23_BIT 7
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-#define TIMER2A_AVAILABLE
-#define TIMER2B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE2A_NUM 4
-#define SIG_OUTPUT_COMPARE2B_NUM 5
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 6
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM2A_NUM 4
-#define PWM2B_NUM 5
-#define PWM_TOTAL_NUM 6
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* OCR2B */
-#define OCR2B_0_REG OCR2B
-#define OCR2B_1_REG OCR2B
-#define OCR2B_2_REG OCR2B
-#define OCR2B_3_REG OCR2B
-#define OCR2B_4_REG OCR2B
-#define OCR2B_5_REG OCR2B
-#define OCR2B_6_REG OCR2B
-#define OCR2B_7_REG OCR2B
-
-/* OCR2A */
-#define OCR2A_0_REG OCR2A
-#define OCR2A_1_REG OCR2A
-#define OCR2A_2_REG OCR2A
-#define OCR2A_3_REG OCR2A
-#define OCR2A_4_REG OCR2A
-#define OCR2A_5_REG OCR2A
-#define OCR2A_6_REG OCR2A
-#define OCR2A_7_REG OCR2A
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSART0_REG PRR
-#define PRSPI_REG PRR
-#define PRTIM1_REG PRR
-#define PRTIM0_REG PRR
-#define PRTIM2_REG PRR
-#define PRTWI_REG PRR
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-
-/* UDR0 */
-#define UDR0_0_REG UDR0
-#define UDR0_1_REG UDR0
-#define UDR0_2_REG UDR0
-#define UDR0_3_REG UDR0
-#define UDR0_4_REG UDR0
-#define UDR0_5_REG UDR0
-#define UDR0_6_REG UDR0
-#define UDR0_7_REG UDR0
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* ASSR */
-#define TCR2BUB_REG ASSR
-#define TCR2AUB_REG ASSR
-#define OCR2BUB_REG ASSR
-#define OCR2AUB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* PCICR */
-#define PCIE0_REG PCICR
-#define PCIE1_REG PCICR
-#define PCIE2_REG PCICR
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-#define OCF2B_REG TIFR2
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* GTCCR */
-#define PSRSYNC_REG GTCCR
-#define TSM_REG GTCCR
-#define PSRASY_REG GTCCR
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* PCIFR */
-#define PCIF0_REG PCIFR
-#define PCIF1_REG PCIFR
-#define PCIF2_REG PCIFR
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* TCCR2A */
-#define WGM20_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2B0_REG TCCR2A
-#define COM2B1_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-
-/* TCCR2B */
-#define CS20_REG TCCR2B
-#define CS21_REG TCCR2B
-#define CS22_REG TCCR2B
-#define WGM22_REG TCCR2B
-#define FOC2B_REG TCCR2B
-#define FOC2A_REG TCCR2B
-
-/* UBRR0H */
-#define UBRR8_REG UBRR0H
-#define UBRR9_REG UBRR0H
-#define UBRR10_REG UBRR0H
-#define UBRR11_REG UBRR0H
-
-/* UBRR0L */
-#define UBRR0_REG UBRR0L
-#define UBRR1_REG UBRR0L
-#define UBRR2_REG UBRR0L
-#define UBRR3_REG UBRR0L
-#define UBRR4_REG UBRR0L
-#define UBRR5_REG UBRR0L
-#define UBRR6_REG UBRR0L
-#define UBRR7_REG UBRR0L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* MCUCR */
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-#define BODSE_REG MCUCR
-#define BODS_REG MCUCR
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ACME_REG ADCSRB
-
-/* OCR0A */
-#define OCROA_0_REG OCR0A
-#define OCROA_1_REG OCR0A
-#define OCROA_2_REG OCR0A
-#define OCROA_3_REG OCR0A
-#define OCROA_4_REG OCR0A
-#define OCROA_5_REG OCR0A
-#define OCROA_6_REG OCR0A
-#define OCROA_7_REG OCR0A
-
-/* OCR0B */
-#define OCR0B_0_REG OCR0B
-#define OCR0B_1_REG OCR0B
-#define OCR0B_2_REG OCR0B
-#define OCR0B_3_REG OCR0B
-#define OCR0B_4_REG OCR0B
-#define OCR0B_5_REG OCR0B
-#define OCR0B_6_REG OCR0B
-#define OCR0B_7_REG OCR0B
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL00_REG UCSR0C
-#define UMSEL01_REG UCSR0C
-
-/* SPMCSR */
-#define SELFPRGEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-#define OCIE2B_REG TIMSK2
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-
-/* PCMSK2 */
-#define PCINT16_REG PCMSK2
-#define PCINT17_REG PCMSK2
-#define PCINT18_REG PCMSK2
-#define PCINT19_REG PCMSK2
-#define PCINT20_REG PCMSK2
-#define PCINT21_REG PCMSK2
-#define PCINT22_REG PCMSK2
-#define PCINT23_REG PCMSK2
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* TWAMR */
-#define TWAM0_REG TWAMR
-#define TWAM1_REG TWAMR
-#define TWAM2_REG TWAMR
-#define TWAM3_REG TWAMR
-#define TWAM4_REG TWAMR
-#define TWAM5_REG TWAMR
-#define TWAM6_REG TWAMR
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* pins mapping */
-#define ICP1_PORT PORTB
-#define ICP1_BIT 0
-#define CLKO_PORT PORTB
-#define CLKO_BIT 0
-#define PCINT0_PORT PORTB
-#define PCINT0_BIT 0
-
-#define OC1A_PORT PORTB
-#define OC1A_BIT 1
-#define PCINT1_PORT PORTB
-#define PCINT1_BIT 1
-
-#define SS_PORT PORTB
-#define SS_BIT 2
-#define OC1B_PORT PORTB
-#define OC1B_BIT 2
-#define PCINT2_PORT PORTB
-#define PCINT2_BIT 2
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 3
-#define OC2A_PORT PORTB
-#define OC2A_BIT 3
-#define PCINT3_PORT PORTB
-#define PCINT3_BIT 3
-
-#define MISO_PORT PORTB
-#define MISO_BIT 4
-#define PCINT4_PORT PORTB
-#define PCINT4_BIT 4
-
-#define SCK_PORT PORTB
-#define SCK_BIT 5
-#define PCINT5_PORT PORTB
-#define PCINT5_BIT 5
-
-#define XTAL1_PORT PORTB
-#define XTAL1_BIT 6
-#define TOSC1_PORT PORTB
-#define TOSC1_BIT 6
-#define PCINT6_PORT PORTB
-#define PCINT6_BIT 6
-
-#define XTAL2_PORT PORTB
-#define XTAL2_BIT 7
-#define TOSC2_PORT PORTB
-#define TOSC2_BIT 7
-#define PCINT7_PORT PORTB
-#define PCINT7_BIT 7
-
-#define ADC0_PORT PORTC
-#define ADC0_BIT 0
-#define PCINT8_PORT PORTC
-#define PCINT8_BIT 0
-
-#define ADC1_PORT PORTC
-#define ADC1_BIT 1
-#define PCINT9_PORT PORTC
-#define PCINT9_BIT 1
-
-#define ADC2_PORT PORTC
-#define ADC2_BIT 2
-#define PCINT10_PORT PORTC
-#define PCINT10_BIT 2
-
-#define ADC3_PORT PORTC
-#define ADC3_BIT 3
-#define PCINT11_PORT PORTC
-#define PCINT11_BIT 3
-
-#define ADC4_PORT PORTC
-#define ADC4_BIT 4
-#define SDA_PORT PORTC
-#define SDA_BIT 4
-#define PCINT12_PORT PORTC
-#define PCINT12_BIT 4
-
-#define ADC5_PORT PORTC
-#define ADC5_BIT 5
-#define SCL_PORT PORTC
-#define SCL_BIT 5
-#define PCINT13_PORT PORTC
-#define PCINT13_BIT 5
-
-#define RESET_PORT PORTC
-#define RESET_BIT 6
-#define PCINT14_PORT PORTC
-#define PCINT14_BIT 6
-
-#define RXD_PORT PORTD
-#define RXD_BIT 0
-#define PCINT16_PORT PORTD
-#define PCINT16_BIT 0
-
-#define TXD_PORT PORTD
-#define TXD_BIT 1
-#define PCINT17_PORT PORTD
-#define PCINT17_BIT 1
-
-#define INT0_PORT PORTD
-#define INT0_BIT 2
-#define PCINT18_PORT PORTD
-#define PCINT18_BIT 2
-
-#define PCINT19_PORT PORTD
-#define PCINT19_BIT 3
-#define OC2B_PORT PORTD
-#define OC2B_BIT 3
-#define INT1_PORT PORTD
-#define INT1_BIT 3
-
-#define XCK_PORT PORTD
-#define XCK_BIT 4
-#define T0_PORT PORTD
-#define T0_BIT 4
-#define PCINT20_PORT PORTD
-#define PCINT20_BIT 4
-
-#define T1_PORT PORTD
-#define T1_BIT 5
-#define OC0B_PORT PORTD
-#define OC0B_BIT 5
-#define PCINT21_PORT PORTD
-#define PCINT21_BIT 5
-
-#define AIN0_PORT PORTD
-#define AIN0_BIT 6
-#define OC0A_PORT PORTD
-#define OC0A_BIT 6
-#define PCINT22_PORT PORTD
-#define PCINT22_BIT 6
-
-#define AIN1_PORT PORTD
-#define AIN1_BIT 7
-#define PCINT23_PORT PORTD
-#define PCINT23_BIT 7
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-#define TIMER2A_AVAILABLE
-#define TIMER2B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE2A_NUM 4
-#define SIG_OUTPUT_COMPARE2B_NUM 5
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 6
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM2A_NUM 4
-#define PWM2B_NUM 5
-#define PWM_TOTAL_NUM 6
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* OCR2B */
-#define OCR2B_0_REG OCR2B
-#define OCR2B_1_REG OCR2B
-#define OCR2B_2_REG OCR2B
-#define OCR2B_3_REG OCR2B
-#define OCR2B_4_REG OCR2B
-#define OCR2B_5_REG OCR2B
-#define OCR2B_6_REG OCR2B
-#define OCR2B_7_REG OCR2B
-
-/* OCR2A */
-#define OCR2A_0_REG OCR2A
-#define OCR2A_1_REG OCR2A
-#define OCR2A_2_REG OCR2A
-#define OCR2A_3_REG OCR2A
-#define OCR2A_4_REG OCR2A
-#define OCR2A_5_REG OCR2A
-#define OCR2A_6_REG OCR2A
-#define OCR2A_7_REG OCR2A
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSART0_REG PRR
-#define PRSPI_REG PRR
-#define PRTIM1_REG PRR
-#define PRTIM0_REG PRR
-#define PRTIM2_REG PRR
-#define PRTWI_REG PRR
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-
-/* UDR0 */
-#define UDR0_0_REG UDR0
-#define UDR0_1_REG UDR0
-#define UDR0_2_REG UDR0
-#define UDR0_3_REG UDR0
-#define UDR0_4_REG UDR0
-#define UDR0_5_REG UDR0
-#define UDR0_6_REG UDR0
-#define UDR0_7_REG UDR0
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* ASSR */
-#define TCR2BUB_REG ASSR
-#define TCR2AUB_REG ASSR
-#define OCR2BUB_REG ASSR
-#define OCR2AUB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* PCICR */
-#define PCIE0_REG PCICR
-#define PCIE1_REG PCICR
-#define PCIE2_REG PCICR
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-#define OCF2B_REG TIFR2
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* GTCCR */
-#define PSRSYNC_REG GTCCR
-#define TSM_REG GTCCR
-#define PSRASY_REG GTCCR
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* PCIFR */
-#define PCIF0_REG PCIFR
-#define PCIF1_REG PCIFR
-#define PCIF2_REG PCIFR
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* TCCR2A */
-#define WGM20_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2B0_REG TCCR2A
-#define COM2B1_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-
-/* TCCR2B */
-#define CS20_REG TCCR2B
-#define CS21_REG TCCR2B
-#define CS22_REG TCCR2B
-#define WGM22_REG TCCR2B
-#define FOC2B_REG TCCR2B
-#define FOC2A_REG TCCR2B
-
-/* UBRR0H */
-#define UBRR8_REG UBRR0H
-#define UBRR9_REG UBRR0H
-#define UBRR10_REG UBRR0H
-#define UBRR11_REG UBRR0H
-
-/* UBRR0L */
-#define UBRR0_REG UBRR0L
-#define UBRR1_REG UBRR0L
-#define UBRR2_REG UBRR0L
-#define UBRR3_REG UBRR0L
-#define UBRR4_REG UBRR0L
-#define UBRR5_REG UBRR0L
-#define UBRR6_REG UBRR0L
-#define UBRR7_REG UBRR0L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* MCUCR */
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-#define BODSE_REG MCUCR
-#define BODS_REG MCUCR
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ACME_REG ADCSRB
-
-/* OCR0A */
-#define OCROA_0_REG OCR0A
-#define OCROA_1_REG OCR0A
-#define OCROA_2_REG OCR0A
-#define OCROA_3_REG OCR0A
-#define OCROA_4_REG OCR0A
-#define OCROA_5_REG OCR0A
-#define OCROA_6_REG OCR0A
-#define OCROA_7_REG OCR0A
-
-/* OCR0B */
-#define OCR0B_0_REG OCR0B
-#define OCR0B_1_REG OCR0B
-#define OCR0B_2_REG OCR0B
-#define OCR0B_3_REG OCR0B
-#define OCR0B_4_REG OCR0B
-#define OCR0B_5_REG OCR0B
-#define OCR0B_6_REG OCR0B
-#define OCR0B_7_REG OCR0B
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL00_REG UCSR0C
-#define UMSEL01_REG UCSR0C
-
-/* SPMCSR */
-#define SELFPRGEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-#define OCIE2B_REG TIMSK2
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-
-/* PCMSK2 */
-#define PCINT16_REG PCMSK2
-#define PCINT17_REG PCMSK2
-#define PCINT18_REG PCMSK2
-#define PCINT19_REG PCMSK2
-#define PCINT20_REG PCMSK2
-#define PCINT21_REG PCMSK2
-#define PCINT22_REG PCMSK2
-#define PCINT23_REG PCMSK2
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* TWAMR */
-#define TWAM0_REG TWAMR
-#define TWAM1_REG TWAMR
-#define TWAM2_REG TWAMR
-#define TWAM3_REG TWAMR
-#define TWAM4_REG TWAMR
-#define TWAM5_REG TWAMR
-#define TWAM6_REG TWAMR
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* pins mapping */
-#define ICP1_PORT PORTB
-#define ICP1_BIT 0
-#define CLKO_PORT PORTB
-#define CLKO_BIT 0
-#define PCINT0_PORT PORTB
-#define PCINT0_BIT 0
-
-#define OC1A_PORT PORTB
-#define OC1A_BIT 1
-#define PCINT1_PORT PORTB
-#define PCINT1_BIT 1
-
-#define SS_PORT PORTB
-#define SS_BIT 2
-#define OC1B_PORT PORTB
-#define OC1B_BIT 2
-#define PCINT2_PORT PORTB
-#define PCINT2_BIT 2
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 3
-#define OC2A_PORT PORTB
-#define OC2A_BIT 3
-#define PCINT3_PORT PORTB
-#define PCINT3_BIT 3
-
-#define MISO_PORT PORTB
-#define MISO_BIT 4
-#define PCINT4_PORT PORTB
-#define PCINT4_BIT 4
-
-#define SCK_PORT PORTB
-#define SCK_BIT 5
-#define PCINT5_PORT PORTB
-#define PCINT5_BIT 5
-
-#define XTAL1_PORT PORTB
-#define XTAL1_BIT 6
-#define TOSC1_PORT PORTB
-#define TOSC1_BIT 6
-#define PCINT6_PORT PORTB
-#define PCINT6_BIT 6
-
-#define XTAL2_PORT PORTB
-#define XTAL2_BIT 7
-#define TOSC2_PORT PORTB
-#define TOSC2_BIT 7
-#define PCINT7_PORT PORTB
-#define PCINT7_BIT 7
-
-#define ADC0_PORT PORTC
-#define ADC0_BIT 0
-#define PCINT8_PORT PORTC
-#define PCINT8_BIT 0
-
-#define ADC1_PORT PORTC
-#define ADC1_BIT 1
-#define PCINT9_PORT PORTC
-#define PCINT9_BIT 1
-
-#define ADC2_PORT PORTC
-#define ADC2_BIT 2
-#define PCINT10_PORT PORTC
-#define PCINT10_BIT 2
-
-#define ADC3_PORT PORTC
-#define ADC3_BIT 3
-#define PCINT11_PORT PORTC
-#define PCINT11_BIT 3
-
-#define ADC4_PORT PORTC
-#define ADC4_BIT 4
-#define SDA_PORT PORTC
-#define SDA_BIT 4
-#define PCINT12_PORT PORTC
-#define PCINT12_BIT 4
-
-#define ADC5_PORT PORTC
-#define ADC5_BIT 5
-#define SCL_PORT PORTC
-#define SCL_BIT 5
-#define PCINT13_PORT PORTC
-#define PCINT13_BIT 5
-
-#define RESET_PORT PORTC
-#define RESET_BIT 6
-#define PCINT14_PORT PORTC
-#define PCINT14_BIT 6
-
-#define RXD_PORT PORTD
-#define RXD_BIT 0
-#define PCINT16_PORT PORTD
-#define PCINT16_BIT 0
-
-#define TXD_PORT PORTD
-#define TXD_BIT 1
-#define PCINT17_PORT PORTD
-#define PCINT17_BIT 1
-
-#define INT0_PORT PORTD
-#define INT0_BIT 2
-#define PCINT18_PORT PORTD
-#define PCINT18_BIT 2
-
-#define PCINT19_PORT PORTD
-#define PCINT19_BIT 3
-#define OC2B_PORT PORTD
-#define OC2B_BIT 3
-#define INT1_PORT PORTD
-#define INT1_BIT 3
-
-#define XCK_PORT PORTD
-#define XCK_BIT 4
-#define T0_PORT PORTD
-#define T0_BIT 4
-#define PCINT20_PORT PORTD
-#define PCINT20_BIT 4
-
-#define T1_PORT PORTD
-#define T1_BIT 5
-#define OC0B_PORT PORTD
-#define OC0B_BIT 5
-#define PCINT21_PORT PORTD
-#define PCINT21_BIT 5
-
-#define AIN0_PORT PORTD
-#define AIN0_BIT 6
-#define OC0A_PORT PORTD
-#define OC0A_BIT 6
-#define PCINT22_PORT PORTD
-#define PCINT22_BIT 6
-
-#define AIN1_PORT PORTD
-#define AIN1_BIT 7
-#define PCINT23_PORT PORTD
-#define PCINT23_BIT 7
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE1A_NUM 1
-#define SIG_OUTPUT_COMPARE1B_NUM 2
-#define SIG_OUTPUT_COMPARE2_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM1A_NUM 1
-#define PWM1B_NUM 2
-#define PWM2_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* OCR2A */
-#define OCR2A0_REG OCR2A
-#define OCR2A1_REG OCR2A
-#define OCR2A2_REG OCR2A
-#define OCR2A3_REG OCR2A
-#define OCR2A4_REG OCR2A
-#define OCR2A5_REG OCR2A
-#define OCR2A6_REG OCR2A
-#define OCR2A7_REG OCR2A
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSART0_REG PRR
-#define PRSPI_REG PRR
-#define PRTIM1_REG PRR
-#define PRLCD_REG PRR
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* PORTG */
-#define PORTG0_REG PORTG
-#define PORTG1_REG PORTG
-#define PORTG2_REG PORTG
-#define PORTG3_REG PORTG
-#define PORTG4_REG PORTG
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL0_REG UCSR0C
-
-/* USISR */
-#define USICNT0_REG USISR
-#define USICNT1_REG USISR
-#define USICNT2_REG USISR
-#define USICNT3_REG USISR
-#define USIDC_REG USISR
-#define USIPF_REG USISR
-#define USIOIF_REG USISR
-#define USISIF_REG USISR
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* UDR0 */
-#define UDR00_REG UDR0
-#define UDR01_REG UDR0
-#define UDR02_REG UDR0
-#define UDR03_REG UDR0
-#define UDR04_REG UDR0
-#define UDR05_REG UDR0
-#define UDR06_REG UDR0
-#define UDR07_REG UDR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* ASSR */
-#define TCR2UB_REG ASSR
-#define OCR2UB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* DDRG */
-#define DDG0_REG DDRG
-#define DDG1_REG DDRG
-#define DDG2_REG DDRG
-#define DDG3_REG DDRG
-#define DDG4_REG DDRG
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* LCDDR3 */
-#define SEG024_REG LCDDR3
-
-/* LCDDR2 */
-#define SEG016_REG LCDDR2
-#define SEG017_REG LCDDR2
-#define SEG018_REG LCDDR2
-#define SEG019_REG LCDDR2
-#define SEG020_REG LCDDR2
-#define SEG021_REG LCDDR2
-#define SEG022_REG LCDDR2
-#define SEG023_REG LCDDR2
-
-/* LCDDR1 */
-#define SEG008_REG LCDDR1
-#define SEG009_REG LCDDR1
-#define SEG010_REG LCDDR1
-#define SEG011_REG LCDDR1
-#define SEG012_REG LCDDR1
-#define SEG013_REG LCDDR1
-#define SEG014_REG LCDDR1
-#define SEG015_REG LCDDR1
-
-/* LCDDR0 */
-#define SEG000_REG LCDDR0
-#define SEG001_REG LCDDR0
-#define SEG002_REG LCDDR0
-#define SEG003_REG LCDDR0
-#define SEG004_REG LCDDR0
-#define SEG005_REG LCDDR0
-#define SEG006_REG LCDDR0
-#define SEG007_REG LCDDR0
-
-/* LCDDR7 */
-#define SEG116_REG LCDDR7
-#define SEG117_REG LCDDR7
-#define SEG118_REG LCDDR7
-#define SEG119_REG LCDDR7
-#define SEG120_REG LCDDR7
-#define SEG121_REG LCDDR7
-#define SEG122_REG LCDDR7
-#define SEG123_REG LCDDR7
-
-/* LCDDR6 */
-#define SEG108_REG LCDDR6
-#define SEG109_REG LCDDR6
-#define SEG110_REG LCDDR6
-#define SEG111_REG LCDDR6
-#define SEG112_REG LCDDR6
-#define SEG113_REG LCDDR6
-#define SEG114_REG LCDDR6
-#define SEG115_REG LCDDR6
-
-/* LCDDR5 */
-#define SEG100_REG LCDDR5
-#define SEG101_REG LCDDR5
-#define SEG102_REG LCDDR5
-#define SEG103_REG LCDDR5
-#define SEG104_REG LCDDR5
-#define SEG105_REG LCDDR5
-#define SEG106_REG LCDDR5
-#define SEG107_REG LCDDR5
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* LCDDR8 */
-#define SEG124_REG LCDDR8
-
-/* LCDCRA */
-#define LCDBL_REG LCDCRA
-#define LCDIE_REG LCDCRA
-#define LCDIF_REG LCDCRA
-#define LCDAB_REG LCDCRA
-#define LCDEN_REG LCDCRA
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-#define DDE3_REG DDRE
-#define DDE4_REG DDRE
-#define DDE5_REG DDRE
-#define DDE6_REG DDRE
-#define DDE7_REG DDRE
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TCCR0A */
-#define CS00_REG TCCR0A
-#define CS01_REG TCCR0A
-#define CS02_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-#define WGM00_REG TCCR0A
-#define FOC0A_REG TCCR0A
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* GTCCR */
-#define PSR310_REG GTCCR
-#define TSM_REG GTCCR
-#define PSR2_REG GTCCR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* LCDCRB */
-#define LCDPM0_REG LCDCRB
-#define LCDPM1_REG LCDCRB
-#define LCDPM2_REG LCDCRB
-#define LCDMUX0_REG LCDCRB
-#define LCDMUX1_REG LCDCRB
-#define LCD2B_REG LCDCRB
-#define LCDCS_REG LCDCRB
-
-/* LCDDR18 */
-#define SEG324_REG LCDDR18
-
-/* LCDDR13 */
-#define SEG224_REG LCDDR13
-
-/* LCDDR12 */
-#define SEG216_REG LCDDR12
-#define SEG217_REG LCDDR12
-#define SEG218_REG LCDDR12
-#define SEG219_REG LCDDR12
-#define SEG220_REG LCDDR12
-#define SEG221_REG LCDDR12
-#define SEG222_REG LCDDR12
-#define SEG223_REG LCDDR12
-
-/* LCDDR11 */
-#define SEG208_REG LCDDR11
-#define SEG209_REG LCDDR11
-#define SEG210_REG LCDDR11
-#define SEG211_REG LCDDR11
-#define SEG212_REG LCDDR11
-#define SEG213_REG LCDDR11
-#define SEG214_REG LCDDR11
-#define SEG215_REG LCDDR11
-
-/* LCDDR10 */
-#define SEG200_REG LCDDR10
-#define SEG201_REG LCDDR10
-#define SEG202_REG LCDDR10
-#define SEG203_REG LCDDR10
-#define SEG204_REG LCDDR10
-#define SEG205_REG LCDDR10
-#define SEG206_REG LCDDR10
-#define SEG207_REG LCDDR10
-
-/* LCDDR17 */
-#define SEG316_REG LCDDR17
-#define SEG317_REG LCDDR17
-#define SEG318_REG LCDDR17
-#define SEG319_REG LCDDR17
-#define SEG320_REG LCDDR17
-#define SEG321_REG LCDDR17
-#define SEG322_REG LCDDR17
-#define SEG323_REG LCDDR17
-
-/* LCDDR16 */
-#define SEG308_REG LCDDR16
-#define SEG309_REG LCDDR16
-#define SEG310_REG LCDDR16
-#define SEG311_REG LCDDR16
-#define SEG312_REG LCDDR16
-#define SEG313_REG LCDDR16
-#define SEG314_REG LCDDR16
-#define SEG315_REG LCDDR16
-
-/* LCDDR15 */
-#define SEG300_REG LCDDR15
-#define SEG301_REG LCDDR15
-#define SEG302_REG LCDDR15
-#define SEG303_REG LCDDR15
-#define SEG304_REG LCDDR15
-#define SEG305_REG LCDDR15
-#define SEG306_REG LCDDR15
-#define SEG307_REG LCDDR15
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* MCUSR */
-#define JTRF_REG MCUSR
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TCCR2A */
-#define CS20_REG TCCR2A
-#define CS21_REG TCCR2A
-#define CS22_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-#define WGM20_REG TCCR2A
-#define FOC2A_REG TCCR2A
-
-/* UBRR0H */
-#define UBRR8_REG UBRR0H
-#define UBRR9_REG UBRR0H
-#define UBRR10_REG UBRR0H
-#define UBRR11_REG UBRR0H
-
-/* UBRR0L */
-#define UBRR0_REG UBRR0L
-#define UBRR1_REG UBRR0L
-#define UBRR2_REG UBRR0L
-#define UBRR3_REG UBRR0L
-#define UBRR4_REG UBRR0L
-#define UBRR5_REG UBRR0L
-#define UBRR6_REG UBRR0L
-#define UBRR7_REG UBRR0L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* MCUCR */
-#define JTD_REG MCUCR
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-#define PORTE3_REG PORTE
-#define PORTE4_REG PORTE
-#define PORTE5_REG PORTE
-#define PORTE6_REG PORTE
-#define PORTE7_REG PORTE
-
-/* LCDCCR */
-#define LCDCC0_REG LCDCCR
-#define LCDCC1_REG LCDCCR
-#define LCDCC2_REG LCDCCR
-#define LCDCC3_REG LCDCCR
-#define LCDDC0_REG LCDCCR
-#define LCDDC1_REG LCDCCR
-#define LCDDC2_REG LCDCCR
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-#define PINE3_REG PINE
-#define PINE4_REG PINE
-#define PINE5_REG PINE
-#define PINE6_REG PINE
-#define PINE7_REG PINE
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ACME_REG ADCSRB
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-
-/* DDRF */
-#define DDF0_REG DDRF
-#define DDF1_REG DDRF
-#define DDF2_REG DDRF
-#define DDF3_REG DDRF
-#define DDF4_REG DDRF
-#define DDF5_REG DDRF
-#define DDF6_REG DDRF
-#define DDF7_REG DDRF
-
-/* OCR0A */
-#define OCR0A0_REG OCR0A
-#define OCR0A1_REG OCR0A
-#define OCR0A2_REG OCR0A
-#define OCR0A3_REG OCR0A
-#define OCR0A4_REG OCR0A
-#define OCR0A5_REG OCR0A
-#define OCR0A6_REG OCR0A
-#define OCR0A7_REG OCR0A
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* USICR */
-#define USITC_REG USICR
-#define USICLK_REG USICR
-#define USICS0_REG USICR
-#define USICS1_REG USICR
-#define USIWM0_REG USICR
-#define USIWM1_REG USICR
-#define USIOIE_REG USICR
-#define USISIE_REG USICR
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* LCDFRR */
-#define LCDCD0_REG LCDFRR
-#define LCDCD1_REG LCDFRR
-#define LCDCD2_REG LCDFRR
-#define LCDPS0_REG LCDFRR
-#define LCDPS1_REG LCDFRR
-#define LCDPS2_REG LCDFRR
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define PCIE0_REG EIMSK
-#define PCIE1_REG EIMSK
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-#define PCINT15_REG PCMSK1
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define PCIF0_REG EIFR
-#define PCIF1_REG EIFR
-
-/* PING */
-#define PING0_REG PING
-#define PING1_REG PING
-#define PING2_REG PING
-#define PING3_REG PING
-#define PING4_REG PING
-
-/* PINF */
-#define PINF0_REG PINF
-#define PINF1_REG PINF
-#define PINF2_REG PINF
-#define PINF3_REG PINF
-#define PINF4_REG PINF
-#define PINF5_REG PINF
-#define PINF6_REG PINF
-#define PINF7_REG PINF
-
-/* PORTF */
-#define PORTF0_REG PORTF
-#define PORTF1_REG PORTF
-#define PORTF2_REG PORTF
-#define PORTF3_REG PORTF
-#define PORTF4_REG PORTF
-#define PORTF5_REG PORTF
-#define PORTF6_REG PORTF
-#define PORTF7_REG PORTF
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-
-/* USIDR */
-#define USIDR0_REG USIDR
-#define USIDR1_REG USIDR
-#define USIDR2_REG USIDR
-#define USIDR3_REG USIDR
-#define USIDR4_REG USIDR
-#define USIDR5_REG USIDR
-#define USIDR6_REG USIDR
-#define USIDR7_REG USIDR
-
-/* pins mapping */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE1A_NUM 1
-#define SIG_OUTPUT_COMPARE1B_NUM 2
-#define SIG_OUTPUT_COMPARE2_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM1A_NUM 1
-#define PWM1B_NUM 2
-#define PWM2_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* OCR2A */
-#define OCR2A0_REG OCR2A
-#define OCR2A1_REG OCR2A
-#define OCR2A2_REG OCR2A
-#define OCR2A3_REG OCR2A
-#define OCR2A4_REG OCR2A
-#define OCR2A5_REG OCR2A
-#define OCR2A6_REG OCR2A
-#define OCR2A7_REG OCR2A
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSART0_REG PRR
-#define PRSPI_REG PRR
-#define PRTIM1_REG PRR
-#define PRLCD_REG PRR
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* PORTG */
-#define PORTG0_REG PORTG
-#define PORTG1_REG PORTG
-#define PORTG2_REG PORTG
-#define PORTG3_REG PORTG
-#define PORTG4_REG PORTG
-#define PORTG5_REG PORTG
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL0_REG UCSR0C
-
-/* USISR */
-#define USICNT0_REG USISR
-#define USICNT1_REG USISR
-#define USICNT2_REG USISR
-#define USICNT3_REG USISR
-#define USIDC_REG USISR
-#define USIPF_REG USISR
-#define USIOIF_REG USISR
-#define USISIF_REG USISR
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* UDR0 */
-#define UDR00_REG UDR0
-#define UDR01_REG UDR0
-#define UDR02_REG UDR0
-#define UDR03_REG UDR0
-#define UDR04_REG UDR0
-#define UDR05_REG UDR0
-#define UDR06_REG UDR0
-#define UDR07_REG UDR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* ASSR */
-#define TCR2UB_REG ASSR
-#define OCR2UB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* DDRG */
-#define DDG0_REG DDRG
-#define DDG1_REG DDRG
-#define DDG2_REG DDRG
-#define DDG3_REG DDRG
-#define DDG4_REG DDRG
-#define DDG5_REG DDRG
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* LCDDR3 */
-#define SEG024_REG LCDDR3
-
-/* LCDDR2 */
-#define SEG016_REG LCDDR2
-#define SEG017_REG LCDDR2
-#define SEG018_REG LCDDR2
-#define SEG019_REG LCDDR2
-#define SEG020_REG LCDDR2
-#define SEG021_REG LCDDR2
-#define SEG022_REG LCDDR2
-#define SEG023_REG LCDDR2
-
-/* LCDDR1 */
-#define SEG008_REG LCDDR1
-#define SEG009_REG LCDDR1
-#define SEG010_REG LCDDR1
-#define SEG011_REG LCDDR1
-#define SEG012_REG LCDDR1
-#define SEG013_REG LCDDR1
-#define SEG014_REG LCDDR1
-#define SEG015_REG LCDDR1
-
-/* LCDDR0 */
-#define SEG000_REG LCDDR0
-#define SEG001_REG LCDDR0
-#define SEG002_REG LCDDR0
-#define SEG003_REG LCDDR0
-#define SEG004_REG LCDDR0
-#define SEG005_REG LCDDR0
-#define SEG006_REG LCDDR0
-#define SEG007_REG LCDDR0
-
-/* LCDDR7 */
-#define SEG116_REG LCDDR7
-#define SEG117_REG LCDDR7
-#define SEG118_REG LCDDR7
-#define SEG119_REG LCDDR7
-#define SEG120_REG LCDDR7
-#define SEG121_REG LCDDR7
-#define SEG122_REG LCDDR7
-#define SEG123_REG LCDDR7
-
-/* LCDDR6 */
-#define SEG108_REG LCDDR6
-#define SEG109_REG LCDDR6
-#define SEG110_REG LCDDR6
-#define SEG111_REG LCDDR6
-#define SEG112_REG LCDDR6
-#define SEG113_REG LCDDR6
-#define SEG114_REG LCDDR6
-#define SEG115_REG LCDDR6
-
-/* LCDDR5 */
-#define SEG100_REG LCDDR5
-#define SEG101_REG LCDDR5
-#define SEG102_REG LCDDR5
-#define SEG103_REG LCDDR5
-#define SEG104_REG LCDDR5
-#define SEG105_REG LCDDR5
-#define SEG106_REG LCDDR5
-#define SEG107_REG LCDDR5
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* LCDDR8 */
-#define SEG124_REG LCDDR8
-
-/* LCDCRA */
-#define LCDBL_REG LCDCRA
-#define LCDCCD_REG LCDCRA
-#define LCDBD_REG LCDCRA
-#define LCDIE_REG LCDCRA
-#define LCDIF_REG LCDCRA
-#define LCDAB_REG LCDCRA
-#define LCDEN_REG LCDCRA
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-#define DDE3_REG DDRE
-#define DDE4_REG DDRE
-#define DDE5_REG DDRE
-#define DDE6_REG DDRE
-#define DDE7_REG DDRE
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TCCR0A */
-#define CS00_REG TCCR0A
-#define CS01_REG TCCR0A
-#define CS02_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-#define WGM00_REG TCCR0A
-#define FOC0A_REG TCCR0A
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* GTCCR */
-#define PSR310_REG GTCCR
-#define TSM_REG GTCCR
-#define PSR2_REG GTCCR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* LCDCRB */
-#define LCDPM0_REG LCDCRB
-#define LCDPM1_REG LCDCRB
-#define LCDPM2_REG LCDCRB
-#define LCDMUX0_REG LCDCRB
-#define LCDMUX1_REG LCDCRB
-#define LCD2B_REG LCDCRB
-#define LCDCS_REG LCDCRB
-
-/* LCDDR18 */
-#define SEG324_REG LCDDR18
-
-/* LCDDR13 */
-#define SEG224_REG LCDDR13
-
-/* LCDDR12 */
-#define SEG216_REG LCDDR12
-#define SEG217_REG LCDDR12
-#define SEG218_REG LCDDR12
-#define SEG219_REG LCDDR12
-#define SEG220_REG LCDDR12
-#define SEG221_REG LCDDR12
-#define SEG222_REG LCDDR12
-#define SEG223_REG LCDDR12
-
-/* LCDDR11 */
-#define SEG208_REG LCDDR11
-#define SEG209_REG LCDDR11
-#define SEG210_REG LCDDR11
-#define SEG211_REG LCDDR11
-#define SEG212_REG LCDDR11
-#define SEG213_REG LCDDR11
-#define SEG214_REG LCDDR11
-#define SEG215_REG LCDDR11
-
-/* LCDDR10 */
-#define SEG200_REG LCDDR10
-#define SEG201_REG LCDDR10
-#define SEG202_REG LCDDR10
-#define SEG203_REG LCDDR10
-#define SEG204_REG LCDDR10
-#define SEG205_REG LCDDR10
-#define SEG206_REG LCDDR10
-#define SEG207_REG LCDDR10
-
-/* LCDDR17 */
-#define SEG316_REG LCDDR17
-#define SEG317_REG LCDDR17
-#define SEG318_REG LCDDR17
-#define SEG319_REG LCDDR17
-#define SEG320_REG LCDDR17
-#define SEG321_REG LCDDR17
-#define SEG322_REG LCDDR17
-#define SEG323_REG LCDDR17
-
-/* LCDDR16 */
-#define SEG308_REG LCDDR16
-#define SEG309_REG LCDDR16
-#define SEG310_REG LCDDR16
-#define SEG311_REG LCDDR16
-#define SEG312_REG LCDDR16
-#define SEG313_REG LCDDR16
-#define SEG314_REG LCDDR16
-#define SEG315_REG LCDDR16
-
-/* LCDDR15 */
-#define SEG300_REG LCDDR15
-#define SEG301_REG LCDDR15
-#define SEG302_REG LCDDR15
-#define SEG303_REG LCDDR15
-#define SEG304_REG LCDDR15
-#define SEG305_REG LCDDR15
-#define SEG306_REG LCDDR15
-#define SEG307_REG LCDDR15
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* MCUSR */
-#define JTRF_REG MCUSR
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TCCR2A */
-#define CS20_REG TCCR2A
-#define CS21_REG TCCR2A
-#define CS22_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-#define WGM20_REG TCCR2A
-#define FOC2A_REG TCCR2A
-
-/* UBRR0H */
-#define UBRR8_REG UBRR0H
-#define UBRR9_REG UBRR0H
-#define UBRR10_REG UBRR0H
-#define UBRR11_REG UBRR0H
-
-/* UBRR0L */
-#define UBRR0_REG UBRR0L
-#define UBRR1_REG UBRR0L
-#define UBRR2_REG UBRR0L
-#define UBRR3_REG UBRR0L
-#define UBRR4_REG UBRR0L
-#define UBRR5_REG UBRR0L
-#define UBRR6_REG UBRR0L
-#define UBRR7_REG UBRR0L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* MCUCR */
-#define JTD_REG MCUCR
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-#define PORTE3_REG PORTE
-#define PORTE4_REG PORTE
-#define PORTE5_REG PORTE
-#define PORTE6_REG PORTE
-#define PORTE7_REG PORTE
-
-/* LCDCCR */
-#define LCDCC0_REG LCDCCR
-#define LCDCC1_REG LCDCCR
-#define LCDCC2_REG LCDCCR
-#define LCDCC3_REG LCDCCR
-#define LCDMDT_REG LCDCCR
-#define LCDDC0_REG LCDCCR
-#define LCDDC1_REG LCDCCR
-#define LCDDC2_REG LCDCCR
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-#define PINE3_REG PINE
-#define PINE4_REG PINE
-#define PINE5_REG PINE
-#define PINE6_REG PINE
-#define PINE7_REG PINE
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ACME_REG ADCSRB
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-
-/* DDRF */
-#define DDF0_REG DDRF
-#define DDF1_REG DDRF
-#define DDF2_REG DDRF
-#define DDF3_REG DDRF
-#define DDF4_REG DDRF
-#define DDF5_REG DDRF
-#define DDF6_REG DDRF
-#define DDF7_REG DDRF
-
-/* OCR0A */
-#define OCR0A0_REG OCR0A
-#define OCR0A1_REG OCR0A
-#define OCR0A2_REG OCR0A
-#define OCR0A3_REG OCR0A
-#define OCR0A4_REG OCR0A
-#define OCR0A5_REG OCR0A
-#define OCR0A6_REG OCR0A
-#define OCR0A7_REG OCR0A
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* USICR */
-#define USITC_REG USICR
-#define USICLK_REG USICR
-#define USICS0_REG USICR
-#define USICS1_REG USICR
-#define USIWM0_REG USICR
-#define USIWM1_REG USICR
-#define USIOIE_REG USICR
-#define USISIE_REG USICR
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* LCDFRR */
-#define LCDCD0_REG LCDFRR
-#define LCDCD1_REG LCDFRR
-#define LCDCD2_REG LCDFRR
-#define LCDPS0_REG LCDFRR
-#define LCDPS1_REG LCDFRR
-#define LCDPS2_REG LCDFRR
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define PCIE0_REG EIMSK
-#define PCIE1_REG EIMSK
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-#define PCINT15_REG PCMSK1
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define PCIF0_REG EIFR
-#define PCIF1_REG EIFR
-
-/* PING */
-#define PING0_REG PING
-#define PING1_REG PING
-#define PING2_REG PING
-#define PING3_REG PING
-#define PING4_REG PING
-#define PING5_REG PING
-
-/* PINF */
-#define PINF0_REG PINF
-#define PINF1_REG PINF
-#define PINF2_REG PINF
-#define PINF3_REG PINF
-#define PINF4_REG PINF
-#define PINF5_REG PINF
-#define PINF6_REG PINF
-#define PINF7_REG PINF
-
-/* PORTF */
-#define PORTF0_REG PORTF
-#define PORTF1_REG PORTF
-#define PORTF2_REG PORTF
-#define PORTF3_REG PORTF
-#define PORTF4_REG PORTF
-#define PORTF5_REG PORTF
-#define PORTF6_REG PORTF
-#define PORTF7_REG PORTF
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-
-/* USIDR */
-#define USIDR0_REG USIDR
-#define USIDR1_REG USIDR
-#define USIDR2_REG USIDR
-#define USIDR3_REG USIDR
-#define USIDR4_REG USIDR
-#define USIDR5_REG USIDR
-#define USIDR6_REG USIDR
-#define USIDR7_REG USIDR
-
-/* pins mapping */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE1A_NUM 1
-#define SIG_OUTPUT_COMPARE1B_NUM 2
-#define SIG_OUTPUT_COMPARE2_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM1A_NUM 1
-#define PWM1B_NUM 2
-#define PWM2_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDTOE_REG WDTCR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* TCCR0 */
-#define CS00_REG TCCR0
-#define CS01_REG TCCR0
-#define CS02_REG TCCR0
-#define WGM01_REG TCCR0
-#define COM00_REG TCCR0
-#define COM01_REG TCCR0
-#define WGM00_REG TCCR0
-#define FOC0_REG TCCR0
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* GICR */
-#define IVCE_REG GICR
-#define IVSEL_REG GICR
-#define INT2_REG GICR
-#define INT0_REG GICR
-#define INT1_REG GICR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define FOC1B_REG TCCR1A
-#define FOC1A_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* GIFR */
-#define INTF2_REG GIFR
-#define INTF0_REG GIFR
-#define INTF1_REG GIFR
-
-/* TIMSK */
-#define TOIE0_REG TIMSK
-#define OCIE0_REG TIMSK
-#define TOIE1_REG TIMSK
-#define OCIE1B_REG TIMSK
-#define OCIE1A_REG TIMSK
-#define TICIE1_REG TIMSK
-#define TOIE2_REG TIMSK
-#define OCIE2_REG TIMSK
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* UCSRA */
-#define MPCM_REG UCSRA
-#define U2X_REG UCSRA
-#define UPE_REG UCSRA
-#define DOR_REG UCSRA
-#define FE_REG UCSRA
-#define UDRE_REG UCSRA
-#define TXC_REG UCSRA
-#define RXC_REG UCSRA
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SFIOR */
-#define PSR10_REG SFIOR
-#define PSR2_REG SFIOR
-#define PUD_REG SFIOR
-#define ACME_REG SFIOR
-#define ADTS0_REG SFIOR
-#define ADTS1_REG SFIOR
-#define ADTS2_REG SFIOR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* UCSRB */
-#define TXB8_REG UCSRB
-#define RXB8_REG UCSRB
-#define UCSZ2_REG UCSRB
-#define TXEN_REG UCSRB
-#define RXEN_REG UCSRB
-#define UDRIE_REG UCSRB
-#define TXCIE_REG UCSRB
-#define RXCIE_REG UCSRB
-
-/* UCSRC */
-#define UCPOL_REG UCSRC
-#define UCSZ0_REG UCSRC
-#define UCSZ1_REG UCSRC
-#define USBS_REG UCSRC
-#define UPM0_REG UCSRC
-#define UPM1_REG UCSRC
-#define UMSEL_REG UCSRC
-#define URSEL_REG UCSRC
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* UDR */
-#define UDR0_REG UDR
-#define UDR1_REG UDR
-#define UDR2_REG UDR
-#define UDR3_REG UDR
-#define UDR4_REG UDR
-#define UDR5_REG UDR
-#define UDR6_REG UDR
-#define UDR7_REG UDR
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* UBRRH */
-#define UBRR8_REG UBRRH
-#define UBRR9_REG UBRRH
-#define UBRR10_REG UBRRH
-#define UBRR11_REG UBRRH
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* UBRRL */
-#define UBRR0_REG UBRRL
-#define UBRR1_REG UBRRL
-#define UBRR2_REG UBRRL
-#define UBRR3_REG UBRRL
-#define UBRR4_REG UBRRL
-#define UBRR5_REG UBRRL
-#define UBRR6_REG UBRRL
-#define UBRR7_REG UBRRL
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* MCUCSR */
-#define ISC2_REG MCUCSR
-#define PORF_REG MCUCSR
-#define EXTRF_REG MCUCSR
-#define BORF_REG MCUCSR
-#define WDRF_REG MCUCSR
-#define JTRF_REG MCUCSR
-#define JTD_REG MCUCSR
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* TCCR2 */
-#define CS20_REG TCCR2
-#define CS21_REG TCCR2
-#define CS22_REG TCCR2
-#define WGM21_REG TCCR2
-#define COM20_REG TCCR2
-#define COM21_REG TCCR2
-#define WGM20_REG TCCR2
-#define FOC2_REG TCCR2
-
-/* TIFR */
-#define TOV0_REG TIFR
-#define OCF0_REG TIFR
-#define TOV1_REG TIFR
-#define OCF1B_REG TIFR
-#define OCF1A_REG TIFR
-#define ICF1_REG TIFR
-#define TOV2_REG TIFR
-#define OCF2_REG TIFR
-
-/* EEARH */
-#define EEAR8_REG EEARH
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* OCR0 */
-#define OCR0_0_REG OCR0
-#define OCR0_1_REG OCR0
-#define OCR0_2_REG OCR0
-#define OCR0_3_REG OCR0
-#define OCR0_4_REG OCR0
-#define OCR0_5_REG OCR0
-#define OCR0_6_REG OCR0
-#define OCR0_7_REG OCR0
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define ISC10_REG MCUCR
-#define ISC11_REG MCUCR
-#define SM0_REG MCUCR
-#define SM1_REG MCUCR
-#define SE_REG MCUCR
-#define SM2_REG MCUCR
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* OCR2 */
-#define OCR2_0_REG OCR2
-#define OCR2_1_REG OCR2
-#define OCR2_2_REG OCR2
-#define OCR2_3_REG OCR2
-#define OCR2_4_REG OCR2
-#define OCR2_5_REG OCR2
-#define OCR2_6_REG OCR2
-#define OCR2_7_REG OCR2
-
-/* ASSR */
-#define TCR2UB_REG ASSR
-#define OCR2UB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-
-/* pins mapping */
-#define ADC0_PORT PORTA
-#define ADC0_BIT 0
-
-#define ADC1_PORT PORTA
-#define ADC1_BIT 1
-
-#define ADC2_PORT PORTA
-#define ADC2_BIT 2
-
-#define ADC3_PORT PORTA
-#define ADC3_BIT 3
-
-#define ADC4_PORT PORTA
-#define ADC4_BIT 4
-
-#define ADc5_PORT PORTA
-#define ADc5_BIT 5
-
-#define ADC6_PORT PORTA
-#define ADC6_BIT 6
-
-#define ADC7_PORT PORTA
-#define ADC7_BIT 7
-
-#define T0_PORT PORTB
-#define T0_BIT 0
-
-#define T1_PORT PORTB
-#define T1_BIT 1
-
-#define AIN0_PORT PORTB
-#define AIN0_BIT 2
-
-#define AIN1_PORT PORTB
-#define AIN1_BIT 3
-
-#define SS_PORT PORTB
-#define SS_BIT 4
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 5
-
-#define MISO_PORT PORTB
-#define MISO_BIT 6
-
-
-#define SCL_PORT PORTC
-#define SCL_BIT 0
-
-#define SDA_PORT PORTC
-#define SDA_BIT 1
-
-#define TMS_PORT PORTC
-#define TMS_BIT 2
-
-
-
-
-#define TOSC1_PORT PORTC
-#define TOSC1_BIT 6
-
-#define TOSC2_PORT PORTC
-#define TOSC2_BIT 7
-
-#define RXD_PORT PORTD
-#define RXD_BIT 0
-
-#define TXD_PORT PORTD
-#define TXD_BIT 1
-
-#define INT0_PORT PORTD
-#define INT0_BIT 2
-
-#define INT1_PORT PORTD
-#define INT1_BIT 3
-
-#define OC1B_PORT PORTD
-#define OC1B_BIT 4
-
-#define OC1A_PORT PORTD
-#define OC1A_BIT 5
-
-#define ICP_PORT PORTD
-#define ICP_BIT 6
-
-#define OC2_PORT PORTD
-#define OC2_BIT 7
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-
-
-/* prescalers timer 1 */
-
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW_TOTAL_NUM 2
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 0
-
-
-/* CADAC2 */
-#define CADAC16_REG CADAC2
-#define CADAC17_REG CADAC2
-#define CADAC18_REG CADAC2
-#define CADAC19_REG CADAC2
-#define CADAC20_REG CADAC2
-#define CADAC21_REG CADAC2
-#define CADAC22_REG CADAC2
-#define CADAC23_REG CADAC2
-
-/* CADAC3 */
-#define CADAC24_REG CADAC3
-#define CADAC25_REG CADAC3
-#define CADAC26_REG CADAC3
-#define CADAC27_REG CADAC3
-#define CADAC28_REG CADAC3
-#define CADAC29_REG CADAC3
-#define CADAC30_REG CADAC3
-#define CADAC31_REG CADAC3
-
-/* CADAC0 */
-#define CADAC00_REG CADAC0
-#define CADAC01_REG CADAC0
-#define CADAC02_REG CADAC0
-#define CADAC03_REG CADAC0
-#define CADAC04_REG CADAC0
-#define CADAC05_REG CADAC0
-#define CADAC06_REG CADAC0
-#define CADAC07_REG CADAC0
-
-/* CADAC1 */
-#define CADAC08_REG CADAC1
-#define CADAC09_REG CADAC1
-#define CADAC10_REG CADAC1
-#define CADAC11_REG CADAC1
-#define CADAC12_REG CADAC1
-#define CADAC13_REG CADAC1
-#define CADAC14_REG CADAC1
-#define CADAC15_REG CADAC1
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-
-/* BPIMSK */
-#define CHCIE_REG BPIMSK
-#define DHCIE_REG BPIMSK
-#define COCIE_REG BPIMSK
-#define DOCIE_REG BPIMSK
-#define SCIE_REG BPIMSK
-
-/* DIDR0 */
-#define PA0DID_REG DIDR0
-#define PA1DID_REG DIDR0
-
-/* TCNT0H */
-#define TCNT0H0_REG TCNT0H
-#define TCNT0H1_REG TCNT0H
-#define TCNT0H2_REG TCNT0H
-#define TCNT0H3_REG TCNT0H
-#define TCNT0H4_REG TCNT0H
-#define TCNT0H5_REG TCNT0H
-#define TCNT0H6_REG TCNT0H
-#define TCNT0H7_REG TCNT0H
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* BPCR */
-#define CHCD_REG BPCR
-#define DHCD_REG BPCR
-#define COCD_REG BPCR
-#define DOCD_REG BPCR
-#define SCD_REG BPCR
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* BPSCTR */
-#define SCPT0_REG BPSCTR
-#define SCPT1_REG BPSCTR
-#define SCPT2_REG BPSCTR
-#define SCPT3_REG BPSCTR
-#define SCPT4_REG BPSCTR
-#define SCPT5_REG BPSCTR
-#define SCPT6_REG BPSCTR
-
-/* MCUCR */
-#define PUD_REG MCUCR
-#define CKOE_REG MCUCR
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define ICS1_REG TCCR1A
-#define ICES1_REG TCCR1A
-#define ICNC1_REG TCCR1A
-#define ICEN1_REG TCCR1A
-#define TCW1_REG TCCR1A
-
-/* BPHCTR */
-#define HCPT0_REG BPHCTR
-#define HCPT1_REG BPHCTR
-#define HCPT2_REG BPHCTR
-#define HCPT3_REG BPHCTR
-#define HCPT4_REG BPHCTR
-#define HCPT5_REG BPHCTR
-
-/* GTCCR */
-#define PSRSYNC_REG GTCCR
-#define TSM_REG GTCCR
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* BGCRR */
-#define BGCR0_REG BGCRR
-#define BGCR1_REG BGCRR
-#define BGCR2_REG BGCRR
-#define BGCR3_REG BGCRR
-#define BGCR4_REG BGCRR
-#define BGCR5_REG BGCRR
-#define BGCR6_REG BGCRR
-#define BGCR7_REG BGCRR
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-
-/* BPCHCD */
-#define CHCDL0_REG BPCHCD
-#define CHCDL1_REG BPCHCD
-#define CHCDL2_REG BPCHCD
-#define CHCDL3_REG BPCHCD
-#define CHCDL4_REG BPCHCD
-#define CHCDL5_REG BPCHCD
-#define CHCDL6_REG BPCHCD
-#define CHCDL7_REG BPCHCD
-
-/* PRR0 */
-#define PRVADC_REG PRR0
-#define PRTIM0_REG PRR0
-#define PRTIM1_REG PRR0
-#define PRSPI_REG PRR0
-#define PRVRM_REG PRR0
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* OCR0A */
-#define OCR0A0_REG OCR0A
-#define OCR0A1_REG OCR0A
-#define OCR0A2_REG OCR0A
-#define OCR0A3_REG OCR0A
-#define OCR0A4_REG OCR0A
-#define OCR0A5_REG OCR0A
-#define OCR0A6_REG OCR0A
-#define OCR0A7_REG OCR0A
-
-/* ROCR */
-#define ROCWIE_REG ROCR
-#define ROCWIF_REG ROCR
-#define ROCS_REG ROCR
-
-/* OCR0B */
-#define OCR0B0_REG OCR0B
-#define OCR0B1_REG OCR0B
-#define OCR0B2_REG OCR0B
-#define OCR0B3_REG OCR0B
-#define OCR0B4_REG OCR0B
-#define OCR0B5_REG OCR0B
-#define OCR0B6_REG OCR0B
-#define OCR0B7_REG OCR0B
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-
-/* CADICH */
-#define CADICH0_REG CADICH
-#define CADICH1_REG CADICH
-#define CADICH2_REG CADICH
-#define CADICH3_REG CADICH
-#define CADICH4_REG CADICH
-#define CADICH5_REG CADICH
-#define CADICH6_REG CADICH
-#define CADICH7_REG CADICH
-
-/* FCSR */
-#define CFE_REG FCSR
-#define DFE_REG FCSR
-#define CPS_REG FCSR
-#define DUVRD_REG FCSR
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* CADCSRB */
-#define CADICIF_REG CADCSRB
-#define CADRCIF_REG CADCSRB
-#define CADACIF_REG CADCSRB
-#define CADICIE_REG CADCSRB
-#define CADRCIE_REG CADCSRB
-#define CADACIE_REG CADCSRB
-
-/* CADICL */
-#define CADICL0_REG CADICL
-#define CADICL1_REG CADICL
-#define CADICL2_REG CADICL
-#define CADICL3_REG CADICL
-#define CADICL4_REG CADICL
-#define CADICL5_REG CADICL
-#define CADICL6_REG CADICL
-#define CADICL7_REG CADICL
-
-/* BPCOCD */
-#define COCDL0_REG BPCOCD
-#define COCDL1_REG BPCOCD
-#define COCDL2_REG BPCOCD
-#define COCDL3_REG BPCOCD
-#define COCDL4_REG BPCOCD
-#define COCDL5_REG BPCOCD
-#define COCDL6_REG BPCOCD
-#define COCDL7_REG BPCOCD
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* BPPLR */
-#define BPPL_REG BPPLR
-#define BPPLE_REG BPPLR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BODRF_REG MCUSR
-#define WDRF_REG MCUSR
-#define OCDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* EEAR */
-#define EEAR0_REG EEAR
-#define EEAR1_REG EEAR
-#define EEAR2_REG EEAR
-#define EEAR3_REG EEAR
-#define EEAR4_REG EEAR
-#define EEAR5_REG EEAR
-#define EEAR6_REG EEAR
-#define EEAR7_REG EEAR
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define RFLB_REG SPMCSR
-#define CTPB_REG SPMCSR
-#define SIGRD_REG SPMCSR
-
-/* CADCSRA */
-#define CADSE_REG CADCSRA
-#define CADSI0_REG CADCSRA
-#define CADSI1_REG CADCSRA
-#define CADAS0_REG CADCSRA
-#define CADAS1_REG CADCSRA
-#define CADUB_REG CADCSRA
-#define CADPOL_REG CADCSRA
-#define CADEN_REG CADCSRA
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-#define ICF0_REG TIFR0
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-
-/* BPSCD */
-#define SCDL0_REG BPSCD
-#define SCDL1_REG BPSCD
-#define SCDL2_REG BPSCD
-#define SCDL3_REG BPSCD
-#define SCDL4_REG BPSCD
-#define SCDL5_REG BPSCD
-#define SCDL6_REG BPSCD
-#define SCDL7_REG BPSCD
-
-/* OSICSR */
-#define OSIEN_REG OSICSR
-#define OSIST_REG OSICSR
-#define OSISEL0_REG OSICSR
-
-/* CADRC */
-#define CADRC0_REG CADRC
-#define CADRC1_REG CADRC
-#define CADRC2_REG CADRC
-#define CADRC3_REG CADRC
-#define CADRC4_REG CADRC
-#define CADRC5_REG CADRC
-#define CADRC6_REG CADRC
-#define CADRC7_REG CADRC
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-#define ICIE0_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-
-/* BGCCR */
-#define BGCC0_REG BGCCR
-#define BGCC1_REG BGCCR
-#define BGCC2_REG BGCCR
-#define BGCC3_REG BGCCR
-#define BGCC4_REG BGCCR
-#define BGCC5_REG BGCCR
-#define BGD_REG BGCCR
-
-/* VADMUX */
-#define VADMUX0_REG VADMUX
-#define VADMUX1_REG VADMUX
-#define VADMUX2_REG VADMUX
-#define VADMUX3_REG VADMUX
-
-/* VADCH */
-#define VADC8_REG VADCH
-#define VADC9_REG VADCH
-#define VADC10_REG VADCH
-#define VADC11_REG VADCH
-
-/* BPIFR */
-#define CHCIF_REG BPIFR
-#define DHCIF_REG BPIFR
-#define COCIF_REG BPIFR
-#define DOCIF_REG BPIFR
-#define SCIF_REG BPIFR
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* BPDHCD */
-#define DHCDL0_REG BPDHCD
-#define DHCDL1_REG BPDHCD
-#define DHCDL2_REG BPDHCD
-#define DHCDL3_REG BPDHCD
-#define DHCDL4_REG BPDHCD
-#define DHCDL5_REG BPDHCD
-#define DHCDL6_REG BPDHCD
-#define DHCDL7_REG BPDHCD
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-#define ISC20_REG EICRA
-#define ISC21_REG EICRA
-
-/* PINC */
-#define PINC0_REG PINC
-
-/* VADCSR */
-#define VADCCIE_REG VADCSR
-#define VADCCIF_REG VADCSR
-#define VADSC_REG VADCSR
-#define VADEN_REG VADCSR
-
-/* FOSCCAL */
-#define FCAL0_REG FOSCCAL
-#define FCAL1_REG FOSCCAL
-#define FCAL2_REG FOSCCAL
-#define FCAL3_REG FOSCCAL
-#define FCAL4_REG FOSCCAL
-#define FCAL5_REG FOSCCAL
-#define FCAL6_REG FOSCCAL
-#define FCAL7_REG FOSCCAL
-
-/* OCR1B */
-#define OCR1B0_REG OCR1B
-#define OCR1B1_REG OCR1B
-#define OCR1B2_REG OCR1B
-#define OCR1B3_REG OCR1B
-#define OCR1B4_REG OCR1B
-#define OCR1B5_REG OCR1B
-#define OCR1B6_REG OCR1B
-#define OCR1B7_REG OCR1B
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define ICS0_REG TCCR0A
-#define ICES0_REG TCCR0A
-#define ICNC0_REG TCCR0A
-#define ICEN0_REG TCCR0A
-#define TCW0_REG TCCR0A
-
-/* OCR1A */
-#define OCR1A0_REG OCR1A
-#define OCR1A1_REG OCR1A
-#define OCR1A2_REG OCR1A
-#define OCR1A3_REG OCR1A
-#define OCR1A4_REG OCR1A
-#define OCR1A5_REG OCR1A
-#define OCR1A6_REG OCR1A
-#define OCR1A7_REG OCR1A
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-
-/* TCNT0L */
-#define TCNT0L0_REG TCNT0L
-#define TCNT0L1_REG TCNT0L
-#define TCNT0L2_REG TCNT0L
-#define TCNT0L3_REG TCNT0L
-#define TCNT0L4_REG TCNT0L
-#define TCNT0L5_REG TCNT0L
-#define TCNT0L6_REG TCNT0L
-#define TCNT0L7_REG TCNT0L
-
-/* BPOCTR */
-#define OCPT0_REG BPOCTR
-#define OCPT1_REG BPOCTR
-#define OCPT2_REG BPOCTR
-#define OCPT3_REG BPOCTR
-#define OCPT4_REG BPOCTR
-#define OCPT5_REG BPOCTR
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-#define INTF2_REG EIFR
-
-/* BPDOCD */
-#define DOCDL0_REG BPDOCD
-#define DOCDL1_REG BPDOCD
-#define DOCDL2_REG BPDOCD
-#define DOCDL3_REG BPDOCD
-#define DOCDL4_REG BPDOCD
-#define DOCDL5_REG BPDOCD
-#define DOCDL6_REG BPDOCD
-#define DOCDL7_REG BPDOCD
-
-/* VADCL */
-#define VADC0_REG VADCL
-#define VADC1_REG VADCL
-#define VADC2_REG VADCL
-#define VADC3_REG VADCL
-#define VADC4_REG VADCL
-#define VADC5_REG VADCL
-#define VADC6_REG VADCL
-#define VADC7_REG VADCL
-
-/* pins mapping */
-
-
-
-
-
-
-
-
-
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 3 */
-#define TIMER3_PRESCALER_DIV_0 0
-#define TIMER3_PRESCALER_DIV_1 1
-#define TIMER3_PRESCALER_DIV_8 2
-#define TIMER3_PRESCALER_DIV_64 3
-#define TIMER3_PRESCALER_DIV_256 4
-#define TIMER3_PRESCALER_DIV_1024 5
-#define TIMER3_PRESCALER_DIV_FALL 6
-#define TIMER3_PRESCALER_DIV_RISE 7
-
-#define TIMER3_PRESCALER_REG_0 0
-#define TIMER3_PRESCALER_REG_1 1
-#define TIMER3_PRESCALER_REG_2 8
-#define TIMER3_PRESCALER_REG_3 64
-#define TIMER3_PRESCALER_REG_4 256
-#define TIMER3_PRESCALER_REG_5 1024
-#define TIMER3_PRESCALER_REG_6 -1
-#define TIMER3_PRESCALER_REG_7 -2
-
-/* prescalers timer 4 */
-
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER1C_AVAILABLE
-#define TIMER3_AVAILABLE
-#define TIMER3A_AVAILABLE
-#define TIMER3B_AVAILABLE
-#define TIMER3C_AVAILABLE
-#define TIMER4_AVAILABLE
-#define TIMER4A_AVAILABLE
-#define TIMER4B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW3_NUM 2
-#define SIG_OVERFLOW4_NUM 3
-#define SIG_OVERFLOW_TOTAL_NUM 4
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE1C_NUM 4
-#define SIG_OUTPUT_COMPARE3A_NUM 5
-#define SIG_OUTPUT_COMPARE3B_NUM 6
-#define SIG_OUTPUT_COMPARE3C_NUM 7
-#define SIG_OUTPUT_COMPARE4_NUM 8
-#define SIG_OUTPUT_COMPARE4A_NUM 9
-#define SIG_OUTPUT_COMPARE4B_NUM 10
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 11
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM1C_NUM 4
-#define PWM3A_NUM 5
-#define PWM3B_NUM 6
-#define PWM3C_NUM 7
-#define PWM4_NUM 8
-#define PWM4A_NUM 9
-#define PWM4B_NUM 10
-#define PWM_TOTAL_NUM 11
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE3_NUM 1
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 2
-
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* UDIEN */
-#define SUSPE_REG UDIEN
-#define SOFE_REG UDIEN
-#define EORSTE_REG UDIEN
-#define WAKEUPE_REG UDIEN
-#define EORSME_REG UDIEN
-#define UPRSME_REG UDIEN
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* OCR0B */
-#define OCR0B_0_REG OCR0B
-#define OCR0B_1_REG OCR0B
-#define OCR0B_2_REG OCR0B
-#define OCR0B_3_REG OCR0B
-#define OCR0B_4_REG OCR0B
-#define OCR0B_5_REG OCR0B
-#define OCR0B_6_REG OCR0B
-#define OCR0B_7_REG OCR0B
-
-/* UDINT */
-#define SUSPI_REG UDINT
-#define SOFI_REG UDINT
-#define EORSTI_REG UDINT
-#define WAKEUPI_REG UDINT
-#define EORSMI_REG UDINT
-#define UPRSMI_REG UDINT
-
-/* UERST */
-#define EPRST0_REG UERST
-#define EPRST1_REG UERST
-#define EPRST2_REG UERST
-#define EPRST3_REG UERST
-#define EPRST4_REG UERST
-#define EPRST5_REG UERST
-#define EPRST6_REG UERST
-
-/* RAMPZ */
-#define RAMPZ0_REG RAMPZ
-
-/* UECFG1X */
-#define ALLOC_REG UECFG1X
-#define EPBK0_REG UECFG1X
-#define EPBK1_REG UECFG1X
-#define EPSIZE0_REG UECFG1X
-#define EPSIZE1_REG UECFG1X
-#define EPSIZE2_REG UECFG1X
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-#define EEAR10_REG EEARH
-#define EEAR11_REG EEARH
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* PORTE */
-#define PORTE2_REG PORTE
-#define PORTE6_REG PORTE
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-#define INT3_REG EIMSK
-#define INT4_REG EIMSK
-#define INT5_REG EIMSK
-#define INT6_REG EIMSK
-#define INT7_REG EIMSK
-
-/* UDR1 */
-#define UDR1_0_REG UDR1
-#define UDR1_1_REG UDR1
-#define UDR1_2_REG UDR1
-#define UDR1_3_REG UDR1
-#define UDR1_4_REG UDR1
-#define UDR1_5_REG UDR1
-#define UDR1_6_REG UDR1
-#define UDR1_7_REG UDR1
-
-/* EICRB */
-#define ISC40_REG EICRB
-#define ISC41_REG EICRB
-#define ISC50_REG EICRB
-#define ISC51_REG EICRB
-#define ISC60_REG EICRB
-#define ISC61_REG EICRB
-#define ISC70_REG EICRB
-#define ISC71_REG EICRB
-
-/* UEDATX */
-#define DAT0_REG UEDATX
-#define DAT1_REG UEDATX
-#define DAT2_REG UEDATX
-#define DAT3_REG UEDATX
-#define DAT4_REG UEDATX
-#define DAT5_REG UEDATX
-#define DAT6_REG UEDATX
-#define DAT7_REG UEDATX
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-#define ISC20_REG EICRA
-#define ISC21_REG EICRA
-#define ISC30_REG EICRA
-#define ISC31_REG EICRA
-
-/* UECFG0X */
-#define EPDIR_REG UECFG0X
-#define EPTYPE0_REG UECFG0X
-#define EPTYPE1_REG UECFG0X
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* DIDR2 */
-#define ADC8D_REG DIDR2
-#define ADC9D_REG DIDR2
-#define ADC10D_REG DIDR2
-#define ADC11D_REG DIDR2
-#define ADC12D_REG DIDR2
-#define ADC13D_REG DIDR2
-
-/* DDRF */
-#define DDF0_REG DDRF
-#define DDF1_REG DDRF
-#define DDF4_REG DDRF
-#define DDF5_REG DDRF
-#define DDF6_REG DDRF
-#define DDF7_REG DDRF
-
-/* CLKSEL1 */
-#define EXCKSEL0_REG CLKSEL1
-#define EXCKSEL1_REG CLKSEL1
-#define EXCKSEL2_REG CLKSEL1
-#define EXCKSEL3_REG CLKSEL1
-#define RCCKSEL0_REG CLKSEL1
-#define RCCKSEL1_REG CLKSEL1
-#define RCCKSEL2_REG CLKSEL1
-#define RCCKSEL3_REG CLKSEL1
-
-/* CLKSEL0 */
-#define CLKS_REG CLKSEL0
-#define EXTE_REG CLKSEL0
-#define RCE_REG CLKSEL0
-#define EXSUT0_REG CLKSEL0
-#define EXSUT1_REG CLKSEL0
-#define RCSUT0_REG CLKSEL0
-#define RCSUT1_REG CLKSEL0
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* UENUM */
-#define UENUM_0_REG UENUM
-#define UENUM_1_REG UENUM
-#define UENUM_2_REG UENUM
-
-/* UBRR1L */
-#define UBRR_0_REG UBRR1L
-#define UBRR_1_REG UBRR1L
-#define UBRR_2_REG UBRR1L
-#define UBRR_3_REG UBRR1L
-#define UBRR_4_REG UBRR1L
-#define UBRR_5_REG UBRR1L
-#define UBRR_6_REG UBRR1L
-#define UBRR_7_REG UBRR1L
-
-/* DDRC */
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* OCR3AL */
-#define OCR3AL0_REG OCR3AL
-#define OCR3AL1_REG OCR3AL
-#define OCR3AL2_REG OCR3AL
-#define OCR3AL3_REG OCR3AL
-#define OCR3AL4_REG OCR3AL
-#define OCR3AL5_REG OCR3AL
-#define OCR3AL6_REG OCR3AL
-#define OCR3AL7_REG OCR3AL
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1C0_REG TCCR1A
-#define COM1C1_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* OCR3AH */
-#define OCR3AH0_REG OCR3AH
-#define OCR3AH1_REG OCR3AH
-#define OCR3AH2_REG OCR3AH
-#define OCR3AH3_REG OCR3AH
-#define OCR3AH4_REG OCR3AH
-#define OCR3AH5_REG OCR3AH
-#define OCR3AH6_REG OCR3AH
-#define OCR3AH7_REG OCR3AH
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* OCR4A */
-#define OCR4A0_REG OCR4A
-#define OCR4A1_REG OCR4A
-#define OCR4A2_REG OCR4A
-#define OCR4A3_REG OCR4A
-#define OCR4A4_REG OCR4A
-#define OCR4A5_REG OCR4A
-#define OCR4A6_REG OCR4A
-#define OCR4A7_REG OCR4A
-
-/* OCR4C */
-#define OCR4C0_REG OCR4C
-#define OCR4C1_REG OCR4C
-#define OCR4C2_REG OCR4C
-#define OCR4C3_REG OCR4C
-#define OCR4C4_REG OCR4C
-#define OCR4C5_REG OCR4C
-#define OCR4C6_REG OCR4C
-#define OCR4C7_REG OCR4C
-
-/* OCR4B */
-#define OCR4B0_REG OCR4B
-#define OCR4B1_REG OCR4B
-#define OCR4B2_REG OCR4B
-#define OCR4B3_REG OCR4B
-#define OCR4B4_REG OCR4B
-#define OCR4B5_REG OCR4B
-#define OCR4B6_REG OCR4B
-#define OCR4B7_REG OCR4B
-
-/* OCR4D */
-#define OCR4D0_REG OCR4D
-#define OCR4D1_REG OCR4D
-#define OCR4D2_REG OCR4D
-#define OCR4D3_REG OCR4D
-#define OCR4D4_REG OCR4D
-#define OCR4D5_REG OCR4D
-#define OCR4D6_REG OCR4D
-#define OCR4D7_REG OCR4D
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* RCCTRL */
-#define RCFREQ_REG RCCTRL
-
-/* UDCON */
-#define DETACH_REG UDCON
-#define RMWKUP_REG UDCON
-#define LSM_REG UDCON
-#define RSTCPU_REG UDCON
-
-/* PCICR */
-#define PCIE0_REG PCICR
-
-/* USBINT */
-#define VBUSTI_REG USBINT
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TCNT4 */
-#define TC40_REG TCNT4
-#define TC41_REG TCNT4
-#define TC42_REG TCNT4
-#define TC43_REG TCNT4
-#define TC44_REG TCNT4
-#define TC45_REG TCNT4
-#define TC46_REG TCNT4
-#define TC47_REG TCNT4
-
-/* TC4H */
-#define TC48_REG TC4H
-#define TC49_REG TC4H
-#define TC410_REG TC4H
-
-/* UHWCON */
-#define UVREGE_REG UHWCON
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* UDMFN */
-#define FNCERR_REG UDMFN
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* TIFR4 */
-#define TOV4_REG TIFR4
-#define OCF4B_REG TIFR4
-#define OCF4A_REG TIFR4
-#define OCF4D_REG TIFR4
-
-/* TIFR3 */
-#define TOV3_REG TIFR3
-#define OCF3A_REG TIFR3
-#define OCF3B_REG TIFR3
-#define OCF3C_REG TIFR3
-#define ICF3_REG TIFR3
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define OCF1C_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* UEBCLX */
-#define BYCT0_REG UEBCLX
-#define BYCT1_REG UEBCLX
-#define BYCT2_REG UEBCLX
-#define BYCT3_REG UEBCLX
-#define BYCT4_REG UEBCLX
-#define BYCT5_REG UEBCLX
-#define BYCT6_REG UEBCLX
-#define BYCT7_REG UEBCLX
-
-/* OCR3CH */
-#define OCR3CH0_REG OCR3CH
-#define OCR3CH1_REG OCR3CH
-#define OCR3CH2_REG OCR3CH
-#define OCR3CH3_REG OCR3CH
-#define OCR3CH4_REG OCR3CH
-#define OCR3CH5_REG OCR3CH
-#define OCR3CH6_REG OCR3CH
-#define OCR3CH7_REG OCR3CH
-
-/* UESTA1X */
-#define CURRBK0_REG UESTA1X
-#define CURRBK1_REG UESTA1X
-#define CTRLDIR_REG UESTA1X
-
-/* OCR3CL */
-#define OCR3CL0_REG OCR3CL
-#define OCR3CL1_REG OCR3CL
-#define OCR3CL2_REG OCR3CL
-#define OCR3CL3_REG OCR3CL
-#define OCR3CL4_REG OCR3CL
-#define OCR3CL5_REG OCR3CL
-#define OCR3CL6_REG OCR3CL
-#define OCR3CL7_REG OCR3CL
-
-/* GTCCR */
-#define PSRSYNC_REG GTCCR
-#define TSM_REG GTCCR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* TCCR3C */
-#define FOC3C_REG TCCR3C
-#define FOC3B_REG TCCR3C
-#define FOC3A_REG TCCR3C
-
-/* TCCR3B */
-#define CS30_REG TCCR3B
-#define CS31_REG TCCR3B
-#define CS32_REG TCCR3B
-#define WGM32_REG TCCR3B
-#define WGM33_REG TCCR3B
-#define ICES3_REG TCCR3B
-#define ICNC3_REG TCCR3B
-
-/* TCCR3A */
-#define WGM30_REG TCCR3A
-#define WGM31_REG TCCR3A
-#define COM3C0_REG TCCR3A
-#define COM3C1_REG TCCR3A
-#define COM3B0_REG TCCR3A
-#define COM3B1_REG TCCR3A
-#define COM3A0_REG TCCR3A
-#define COM3A1_REG TCCR3A
-
-/* UEINTX */
-#define TXINI_REG UEINTX
-#define STALLEDI_REG UEINTX
-#define RXOUTI_REG UEINTX
-#define RXSTPI_REG UEINTX
-#define NAKOUTI_REG UEINTX
-#define RWAL_REG UEINTX
-#define NAKINI_REG UEINTX
-#define FIFOCON_REG UEINTX
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* TCNT3H */
-#define TCNT3H0_REG TCNT3H
-#define TCNT3H1_REG TCNT3H
-#define TCNT3H2_REG TCNT3H
-#define TCNT3H3_REG TCNT3H
-#define TCNT3H4_REG TCNT3H
-#define TCNT3H5_REG TCNT3H
-#define TCNT3H6_REG TCNT3H
-#define TCNT3H7_REG TCNT3H
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* TCNT3L */
-#define TCNT3L0_REG TCNT3L
-#define TCNT3L1_REG TCNT3L
-#define TCNT3L2_REG TCNT3L
-#define TCNT3L3_REG TCNT3L
-#define TCNT3L4_REG TCNT3L
-#define TCNT3L5_REG TCNT3L
-#define TCNT3L6_REG TCNT3L
-#define TCNT3L7_REG TCNT3L
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* USBCON */
-#define VBUSTE_REG USBCON
-#define OTGPADE_REG USBCON
-#define FRZCLK_REG USBCON
-#define USBE_REG USBCON
-
-/* MCUSR */
-#define JTRF_REG MCUSR
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* PCIFR */
-#define PCIF0_REG PCIFR
-
-/* UECONX */
-#define EPEN_REG UECONX
-#define RSTDT_REG UECONX
-#define STALLRQC_REG UECONX
-#define STALLRQ_REG UECONX
-
-/* PLLFRQ */
-#define PDIV0_REG PLLFRQ
-#define PDIV1_REG PLLFRQ
-#define PDIV2_REG PLLFRQ
-#define PDIV3_REG PLLFRQ
-#define PLLTM0_REG PLLFRQ
-#define PLLTM1_REG PLLFRQ
-#define PLLUSB_REG PLLFRQ
-#define PINMUX_REG PLLFRQ
-
-/* UEINT */
-#define EPINT0_REG UEINT
-#define EPINT1_REG UEINT
-#define EPINT2_REG UEINT
-#define EPINT3_REG UEINT
-#define EPINT4_REG UEINT
-#define EPINT5_REG UEINT
-#define EPINT6_REG UEINT
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* MCUCR */
-#define JTD_REG MCUCR
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-
-/* OCR1CL */
-#define OCR1CL0_REG OCR1CL
-#define OCR1CL1_REG OCR1CL
-#define OCR1CL2_REG OCR1CL
-#define OCR1CL3_REG OCR1CL
-#define OCR1CL4_REG OCR1CL
-#define OCR1CL5_REG OCR1CL
-#define OCR1CL6_REG OCR1CL
-#define OCR1CL7_REG OCR1CL
-
-/* OCR1CH */
-#define OCR1CH0_REG OCR1CH
-#define OCR1CH1_REG OCR1CH
-#define OCR1CH2_REG OCR1CH
-#define OCR1CH3_REG OCR1CH
-#define OCR1CH4_REG OCR1CH
-#define OCR1CH5_REG OCR1CH
-#define OCR1CH6_REG OCR1CH
-#define OCR1CH7_REG OCR1CH
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* USBSTA */
-#define VBUS_REG USBSTA
-#define SPEED_REG USBSTA
-
-/* UEIENX */
-#define TXINE_REG UEIENX
-#define STALLEDE_REG UEIENX
-#define RXOUTE_REG UEIENX
-#define RXSTPE_REG UEIENX
-#define NAKOUTE_REG UEIENX
-#define NAKINE_REG UEIENX
-#define FLERRE_REG UEIENX
-
-/* UCSR1B */
-#define TXB81_REG UCSR1B
-#define RXB81_REG UCSR1B
-#define UCSZ12_REG UCSR1B
-#define TXEN1_REG UCSR1B
-#define RXEN1_REG UCSR1B
-#define UDRIE1_REG UCSR1B
-#define TXCIE1_REG UCSR1B
-#define RXCIE1_REG UCSR1B
-
-/* UCSR1C */
-#define UCPOL1_REG UCSR1C
-#define UCSZ10_REG UCSR1C
-#define UCSZ11_REG UCSR1C
-#define USBS1_REG UCSR1C
-#define UPM10_REG UCSR1C
-#define UPM11_REG UCSR1C
-#define UMSEL10_REG UCSR1C
-#define UMSEL11_REG UCSR1C
-
-/* UCSR1A */
-#define MPCM1_REG UCSR1A
-#define U2X1_REG UCSR1A
-#define UPE1_REG UCSR1A
-#define DOR1_REG UCSR1A
-#define FE1_REG UCSR1A
-#define UDRE1_REG UCSR1A
-#define TXC1_REG UCSR1A
-#define RXC1_REG UCSR1A
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* EIND */
-#define EIND0_REG EIND
-
-/* UDFNUML */
-#define FNUM0_REG UDFNUML
-#define FNUM1_REG UDFNUML
-#define FNUM2_REG UDFNUML
-#define FNUM3_REG UDFNUML
-#define FNUM4_REG UDFNUML
-#define FNUM5_REG UDFNUML
-#define FNUM6_REG UDFNUML
-#define FNUM7_REG UDFNUML
-
-/* UDFNUMH */
-#define FNUM8_REG UDFNUMH
-#define FNUM9_REG UDFNUMH
-#define FNUM10_REG UDFNUMH
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ADTS3_REG ADCSRB
-#define MUX5_REG ADCSRB
-#define ADHSM_REG ADCSRB
-#define ACME_REG ADCSRB
-
-/* PRR0 */
-#define PRADC_REG PRR0
-#define PRUSART0_REG PRR0
-#define PRSPI_REG PRR0
-#define PRTIM1_REG PRR0
-#define PRTIM0_REG PRR0
-#define PRTIM2_REG PRR0
-#define PRTWI_REG PRR0
-
-/* UBRR1H */
-#define UBRR_8_REG UBRR1H
-#define UBRR_9_REG UBRR1H
-#define UBRR_10_REG UBRR1H
-#define UBRR_11_REG UBRR1H
-
-/* OCR0A */
-#define OCROA_0_REG OCR0A
-#define OCROA_1_REG OCR0A
-#define OCROA_2_REG OCR0A
-#define OCROA_3_REG OCR0A
-#define OCROA_4_REG OCR0A
-#define OCROA_5_REG OCR0A
-#define OCROA_6_REG OCR0A
-#define OCROA_7_REG OCR0A
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* PORTF */
-#define PORTF0_REG PORTF
-#define PORTF1_REG PORTF
-#define PORTF4_REG PORTF
-#define PORTF5_REG PORTF
-#define PORTF6_REG PORTF
-#define PORTF7_REG PORTF
-
-/* TCCR1C */
-#define FOC1C_REG TCCR1C
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* ICR3H */
-#define ICR3H0_REG ICR3H
-#define ICR3H1_REG ICR3H
-#define ICR3H2_REG ICR3H
-#define ICR3H3_REG ICR3H
-#define ICR3H4_REG ICR3H
-#define ICR3H5_REG ICR3H
-#define ICR3H6_REG ICR3H
-#define ICR3H7_REG ICR3H
-
-/* DDRE */
-#define DDE2_REG DDRE
-#define DDE6_REG DDRE
-
-/* UDADDR */
-#define UADD0_REG UDADDR
-#define UADD1_REG UDADDR
-#define UADD2_REG UDADDR
-#define UADD3_REG UDADDR
-#define UADD4_REG UDADDR
-#define UADD5_REG UDADDR
-#define UADD6_REG UDADDR
-#define ADDEN_REG UDADDR
-
-/* ICR3L */
-#define ICR3L0_REG ICR3L
-#define ICR3L1_REG ICR3L
-#define ICR3L2_REG ICR3L
-#define ICR3L3_REG ICR3L
-#define ICR3L4_REG ICR3L
-#define ICR3L5_REG ICR3L
-#define ICR3L6_REG ICR3L
-#define ICR3L7_REG ICR3L
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define SIGRD_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* UESTA0X */
-#define NBUSYBK0_REG UESTA0X
-#define NBUSYBK1_REG UESTA0X
-#define DTSEQ0_REG UESTA0X
-#define DTSEQ1_REG UESTA0X
-#define UNDERFI_REG UESTA0X
-#define OVERFI_REG UESTA0X
-#define CFGOK_REG UESTA0X
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* OCR3BL */
-#define OCR3BL0_REG OCR3BL
-#define OCR3BL1_REG OCR3BL
-#define OCR3BL2_REG OCR3BL
-#define OCR3BL3_REG OCR3BL
-#define OCR3BL4_REG OCR3BL
-#define OCR3BL5_REG OCR3BL
-#define OCR3BL6_REG OCR3BL
-#define OCR3BL7_REG OCR3BL
-
-/* OCR3BH */
-#define OCR3BH0_REG OCR3BH
-#define OCR3BH1_REG OCR3BH
-#define OCR3BH2_REG OCR3BH
-#define OCR3BH3_REG OCR3BH
-#define OCR3BH4_REG OCR3BH
-#define OCR3BH5_REG OCR3BH
-#define OCR3BH6_REG OCR3BH
-#define OCR3BH7_REG OCR3BH
-
-/* TIMSK3 */
-#define TOIE3_REG TIMSK3
-#define OCIE3A_REG TIMSK3
-#define OCIE3B_REG TIMSK3
-#define OCIE3C_REG TIMSK3
-#define ICIE3_REG TIMSK3
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define OCIE1C_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* CLKSTA */
-#define EXTON_REG CLKSTA
-#define RCON_REG CLKSTA
-
-/* TIMSK4 */
-#define TOIE4_REG TIMSK4
-#define OCIE4B_REG TIMSK4
-#define OCIE4A_REG TIMSK4
-#define OCIE4D_REG TIMSK4
-
-/* TCCR4B */
-#define CS40_REG TCCR4B
-#define CS41_REG TCCR4B
-#define CS42_REG TCCR4B
-#define CS43_REG TCCR4B
-#define DTPS40_REG TCCR4B
-#define DTPS41_REG TCCR4B
-#define PSR4_REG TCCR4B
-#define PWM4X_REG TCCR4B
-
-/* TCCR4C */
-#define PWM4D_REG TCCR4C
-#define FOC4D_REG TCCR4C
-#define COM4D0_REG TCCR4C
-#define COM4D1_REG TCCR4C
-#define COM4B0S_REG TCCR4C
-#define COM4B1S_REG TCCR4C
-#define COM4A0S_REG TCCR4C
-#define COM4A1S_REG TCCR4C
-
-/* PLLCSR */
-#define PLOCK_REG PLLCSR
-#define PLLE_REG PLLCSR
-#define PINDIV_REG PLLCSR
-
-/* TCCR4A */
-#define PWM4B_REG TCCR4A
-#define PWM4A_REG TCCR4A
-#define FOC4B_REG TCCR4A
-#define FOC4A_REG TCCR4A
-#define COM4B0_REG TCCR4A
-#define COM4B1_REG TCCR4A
-#define COM4A0_REG TCCR4A
-#define COM4A1_REG TCCR4A
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* TCCR4D */
-#define WGM40_REG TCCR4D
-#define WGM41_REG TCCR4D
-#define FPF4_REG TCCR4D
-#define FPAC4_REG TCCR4D
-#define FPES4_REG TCCR4D
-#define FPNC4_REG TCCR4D
-#define FPEN4_REG TCCR4D
-#define FPIE4_REG TCCR4D
-
-/* TCCR4E */
-#define OC4OE0_REG TCCR4E
-#define OC4OE1_REG TCCR4E
-#define OC4OE2_REG TCCR4E
-#define OC4OE3_REG TCCR4E
-#define OC4OE4_REG TCCR4E
-#define OC4OE5_REG TCCR4E
-#define ENHC4_REG TCCR4E
-#define TLOCK4_REG TCCR4E
-
-/* PINC */
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-#define INTF2_REG EIFR
-#define INTF3_REG EIFR
-#define INTF4_REG EIFR
-#define INTF5_REG EIFR
-#define INTF6_REG EIFR
-#define INTF7_REG EIFR
-
-/* PINF */
-#define PINF0_REG PINF
-#define PINF1_REG PINF
-#define PINF4_REG PINF
-#define PINF5_REG PINF
-#define PINF6_REG PINF
-#define PINF7_REG PINF
-
-/* PINE */
-#define PINE2_REG PINE
-#define PINE6_REG PINE
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* PRR1 */
-#define PRUSART1_REG PRR1
-#define PRTIM3_REG PRR1
-#define PRUSB_REG PRR1
-
-/* DT4 */
-#define DT4L0_REG DT4
-#define DT4L1_REG DT4
-#define DT4L2_REG DT4
-#define DT4L3_REG DT4
-#define DT4L4_REG DT4
-#define DT4L5_REG DT4
-#define DT4L6_REG DT4
-#define DT4L7_REG DT4
-
-/* pins mapping */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-/* prescalers timer 3 */
-#define TIMER3_PRESCALER_DIV_0 0
-#define TIMER3_PRESCALER_DIV_1 1
-#define TIMER3_PRESCALER_DIV_8 2
-#define TIMER3_PRESCALER_DIV_64 3
-#define TIMER3_PRESCALER_DIV_256 4
-#define TIMER3_PRESCALER_DIV_1024 5
-#define TIMER3_PRESCALER_DIV_FALL 6
-#define TIMER3_PRESCALER_DIV_RISE 7
-
-#define TIMER3_PRESCALER_REG_0 0
-#define TIMER3_PRESCALER_REG_1 1
-#define TIMER3_PRESCALER_REG_2 8
-#define TIMER3_PRESCALER_REG_3 64
-#define TIMER3_PRESCALER_REG_4 256
-#define TIMER3_PRESCALER_REG_5 1024
-#define TIMER3_PRESCALER_REG_6 -1
-#define TIMER3_PRESCALER_REG_7 -2
-
-/* prescalers timer 4 */
-#define TIMER4_PRESCALER_DIV_0 0
-#define TIMER4_PRESCALER_DIV_1 1
-#define TIMER4_PRESCALER_DIV_8 2
-#define TIMER4_PRESCALER_DIV_64 3
-#define TIMER4_PRESCALER_DIV_256 4
-#define TIMER4_PRESCALER_DIV_1024 5
-#define TIMER4_PRESCALER_DIV_FALL 6
-#define TIMER4_PRESCALER_DIV_RISE 7
-
-#define TIMER4_PRESCALER_REG_0 0
-#define TIMER4_PRESCALER_REG_1 1
-#define TIMER4_PRESCALER_REG_2 8
-#define TIMER4_PRESCALER_REG_3 64
-#define TIMER4_PRESCALER_REG_4 256
-#define TIMER4_PRESCALER_REG_5 1024
-#define TIMER4_PRESCALER_REG_6 -1
-#define TIMER4_PRESCALER_REG_7 -2
-
-/* prescalers timer 5 */
-#define TIMER5_PRESCALER_DIV_0 0
-#define TIMER5_PRESCALER_DIV_1 1
-#define TIMER5_PRESCALER_DIV_8 2
-#define TIMER5_PRESCALER_DIV_64 3
-#define TIMER5_PRESCALER_DIV_256 4
-#define TIMER5_PRESCALER_DIV_1024 5
-#define TIMER5_PRESCALER_DIV_FALL 6
-#define TIMER5_PRESCALER_DIV_RISE 7
-
-#define TIMER5_PRESCALER_REG_0 0
-#define TIMER5_PRESCALER_REG_1 1
-#define TIMER5_PRESCALER_REG_2 8
-#define TIMER5_PRESCALER_REG_3 64
-#define TIMER5_PRESCALER_REG_4 256
-#define TIMER5_PRESCALER_REG_5 1024
-#define TIMER5_PRESCALER_REG_6 -1
-#define TIMER5_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER1C_AVAILABLE
-#define TIMER2_AVAILABLE
-#define TIMER2A_AVAILABLE
-#define TIMER2B_AVAILABLE
-#define TIMER3_AVAILABLE
-#define TIMER3A_AVAILABLE
-#define TIMER3B_AVAILABLE
-#define TIMER3C_AVAILABLE
-#define TIMER4_AVAILABLE
-#define TIMER4A_AVAILABLE
-#define TIMER4B_AVAILABLE
-#define TIMER4C_AVAILABLE
-#define TIMER5_AVAILABLE
-#define TIMER5A_AVAILABLE
-#define TIMER5B_AVAILABLE
-#define TIMER5C_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW3_NUM 3
-#define SIG_OVERFLOW4_NUM 4
-#define SIG_OVERFLOW5_NUM 5
-#define SIG_OVERFLOW_TOTAL_NUM 6
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE1C_NUM 4
-#define SIG_OUTPUT_COMPARE2A_NUM 5
-#define SIG_OUTPUT_COMPARE2B_NUM 6
-#define SIG_OUTPUT_COMPARE3A_NUM 7
-#define SIG_OUTPUT_COMPARE3B_NUM 8
-#define SIG_OUTPUT_COMPARE3C_NUM 9
-#define SIG_OUTPUT_COMPARE4A_NUM 10
-#define SIG_OUTPUT_COMPARE4B_NUM 11
-#define SIG_OUTPUT_COMPARE4C_NUM 12
-#define SIG_OUTPUT_COMPARE5A_NUM 13
-#define SIG_OUTPUT_COMPARE5B_NUM 14
-#define SIG_OUTPUT_COMPARE5C_NUM 15
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 16
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM1C_NUM 4
-#define PWM2A_NUM 5
-#define PWM2B_NUM 6
-#define PWM3A_NUM 7
-#define PWM3B_NUM 8
-#define PWM3C_NUM 9
-#define PWM4A_NUM 10
-#define PWM4B_NUM 11
-#define PWM4C_NUM 12
-#define PWM5A_NUM 13
-#define PWM5B_NUM 14
-#define PWM5C_NUM 15
-#define PWM_TOTAL_NUM 16
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE3_NUM 1
-#define SIG_INPUT_CAPTURE4_NUM 2
-#define SIG_INPUT_CAPTURE5_NUM 3
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 4
-
-
-/* UBRR3H */
-/* #define UBRR8_REG UBRR3H */ /* dup in UBRR2H, UBRR0H */
-/* #define UBRR9_REG UBRR3H */ /* dup in UBRR2H, UBRR0H */
-/* #define UBRR10_REG UBRR3H */ /* dup in UBRR2H, UBRR0H */
-/* #define UBRR11_REG UBRR3H */ /* dup in UBRR2H, UBRR0H */
-
-/* UBRR3L */
-/* #define UBRR0_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */
-/* #define UBRR1_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */
-/* #define UBRR2_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */
-/* #define UBRR3_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */
-/* #define UBRR4_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */
-/* #define UBRR5_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */
-/* #define UBRR6_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */
-/* #define UBRR7_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */
-
-/* OCR0A */
-#define OCROA_0_REG OCR0A
-#define OCROA_1_REG OCR0A
-#define OCROA_2_REG OCR0A
-#define OCROA_3_REG OCR0A
-#define OCROA_4_REG OCR0A
-#define OCROA_5_REG OCR0A
-#define OCROA_6_REG OCR0A
-#define OCROA_7_REG OCR0A
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* UCSR3A */
-#define MPCM3_REG UCSR3A
-#define U2X3_REG UCSR3A
-#define UPE3_REG UCSR3A
-#define DOR3_REG UCSR3A
-#define FE3_REG UCSR3A
-#define UDRE3_REG UCSR3A
-#define TXC3_REG UCSR3A
-#define RXC3_REG UCSR3A
-
-/* UCSR3B */
-#define TXB83_REG UCSR3B
-#define RXB83_REG UCSR3B
-#define UCSZ32_REG UCSR3B
-#define TXEN3_REG UCSR3B
-#define RXEN3_REG UCSR3B
-#define UDRIE3_REG UCSR3B
-#define TXCIE3_REG UCSR3B
-#define RXCIE3_REG UCSR3B
-
-/* UCSR3C */
-#define UCPOL3_REG UCSR3C
-#define UCSZ30_REG UCSR3C
-#define UCSZ31_REG UCSR3C
-#define USBS3_REG UCSR3C
-#define UPM30_REG UCSR3C
-#define UPM31_REG UCSR3C
-#define UMSEL30_REG UCSR3C
-#define UMSEL31_REG UCSR3C
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* RAMPZ */
-#define RAMPZ0_REG RAMPZ
-#define RAMPZ1_REG RAMPZ
-
-/* OCR2B */
-#define OCR2B_0_REG OCR2B
-#define OCR2B_1_REG OCR2B
-#define OCR2B_2_REG OCR2B
-#define OCR2B_3_REG OCR2B
-#define OCR2B_4_REG OCR2B
-#define OCR2B_5_REG OCR2B
-#define OCR2B_6_REG OCR2B
-#define OCR2B_7_REG OCR2B
-
-/* OCR2A */
-#define OCR2A_0_REG OCR2A
-#define OCR2A_1_REG OCR2A
-#define OCR2A_2_REG OCR2A
-#define OCR2A_3_REG OCR2A
-#define OCR2A_4_REG OCR2A
-#define OCR2A_5_REG OCR2A
-#define OCR2A_6_REG OCR2A
-#define OCR2A_7_REG OCR2A
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-#define EEAR10_REG EEARH
-#define EEAR11_REG EEARH
-
-/* PORTL */
-#define PORTL0_REG PORTL
-#define PORTL1_REG PORTL
-#define PORTL2_REG PORTL
-#define PORTL3_REG PORTL
-#define PORTL4_REG PORTL
-#define PORTL5_REG PORTL
-#define PORTL6_REG PORTL
-#define PORTL7_REG PORTL
-
-/* PORTJ */
-#define PORTJ0_REG PORTJ
-#define PORTJ1_REG PORTJ
-#define PORTJ2_REG PORTJ
-#define PORTJ3_REG PORTJ
-#define PORTJ4_REG PORTJ
-#define PORTJ5_REG PORTJ
-#define PORTJ6_REG PORTJ
-#define PORTJ7_REG PORTJ
-
-/* PORTK */
-#define PORTK0_REG PORTK
-#define PORTK1_REG PORTK
-#define PORTK2_REG PORTK
-#define PORTK3_REG PORTK
-#define PORTK4_REG PORTK
-#define PORTK5_REG PORTK
-#define PORTK6_REG PORTK
-#define PORTK7_REG PORTK
-
-/* PORTH */
-#define PORTH0_REG PORTH
-#define PORTH1_REG PORTH
-#define PORTH2_REG PORTH
-#define PORTH3_REG PORTH
-#define PORTH4_REG PORTH
-#define PORTH5_REG PORTH
-#define PORTH6_REG PORTH
-#define PORTH7_REG PORTH
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* PORTG */
-#define PORTG0_REG PORTG
-#define PORTG1_REG PORTG
-#define PORTG2_REG PORTG
-#define PORTG3_REG PORTG
-#define PORTG4_REG PORTG
-#define PORTG5_REG PORTG
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL00_REG UCSR0C
-#define UMSEL01_REG UCSR0C
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-#define INT3_REG EIMSK
-#define INT4_REG EIMSK
-#define INT5_REG EIMSK
-#define INT6_REG EIMSK
-#define INT7_REG EIMSK
-
-/* UDR1 */
-#define UDR1_0_REG UDR1
-#define UDR1_1_REG UDR1
-#define UDR1_2_REG UDR1
-#define UDR1_3_REG UDR1
-#define UDR1_4_REG UDR1
-#define UDR1_5_REG UDR1
-#define UDR1_6_REG UDR1
-#define UDR1_7_REG UDR1
-
-/* UDR0 */
-#define UDR0_0_REG UDR0
-#define UDR0_1_REG UDR0
-#define UDR0_2_REG UDR0
-#define UDR0_3_REG UDR0
-#define UDR0_4_REG UDR0
-#define UDR0_5_REG UDR0
-#define UDR0_6_REG UDR0
-#define UDR0_7_REG UDR0
-
-/* UDR3 */
-#define UDR3_0_REG UDR3
-#define UDR3_1_REG UDR3
-#define UDR3_2_REG UDR3
-#define UDR3_3_REG UDR3
-#define UDR3_4_REG UDR3
-#define UDR3_5_REG UDR3
-#define UDR3_6_REG UDR3
-#define UDR3_7_REG UDR3
-
-/* UDR2 */
-#define UDR2_0_REG UDR2
-#define UDR2_1_REG UDR2
-#define UDR2_2_REG UDR2
-#define UDR2_3_REG UDR2
-#define UDR2_4_REG UDR2
-#define UDR2_5_REG UDR2
-#define UDR2_6_REG UDR2
-#define UDR2_7_REG UDR2
-
-/* EICRB */
-#define ISC40_REG EICRB
-#define ISC41_REG EICRB
-#define ISC50_REG EICRB
-#define ISC51_REG EICRB
-#define ISC60_REG EICRB
-#define ISC61_REG EICRB
-#define ISC70_REG EICRB
-#define ISC71_REG EICRB
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-#define ISC20_REG EICRA
-#define ISC21_REG EICRA
-#define ISC30_REG EICRA
-#define ISC31_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* DIDR2 */
-#define ADC8D_REG DIDR2
-#define ADC9D_REG DIDR2
-#define ADC10D_REG DIDR2
-#define ADC11D_REG DIDR2
-#define ADC12D_REG DIDR2
-#define ADC13D_REG DIDR2
-#define ADC14D_REG DIDR2
-#define ADC15D_REG DIDR2
-
-/* DDRF */
-#define DDF0_REG DDRF
-#define DDF1_REG DDRF
-#define DDF2_REG DDRF
-#define DDF3_REG DDRF
-#define DDF4_REG DDRF
-#define DDF5_REG DDRF
-#define DDF6_REG DDRF
-#define DDF7_REG DDRF
-
-/* ASSR */
-#define TCR2BUB_REG ASSR
-#define TCR2AUB_REG ASSR
-#define OCR2BUB_REG ASSR
-#define OCR2AUB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* OCR0B */
-#define OCR0B_0_REG OCR0B
-#define OCR0B_1_REG OCR0B
-#define OCR0B_2_REG OCR0B
-#define OCR0B_3_REG OCR0B
-#define OCR0B_4_REG OCR0B
-#define OCR0B_5_REG OCR0B
-#define OCR0B_6_REG OCR0B
-#define OCR0B_7_REG OCR0B
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRJ */
-#define DDJ0_REG DDRJ
-#define DDJ1_REG DDRJ
-#define DDJ2_REG DDRJ
-#define DDJ3_REG DDRJ
-#define DDJ4_REG DDRJ
-#define DDJ5_REG DDRJ
-#define DDJ6_REG DDRJ
-#define DDJ7_REG DDRJ
-
-/* DDRK */
-#define DDK0_REG DDRK
-#define DDK1_REG DDRK
-#define DDK2_REG DDRK
-#define DDK3_REG DDRK
-#define DDK4_REG DDRK
-#define DDK5_REG DDRK
-#define DDK6_REG DDRK
-#define DDK7_REG DDRK
-
-/* DDRH */
-#define DDH0_REG DDRH
-#define DDH1_REG DDRH
-#define DDH2_REG DDRH
-#define DDH3_REG DDRH
-#define DDH4_REG DDRH
-#define DDH5_REG DDRH
-#define DDH6_REG DDRH
-#define DDH7_REG DDRH
-
-/* DDRL */
-#define DDL0_REG DDRL
-#define DDL1_REG DDRL
-#define DDL2_REG DDRL
-#define DDL3_REG DDRL
-#define DDL4_REG DDRL
-#define DDL5_REG DDRL
-#define DDL6_REG DDRL
-#define DDL7_REG DDRL
-
-/* UBRR1L */
-#define UBRR_0_REG UBRR1L
-#define UBRR_1_REG UBRR1L
-#define UBRR_2_REG UBRR1L
-#define UBRR_3_REG UBRR1L
-#define UBRR_4_REG UBRR1L
-#define UBRR_5_REG UBRR1L
-#define UBRR_6_REG UBRR1L
-#define UBRR_7_REG UBRR1L
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* OCR3AL */
-#define OCR3AL0_REG OCR3AL
-#define OCR3AL1_REG OCR3AL
-#define OCR3AL2_REG OCR3AL
-#define OCR3AL3_REG OCR3AL
-#define OCR3AL4_REG OCR3AL
-#define OCR3AL5_REG OCR3AL
-#define OCR3AL6_REG OCR3AL
-#define OCR3AL7_REG OCR3AL
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* UBRR1H */
-#define UBRR_8_REG UBRR1H
-#define UBRR_9_REG UBRR1H
-#define UBRR_10_REG UBRR1H
-#define UBRR_11_REG UBRR1H
-
-/* DDRG */
-#define DDG0_REG DDRG
-#define DDG1_REG DDRG
-#define DDG2_REG DDRG
-#define DDG3_REG DDRG
-#define DDG4_REG DDRG
-#define DDG5_REG DDRG
-
-/* OCR3AH */
-#define OCR3AH0_REG OCR3AH
-#define OCR3AH1_REG OCR3AH
-#define OCR3AH2_REG OCR3AH
-#define OCR3AH3_REG OCR3AH
-#define OCR3AH4_REG OCR3AH
-#define OCR3AH5_REG OCR3AH
-#define OCR3AH6_REG OCR3AH
-#define OCR3AH7_REG OCR3AH
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* TCNT5H */
-#define TCNT5H0_REG TCNT5H
-#define TCNT5H1_REG TCNT5H
-#define TCNT5H2_REG TCNT5H
-#define TCNT5H3_REG TCNT5H
-#define TCNT5H4_REG TCNT5H
-#define TCNT5H5_REG TCNT5H
-#define TCNT5H6_REG TCNT5H
-#define TCNT5H7_REG TCNT5H
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* TCNT5L */
-#define TCNT5L0_REG TCNT5L
-#define TCNT5L1_REG TCNT5L
-#define TCNT5L2_REG TCNT5L
-#define TCNT5L3_REG TCNT5L
-#define TCNT5L4_REG TCNT5L
-#define TCNT5L5_REG TCNT5L
-#define TCNT5L6_REG TCNT5L
-#define TCNT5L7_REG TCNT5L
-
-/* UBRR2H */
-/* #define UBRR8_REG UBRR2H */ /* dup in UBRR3H, UBRR0H */
-/* #define UBRR9_REG UBRR2H */ /* dup in UBRR3H, UBRR0H */
-/* #define UBRR10_REG UBRR2H */ /* dup in UBRR3H, UBRR0H */
-/* #define UBRR11_REG UBRR2H */ /* dup in UBRR3H, UBRR0H */
-
-/* UBRR2L */
-/* #define UBRR0_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */
-/* #define UBRR1_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */
-/* #define UBRR2_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */
-/* #define UBRR3_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */
-/* #define UBRR4_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */
-/* #define UBRR5_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */
-/* #define UBRR6_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */
-/* #define UBRR7_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */
-
-/* PCICR */
-#define PCIE0_REG PCICR
-#define PCIE1_REG PCICR
-#define PCIE2_REG PCICR
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* UCSR2B */
-#define TXB82_REG UCSR2B
-#define RXB82_REG UCSR2B
-#define UCSZ22_REG UCSR2B
-#define TXEN2_REG UCSR2B
-#define RXEN2_REG UCSR2B
-#define UDRIE2_REG UCSR2B
-#define TXCIE2_REG UCSR2B
-#define RXCIE2_REG UCSR2B
-
-/* UCSR2A */
-#define MPCM2_REG UCSR2A
-#define U2X2_REG UCSR2A
-#define UPE2_REG UCSR2A
-#define DOR2_REG UCSR2A
-#define FE2_REG UCSR2A
-#define UDRE2_REG UCSR2A
-#define TXC2_REG UCSR2A
-#define RXC2_REG UCSR2A
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* UCSR2C */
-#define UCPOL2_REG UCSR2C
-#define UCSZ20_REG UCSR2C
-#define UCSZ21_REG UCSR2C
-#define USBS2_REG UCSR2C
-#define UPM20_REG UCSR2C
-#define UPM21_REG UCSR2C
-#define UMSEL20_REG UCSR2C
-#define UMSEL21_REG UCSR2C
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TIFR4 */
-#define TOV4_REG TIFR4
-#define OCF4A_REG TIFR4
-#define OCF4B_REG TIFR4
-#define OCF4C_REG TIFR4
-#define ICF4_REG TIFR4
-
-/* TIFR5 */
-#define TOV5_REG TIFR5
-#define OCF5A_REG TIFR5
-#define OCF5B_REG TIFR5
-#define OCF5C_REG TIFR5
-#define ICF5_REG TIFR5
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-#define OCF2B_REG TIFR2
-
-/* TIFR3 */
-#define TOV3_REG TIFR3
-#define OCF3A_REG TIFR3
-#define OCF3B_REG TIFR3
-#define OCF3C_REG TIFR3
-#define ICF3_REG TIFR3
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define OCF1C_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* OCR4AH */
-#define OCR4AH0_REG OCR4AH
-#define OCR4AH1_REG OCR4AH
-#define OCR4AH2_REG OCR4AH
-#define OCR4AH3_REG OCR4AH
-#define OCR4AH4_REG OCR4AH
-#define OCR4AH5_REG OCR4AH
-#define OCR4AH6_REG OCR4AH
-#define OCR4AH7_REG OCR4AH
-
-/* OCR5CH */
-#define OCR5CH0_REG OCR5CH
-#define OCR5CH1_REG OCR5CH
-#define OCR5CH2_REG OCR5CH
-#define OCR5CH3_REG OCR5CH
-#define OCR5CH4_REG OCR5CH
-#define OCR5CH5_REG OCR5CH
-#define OCR5CH6_REG OCR5CH
-#define OCR5CH7_REG OCR5CH
-
-/* OCR4AL */
-#define OCR4AL0_REG OCR4AL
-#define OCR4AL1_REG OCR4AL
-#define OCR4AL2_REG OCR4AL
-#define OCR4AL3_REG OCR4AL
-#define OCR4AL4_REG OCR4AL
-#define OCR4AL5_REG OCR4AL
-#define OCR4AL6_REG OCR4AL
-#define OCR4AL7_REG OCR4AL
-
-/* OCR5CL */
-#define OCR5CL0_REG OCR5CL
-#define OCR5CL1_REG OCR5CL
-#define OCR5CL2_REG OCR5CL
-#define OCR5CL3_REG OCR5CL
-#define OCR5CL4_REG OCR5CL
-#define OCR5CL5_REG OCR5CL
-#define OCR5CL6_REG OCR5CL
-#define OCR5CL7_REG OCR5CL
-
-/* OCR3CH */
-#define OCR3CH0_REG OCR3CH
-#define OCR3CH1_REG OCR3CH
-#define OCR3CH2_REG OCR3CH
-#define OCR3CH3_REG OCR3CH
-#define OCR3CH4_REG OCR3CH
-#define OCR3CH5_REG OCR3CH
-#define OCR3CH6_REG OCR3CH
-#define OCR3CH7_REG OCR3CH
-
-/* OCR3CL */
-#define OCR3CL0_REG OCR3CL
-#define OCR3CL1_REG OCR3CL
-#define OCR3CL2_REG OCR3CL
-#define OCR3CL3_REG OCR3CL
-#define OCR3CL4_REG OCR3CL
-#define OCR3CL5_REG OCR3CL
-#define OCR3CL6_REG OCR3CL
-#define OCR3CL7_REG OCR3CL
-
-/* GTCCR */
-#define PSRSYNC_REG GTCCR
-#define TSM_REG GTCCR
-#define PSRASY_REG GTCCR
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* TCCR3C */
-#define FOC3C_REG TCCR3C
-#define FOC3B_REG TCCR3C
-#define FOC3A_REG TCCR3C
-
-/* TCCR3B */
-#define CS30_REG TCCR3B
-#define CS31_REG TCCR3B
-#define CS32_REG TCCR3B
-#define WGM32_REG TCCR3B
-#define WGM33_REG TCCR3B
-#define ICES3_REG TCCR3B
-#define ICNC3_REG TCCR3B
-
-/* TCCR3A */
-#define WGM30_REG TCCR3A
-#define WGM31_REG TCCR3A
-#define COM3C0_REG TCCR3A
-#define COM3C1_REG TCCR3A
-#define COM3B0_REG TCCR3A
-#define COM3B1_REG TCCR3A
-#define COM3A0_REG TCCR3A
-#define COM3A1_REG TCCR3A
-
-/* PORTF */
-#define PORTF0_REG PORTF
-#define PORTF1_REG PORTF
-#define PORTF2_REG PORTF
-#define PORTF3_REG PORTF
-#define PORTF4_REG PORTF
-#define PORTF5_REG PORTF
-#define PORTF6_REG PORTF
-#define PORTF7_REG PORTF
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-#define PCINT15_REG PCMSK1
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* TCNT3H */
-#define TCNT3H0_REG TCNT3H
-#define TCNT3H1_REG TCNT3H
-#define TCNT3H2_REG TCNT3H
-#define TCNT3H3_REG TCNT3H
-#define TCNT3H4_REG TCNT3H
-#define TCNT3H5_REG TCNT3H
-#define TCNT3H6_REG TCNT3H
-#define TCNT3H7_REG TCNT3H
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* TCNT3L */
-#define TCNT3L0_REG TCNT3L
-#define TCNT3L1_REG TCNT3L
-#define TCNT3L2_REG TCNT3L
-#define TCNT3L3_REG TCNT3L
-#define TCNT3L4_REG TCNT3L
-#define TCNT3L5_REG TCNT3L
-#define TCNT3L6_REG TCNT3L
-#define TCNT3L7_REG TCNT3L
-
-/* ICR5L */
-#define ICR5L0_REG ICR5L
-#define ICR5L1_REG ICR5L
-#define ICR5L2_REG ICR5L
-#define ICR5L3_REG ICR5L
-#define ICR5L4_REG ICR5L
-#define ICR5L5_REG ICR5L
-#define ICR5L6_REG ICR5L
-#define ICR5L7_REG ICR5L
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* ICR5H */
-#define ICR5H0_REG ICR5H
-#define ICR5H1_REG ICR5H
-#define ICR5H2_REG ICR5H
-#define ICR5H3_REG ICR5H
-#define ICR5H4_REG ICR5H
-#define ICR5H5_REG ICR5H
-#define ICR5H6_REG ICR5H
-#define ICR5H7_REG ICR5H
-
-/* MCUSR */
-#define JTRF_REG MCUSR
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* PINK */
-#define PINK0_REG PINK
-#define PINK1_REG PINK
-#define PINK2_REG PINK
-#define PINK3_REG PINK
-#define PINK4_REG PINK
-#define PINK5_REG PINK
-#define PINK6_REG PINK
-#define PINK7_REG PINK
-
-/* PINJ */
-#define PINJ0_REG PINJ
-#define PINJ1_REG PINJ
-#define PINJ2_REG PINJ
-#define PINJ3_REG PINJ
-#define PINJ4_REG PINJ
-#define PINJ5_REG PINJ
-#define PINJ6_REG PINJ
-#define PINJ7_REG PINJ
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* PINH */
-#define PINH0_REG PINH
-#define PINH1_REG PINH
-#define PINH2_REG PINH
-#define PINH3_REG PINH
-#define PINH4_REG PINH
-#define PINH5_REG PINH
-#define PINH6_REG PINH
-#define PINH7_REG PINH
-
-/* PCIFR */
-#define PCIF0_REG PCIFR
-#define PCIF1_REG PCIFR
-#define PCIF2_REG PCIFR
-
-/* TCCR2A */
-#define WGM20_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2B0_REG TCCR2A
-#define COM2B1_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-
-/* TCCR2B */
-#define CS20_REG TCCR2B
-#define CS21_REG TCCR2B
-#define CS22_REG TCCR2B
-#define WGM22_REG TCCR2B
-#define FOC2B_REG TCCR2B
-#define FOC2A_REG TCCR2B
-
-/* UBRR0H */
-/* #define UBRR8_REG UBRR0H */ /* dup in UBRR3H, UBRR2H */
-/* #define UBRR9_REG UBRR0H */ /* dup in UBRR3H, UBRR2H */
-/* #define UBRR10_REG UBRR0H */ /* dup in UBRR3H, UBRR2H */
-/* #define UBRR11_REG UBRR0H */ /* dup in UBRR3H, UBRR2H */
-
-/* PING */
-#define PING0_REG PING
-#define PING1_REG PING
-#define PING2_REG PING
-#define PING3_REG PING
-#define PING4_REG PING
-#define PING5_REG PING
-
-/* UBRR0L */
-/* #define UBRR0_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */
-/* #define UBRR1_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */
-/* #define UBRR2_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */
-/* #define UBRR3_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */
-/* #define UBRR4_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */
-/* #define UBRR5_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */
-/* #define UBRR6_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */
-/* #define UBRR7_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* ICR4H */
-#define ICR4H0_REG ICR4H
-#define ICR4H1_REG ICR4H
-#define ICR4H2_REG ICR4H
-#define ICR4H3_REG ICR4H
-#define ICR4H4_REG ICR4H
-#define ICR4H5_REG ICR4H
-#define ICR4H6_REG ICR4H
-#define ICR4H7_REG ICR4H
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* PCMSK2 */
-#define PCINT16_REG PCMSK2
-#define PCINT17_REG PCMSK2
-#define PCINT18_REG PCMSK2
-#define PCINT19_REG PCMSK2
-#define PCINT20_REG PCMSK2
-#define PCINT21_REG PCMSK2
-#define PCINT22_REG PCMSK2
-#define PCINT23_REG PCMSK2
-
-/* ICR4L */
-#define ICR4L0_REG ICR4L
-#define ICR4L1_REG ICR4L
-#define ICR4L2_REG ICR4L
-#define ICR4L3_REG ICR4L
-#define ICR4L4_REG ICR4L
-#define ICR4L5_REG ICR4L
-#define ICR4L6_REG ICR4L
-#define ICR4L7_REG ICR4L
-
-/* MCUCR */
-#define JTD_REG MCUCR
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* OCR1CL */
-#define OCR1CL0_REG OCR1CL
-#define OCR1CL1_REG OCR1CL
-#define OCR1CL2_REG OCR1CL
-#define OCR1CL3_REG OCR1CL
-#define OCR1CL4_REG OCR1CL
-#define OCR1CL5_REG OCR1CL
-#define OCR1CL6_REG OCR1CL
-#define OCR1CL7_REG OCR1CL
-
-/* TCNT4L */
-#define TCNT4L0_REG TCNT4L
-#define TCNT4L1_REG TCNT4L
-#define TCNT4L2_REG TCNT4L
-#define TCNT4L3_REG TCNT4L
-#define TCNT4L4_REG TCNT4L
-#define TCNT4L5_REG TCNT4L
-#define TCNT4L6_REG TCNT4L
-#define TCNT4L7_REG TCNT4L
-
-/* OCR1CH */
-#define OCR1CH0_REG OCR1CH
-#define OCR1CH1_REG OCR1CH
-#define OCR1CH2_REG OCR1CH
-#define OCR1CH3_REG OCR1CH
-#define OCR1CH4_REG OCR1CH
-#define OCR1CH5_REG OCR1CH
-#define OCR1CH6_REG OCR1CH
-#define OCR1CH7_REG OCR1CH
-
-/* TCNT4H */
-#define TCNT4H0_REG TCNT4H
-#define TCNT4H1_REG TCNT4H
-#define TCNT4H2_REG TCNT4H
-#define TCNT4H3_REG TCNT4H
-#define TCNT4H4_REG TCNT4H
-#define TCNT4H5_REG TCNT4H
-#define TCNT4H6_REG TCNT4H
-#define TCNT4H7_REG TCNT4H
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* UCSR1B */
-#define TXB81_REG UCSR1B
-#define RXB81_REG UCSR1B
-#define UCSZ12_REG UCSR1B
-#define TXEN1_REG UCSR1B
-#define RXEN1_REG UCSR1B
-#define UDRIE1_REG UCSR1B
-#define TXCIE1_REG UCSR1B
-#define RXCIE1_REG UCSR1B
-
-/* UCSR1C */
-#define UCPOL1_REG UCSR1C
-#define UCSZ10_REG UCSR1C
-#define UCSZ11_REG UCSR1C
-#define USBS1_REG UCSR1C
-#define UPM10_REG UCSR1C
-#define UPM11_REG UCSR1C
-#define UMSEL10_REG UCSR1C
-#define UMSEL11_REG UCSR1C
-
-/* UCSR1A */
-#define MPCM1_REG UCSR1A
-#define U2X1_REG UCSR1A
-#define UPE1_REG UCSR1A
-#define DOR1_REG UCSR1A
-#define FE1_REG UCSR1A
-#define UDRE1_REG UCSR1A
-#define TXC1_REG UCSR1A
-#define RXC1_REG UCSR1A
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* EIND */
-#define EIND0_REG EIND
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* TCCR5A */
-#define WGM50_REG TCCR5A
-#define WGM51_REG TCCR5A
-#define COM5C0_REG TCCR5A
-#define COM5C1_REG TCCR5A
-#define COM5B0_REG TCCR5A
-#define COM5B1_REG TCCR5A
-#define COM5A0_REG TCCR5A
-#define COM5A1_REG TCCR5A
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* TCCR5C */
-#define FOC5C_REG TCCR5C
-#define FOC5B_REG TCCR5C
-#define FOC5A_REG TCCR5C
-
-/* TCCR5B */
-#define CS50_REG TCCR5B
-#define CS51_REG TCCR5B
-#define CS52_REG TCCR5B
-#define WGM52_REG TCCR5B
-#define WGM53_REG TCCR5B
-#define ICES5_REG TCCR5B
-#define ICNC5_REG TCCR5B
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ACME_REG ADCSRB
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define MUX5_REG ADCSRB
-
-/* OCR5AL */
-#define OCR5AL0_REG OCR5AL
-#define OCR5AL1_REG OCR5AL
-#define OCR5AL2_REG OCR5AL
-#define OCR5AL3_REG OCR5AL
-#define OCR5AL4_REG OCR5AL
-#define OCR5AL5_REG OCR5AL
-#define OCR5AL6_REG OCR5AL
-#define OCR5AL7_REG OCR5AL
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1C0_REG TCCR1A
-#define COM1C1_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* OCR4CH */
-#define OCR4CH0_REG OCR4CH
-#define OCR4CH1_REG OCR4CH
-#define OCR4CH2_REG OCR4CH
-#define OCR4CH3_REG OCR4CH
-#define OCR4CH4_REG OCR4CH
-#define OCR4CH5_REG OCR4CH
-#define OCR4CH6_REG OCR4CH
-#define OCR4CH7_REG OCR4CH
-
-/* OCR5AH */
-#define OCR5AH0_REG OCR5AH
-#define OCR5AH1_REG OCR5AH
-#define OCR5AH2_REG OCR5AH
-#define OCR5AH3_REG OCR5AH
-#define OCR5AH4_REG OCR5AH
-#define OCR5AH5_REG OCR5AH
-#define OCR5AH6_REG OCR5AH
-#define OCR5AH7_REG OCR5AH
-
-/* OCR4CL */
-#define OCR4CL0_REG OCR4CL
-#define OCR4CL1_REG OCR4CL
-#define OCR4CL2_REG OCR4CL
-#define OCR4CL3_REG OCR4CL
-#define OCR4CL4_REG OCR4CL
-#define OCR4CL5_REG OCR4CL
-#define OCR4CL6_REG OCR4CL
-#define OCR4CL7_REG OCR4CL
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* TCCR1C */
-#define FOC1C_REG TCCR1C
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* ICR3H */
-#define ICR3H0_REG ICR3H
-#define ICR3H1_REG ICR3H
-#define ICR3H2_REG ICR3H
-#define ICR3H3_REG ICR3H
-#define ICR3H4_REG ICR3H
-#define ICR3H5_REG ICR3H
-#define ICR3H6_REG ICR3H
-#define ICR3H7_REG ICR3H
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-#define DDE3_REG DDRE
-#define DDE4_REG DDRE
-#define DDE5_REG DDRE
-#define DDE6_REG DDRE
-#define DDE7_REG DDRE
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* ICR3L */
-#define ICR3L0_REG ICR3L
-#define ICR3L1_REG ICR3L
-#define ICR3L2_REG ICR3L
-#define ICR3L3_REG ICR3L
-#define ICR3L4_REG ICR3L
-#define ICR3L5_REG ICR3L
-#define ICR3L6_REG ICR3L
-#define ICR3L7_REG ICR3L
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-#define PORTE3_REG PORTE
-#define PORTE4_REG PORTE
-#define PORTE5_REG PORTE
-#define PORTE6_REG PORTE
-#define PORTE7_REG PORTE
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define SIGRD_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* OCR5BH */
-#define OCR5BH0_REG OCR5BH
-#define OCR5BH1_REG OCR5BH
-#define OCR5BH2_REG OCR5BH
-#define OCR5BH3_REG OCR5BH
-#define OCR5BH4_REG OCR5BH
-#define OCR5BH5_REG OCR5BH
-#define OCR5BH6_REG OCR5BH
-#define OCR5BH7_REG OCR5BH
-
-/* OCR3BL */
-#define OCR3BL0_REG OCR3BL
-#define OCR3BL1_REG OCR3BL
-#define OCR3BL2_REG OCR3BL
-#define OCR3BL3_REG OCR3BL
-#define OCR3BL4_REG OCR3BL
-#define OCR3BL5_REG OCR3BL
-#define OCR3BL6_REG OCR3BL
-#define OCR3BL7_REG OCR3BL
-
-/* OCR5BL */
-#define OCR5BL0_REG OCR5BL
-#define OCR5BL1_REG OCR5BL
-#define OCR5BL2_REG OCR5BL
-#define OCR5BL3_REG OCR5BL
-#define OCR5BL4_REG OCR5BL
-#define OCR5BL5_REG OCR5BL
-#define OCR5BL6_REG OCR5BL
-#define OCR5BL7_REG OCR5BL
-
-/* OCR3BH */
-#define OCR3BH0_REG OCR3BH
-#define OCR3BH1_REG OCR3BH
-#define OCR3BH2_REG OCR3BH
-#define OCR3BH3_REG OCR3BH
-#define OCR3BH4_REG OCR3BH
-#define OCR3BH5_REG OCR3BH
-#define OCR3BH6_REG OCR3BH
-#define OCR3BH7_REG OCR3BH
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-#define OCIE2B_REG TIMSK2
-
-/* TIMSK3 */
-#define TOIE3_REG TIMSK3
-#define OCIE3A_REG TIMSK3
-#define OCIE3B_REG TIMSK3
-#define OCIE3C_REG TIMSK3
-#define ICIE3_REG TIMSK3
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define OCIE1C_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* TIMSK4 */
-#define TOIE4_REG TIMSK4
-#define OCIE4A_REG TIMSK4
-#define OCIE4B_REG TIMSK4
-#define OCIE4C_REG TIMSK4
-#define ICIE4_REG TIMSK4
-
-/* TIMSK5 */
-#define TOIE5_REG TIMSK5
-#define OCIE5A_REG TIMSK5
-#define OCIE5B_REG TIMSK5
-#define OCIE5C_REG TIMSK5
-#define ICIE5_REG TIMSK5
-
-/* TCCR4B */
-#define CS40_REG TCCR4B
-#define CS41_REG TCCR4B
-#define CS42_REG TCCR4B
-#define WGM42_REG TCCR4B
-#define WGM43_REG TCCR4B
-#define ICES4_REG TCCR4B
-#define ICNC4_REG TCCR4B
-
-/* TCCR4C */
-#define FOC4C_REG TCCR4C
-#define FOC4B_REG TCCR4C
-#define FOC4A_REG TCCR4C
-
-/* TCCR4A */
-#define WGM40_REG TCCR4A
-#define WGM41_REG TCCR4A
-#define COM4C0_REG TCCR4A
-#define COM4C1_REG TCCR4A
-#define COM4B0_REG TCCR4A
-#define COM4B1_REG TCCR4A
-#define COM4A0_REG TCCR4A
-#define COM4A1_REG TCCR4A
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* XMCRB */
-#define XMM0_REG XMCRB
-#define XMM1_REG XMCRB
-#define XMM2_REG XMCRB
-#define XMBK_REG XMCRB
-
-/* XMCRA */
-#define SRW00_REG XMCRA
-#define SRW01_REG XMCRA
-#define SRW10_REG XMCRA
-#define SRW11_REG XMCRA
-#define SRL0_REG XMCRA
-#define SRL1_REG XMCRA
-#define SRL2_REG XMCRA
-#define SRE_REG XMCRA
-
-/* PINL */
-#define PINL0_REG PINL
-#define PINL1_REG PINL
-#define PINL2_REG PINL
-#define PINL3_REG PINL
-#define PINL4_REG PINL
-#define PINL5_REG PINL
-#define PINL6_REG PINL
-#define PINL7_REG PINL
-
-/* OCR4BL */
-#define OCR4BL0_REG OCR4BL
-#define OCR4BL1_REG OCR4BL
-#define OCR4BL2_REG OCR4BL
-#define OCR4BL3_REG OCR4BL
-#define OCR4BL4_REG OCR4BL
-#define OCR4BL5_REG OCR4BL
-#define OCR4BL6_REG OCR4BL
-#define OCR4BL7_REG OCR4BL
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-#define INTF2_REG EIFR
-#define INTF3_REG EIFR
-#define INTF4_REG EIFR
-#define INTF5_REG EIFR
-#define INTF6_REG EIFR
-#define INTF7_REG EIFR
-
-/* OCR4BH */
-#define OCR4BH0_REG OCR4BH
-#define OCR4BH1_REG OCR4BH
-#define OCR4BH2_REG OCR4BH
-#define OCR4BH3_REG OCR4BH
-#define OCR4BH4_REG OCR4BH
-#define OCR4BH5_REG OCR4BH
-#define OCR4BH6_REG OCR4BH
-#define OCR4BH7_REG OCR4BH
-
-/* PINF */
-#define PINF0_REG PINF
-#define PINF1_REG PINF
-#define PINF2_REG PINF
-#define PINF3_REG PINF
-#define PINF4_REG PINF
-#define PINF5_REG PINF
-#define PINF6_REG PINF
-#define PINF7_REG PINF
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-#define PINE3_REG PINE
-#define PINE4_REG PINE
-#define PINE5_REG PINE
-#define PINE6_REG PINE
-#define PINE7_REG PINE
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* TWAMR */
-#define TWAM0_REG TWAMR
-#define TWAM1_REG TWAMR
-#define TWAM2_REG TWAMR
-#define TWAM3_REG TWAMR
-#define TWAM4_REG TWAMR
-#define TWAM5_REG TWAMR
-#define TWAM6_REG TWAMR
-
-/* PRR0 */
-#define PRADC_REG PRR0
-#define PRUSART0_REG PRR0
-#define PRSPI_REG PRR0
-#define PRTIM1_REG PRR0
-#define PRTIM0_REG PRR0
-#define PRTIM2_REG PRR0
-#define PRTWI_REG PRR0
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* PRR1 */
-#define PRUSART1_REG PRR1
-#define PRUSART2_REG PRR1
-#define PRUSART3_REG PRR1
-#define PRTIM3_REG PRR1
-#define PRTIM4_REG PRR1
-#define PRTIM5_REG PRR1
-
-/* pins mapping */
-#define AD0_PORT PORTA
-#define AD0_BIT 0
-
-#define AD1_PORT PORTA
-#define AD1_BIT 1
-
-#define AD2_PORT PORTA
-#define AD2_BIT 2
-
-#define AD3_PORT PORTA
-#define AD3_BIT 3
-
-#define AD4_PORT PORTA
-#define AD4_BIT 4
-
-#define AD5_PORT PORTA
-#define AD5_BIT 5
-
-#define AD6_PORT PORTA
-#define AD6_BIT 6
-
-#define AD7_PORT PORTA
-#define AD7_BIT 7
-
-#define SS_PORT PORTB
-#define SS_BIT 0
-#define PCINT0_PORT PORTB
-#define PCINT0_BIT 0
-
-#define SCK_PORT PORTB
-#define SCK_BIT 1
-#define PCINT1_PORT PORTB
-#define PCINT1_BIT 1
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 2
-#define PCINT2_PORT PORTB
-#define PCINT2_BIT 2
-
-#define MISO_PORT PORTB
-#define MISO_BIT 3
-#define PCINT3_PORT PORTB
-#define PCINT3_BIT 3
-
-#define OC2A_PORT PORTB
-#define OC2A_BIT 4
-#define PCINT4_PORT PORTB
-#define PCINT4_BIT 4
-
-#define OC1A_PORT PORTB
-#define OC1A_BIT 5
-#define PCINT5_PORT PORTB
-#define PCINT5_BIT 5
-
-#define OC1B_PORT PORTB
-#define OC1B_BIT 6
-#define PCINT6_PORT PORTB
-#define PCINT6_BIT 6
-
-#define OC0A_PORT PORTB
-#define OC0A_BIT 7
-#define OC1C_PORT PORTB
-#define OC1C_BIT 7
-#define PCINT7_PORT PORTB
-#define PCINT7_BIT 7
-
-#define A8_PORT PORTC
-#define A8_BIT 0
-
-#define A9_PORT PORTC
-#define A9_BIT 1
-
-#define A10_PORT PORTC
-#define A10_BIT 2
-
-#define A11_PORT PORTC
-#define A11_BIT 3
-
-#define A12_PORT PORTC
-#define A12_BIT 4
-
-#define A13_PORT PORTC
-#define A13_BIT 5
-
-#define A14_PORT PORTC
-#define A14_BIT 6
-
-#define A15_PORT PORTC
-#define A15_BIT 7
-
-#define SCL_PORT PORTD
-#define SCL_BIT 0
-#define INT0_PORT PORTD
-#define INT0_BIT 0
-
-#define SDA_PORT PORTD
-#define SDA_BIT 1
-#define INT1_PORT PORTD
-#define INT1_BIT 1
-
-#define RXD1_PORT PORTD
-#define RXD1_BIT 2
-#define INT2_PORT PORTD
-#define INT2_BIT 2
-
-#define TXD1_PORT PORTD
-#define TXD1_BIT 3
-#define INT3_PORT PORTD
-#define INT3_BIT 3
-
-#define ICP1_PORT PORTD
-#define ICP1_BIT 4
-
-#define XCK1_PORT PORTD
-#define XCK1_BIT 5
-
-#define T1_PORT PORTD
-#define T1_BIT 6
-
-#define T0_PORT PORTD
-#define T0_BIT 7
-
-#define RXD_PORT PORTE
-#define RXD_BIT 0
-#define PCINT8_PORT PORTE
-#define PCINT8_BIT 0
-
-#define TXD0_PORT PORTE
-#define TXD0_BIT 1
-
-#define XCK_PORT PORTE
-#define XCK_BIT 2
-#define AIN0_PORT PORTE
-#define AIN0_BIT 2
-
-#define OC3A_PORT PORTE
-#define OC3A_BIT 3
-#define AIN1_PORT PORTE
-#define AIN1_BIT 3
-
-#define OC3B_PORT PORTE
-#define OC3B_BIT 4
-#define INT4_PORT PORTE
-#define INT4_BIT 4
-
-#define OC3C_PORT PORTE
-#define OC3C_BIT 5
-#define INT5_PORT PORTE
-#define INT5_BIT 5
-
-#define T3_PORT PORTE
-#define T3_BIT 6
-#define INT6_PORT PORTE
-#define INT6_BIT 6
-
-#define CLKO_PORT PORTE
-#define CLKO_BIT 7
-#define ICP3_PORT PORTE
-#define ICP3_BIT 7
-#define INT7_PORT PORTE
-#define INT7_BIT 7
-
-#define ADC0_PORT PORTF
-#define ADC0_BIT 0
-
-#define ADC1_PORT PORTF
-#define ADC1_BIT 1
-
-#define ADC2_PORT PORTF
-#define ADC2_BIT 2
-
-#define ADC3_PORT PORTF
-#define ADC3_BIT 3
-
-#define ADC4_PORT PORTF
-#define ADC4_BIT 4
-#define TCK_PORT PORTF
-#define TCK_BIT 4
-
-#define ADC5_PORT PORTF
-#define ADC5_BIT 5
-#define TMS_PORT PORTF
-#define TMS_BIT 5
-
-#define ADC6_PORT PORTF
-#define ADC6_BIT 6
-#define TDO_PORT PORTF
-#define TDO_BIT 6
-
-#define ADC7_PORT PORTF
-#define ADC7_BIT 7
-#define TDI_PORT PORTF
-#define TDI_BIT 7
-
-#define WR_PORT PORTG
-#define WR_BIT 0
-
-#define RD_PORT PORTG
-#define RD_BIT 1
-
-#define ALE_PORT PORTG
-#define ALE_BIT 2
-
-#define TOSC2_PORT PORTG
-#define TOSC2_BIT 3
-
-#define TOSC1_PORT PORTG
-#define TOSC1_BIT 4
-
-#define OC0B_PORT PORTG
-#define OC0B_BIT 5
-
-#define RXD2_PORT PORTH
-#define RXD2_BIT 0
-
-#define TXD2_PORT PORTH
-#define TXD2_BIT 1
-
-#define XCK2_PORT PORTH
-#define XCK2_BIT 2
-
-#define OC4A_PORT PORTH
-#define OC4A_BIT 3
-
-#define OC4B_PORT PORTH
-#define OC4B_BIT 4
-
-#define OC2B_PORT PORTH
-#define OC2B_BIT 6
-
-#define T4_PORT PORTH
-#define T4_BIT 7
-
-#define RXD3_PORT PORTJ
-#define RXD3_BIT 0
-#define PCINT9_PORT PORTJ
-#define PCINT9_BIT 0
-
-#define TXD3_PORT PORTJ
-#define TXD3_BIT 1
-#define PCINT10_PORT PORTJ
-#define PCINT10_BIT 1
-
-#define XCK3_PORT PORTJ
-#define XCK3_BIT 2
-#define PCINT11_PORT PORTJ
-#define PCINT11_BIT 2
-
-#define PCINT12_PORT PORTJ
-#define PCINT12_BIT 3
-
-#define PCINT13_PORT PORTJ
-#define PCINT13_BIT 4
-
-#define PCINT14_PORT PORTJ
-#define PCINT14_BIT 5
-
-#define PCINT15_PORT PORTJ
-#define PCINT15_BIT 6
-
-#define ADC8_PORT PORTK
-#define ADC8_BIT 0
-#define PCINT16_PORT PORTK
-#define PCINT16_BIT 0
-
-#define ADC9_PORT PORTK
-#define ADC9_BIT 1
-#define PCINT17_PORT PORTK
-#define PCINT17_BIT 1
-
-#define ADC10_PORT PORTK
-#define ADC10_BIT 2
-#define PCINT18_PORT PORTK
-#define PCINT18_BIT 2
-
-#define ADC11_PORT PORTK
-#define ADC11_BIT 3
-#define PCINT19_PORT PORTK
-#define PCINT19_BIT 3
-
-#define ADC12_PORT PORTK
-#define ADC12_BIT 4
-#define PCINT20_PORT PORTK
-#define PCINT20_BIT 4
-
-#define ADC13_PORT PORTK
-#define ADC13_BIT 5
-#define PCINT21_PORT PORTK
-#define PCINT21_BIT 5
-
-#define ADC14_PORT PORTK
-#define ADC14_BIT 6
-#define PCINT22_PORT PORTK
-#define PCINT22_BIT 6
-
-#define ADC15_PORT PORTK
-#define ADC15_BIT 7
-#define PCINT23_PORT PORTK
-#define PCINT23_BIT 7
-
-#define ICP4_PORT PORTL
-#define ICP4_BIT 0
-
-#define ICP5_PORT PORTL
-#define ICP5_BIT 1
-
-#define T5_PORT PORTL
-#define T5_BIT 2
-
-#define OC5A_PORT PORTL
-#define OC5A_BIT 3
-
-#define OC5B_PORT PORTL
-#define OC5B_BIT 4
-
-#define OC5C_PORT PORTL
-#define OC5C_BIT 5
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-/* prescalers timer 3 */
-#define TIMER3_PRESCALER_DIV_0 0
-#define TIMER3_PRESCALER_DIV_1 1
-#define TIMER3_PRESCALER_DIV_8 2
-#define TIMER3_PRESCALER_DIV_64 3
-#define TIMER3_PRESCALER_DIV_256 4
-#define TIMER3_PRESCALER_DIV_1024 5
-#define TIMER3_PRESCALER_DIV_FALL 6
-#define TIMER3_PRESCALER_DIV_RISE 7
-
-#define TIMER3_PRESCALER_REG_0 0
-#define TIMER3_PRESCALER_REG_1 1
-#define TIMER3_PRESCALER_REG_2 8
-#define TIMER3_PRESCALER_REG_3 64
-#define TIMER3_PRESCALER_REG_4 256
-#define TIMER3_PRESCALER_REG_5 1024
-#define TIMER3_PRESCALER_REG_6 -1
-#define TIMER3_PRESCALER_REG_7 -2
-
-/* prescalers timer 4 */
-#define TIMER4_PRESCALER_DIV_0 0
-#define TIMER4_PRESCALER_DIV_1 1
-#define TIMER4_PRESCALER_DIV_8 2
-#define TIMER4_PRESCALER_DIV_64 3
-#define TIMER4_PRESCALER_DIV_256 4
-#define TIMER4_PRESCALER_DIV_1024 5
-#define TIMER4_PRESCALER_DIV_FALL 6
-#define TIMER4_PRESCALER_DIV_RISE 7
-
-#define TIMER4_PRESCALER_REG_0 0
-#define TIMER4_PRESCALER_REG_1 1
-#define TIMER4_PRESCALER_REG_2 8
-#define TIMER4_PRESCALER_REG_3 64
-#define TIMER4_PRESCALER_REG_4 256
-#define TIMER4_PRESCALER_REG_5 1024
-#define TIMER4_PRESCALER_REG_6 -1
-#define TIMER4_PRESCALER_REG_7 -2
-
-/* prescalers timer 5 */
-#define TIMER5_PRESCALER_DIV_0 0
-#define TIMER5_PRESCALER_DIV_1 1
-#define TIMER5_PRESCALER_DIV_8 2
-#define TIMER5_PRESCALER_DIV_64 3
-#define TIMER5_PRESCALER_DIV_256 4
-#define TIMER5_PRESCALER_DIV_1024 5
-#define TIMER5_PRESCALER_DIV_FALL 6
-#define TIMER5_PRESCALER_DIV_RISE 7
-
-#define TIMER5_PRESCALER_REG_0 0
-#define TIMER5_PRESCALER_REG_1 1
-#define TIMER5_PRESCALER_REG_2 8
-#define TIMER5_PRESCALER_REG_3 64
-#define TIMER5_PRESCALER_REG_4 256
-#define TIMER5_PRESCALER_REG_5 1024
-#define TIMER5_PRESCALER_REG_6 -1
-#define TIMER5_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER1C_AVAILABLE
-#define TIMER2_AVAILABLE
-#define TIMER2A_AVAILABLE
-#define TIMER2B_AVAILABLE
-#define TIMER3_AVAILABLE
-#define TIMER3A_AVAILABLE
-#define TIMER3B_AVAILABLE
-#define TIMER3C_AVAILABLE
-#define TIMER4_AVAILABLE
-#define TIMER4A_AVAILABLE
-#define TIMER4B_AVAILABLE
-#define TIMER4C_AVAILABLE
-#define TIMER5_AVAILABLE
-#define TIMER5A_AVAILABLE
-#define TIMER5B_AVAILABLE
-#define TIMER5C_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW3_NUM 3
-#define SIG_OVERFLOW4_NUM 4
-#define SIG_OVERFLOW5_NUM 5
-#define SIG_OVERFLOW_TOTAL_NUM 6
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE1C_NUM 4
-#define SIG_OUTPUT_COMPARE2A_NUM 5
-#define SIG_OUTPUT_COMPARE2B_NUM 6
-#define SIG_OUTPUT_COMPARE3A_NUM 7
-#define SIG_OUTPUT_COMPARE3B_NUM 8
-#define SIG_OUTPUT_COMPARE3C_NUM 9
-#define SIG_OUTPUT_COMPARE4A_NUM 10
-#define SIG_OUTPUT_COMPARE4B_NUM 11
-#define SIG_OUTPUT_COMPARE4C_NUM 12
-#define SIG_OUTPUT_COMPARE5A_NUM 13
-#define SIG_OUTPUT_COMPARE5B_NUM 14
-#define SIG_OUTPUT_COMPARE5C_NUM 15
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 16
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM1C_NUM 4
-#define PWM2A_NUM 5
-#define PWM2B_NUM 6
-#define PWM3A_NUM 7
-#define PWM3B_NUM 8
-#define PWM3C_NUM 9
-#define PWM4A_NUM 10
-#define PWM4B_NUM 11
-#define PWM4C_NUM 12
-#define PWM5A_NUM 13
-#define PWM5B_NUM 14
-#define PWM5C_NUM 15
-#define PWM_TOTAL_NUM 16
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE3_NUM 1
-#define SIG_INPUT_CAPTURE4_NUM 2
-#define SIG_INPUT_CAPTURE5_NUM 3
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 4
-
-
-/* OCR0A */
-#define OCROA_0_REG OCR0A
-#define OCROA_1_REG OCR0A
-#define OCROA_2_REG OCR0A
-#define OCROA_3_REG OCR0A
-#define OCROA_4_REG OCR0A
-#define OCROA_5_REG OCR0A
-#define OCROA_6_REG OCR0A
-#define OCROA_7_REG OCR0A
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* RAMPZ */
-#define RAMPZ0_REG RAMPZ
-#define RAMPZ1_REG RAMPZ
-
-/* OCR2B */
-#define OCR2B_0_REG OCR2B
-#define OCR2B_1_REG OCR2B
-#define OCR2B_2_REG OCR2B
-#define OCR2B_3_REG OCR2B
-#define OCR2B_4_REG OCR2B
-#define OCR2B_5_REG OCR2B
-#define OCR2B_6_REG OCR2B
-#define OCR2B_7_REG OCR2B
-
-/* OCR2A */
-#define OCR2A_0_REG OCR2A
-#define OCR2A_1_REG OCR2A
-#define OCR2A_2_REG OCR2A
-#define OCR2A_3_REG OCR2A
-#define OCR2A_4_REG OCR2A
-#define OCR2A_5_REG OCR2A
-#define OCR2A_6_REG OCR2A
-#define OCR2A_7_REG OCR2A
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-#define EEAR10_REG EEARH
-#define EEAR11_REG EEARH
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTG */
-#define PORTG0_REG PORTG
-#define PORTG1_REG PORTG
-#define PORTG2_REG PORTG
-#define PORTG3_REG PORTG
-#define PORTG4_REG PORTG
-#define PORTG5_REG PORTG
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL00_REG UCSR0C
-#define UMSEL01_REG UCSR0C
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-#define INT3_REG EIMSK
-#define INT4_REG EIMSK
-#define INT5_REG EIMSK
-#define INT6_REG EIMSK
-#define INT7_REG EIMSK
-
-/* UDR1 */
-#define UDR1_0_REG UDR1
-#define UDR1_1_REG UDR1
-#define UDR1_2_REG UDR1
-#define UDR1_3_REG UDR1
-#define UDR1_4_REG UDR1
-#define UDR1_5_REG UDR1
-#define UDR1_6_REG UDR1
-#define UDR1_7_REG UDR1
-
-/* UDR0 */
-#define UDR0_0_REG UDR0
-#define UDR0_1_REG UDR0
-#define UDR0_2_REG UDR0
-#define UDR0_3_REG UDR0
-#define UDR0_4_REG UDR0
-#define UDR0_5_REG UDR0
-#define UDR0_6_REG UDR0
-#define UDR0_7_REG UDR0
-
-/* EICRB */
-#define ISC40_REG EICRB
-#define ISC41_REG EICRB
-#define ISC50_REG EICRB
-#define ISC51_REG EICRB
-#define ISC60_REG EICRB
-#define ISC61_REG EICRB
-#define ISC70_REG EICRB
-#define ISC71_REG EICRB
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-#define ISC20_REG EICRA
-#define ISC21_REG EICRA
-#define ISC30_REG EICRA
-#define ISC31_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* DIDR2 */
-#define ADC8D_REG DIDR2
-#define ADC9D_REG DIDR2
-#define ADC10D_REG DIDR2
-#define ADC11D_REG DIDR2
-#define ADC12D_REG DIDR2
-#define ADC13D_REG DIDR2
-#define ADC14D_REG DIDR2
-#define ADC15D_REG DIDR2
-
-/* DDRF */
-#define DDF0_REG DDRF
-#define DDF1_REG DDRF
-#define DDF2_REG DDRF
-#define DDF3_REG DDRF
-#define DDF4_REG DDRF
-#define DDF5_REG DDRF
-#define DDF6_REG DDRF
-#define DDF7_REG DDRF
-
-/* ASSR */
-#define TCR2BUB_REG ASSR
-#define TCR2AUB_REG ASSR
-#define OCR2BUB_REG ASSR
-#define OCR2AUB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* OCR0B */
-#define OCR0B_0_REG OCR0B
-#define OCR0B_1_REG OCR0B
-#define OCR0B_2_REG OCR0B
-#define OCR0B_3_REG OCR0B
-#define OCR0B_4_REG OCR0B
-#define OCR0B_5_REG OCR0B
-#define OCR0B_6_REG OCR0B
-#define OCR0B_7_REG OCR0B
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* UBRR1L */
-#define UBRR_0_REG UBRR1L
-#define UBRR_1_REG UBRR1L
-#define UBRR_2_REG UBRR1L
-#define UBRR_3_REG UBRR1L
-#define UBRR_4_REG UBRR1L
-#define UBRR_5_REG UBRR1L
-#define UBRR_6_REG UBRR1L
-#define UBRR_7_REG UBRR1L
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* OCR3AL */
-#define OCR3AL0_REG OCR3AL
-#define OCR3AL1_REG OCR3AL
-#define OCR3AL2_REG OCR3AL
-#define OCR3AL3_REG OCR3AL
-#define OCR3AL4_REG OCR3AL
-#define OCR3AL5_REG OCR3AL
-#define OCR3AL6_REG OCR3AL
-#define OCR3AL7_REG OCR3AL
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* UBRR1H */
-#define UBRR_8_REG UBRR1H
-#define UBRR_9_REG UBRR1H
-#define UBRR_10_REG UBRR1H
-#define UBRR_11_REG UBRR1H
-
-/* DDRG */
-#define DDG0_REG DDRG
-#define DDG1_REG DDRG
-#define DDG2_REG DDRG
-#define DDG3_REG DDRG
-#define DDG4_REG DDRG
-#define DDG5_REG DDRG
-
-/* OCR3AH */
-#define OCR3AH0_REG OCR3AH
-#define OCR3AH1_REG OCR3AH
-#define OCR3AH2_REG OCR3AH
-#define OCR3AH3_REG OCR3AH
-#define OCR3AH4_REG OCR3AH
-#define OCR3AH5_REG OCR3AH
-#define OCR3AH6_REG OCR3AH
-#define OCR3AH7_REG OCR3AH
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* TCNT5H */
-#define TCNT5H0_REG TCNT5H
-#define TCNT5H1_REG TCNT5H
-#define TCNT5H2_REG TCNT5H
-#define TCNT5H3_REG TCNT5H
-#define TCNT5H4_REG TCNT5H
-#define TCNT5H5_REG TCNT5H
-#define TCNT5H6_REG TCNT5H
-#define TCNT5H7_REG TCNT5H
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* TCNT5L */
-#define TCNT5L0_REG TCNT5L
-#define TCNT5L1_REG TCNT5L
-#define TCNT5L2_REG TCNT5L
-#define TCNT5L3_REG TCNT5L
-#define TCNT5L4_REG TCNT5L
-#define TCNT5L5_REG TCNT5L
-#define TCNT5L6_REG TCNT5L
-#define TCNT5L7_REG TCNT5L
-
-/* PCICR */
-#define PCIE0_REG PCICR
-#define PCIE1_REG PCICR
-#define PCIE2_REG PCICR
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* TIFR4 */
-#define TOV4_REG TIFR4
-#define OCF4A_REG TIFR4
-#define OCF4B_REG TIFR4
-#define OCF4C_REG TIFR4
-#define ICF4_REG TIFR4
-
-/* TIFR5 */
-#define TOV5_REG TIFR5
-#define OCF5A_REG TIFR5
-#define OCF5B_REG TIFR5
-#define OCF5C_REG TIFR5
-#define ICF5_REG TIFR5
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-#define OCF2B_REG TIFR2
-
-/* TIFR3 */
-#define TOV3_REG TIFR3
-#define OCF3A_REG TIFR3
-#define OCF3B_REG TIFR3
-#define OCF3C_REG TIFR3
-#define ICF3_REG TIFR3
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define OCF1C_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* OCR4AH */
-#define OCR4AH0_REG OCR4AH
-#define OCR4AH1_REG OCR4AH
-#define OCR4AH2_REG OCR4AH
-#define OCR4AH3_REG OCR4AH
-#define OCR4AH4_REG OCR4AH
-#define OCR4AH5_REG OCR4AH
-#define OCR4AH6_REG OCR4AH
-#define OCR4AH7_REG OCR4AH
-
-/* OCR5CH */
-#define OCR5CH0_REG OCR5CH
-#define OCR5CH1_REG OCR5CH
-#define OCR5CH2_REG OCR5CH
-#define OCR5CH3_REG OCR5CH
-#define OCR5CH4_REG OCR5CH
-#define OCR5CH5_REG OCR5CH
-#define OCR5CH6_REG OCR5CH
-#define OCR5CH7_REG OCR5CH
-
-/* OCR4AL */
-#define OCR4AL0_REG OCR4AL
-#define OCR4AL1_REG OCR4AL
-#define OCR4AL2_REG OCR4AL
-#define OCR4AL3_REG OCR4AL
-#define OCR4AL4_REG OCR4AL
-#define OCR4AL5_REG OCR4AL
-#define OCR4AL6_REG OCR4AL
-#define OCR4AL7_REG OCR4AL
-
-/* OCR5CL */
-#define OCR5CL0_REG OCR5CL
-#define OCR5CL1_REG OCR5CL
-#define OCR5CL2_REG OCR5CL
-#define OCR5CL3_REG OCR5CL
-#define OCR5CL4_REG OCR5CL
-#define OCR5CL5_REG OCR5CL
-#define OCR5CL6_REG OCR5CL
-#define OCR5CL7_REG OCR5CL
-
-/* OCR3CH */
-#define OCR3CH0_REG OCR3CH
-#define OCR3CH1_REG OCR3CH
-#define OCR3CH2_REG OCR3CH
-#define OCR3CH3_REG OCR3CH
-#define OCR3CH4_REG OCR3CH
-#define OCR3CH5_REG OCR3CH
-#define OCR3CH6_REG OCR3CH
-#define OCR3CH7_REG OCR3CH
-
-/* OCR3CL */
-#define OCR3CL0_REG OCR3CL
-#define OCR3CL1_REG OCR3CL
-#define OCR3CL2_REG OCR3CL
-#define OCR3CL3_REG OCR3CL
-#define OCR3CL4_REG OCR3CL
-#define OCR3CL5_REG OCR3CL
-#define OCR3CL6_REG OCR3CL
-#define OCR3CL7_REG OCR3CL
-
-/* GTCCR */
-#define PSRSYNC_REG GTCCR
-#define TSM_REG GTCCR
-#define PSRASY_REG GTCCR
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* TCCR3C */
-#define FOC3C_REG TCCR3C
-#define FOC3B_REG TCCR3C
-#define FOC3A_REG TCCR3C
-
-/* TCCR3B */
-#define CS30_REG TCCR3B
-#define CS31_REG TCCR3B
-#define CS32_REG TCCR3B
-#define WGM32_REG TCCR3B
-#define WGM33_REG TCCR3B
-#define ICES3_REG TCCR3B
-#define ICNC3_REG TCCR3B
-
-/* TCCR3A */
-#define WGM30_REG TCCR3A
-#define WGM31_REG TCCR3A
-#define COM3C0_REG TCCR3A
-#define COM3C1_REG TCCR3A
-#define COM3B0_REG TCCR3A
-#define COM3B1_REG TCCR3A
-#define COM3A0_REG TCCR3A
-#define COM3A1_REG TCCR3A
-
-/* PORTF */
-#define PORTF0_REG PORTF
-#define PORTF1_REG PORTF
-#define PORTF2_REG PORTF
-#define PORTF3_REG PORTF
-#define PORTF4_REG PORTF
-#define PORTF5_REG PORTF
-#define PORTF6_REG PORTF
-#define PORTF7_REG PORTF
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-#define PCINT15_REG PCMSK1
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* TCNT3H */
-#define TCNT3H0_REG TCNT3H
-#define TCNT3H1_REG TCNT3H
-#define TCNT3H2_REG TCNT3H
-#define TCNT3H3_REG TCNT3H
-#define TCNT3H4_REG TCNT3H
-#define TCNT3H5_REG TCNT3H
-#define TCNT3H6_REG TCNT3H
-#define TCNT3H7_REG TCNT3H
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* TCNT3L */
-#define TCNT3L0_REG TCNT3L
-#define TCNT3L1_REG TCNT3L
-#define TCNT3L2_REG TCNT3L
-#define TCNT3L3_REG TCNT3L
-#define TCNT3L4_REG TCNT3L
-#define TCNT3L5_REG TCNT3L
-#define TCNT3L6_REG TCNT3L
-#define TCNT3L7_REG TCNT3L
-
-/* ICR5L */
-#define ICR5L0_REG ICR5L
-#define ICR5L1_REG ICR5L
-#define ICR5L2_REG ICR5L
-#define ICR5L3_REG ICR5L
-#define ICR5L4_REG ICR5L
-#define ICR5L5_REG ICR5L
-#define ICR5L6_REG ICR5L
-#define ICR5L7_REG ICR5L
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* ICR5H */
-#define ICR5H0_REG ICR5H
-#define ICR5H1_REG ICR5H
-#define ICR5H2_REG ICR5H
-#define ICR5H3_REG ICR5H
-#define ICR5H4_REG ICR5H
-#define ICR5H5_REG ICR5H
-#define ICR5H6_REG ICR5H
-#define ICR5H7_REG ICR5H
-
-/* MCUSR */
-#define JTRF_REG MCUSR
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* PCIFR */
-#define PCIF0_REG PCIFR
-#define PCIF1_REG PCIFR
-#define PCIF2_REG PCIFR
-
-/* TCCR2A */
-#define WGM20_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2B0_REG TCCR2A
-#define COM2B1_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-
-/* TCCR2B */
-#define CS20_REG TCCR2B
-#define CS21_REG TCCR2B
-#define CS22_REG TCCR2B
-#define WGM22_REG TCCR2B
-#define FOC2B_REG TCCR2B
-#define FOC2A_REG TCCR2B
-
-/* UBRR0H */
-#define UBRR8_REG UBRR0H
-#define UBRR9_REG UBRR0H
-#define UBRR10_REG UBRR0H
-#define UBRR11_REG UBRR0H
-
-/* PING */
-#define PING0_REG PING
-#define PING1_REG PING
-#define PING2_REG PING
-#define PING3_REG PING
-#define PING4_REG PING
-#define PING5_REG PING
-
-/* UBRR0L */
-#define UBRR0_REG UBRR0L
-#define UBRR1_REG UBRR0L
-#define UBRR2_REG UBRR0L
-#define UBRR3_REG UBRR0L
-#define UBRR4_REG UBRR0L
-#define UBRR5_REG UBRR0L
-#define UBRR6_REG UBRR0L
-#define UBRR7_REG UBRR0L
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* ICR4H */
-#define ICR4H0_REG ICR4H
-#define ICR4H1_REG ICR4H
-#define ICR4H2_REG ICR4H
-#define ICR4H3_REG ICR4H
-#define ICR4H4_REG ICR4H
-#define ICR4H5_REG ICR4H
-#define ICR4H6_REG ICR4H
-#define ICR4H7_REG ICR4H
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* PCMSK2 */
-#define PCINT16_REG PCMSK2
-#define PCINT17_REG PCMSK2
-#define PCINT18_REG PCMSK2
-#define PCINT19_REG PCMSK2
-#define PCINT20_REG PCMSK2
-#define PCINT21_REG PCMSK2
-#define PCINT22_REG PCMSK2
-#define PCINT23_REG PCMSK2
-
-/* ICR4L */
-#define ICR4L0_REG ICR4L
-#define ICR4L1_REG ICR4L
-#define ICR4L2_REG ICR4L
-#define ICR4L3_REG ICR4L
-#define ICR4L4_REG ICR4L
-#define ICR4L5_REG ICR4L
-#define ICR4L6_REG ICR4L
-#define ICR4L7_REG ICR4L
-
-/* MCUCR */
-#define JTD_REG MCUCR
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* OCR1CL */
-#define OCR1CL0_REG OCR1CL
-#define OCR1CL1_REG OCR1CL
-#define OCR1CL2_REG OCR1CL
-#define OCR1CL3_REG OCR1CL
-#define OCR1CL4_REG OCR1CL
-#define OCR1CL5_REG OCR1CL
-#define OCR1CL6_REG OCR1CL
-#define OCR1CL7_REG OCR1CL
-
-/* TCNT4L */
-#define TCNT4L0_REG TCNT4L
-#define TCNT4L1_REG TCNT4L
-#define TCNT4L2_REG TCNT4L
-#define TCNT4L3_REG TCNT4L
-#define TCNT4L4_REG TCNT4L
-#define TCNT4L5_REG TCNT4L
-#define TCNT4L6_REG TCNT4L
-#define TCNT4L7_REG TCNT4L
-
-/* OCR1CH */
-#define OCR1CH0_REG OCR1CH
-#define OCR1CH1_REG OCR1CH
-#define OCR1CH2_REG OCR1CH
-#define OCR1CH3_REG OCR1CH
-#define OCR1CH4_REG OCR1CH
-#define OCR1CH5_REG OCR1CH
-#define OCR1CH6_REG OCR1CH
-#define OCR1CH7_REG OCR1CH
-
-/* TCNT4H */
-#define TCNT4H0_REG TCNT4H
-#define TCNT4H1_REG TCNT4H
-#define TCNT4H2_REG TCNT4H
-#define TCNT4H3_REG TCNT4H
-#define TCNT4H4_REG TCNT4H
-#define TCNT4H5_REG TCNT4H
-#define TCNT4H6_REG TCNT4H
-#define TCNT4H7_REG TCNT4H
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* UCSR1B */
-#define TXB81_REG UCSR1B
-#define RXB81_REG UCSR1B
-#define UCSZ12_REG UCSR1B
-#define TXEN1_REG UCSR1B
-#define RXEN1_REG UCSR1B
-#define UDRIE1_REG UCSR1B
-#define TXCIE1_REG UCSR1B
-#define RXCIE1_REG UCSR1B
-
-/* UCSR1C */
-#define UCPOL1_REG UCSR1C
-#define UCSZ10_REG UCSR1C
-#define UCSZ11_REG UCSR1C
-#define USBS1_REG UCSR1C
-#define UPM10_REG UCSR1C
-#define UPM11_REG UCSR1C
-#define UMSEL10_REG UCSR1C
-#define UMSEL11_REG UCSR1C
-
-/* UCSR1A */
-#define MPCM1_REG UCSR1A
-#define U2X1_REG UCSR1A
-#define UPE1_REG UCSR1A
-#define DOR1_REG UCSR1A
-#define FE1_REG UCSR1A
-#define UDRE1_REG UCSR1A
-#define TXC1_REG UCSR1A
-#define RXC1_REG UCSR1A
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* EIND */
-#define EIND0_REG EIND
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* TCCR5A */
-#define WGM50_REG TCCR5A
-#define WGM51_REG TCCR5A
-#define COM5C0_REG TCCR5A
-#define COM5C1_REG TCCR5A
-#define COM5B0_REG TCCR5A
-#define COM5B1_REG TCCR5A
-#define COM5A0_REG TCCR5A
-#define COM5A1_REG TCCR5A
-
-/* TWAMR */
-#define TWAM0_REG TWAMR
-#define TWAM1_REG TWAMR
-#define TWAM2_REG TWAMR
-#define TWAM3_REG TWAMR
-#define TWAM4_REG TWAMR
-#define TWAM5_REG TWAMR
-#define TWAM6_REG TWAMR
-
-/* TCCR5C */
-#define FOC5C_REG TCCR5C
-#define FOC5B_REG TCCR5C
-#define FOC5A_REG TCCR5C
-
-/* TCCR5B */
-#define CS50_REG TCCR5B
-#define CS51_REG TCCR5B
-#define CS52_REG TCCR5B
-#define WGM52_REG TCCR5B
-#define WGM53_REG TCCR5B
-#define ICES5_REG TCCR5B
-#define ICNC5_REG TCCR5B
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ACME_REG ADCSRB
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define MUX5_REG ADCSRB
-
-/* OCR5AL */
-#define OCR5AL0_REG OCR5AL
-#define OCR5AL1_REG OCR5AL
-#define OCR5AL2_REG OCR5AL
-#define OCR5AL3_REG OCR5AL
-#define OCR5AL4_REG OCR5AL
-#define OCR5AL5_REG OCR5AL
-#define OCR5AL6_REG OCR5AL
-#define OCR5AL7_REG OCR5AL
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1C0_REG TCCR1A
-#define COM1C1_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* OCR4CH */
-#define OCR4CH0_REG OCR4CH
-#define OCR4CH1_REG OCR4CH
-#define OCR4CH2_REG OCR4CH
-#define OCR4CH3_REG OCR4CH
-#define OCR4CH4_REG OCR4CH
-#define OCR4CH5_REG OCR4CH
-#define OCR4CH6_REG OCR4CH
-#define OCR4CH7_REG OCR4CH
-
-/* OCR5AH */
-#define OCR5AH0_REG OCR5AH
-#define OCR5AH1_REG OCR5AH
-#define OCR5AH2_REG OCR5AH
-#define OCR5AH3_REG OCR5AH
-#define OCR5AH4_REG OCR5AH
-#define OCR5AH5_REG OCR5AH
-#define OCR5AH6_REG OCR5AH
-#define OCR5AH7_REG OCR5AH
-
-/* OCR4CL */
-#define OCR4CL0_REG OCR4CL
-#define OCR4CL1_REG OCR4CL
-#define OCR4CL2_REG OCR4CL
-#define OCR4CL3_REG OCR4CL
-#define OCR4CL4_REG OCR4CL
-#define OCR4CL5_REG OCR4CL
-#define OCR4CL6_REG OCR4CL
-#define OCR4CL7_REG OCR4CL
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* TCCR1C */
-#define FOC1C_REG TCCR1C
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* ICR3H */
-#define ICR3H0_REG ICR3H
-#define ICR3H1_REG ICR3H
-#define ICR3H2_REG ICR3H
-#define ICR3H3_REG ICR3H
-#define ICR3H4_REG ICR3H
-#define ICR3H5_REG ICR3H
-#define ICR3H6_REG ICR3H
-#define ICR3H7_REG ICR3H
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-#define DDE3_REG DDRE
-#define DDE4_REG DDRE
-#define DDE5_REG DDRE
-#define DDE6_REG DDRE
-#define DDE7_REG DDRE
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* ICR3L */
-#define ICR3L0_REG ICR3L
-#define ICR3L1_REG ICR3L
-#define ICR3L2_REG ICR3L
-#define ICR3L3_REG ICR3L
-#define ICR3L4_REG ICR3L
-#define ICR3L5_REG ICR3L
-#define ICR3L6_REG ICR3L
-#define ICR3L7_REG ICR3L
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-#define PORTE3_REG PORTE
-#define PORTE4_REG PORTE
-#define PORTE5_REG PORTE
-#define PORTE6_REG PORTE
-#define PORTE7_REG PORTE
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define SIGRD_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* OCR5BH */
-#define OCR5BH0_REG OCR5BH
-#define OCR5BH1_REG OCR5BH
-#define OCR5BH2_REG OCR5BH
-#define OCR5BH3_REG OCR5BH
-#define OCR5BH4_REG OCR5BH
-#define OCR5BH5_REG OCR5BH
-#define OCR5BH6_REG OCR5BH
-#define OCR5BH7_REG OCR5BH
-
-/* OCR3BL */
-#define OCR3BL0_REG OCR3BL
-#define OCR3BL1_REG OCR3BL
-#define OCR3BL2_REG OCR3BL
-#define OCR3BL3_REG OCR3BL
-#define OCR3BL4_REG OCR3BL
-#define OCR3BL5_REG OCR3BL
-#define OCR3BL6_REG OCR3BL
-#define OCR3BL7_REG OCR3BL
-
-/* OCR5BL */
-#define OCR5BL0_REG OCR5BL
-#define OCR5BL1_REG OCR5BL
-#define OCR5BL2_REG OCR5BL
-#define OCR5BL3_REG OCR5BL
-#define OCR5BL4_REG OCR5BL
-#define OCR5BL5_REG OCR5BL
-#define OCR5BL6_REG OCR5BL
-#define OCR5BL7_REG OCR5BL
-
-/* OCR3BH */
-#define OCR3BH0_REG OCR3BH
-#define OCR3BH1_REG OCR3BH
-#define OCR3BH2_REG OCR3BH
-#define OCR3BH3_REG OCR3BH
-#define OCR3BH4_REG OCR3BH
-#define OCR3BH5_REG OCR3BH
-#define OCR3BH6_REG OCR3BH
-#define OCR3BH7_REG OCR3BH
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-#define OCIE2B_REG TIMSK2
-
-/* TIMSK3 */
-#define TOIE3_REG TIMSK3
-#define OCIE3A_REG TIMSK3
-#define OCIE3B_REG TIMSK3
-#define OCIE3C_REG TIMSK3
-#define ICIE3_REG TIMSK3
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define OCIE1C_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* TIMSK4 */
-#define TOIE4_REG TIMSK4
-#define OCIE4A_REG TIMSK4
-#define OCIE4B_REG TIMSK4
-#define OCIE4C_REG TIMSK4
-#define ICIE4_REG TIMSK4
-
-/* TIMSK5 */
-#define TOIE5_REG TIMSK5
-#define OCIE5A_REG TIMSK5
-#define OCIE5B_REG TIMSK5
-#define OCIE5C_REG TIMSK5
-#define ICIE5_REG TIMSK5
-
-/* TCCR4B */
-#define CS40_REG TCCR4B
-#define CS41_REG TCCR4B
-#define CS42_REG TCCR4B
-#define WGM42_REG TCCR4B
-#define WGM43_REG TCCR4B
-#define ICES4_REG TCCR4B
-#define ICNC4_REG TCCR4B
-
-/* TCCR4C */
-#define FOC4C_REG TCCR4C
-#define FOC4B_REG TCCR4C
-#define FOC4A_REG TCCR4C
-
-/* TCCR4A */
-#define WGM40_REG TCCR4A
-#define WGM41_REG TCCR4A
-#define COM4C0_REG TCCR4A
-#define COM4C1_REG TCCR4A
-#define COM4B0_REG TCCR4A
-#define COM4B1_REG TCCR4A
-#define COM4A0_REG TCCR4A
-#define COM4A1_REG TCCR4A
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* XMCRB */
-#define XMM0_REG XMCRB
-#define XMM1_REG XMCRB
-#define XMM2_REG XMCRB
-#define XMBK_REG XMCRB
-
-/* XMCRA */
-#define SRW00_REG XMCRA
-#define SRW01_REG XMCRA
-#define SRW10_REG XMCRA
-#define SRW11_REG XMCRA
-#define SRL0_REG XMCRA
-#define SRL1_REG XMCRA
-#define SRL2_REG XMCRA
-#define SRE_REG XMCRA
-
-/* OCR4BL */
-#define OCR4BL0_REG OCR4BL
-#define OCR4BL1_REG OCR4BL
-#define OCR4BL2_REG OCR4BL
-#define OCR4BL3_REG OCR4BL
-#define OCR4BL4_REG OCR4BL
-#define OCR4BL5_REG OCR4BL
-#define OCR4BL6_REG OCR4BL
-#define OCR4BL7_REG OCR4BL
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-#define INTF2_REG EIFR
-#define INTF3_REG EIFR
-#define INTF4_REG EIFR
-#define INTF5_REG EIFR
-#define INTF6_REG EIFR
-#define INTF7_REG EIFR
-
-/* OCR4BH */
-#define OCR4BH0_REG OCR4BH
-#define OCR4BH1_REG OCR4BH
-#define OCR4BH2_REG OCR4BH
-#define OCR4BH3_REG OCR4BH
-#define OCR4BH4_REG OCR4BH
-#define OCR4BH5_REG OCR4BH
-#define OCR4BH6_REG OCR4BH
-#define OCR4BH7_REG OCR4BH
-
-/* PINF */
-#define PINF0_REG PINF
-#define PINF1_REG PINF
-#define PINF2_REG PINF
-#define PINF3_REG PINF
-#define PINF4_REG PINF
-#define PINF5_REG PINF
-#define PINF6_REG PINF
-#define PINF7_REG PINF
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-#define PINE3_REG PINE
-#define PINE4_REG PINE
-#define PINE5_REG PINE
-#define PINE6_REG PINE
-#define PINE7_REG PINE
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* PRR0 */
-#define PRADC_REG PRR0
-#define PRUSART0_REG PRR0
-#define PRSPI_REG PRR0
-#define PRTIM1_REG PRR0
-#define PRTIM0_REG PRR0
-#define PRTIM2_REG PRR0
-#define PRTWI_REG PRR0
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* PRR1 */
-#define PRUSART1_REG PRR1
-#define PRUSART2_REG PRR1
-#define PRUSART3_REG PRR1
-#define PRTIM3_REG PRR1
-#define PRTIM4_REG PRR1
-#define PRTIM5_REG PRR1
-
-/* pins mapping */
-#define AD0_PORT PORTA
-#define AD0_BIT 0
-
-#define AD1_PORT PORTA
-#define AD1_BIT 1
-
-#define AD2_PORT PORTA
-#define AD2_BIT 2
-
-#define AD3_PORT PORTA
-#define AD3_BIT 3
-
-#define AD4_PORT PORTA
-#define AD4_BIT 4
-
-#define AD5_PORT PORTA
-#define AD5_BIT 5
-
-#define AD6_PORT PORTA
-#define AD6_BIT 6
-
-#define AD7_PORT PORTA
-#define AD7_BIT 7
-
-#define SS_PORT PORTB
-#define SS_BIT 0
-#define PCINT0_PORT PORTB
-#define PCINT0_BIT 0
-
-#define SCK_PORT PORTB
-#define SCK_BIT 1
-#define PCINT1_PORT PORTB
-#define PCINT1_BIT 1
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 2
-#define PCINT2_PORT PORTB
-#define PCINT2_BIT 2
-
-#define MISO_PORT PORTB
-#define MISO_BIT 3
-#define PCINT3_PORT PORTB
-#define PCINT3_BIT 3
-
-#define OC2_PORT PORTB
-#define OC2_BIT 4
-#define PCINT4_PORT PORTB
-#define PCINT4_BIT 4
-
-#define OC1A_PORT PORTB
-#define OC1A_BIT 5
-#define PCINT5_PORT PORTB
-#define PCINT5_BIT 5
-
-#define OC1B_PORT PORTB
-#define OC1B_BIT 6
-#define PCINT6_PORT PORTB
-#define PCINT6_BIT 6
-
-#define OC0A_PORT PORTB
-#define OC0A_BIT 7
-#define OC1C_PORT PORTB
-#define OC1C_BIT 7
-#define PCINT7_PORT PORTB
-#define PCINT7_BIT 7
-
-#define A8_PORT PORTC
-#define A8_BIT 0
-
-#define A9_PORT PORTC
-#define A9_BIT 1
-
-#define A10_PORT PORTC
-#define A10_BIT 2
-
-#define A11_PORT PORTC
-#define A11_BIT 3
-
-#define A12_PORT PORTC
-#define A12_BIT 4
-
-#define A13_PORT PORTC
-#define A13_BIT 5
-
-#define A14_PORT PORTC
-#define A14_BIT 6
-
-#define A15_PORT PORTC
-#define A15_BIT 7
-
-#define SCL_PORT PORTD
-#define SCL_BIT 0
-#define INT0_PORT PORTD
-#define INT0_BIT 0
-
-#define SDA_PORT PORTD
-#define SDA_BIT 1
-#define INT1_PORT PORTD
-#define INT1_BIT 1
-
-#define RXD1_PORT PORTD
-#define RXD1_BIT 2
-#define INT2_PORT PORTD
-#define INT2_BIT 2
-
-#define TXD1_PORT PORTD
-#define TXD1_BIT 3
-#define INT3_PORT PORTD
-#define INT3_BIT 3
-
-#define ICP1_PORT PORTD
-#define ICP1_BIT 4
-
-#define XCK1_PORT PORTD
-#define XCK1_BIT 5
-
-#define T1_PORT PORTD
-#define T1_BIT 6
-
-#define T0_PORT PORTD
-#define T0_BIT 7
-
-#define RXD0_PORT PORTE
-#define RXD0_BIT 0
-#define PDI_PORT PORTE
-#define PDI_BIT 0
-#define PCINT8_PORT PORTE
-#define PCINT8_BIT 0
-
-#define TXD0_PORT PORTE
-#define TXD0_BIT 1
-#define PDO_PORT PORTE
-#define PDO_BIT 1
-
-#define XCK0_PORT PORTE
-#define XCK0_BIT 2
-#define AIN0_PORT PORTE
-#define AIN0_BIT 2
-
-#define OC3A_PORT PORTE
-#define OC3A_BIT 3
-#define AIN1_PORT PORTE
-#define AIN1_BIT 3
-
-#define OC3B_PORT PORTE
-#define OC3B_BIT 4
-#define INT4_PORT PORTE
-#define INT4_BIT 4
-
-#define OC3C_PORT PORTE
-#define OC3C_BIT 5
-#define INT5_PORT PORTE
-#define INT5_BIT 5
-
-#define T3_PORT PORTE
-#define T3_BIT 6
-#define INT6_PORT PORTE
-#define INT6_BIT 6
-
-#define ICP3_PORT PORTE
-#define ICP3_BIT 7
-#define INT7_PORT PORTE
-#define INT7_BIT 7
-#define CLKO_PORT PORTE
-#define CLKO_BIT 7
-
-#define ADC0_PORT PORTF
-#define ADC0_BIT 0
-
-#define ADC1_PORT PORTF
-#define ADC1_BIT 1
-
-#define ADC2_PORT PORTF
-#define ADC2_BIT 2
-
-#define ADC3_PORT PORTF
-#define ADC3_BIT 3
-
-#define ADC4_PORT PORTF
-#define ADC4_BIT 4
-#define TCK_PORT PORTF
-#define TCK_BIT 4
-
-#define ADC5_PORT PORTF
-#define ADC5_BIT 5
-#define TMS_PORT PORTF
-#define TMS_BIT 5
-
-#define ADC6_PORT PORTF
-#define ADC6_BIT 6
-#define TD0_PORT PORTF
-#define TD0_BIT 6
-
-#define ADC7_PORT PORTF
-#define ADC7_BIT 7
-#define TDI_PORT PORTF
-#define TDI_BIT 7
-
-#define WR_PORT PORTG
-#define WR_BIT 0
-
-#define RD_PORT PORTG
-#define RD_BIT 1
-
-#define ALE_PORT PORTG
-#define ALE_BIT 2
-
-#define TOSC2_PORT PORTG
-#define TOSC2_BIT 3
-
-#define TOSC1_PORT PORTG
-#define TOSC1_BIT 4
-
-#define OC0B_PORT PORTG
-#define OC0B_BIT 5
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE1A_NUM 1
-#define SIG_OUTPUT_COMPARE1B_NUM 2
-#define SIG_OUTPUT_COMPARE2_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM1A_NUM 1
-#define PWM1B_NUM 2
-#define PWM2_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDTOE_REG WDTCR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* TCCR0 */
-#define CS00_REG TCCR0
-#define CS01_REG TCCR0
-#define CS02_REG TCCR0
-#define WGM01_REG TCCR0
-#define COM00_REG TCCR0
-#define COM01_REG TCCR0
-#define WGM00_REG TCCR0
-#define FOC0_REG TCCR0
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* GICR */
-#define IVCE_REG GICR
-#define IVSEL_REG GICR
-#define INT2_REG GICR
-#define INT0_REG GICR
-#define INT1_REG GICR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define FOC1B_REG TCCR1A
-#define FOC1A_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* GIFR */
-#define INTF2_REG GIFR
-#define INTF0_REG GIFR
-#define INTF1_REG GIFR
-
-/* TIMSK */
-#define TOIE0_REG TIMSK
-#define OCIE0_REG TIMSK
-#define TOIE2_REG TIMSK
-#define OCIE2_REG TIMSK
-#define TOIE1_REG TIMSK
-#define OCIE1B_REG TIMSK
-#define OCIE1A_REG TIMSK
-#define TICIE1_REG TIMSK
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* UCSRA */
-#define MPCM_REG UCSRA
-#define U2X_REG UCSRA
-#define UPE_REG UCSRA
-#define DOR_REG UCSRA
-#define FE_REG UCSRA
-#define UDRE_REG UCSRA
-#define TXC_REG UCSRA
-#define RXC_REG UCSRA
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SFIOR */
-#define ACME_REG SFIOR
-#define ADTS0_REG SFIOR
-#define ADTS1_REG SFIOR
-#define ADTS2_REG SFIOR
-#define PSR10_REG SFIOR
-#define PSR2_REG SFIOR
-#define PUD_REG SFIOR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* UCSRB */
-#define TXB8_REG UCSRB
-#define RXB8_REG UCSRB
-#define UCSZ2_REG UCSRB
-#define TXEN_REG UCSRB
-#define RXEN_REG UCSRB
-#define UDRIE_REG UCSRB
-#define TXCIE_REG UCSRB
-#define RXCIE_REG UCSRB
-
-/* UCSRC */
-#define UCPOL_REG UCSRC
-#define UCSZ0_REG UCSRC
-#define UCSZ1_REG UCSRC
-#define USBS_REG UCSRC
-#define UPM0_REG UCSRC
-#define UPM1_REG UCSRC
-#define UMSEL_REG UCSRC
-#define URSEL_REG UCSRC
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* UDR */
-#define UDR0_REG UDR
-#define UDR1_REG UDR
-#define UDR2_REG UDR
-#define UDR3_REG UDR
-#define UDR4_REG UDR
-#define UDR5_REG UDR
-#define UDR6_REG UDR
-#define UDR7_REG UDR
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* SPMCR */
-#define SPMEN_REG SPMCR
-#define PGERS_REG SPMCR
-#define PGWRT_REG SPMCR
-#define BLBSET_REG SPMCR
-#define RWWSRE_REG SPMCR
-#define RWWSB_REG SPMCR
-#define SPMIE_REG SPMCR
-
-/* UBRRH */
-#define UBRR8_REG UBRRH
-#define UBRR9_REG UBRRH
-#define UBRR10_REG UBRRH
-#define UBRR11_REG UBRRH
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* UBRRL */
-#define UBRR0_REG UBRRL
-#define UBRR1_REG UBRRL
-#define UBRR2_REG UBRRL
-#define UBRR3_REG UBRRL
-#define UBRR4_REG UBRRL
-#define UBRR5_REG UBRRL
-#define UBRR6_REG UBRRL
-#define UBRR7_REG UBRRL
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* MCUCSR */
-#define ISC2_REG MCUCSR
-#define PORF_REG MCUCSR
-#define EXTRF_REG MCUCSR
-#define BORF_REG MCUCSR
-#define WDRF_REG MCUCSR
-#define JTRF_REG MCUCSR
-#define JTD_REG MCUCSR
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* TCCR2 */
-#define CS20_REG TCCR2
-#define CS21_REG TCCR2
-#define CS22_REG TCCR2
-#define WGM21_REG TCCR2
-#define COM20_REG TCCR2
-#define COM21_REG TCCR2
-#define WGM20_REG TCCR2
-#define FOC2_REG TCCR2
-
-/* TIFR */
-#define TOV0_REG TIFR
-#define OCF0_REG TIFR
-#define TOV2_REG TIFR
-#define OCF2_REG TIFR
-#define TOV1_REG TIFR
-#define OCF1B_REG TIFR
-#define OCF1A_REG TIFR
-#define ICF1_REG TIFR
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* EEARL */
-#define EEAR00_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define ISC10_REG MCUCR
-#define ISC11_REG MCUCR
-#define SM0_REG MCUCR
-#define SM1_REG MCUCR
-#define SM2_REG MCUCR
-#define SE_REG MCUCR
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* ASSR */
-#define TCR2UB_REG ASSR
-#define OCR2UB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-
-/* OCR0 */
-#define OCR0_0_REG OCR0
-#define OCR0_1_REG OCR0
-#define OCR0_2_REG OCR0
-#define OCR0_3_REG OCR0
-#define OCR0_4_REG OCR0
-#define OCR0_5_REG OCR0
-#define OCR0_6_REG OCR0
-#define OCR0_7_REG OCR0
-
-/* OCR2 */
-#define OCR2_0_REG OCR2
-#define OCR2_1_REG OCR2
-#define OCR2_2_REG OCR2
-#define OCR2_3_REG OCR2
-#define OCR2_4_REG OCR2
-#define OCR2_5_REG OCR2
-#define OCR2_6_REG OCR2
-#define OCR2_7_REG OCR2
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* pins mapping */
-#define ADC0_PORT PORTA
-#define ADC0_BIT 0
-
-#define ADC1_PORT PORTA
-#define ADC1_BIT 1
-
-#define ADC2_PORT PORTA
-#define ADC2_BIT 2
-
-#define ADC3_PORT PORTA
-#define ADC3_BIT 3
-
-#define ADC4_PORT PORTA
-#define ADC4_BIT 4
-
-#define ADc5_PORT PORTA
-#define ADc5_BIT 5
-
-#define ADC6_PORT PORTA
-#define ADC6_BIT 6
-
-#define ADC7_PORT PORTA
-#define ADC7_BIT 7
-
-#define XCK_PORT PORTB
-#define XCK_BIT 0
-#define T0_PORT PORTB
-#define T0_BIT 0
-
-#define T1_PORT PORTB
-#define T1_BIT 1
-
-#define AIN0_PORT PORTB
-#define AIN0_BIT 2
-#define INT2_PORT PORTB
-#define INT2_BIT 2
-
-#define AIN1_PORT PORTB
-#define AIN1_BIT 3
-#define OC0_PORT PORTB
-#define OC0_BIT 3
-
-#define SS_PORT PORTB
-#define SS_BIT 4
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 5
-
-#define MISO_PORT PORTB
-#define MISO_BIT 6
-
-
-#define SCL_PORT PORTC
-#define SCL_BIT 0
-
-#define SDA_PORT PORTC
-#define SDA_BIT 1
-
-#define TMS_PORT PORTC
-#define TMS_BIT 2
-
-#define TCK_PORT PORTC
-#define TCK_BIT 3
-
-#define TDO_PORT PORTC
-#define TDO_BIT 4
-
-#define TDI_PORT PORTC
-#define TDI_BIT 5
-
-#define TOSC1_PORT PORTC
-#define TOSC1_BIT 6
-
-#define TOSC2_PORT PORTC
-#define TOSC2_BIT 7
-
-#define RXD_PORT PORTD
-#define RXD_BIT 0
-
-#define TXD_PORT PORTD
-#define TXD_BIT 1
-
-#define INT0_PORT PORTD
-#define INT0_BIT 2
-
-#define INT1_PORT PORTD
-#define INT1_BIT 3
-
-#define OC1B_PORT PORTD
-#define OC1B_BIT 4
-
-#define OC1A_PORT PORTD
-#define OC1A_BIT 5
-
-#define ICP_PORT PORTD
-#define ICP_BIT 6
-
-#define OC2_PORT PORTD
-#define OC2_BIT 7
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE1A_NUM 1
-#define SIG_OUTPUT_COMPARE1B_NUM 2
-#define SIG_OUTPUT_COMPARE2_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM1A_NUM 1
-#define PWM1B_NUM 2
-#define PWM2_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDTOE_REG WDTCR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* TCCR0 */
-#define CS00_REG TCCR0
-#define CS01_REG TCCR0
-#define CS02_REG TCCR0
-#define WGM01_REG TCCR0
-#define COM00_REG TCCR0
-#define COM01_REG TCCR0
-#define PWM0_REG TCCR0
-#define FOC0_REG TCCR0
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* GICR */
-#define IVCE_REG GICR
-#define IVSEL_REG GICR
-#define INT2_REG GICR
-#define INT0_REG GICR
-#define INT1_REG GICR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define FOC1B_REG TCCR1A
-#define FOC1A_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define CTC1_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* GIFR */
-#define INTF2_REG GIFR
-#define INTF0_REG GIFR
-#define INTF1_REG GIFR
-
-/* TIMSK */
-#define TOIE0_REG TIMSK
-#define OCIE0_REG TIMSK
-#define TOIE1_REG TIMSK
-#define OCIE1B_REG TIMSK
-#define OCIE1A_REG TIMSK
-#define TICIE1_REG TIMSK
-#define TOIE2_REG TIMSK
-#define OCIE2_REG TIMSK
-
-/* UCSRA */
-#define MPCM_REG UCSRA
-#define U2X_REG UCSRA
-#define UPE_REG UCSRA
-#define DOR_REG UCSRA
-#define FE_REG UCSRA
-#define UDRE_REG UCSRA
-#define TXC_REG UCSRA
-#define RXC_REG UCSRA
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SFIOR */
-#define ACME_REG SFIOR
-#define PSR10_REG SFIOR
-#define PSR2_REG SFIOR
-#define PUD_REG SFIOR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* UCSRB */
-#define TXB8_REG UCSRB
-#define RXB8_REG UCSRB
-#define UCSZ2_REG UCSRB
-#define TXEN_REG UCSRB
-#define RXEN_REG UCSRB
-#define UDRIE_REG UCSRB
-#define TXCIE_REG UCSRB
-#define RXCIE_REG UCSRB
-
-/* UCSRC */
-#define UCPOL_REG UCSRC
-#define UCSZ0_REG UCSRC
-#define UCSZ1_REG UCSRC
-#define USBS_REG UCSRC
-#define UPM0_REG UCSRC
-#define UPM1_REG UCSRC
-#define UMSEL_REG UCSRC
-#define URSEL_REG UCSRC
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* UDR */
-#define UDR0_REG UDR
-#define UDR1_REG UDR
-#define UDR2_REG UDR
-#define UDR3_REG UDR
-#define UDR4_REG UDR
-#define UDR5_REG UDR
-#define UDR6_REG UDR
-#define UDR7_REG UDR
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* SPMCR */
-#define SPMEN_REG SPMCR
-#define PGERS_REG SPMCR
-#define PGWRT_REG SPMCR
-#define BLBSET_REG SPMCR
-#define ASRE_REG SPMCR
-#define ASB_REG SPMCR
-
-/* UBRRH */
-#define UBRR8_REG UBRRH
-#define UBRR9_REG UBRRH
-#define UBRR10_REG UBRRH
-#define UBRR11_REG UBRRH
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* UBRRL */
-#define UBRR0_REG UBRRL
-#define UBRR1_REG UBRRL
-#define UBRR2_REG UBRRL
-#define UBRR3_REG UBRRL
-#define UBRR4_REG UBRRL
-#define UBRR5_REG UBRRL
-#define UBRR6_REG UBRRL
-#define UBRR7_REG UBRRL
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* MCUCSR */
-#define PORF_REG MCUCSR
-#define EXTRF_REG MCUCSR
-#define BORF_REG MCUCSR
-#define WDRF_REG MCUCSR
-#define JTRF_REG MCUCSR
-#define ISC2_REG MCUCSR
-#define JDT_REG MCUCSR
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* ADCSR */
-#define ADPS0_REG ADCSR
-#define ADPS1_REG ADCSR
-#define ADPS2_REG ADCSR
-#define ADIE_REG ADCSR
-#define ADIF_REG ADCSR
-#define ADATE_REG ADCSR
-#define ADSC_REG ADCSR
-#define ADEN_REG ADCSR
-
-/* TCCR2 */
-#define CS20_REG TCCR2
-#define CS21_REG TCCR2
-#define CS22_REG TCCR2
-#define CTC2_REG TCCR2
-#define COM20_REG TCCR2
-#define COM21_REG TCCR2
-#define PWM2_REG TCCR2
-#define FOC2_REG TCCR2
-
-/* TIFR */
-#define TOV0_REG TIFR
-#define OCF0_REG TIFR
-#define TOV1_REG TIFR
-#define OCF1B_REG TIFR
-#define OCF1A_REG TIFR
-#define ICF1_REG TIFR
-#define TOV2_REG TIFR
-#define OCF2_REG TIFR
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* EEARL */
-#define EEAR00_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* TWSR */
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define ISC10_REG MCUCR
-#define ISC11_REG MCUCR
-#define SM0_REG MCUCR
-#define SM1_REG MCUCR
-#define SM2_REG MCUCR
-#define SE_REG MCUCR
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* ASSR */
-#define TCR2UB_REG ASSR
-#define OCR2UB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-
-/* OCR0 */
-#define OCR0_0_REG OCR0
-#define OCR0_1_REG OCR0
-#define OCR0_2_REG OCR0
-#define OCR0_3_REG OCR0
-#define OCR0_4_REG OCR0
-#define OCR0_5_REG OCR0
-#define OCR0_6_REG OCR0
-#define OCR0_7_REG OCR0
-
-/* OCR2 */
-#define OCR2_0_REG OCR2
-#define OCR2_1_REG OCR2
-#define OCR2_2_REG OCR2
-#define OCR2_3_REG OCR2
-#define OCR2_4_REG OCR2
-#define OCR2_5_REG OCR2
-#define OCR2_6_REG OCR2
-#define OCR2_7_REG OCR2
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* pins mapping */
-#define ADC0_PORT PORTA
-#define ADC0_BIT 0
-
-#define ADC1_PORT PORTA
-#define ADC1_BIT 1
-
-#define ADC2_PORT PORTA
-#define ADC2_BIT 2
-
-#define ADC3_PORT PORTA
-#define ADC3_BIT 3
-
-#define ADC4_PORT PORTA
-#define ADC4_BIT 4
-
-#define ADc5_PORT PORTA
-#define ADc5_BIT 5
-
-#define ADC6_PORT PORTA
-#define ADC6_BIT 6
-
-#define ADC7_PORT PORTA
-#define ADC7_BIT 7
-
-#define XCK_PORT PORTB
-#define XCK_BIT 0
-#define T0_PORT PORTB
-#define T0_BIT 0
-
-#define T1_PORT PORTB
-#define T1_BIT 1
-
-#define AIN0_PORT PORTB
-#define AIN0_BIT 2
-#define INT2_PORT PORTB
-#define INT2_BIT 2
-
-#define AIN1_PORT PORTB
-#define AIN1_BIT 3
-#define OC0_PORT PORTB
-#define OC0_BIT 3
-
-#define SS_PORT PORTB
-#define SS_BIT 4
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 5
-
-#define MISO_PORT PORTB
-#define MISO_BIT 6
-
-
-#define SCL_PORT PORTC
-#define SCL_BIT 0
-
-#define SDA_PORT PORTC
-#define SDA_BIT 1
-
-#define TMS_PORT PORTC
-#define TMS_BIT 2
-
-#define TCK_PORT PORTC
-#define TCK_BIT 3
-
-#define TDO_PORT PORTC
-#define TDO_BIT 4
-
-#define TDI_PORT PORTC
-#define TDI_BIT 5
-
-#define TOSC1_PORT PORTC
-#define TOSC1_BIT 6
-
-#define TOSC2_PORT PORTC
-#define TOSC2_BIT 7
-
-#define RXD_PORT PORTD
-#define RXD_BIT 0
-
-#define TXD_PORT PORTD
-#define TXD_BIT 1
-
-#define INT0_PORT PORTD
-#define INT0_BIT 2
-
-#define INT1_PORT PORTD
-#define INT1_BIT 3
-
-#define OC1B_PORT PORTD
-#define OC1B_BIT 4
-
-#define OC1A_PORT PORTD
-#define OC1A_BIT 5
-
-#define ICP_PORT PORTD
-#define ICP_BIT 6
-
-#define OC2_PORT PORTD
-#define OC2_BIT 7
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-#define TIMER2A_AVAILABLE
-#define TIMER2B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE2A_NUM 4
-#define SIG_OUTPUT_COMPARE2B_NUM 5
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 6
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM2A_NUM 4
-#define PWM2B_NUM 5
-#define PWM_TOTAL_NUM 6
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* SPCR0 */
-#define SPR00_REG SPCR0
-#define SPR10_REG SPCR0
-#define CPHA0_REG SPCR0
-#define CPOL0_REG SPCR0
-#define MSTR0_REG SPCR0
-#define DORD0_REG SPCR0
-#define SPE0_REG SPCR0
-#define SPIE0_REG SPCR0
-
-/* RAMPZ */
-#define RAMPZ0_REG RAMPZ
-
-/* OCR2B */
-#define OCR2B_0_REG OCR2B
-#define OCR2B_1_REG OCR2B
-#define OCR2B_2_REG OCR2B
-#define OCR2B_3_REG OCR2B
-#define OCR2B_4_REG OCR2B
-#define OCR2B_5_REG OCR2B
-#define OCR2B_6_REG OCR2B
-#define OCR2B_7_REG OCR2B
-
-/* OCR2A */
-#define OCR2A_0_REG OCR2A
-#define OCR2A_1_REG OCR2A
-#define OCR2A_2_REG OCR2A
-#define OCR2A_3_REG OCR2A
-#define OCR2A_4_REG OCR2A
-#define OCR2A_5_REG OCR2A
-#define OCR2A_6_REG OCR2A
-#define OCR2A_7_REG OCR2A
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL00_REG UCSR0C
-#define UMSEL01_REG UCSR0C
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* UDR1 */
-#define UDR1_0_REG UDR1
-#define UDR1_1_REG UDR1
-#define UDR1_2_REG UDR1
-#define UDR1_3_REG UDR1
-#define UDR1_4_REG UDR1
-#define UDR1_5_REG UDR1
-#define UDR1_6_REG UDR1
-#define UDR1_7_REG UDR1
-
-/* UDR0 */
-#define UDR0_0_REG UDR0
-#define UDR0_1_REG UDR0
-#define UDR0_2_REG UDR0
-#define UDR0_3_REG UDR0
-#define UDR0_4_REG UDR0
-#define UDR0_5_REG UDR0
-#define UDR0_6_REG UDR0
-#define UDR0_7_REG UDR0
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-#define ISC20_REG EICRA
-#define ISC21_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* SPDR0 */
-#define SPDRB0_REG SPDR0
-#define SPDRB1_REG SPDR0
-#define SPDRB2_REG SPDR0
-#define SPDRB3_REG SPDR0
-#define SPDRB4_REG SPDR0
-#define SPDRB5_REG SPDR0
-#define SPDRB6_REG SPDR0
-#define SPDRB7_REG SPDR0
-
-/* ASSR */
-#define TCR2BUB_REG ASSR
-#define TCR2AUB_REG ASSR
-#define OCR2BUB_REG ASSR
-#define OCR2AUB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* UBRR1L */
-#define UBRR_0_REG UBRR1L
-#define UBRR_1_REG UBRR1L
-#define UBRR_2_REG UBRR1L
-#define UBRR_3_REG UBRR1L
-#define UBRR_4_REG UBRR1L
-#define UBRR_5_REG UBRR1L
-#define UBRR_6_REG UBRR1L
-#define UBRR_7_REG UBRR1L
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* UBRR1H */
-#define UBRR_8_REG UBRR1H
-#define UBRR_9_REG UBRR1H
-#define UBRR_10_REG UBRR1H
-#define UBRR_11_REG UBRR1H
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* SPSR0 */
-#define SPI2X0_REG SPSR0
-#define WCOL0_REG SPSR0
-#define SPIF0_REG SPSR0
-
-/* PCICR */
-#define PCIE0_REG PCICR
-#define PCIE1_REG PCICR
-#define PCIE2_REG PCICR
-#define PCIE3_REG PCICR
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-#define OCF2B_REG TIFR2
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* GTCCR */
-#define PSRSYNC_REG GTCCR
-#define TSM_REG GTCCR
-#define PSRASY_REG GTCCR
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* OCR1BL */
-/* #define OCR1AL0_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL1_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL2_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL3_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL4_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL5_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL6_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL7_REG OCR1BL */ /* dup in OCR1AL */
-
-/* PCIFR */
-#define PCIF0_REG PCIFR
-#define PCIF1_REG PCIFR
-#define PCIF2_REG PCIFR
-#define PCIF3_REG PCIFR
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* OCR1BH */
-/* #define OCR1AH0_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH1_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH2_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH3_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH4_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH5_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH6_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH7_REG OCR1BH */ /* dup in OCR1AH */
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* TCCR2A */
-#define WGM20_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2B0_REG TCCR2A
-#define COM2B1_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-
-/* TCCR2B */
-#define CS20_REG TCCR2B
-#define CS21_REG TCCR2B
-#define CS22_REG TCCR2B
-#define WGM22_REG TCCR2B
-#define FOC2B_REG TCCR2B
-#define FOC2A_REG TCCR2B
-
-/* UBRR0H */
-#define UBRR8_REG UBRR0H
-#define UBRR9_REG UBRR0H
-#define UBRR10_REG UBRR0H
-#define UBRR11_REG UBRR0H
-
-/* UBRR0L */
-#define UBRR0_REG UBRR0L
-#define UBRR1_REG UBRR0L
-#define UBRR2_REG UBRR0L
-#define UBRR3_REG UBRR0L
-#define UBRR4_REG UBRR0L
-#define UBRR5_REG UBRR0L
-#define UBRR6_REG UBRR0L
-#define UBRR7_REG UBRR0L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-#define EEAR10_REG EEARH
-#define EEAR11_REG EEARH
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* MCUCR */
-#define JTD_REG MCUCR
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-#define BODSE_REG MCUCR
-#define BODS_REG MCUCR
-
-/* MCUSR */
-#define JTRF_REG MCUSR
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* UCSR1B */
-#define TXB81_REG UCSR1B
-#define RXB81_REG UCSR1B
-#define UCSZ12_REG UCSR1B
-#define TXEN1_REG UCSR1B
-#define RXEN1_REG UCSR1B
-#define UDRIE1_REG UCSR1B
-#define TXCIE1_REG UCSR1B
-#define RXCIE1_REG UCSR1B
-
-/* UCSR1C */
-#define UCPOL1_REG UCSR1C
-#define UCSZ10_REG UCSR1C
-#define UCSZ11_REG UCSR1C
-#define USBS1_REG UCSR1C
-#define UPM10_REG UCSR1C
-#define UPM11_REG UCSR1C
-#define UMSEL10_REG UCSR1C
-#define UMSEL11_REG UCSR1C
-
-/* UCSR1A */
-#define MPCM1_REG UCSR1A
-#define U2X1_REG UCSR1A
-#define UPE1_REG UCSR1A
-#define DOR1_REG UCSR1A
-#define FE1_REG UCSR1A
-#define UDRE1_REG UCSR1A
-#define TXC1_REG UCSR1A
-#define RXC1_REG UCSR1A
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* TWAMR */
-#define TWAM0_REG TWAMR
-#define TWAM1_REG TWAMR
-#define TWAM2_REG TWAMR
-#define TWAM3_REG TWAMR
-#define TWAM4_REG TWAMR
-#define TWAM5_REG TWAMR
-#define TWAM6_REG TWAMR
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ACME_REG ADCSRB
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-
-/* PRR0 */
-#define PRADC_REG PRR0
-#define PRUSART0_REG PRR0
-#define PRSPI_REG PRR0
-#define PRTIM1_REG PRR0
-#define PRUSART1_REG PRR0
-#define PRTIM0_REG PRR0
-#define PRTIM2_REG PRR0
-#define PRTWI_REG PRR0
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* OCR0A */
-#define OCROA_0_REG OCR0A
-#define OCROA_1_REG OCR0A
-#define OCROA_2_REG OCR0A
-#define OCROA_3_REG OCR0A
-#define OCROA_4_REG OCR0A
-#define OCROA_5_REG OCR0A
-#define OCROA_6_REG OCR0A
-#define OCROA_7_REG OCR0A
-
-/* OCR0B */
-#define OCR0B_0_REG OCR0B
-#define OCR0B_1_REG OCR0B
-#define OCR0B_2_REG OCR0B
-#define OCR0B_3_REG OCR0B
-#define OCR0B_4_REG OCR0B
-#define OCR0B_5_REG OCR0B
-#define OCR0B_6_REG OCR0B
-#define OCR0B_7_REG OCR0B
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define SIGRD_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-#define OCIE2B_REG TIMSK2
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-#define PCINT15_REG PCMSK1
-
-/* PCMSK2 */
-#define PCINT16_REG PCMSK2
-#define PCINT17_REG PCMSK2
-#define PCINT18_REG PCMSK2
-#define PCINT19_REG PCMSK2
-#define PCINT20_REG PCMSK2
-#define PCINT21_REG PCMSK2
-#define PCINT22_REG PCMSK2
-#define PCINT23_REG PCMSK2
-
-/* PCMSK3 */
-#define PCINT24_REG PCMSK3
-#define PCINT25_REG PCMSK3
-#define PCINT26_REG PCMSK3
-#define PCINT27_REG PCMSK3
-#define PCINT28_REG PCMSK3
-#define PCINT29_REG PCMSK3
-#define PCINT30_REG PCMSK3
-#define PCINT31_REG PCMSK3
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-#define INTF2_REG EIFR
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-/* #define OCR1AH0_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH1_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH2_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH3_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH4_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH5_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH6_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH7_REG OCR1AH */ /* dup in OCR1BH */
-
-/* OCR1AL */
-/* #define OCR1AL0_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL1_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL2_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL3_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL4_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL5_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL6_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL7_REG OCR1AL */ /* dup in OCR1BL */
-
-/* pins mapping */
-#define ADC0_PORT PORTA
-#define ADC0_BIT 0
-#define PCINT0_PORT PORTA
-#define PCINT0_BIT 0
-
-#define ADC1_PORT PORTA
-#define ADC1_BIT 1
-#define PCINT1_PORT PORTA
-#define PCINT1_BIT 1
-
-#define ADC2_PORT PORTA
-#define ADC2_BIT 2
-#define PCINT2_PORT PORTA
-#define PCINT2_BIT 2
-
-#define ADC3_PORT PORTA
-#define ADC3_BIT 3
-#define PCINT3_PORT PORTA
-#define PCINT3_BIT 3
-
-#define ADC4_PORT PORTA
-#define ADC4_BIT 4
-#define PCINT4_PORT PORTA
-#define PCINT4_BIT 4
-
-#define ADC5_PORT PORTA
-#define ADC5_BIT 5
-#define PCINT5_PORT PORTA
-#define PCINT5_BIT 5
-
-#define ADC6_PORT PORTA
-#define ADC6_BIT 6
-#define PCINT6_PORT PORTA
-#define PCINT6_BIT 6
-
-#define ADC7_PORT PORTA
-#define ADC7_BIT 7
-#define PCINT7_PORT PORTA
-#define PCINT7_BIT 7
-
-#define XCK_PORT PORTB
-#define XCK_BIT 0
-#define T0_PORT PORTB
-#define T0_BIT 0
-#define PCINT9_PORT PORTB
-#define PCINT9_BIT 0
-
-#define T1_PORT PORTB
-#define T1_BIT 1
-#define CLKO_PORT PORTB
-#define CLKO_BIT 1
-#define PCINT9_PORT PORTB
-#define PCINT9_BIT 1
-
-#define AIN0_PORT PORTB
-#define AIN0_BIT 2
-#define INT2_PORT PORTB
-#define INT2_BIT 2
-#define PCINT10_PORT PORTB
-#define PCINT10_BIT 2
-
-#define AIN1_PORT PORTB
-#define AIN1_BIT 3
-#define OC0A_PORT PORTB
-#define OC0A_BIT 3
-#define PCINT11_PORT PORTB
-#define PCINT11_BIT 3
-
-#define SS_PORT PORTB
-#define SS_BIT 4
-#define OC0B_PORT PORTB
-#define OC0B_BIT 4
-#define PCINT12_PORT PORTB
-#define PCINT12_BIT 4
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 5
-#define PCINT13_PORT PORTB
-#define PCINT13_BIT 5
-
-#define MISO_PORT PORTB
-#define MISO_BIT 6
-#define PCINT14_PORT PORTB
-#define PCINT14_BIT 6
-
-#define SCK_PORT PORTB
-#define SCK_BIT 7
-#define PCINT15_PORT PORTB
-#define PCINT15_BIT 7
-
-#define SCL_PORT PORTC
-#define SCL_BIT 0
-#define PCINT16_PORT PORTC
-#define PCINT16_BIT 0
-
-#define SDA_PORT PORTC
-#define SDA_BIT 1
-#define PCINT17_PORT PORTC
-#define PCINT17_BIT 1
-
-#define TCK_PORT PORTC
-#define TCK_BIT 2
-#define PCINT18_PORT PORTC
-#define PCINT18_BIT 2
-
-#define TMS_PORT PORTC
-#define TMS_BIT 3
-#define PCINT19_PORT PORTC
-#define PCINT19_BIT 3
-
-#define TDO_PORT PORTC
-#define TDO_BIT 4
-#define PCINT20_PORT PORTC
-#define PCINT20_BIT 4
-
-#define TDI_PORT PORTC
-#define TDI_BIT 5
-#define PCINT21_PORT PORTC
-#define PCINT21_BIT 5
-
-#define TOSC1_PORT PORTC
-#define TOSC1_BIT 6
-#define PCINT22_PORT PORTC
-#define PCINT22_BIT 6
-
-#define TOSC2_PORT PORTC
-#define TOSC2_BIT 7
-#define PCINT23_PORT PORTC
-#define PCINT23_BIT 7
-
-#define RXD_PORT PORTD
-#define RXD_BIT 0
-#define PCINT24_PORT PORTD
-#define PCINT24_BIT 0
-
-#define TXD_PORT PORTD
-#define TXD_BIT 1
-#define PCINT25_PORT PORTD
-#define PCINT25_BIT 1
-
-#define INT0_PORT PORTD
-#define INT0_BIT 2
-#define PCINT26_PORT PORTD
-#define PCINT26_BIT 2
-
-#define INT1_PORT PORTD
-#define INT1_BIT 3
-#define PCINT27_PORT PORTD
-#define PCINT27_BIT 3
-
-#define OC1B_PORT PORTD
-#define OC1B_BIT 4
-#define PCINT28_PORT PORTD
-#define PCINT28_BIT 4
-
-#define OC1A_PORT PORTD
-#define OC1A_BIT 5
-#define PCINT29_PORT PORTD
-#define PCINT29_BIT 5
-
-#define ICP_PORT PORTD
-#define ICP_BIT 6
-#define OC2B_PORT PORTD
-#define OC2B_BIT 6
-#define PCINT30_PORT PORTD
-#define PCINT30_BIT 6
-
-#define OC2A_PORT PORTD
-#define OC2A_BIT 7
-#define PCINT31_PORT PORTD
-#define PCINT31_BIT 7
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-#define TIMER2A_AVAILABLE
-#define TIMER2B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE2A_NUM 4
-#define SIG_OUTPUT_COMPARE2B_NUM 5
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 6
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM2A_NUM 4
-#define PWM2B_NUM 5
-#define PWM_TOTAL_NUM 6
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* SPCR0 */
-#define SPR00_REG SPCR0
-#define SPR10_REG SPCR0
-#define CPHA0_REG SPCR0
-#define CPOL0_REG SPCR0
-#define MSTR0_REG SPCR0
-#define DORD0_REG SPCR0
-#define SPE0_REG SPCR0
-#define SPIE0_REG SPCR0
-
-/* RAMPZ */
-#define RAMPZ0_REG RAMPZ
-
-/* OCR2B */
-#define OCR2B_0_REG OCR2B
-#define OCR2B_1_REG OCR2B
-#define OCR2B_2_REG OCR2B
-#define OCR2B_3_REG OCR2B
-#define OCR2B_4_REG OCR2B
-#define OCR2B_5_REG OCR2B
-#define OCR2B_6_REG OCR2B
-#define OCR2B_7_REG OCR2B
-
-/* OCR2A */
-#define OCR2A_0_REG OCR2A
-#define OCR2A_1_REG OCR2A
-#define OCR2A_2_REG OCR2A
-#define OCR2A_3_REG OCR2A
-#define OCR2A_4_REG OCR2A
-#define OCR2A_5_REG OCR2A
-#define OCR2A_6_REG OCR2A
-#define OCR2A_7_REG OCR2A
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL00_REG UCSR0C
-#define UMSEL01_REG UCSR0C
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* UDR1 */
-#define UDR1_0_REG UDR1
-#define UDR1_1_REG UDR1
-#define UDR1_2_REG UDR1
-#define UDR1_3_REG UDR1
-#define UDR1_4_REG UDR1
-#define UDR1_5_REG UDR1
-#define UDR1_6_REG UDR1
-#define UDR1_7_REG UDR1
-
-/* UDR0 */
-#define UDR0_0_REG UDR0
-#define UDR0_1_REG UDR0
-#define UDR0_2_REG UDR0
-#define UDR0_3_REG UDR0
-#define UDR0_4_REG UDR0
-#define UDR0_5_REG UDR0
-#define UDR0_6_REG UDR0
-#define UDR0_7_REG UDR0
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-#define ISC20_REG EICRA
-#define ISC21_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* SPDR0 */
-#define SPDRB0_REG SPDR0
-#define SPDRB1_REG SPDR0
-#define SPDRB2_REG SPDR0
-#define SPDRB3_REG SPDR0
-#define SPDRB4_REG SPDR0
-#define SPDRB5_REG SPDR0
-#define SPDRB6_REG SPDR0
-#define SPDRB7_REG SPDR0
-
-/* ASSR */
-#define TCR2BUB_REG ASSR
-#define TCR2AUB_REG ASSR
-#define OCR2BUB_REG ASSR
-#define OCR2AUB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* UBRR1L */
-#define UBRR_0_REG UBRR1L
-#define UBRR_1_REG UBRR1L
-#define UBRR_2_REG UBRR1L
-#define UBRR_3_REG UBRR1L
-#define UBRR_4_REG UBRR1L
-#define UBRR_5_REG UBRR1L
-#define UBRR_6_REG UBRR1L
-#define UBRR_7_REG UBRR1L
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* UBRR1H */
-#define UBRR_8_REG UBRR1H
-#define UBRR_9_REG UBRR1H
-#define UBRR_10_REG UBRR1H
-#define UBRR_11_REG UBRR1H
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* SPSR0 */
-#define SPI2X0_REG SPSR0
-#define WCOL0_REG SPSR0
-#define SPIF0_REG SPSR0
-
-/* PCICR */
-#define PCIE0_REG PCICR
-#define PCIE1_REG PCICR
-#define PCIE2_REG PCICR
-#define PCIE3_REG PCICR
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-#define OCF2B_REG TIFR2
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* GTCCR */
-#define PSRSYNC_REG GTCCR
-#define TSM_REG GTCCR
-#define PSRASY_REG GTCCR
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* OCR1BL */
-/* #define OCR1AL0_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL1_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL2_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL3_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL4_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL5_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL6_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL7_REG OCR1BL */ /* dup in OCR1AL */
-
-/* PCIFR */
-#define PCIF0_REG PCIFR
-#define PCIF1_REG PCIFR
-#define PCIF2_REG PCIFR
-#define PCIF3_REG PCIFR
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* OCR1BH */
-/* #define OCR1AH0_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH1_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH2_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH3_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH4_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH5_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH6_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH7_REG OCR1BH */ /* dup in OCR1AH */
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* TCCR2A */
-#define WGM20_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2B0_REG TCCR2A
-#define COM2B1_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-
-/* TCCR2B */
-#define CS20_REG TCCR2B
-#define CS21_REG TCCR2B
-#define CS22_REG TCCR2B
-#define WGM22_REG TCCR2B
-#define FOC2B_REG TCCR2B
-#define FOC2A_REG TCCR2B
-
-/* UBRR0H */
-#define UBRR8_REG UBRR0H
-#define UBRR9_REG UBRR0H
-#define UBRR10_REG UBRR0H
-#define UBRR11_REG UBRR0H
-
-/* UBRR0L */
-#define UBRR0_REG UBRR0L
-#define UBRR1_REG UBRR0L
-#define UBRR2_REG UBRR0L
-#define UBRR3_REG UBRR0L
-#define UBRR4_REG UBRR0L
-#define UBRR5_REG UBRR0L
-#define UBRR6_REG UBRR0L
-#define UBRR7_REG UBRR0L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-#define EEAR10_REG EEARH
-#define EEAR11_REG EEARH
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* MCUCR */
-#define JTD_REG MCUCR
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-#define BODSE_REG MCUCR
-#define BODS_REG MCUCR
-
-/* MCUSR */
-#define JTRF_REG MCUSR
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* UCSR1B */
-#define TXB81_REG UCSR1B
-#define RXB81_REG UCSR1B
-#define UCSZ12_REG UCSR1B
-#define TXEN1_REG UCSR1B
-#define RXEN1_REG UCSR1B
-#define UDRIE1_REG UCSR1B
-#define TXCIE1_REG UCSR1B
-#define RXCIE1_REG UCSR1B
-
-/* UCSR1C */
-#define UCPOL1_REG UCSR1C
-#define UCSZ10_REG UCSR1C
-#define UCSZ11_REG UCSR1C
-#define USBS1_REG UCSR1C
-#define UPM10_REG UCSR1C
-#define UPM11_REG UCSR1C
-#define UMSEL10_REG UCSR1C
-#define UMSEL11_REG UCSR1C
-
-/* UCSR1A */
-#define MPCM1_REG UCSR1A
-#define U2X1_REG UCSR1A
-#define UPE1_REG UCSR1A
-#define DOR1_REG UCSR1A
-#define FE1_REG UCSR1A
-#define UDRE1_REG UCSR1A
-#define TXC1_REG UCSR1A
-#define RXC1_REG UCSR1A
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* TWAMR */
-#define TWAM0_REG TWAMR
-#define TWAM1_REG TWAMR
-#define TWAM2_REG TWAMR
-#define TWAM3_REG TWAMR
-#define TWAM4_REG TWAMR
-#define TWAM5_REG TWAMR
-#define TWAM6_REG TWAMR
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ACME_REG ADCSRB
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-
-/* PRR0 */
-#define PRADC_REG PRR0
-#define PRUSART0_REG PRR0
-#define PRSPI_REG PRR0
-#define PRTIM1_REG PRR0
-#define PRUSART1_REG PRR0
-#define PRTIM0_REG PRR0
-#define PRTIM2_REG PRR0
-#define PRTWI_REG PRR0
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* OCR0A */
-#define OCROA_0_REG OCR0A
-#define OCROA_1_REG OCR0A
-#define OCROA_2_REG OCR0A
-#define OCROA_3_REG OCR0A
-#define OCROA_4_REG OCR0A
-#define OCROA_5_REG OCR0A
-#define OCROA_6_REG OCR0A
-#define OCROA_7_REG OCR0A
-
-/* OCR0B */
-#define OCR0B_0_REG OCR0B
-#define OCR0B_1_REG OCR0B
-#define OCR0B_2_REG OCR0B
-#define OCR0B_3_REG OCR0B
-#define OCR0B_4_REG OCR0B
-#define OCR0B_5_REG OCR0B
-#define OCR0B_6_REG OCR0B
-#define OCR0B_7_REG OCR0B
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define SIGRD_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-#define OCIE2B_REG TIMSK2
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-#define PCINT15_REG PCMSK1
-
-/* PCMSK2 */
-#define PCINT16_REG PCMSK2
-#define PCINT17_REG PCMSK2
-#define PCINT18_REG PCMSK2
-#define PCINT19_REG PCMSK2
-#define PCINT20_REG PCMSK2
-#define PCINT21_REG PCMSK2
-#define PCINT22_REG PCMSK2
-#define PCINT23_REG PCMSK2
-
-/* PCMSK3 */
-#define PCINT24_REG PCMSK3
-#define PCINT25_REG PCMSK3
-#define PCINT26_REG PCMSK3
-#define PCINT27_REG PCMSK3
-#define PCINT28_REG PCMSK3
-#define PCINT29_REG PCMSK3
-#define PCINT30_REG PCMSK3
-#define PCINT31_REG PCMSK3
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-#define INTF2_REG EIFR
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-/* #define OCR1AH0_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH1_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH2_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH3_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH4_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH5_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH6_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH7_REG OCR1AH */ /* dup in OCR1BH */
-
-/* OCR1AL */
-/* #define OCR1AL0_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL1_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL2_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL3_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL4_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL5_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL6_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL7_REG OCR1AL */ /* dup in OCR1BL */
-
-/* pins mapping */
-#define ADC0_PORT PORTA
-#define ADC0_BIT 0
-#define PCINT0_PORT PORTA
-#define PCINT0_BIT 0
-
-#define ADC1_PORT PORTA
-#define ADC1_BIT 1
-#define PCINT1_PORT PORTA
-#define PCINT1_BIT 1
-
-#define ADC2_PORT PORTA
-#define ADC2_BIT 2
-#define PCINT2_PORT PORTA
-#define PCINT2_BIT 2
-
-#define ADC3_PORT PORTA
-#define ADC3_BIT 3
-#define PCINT3_PORT PORTA
-#define PCINT3_BIT 3
-
-#define ADC4_PORT PORTA
-#define ADC4_BIT 4
-#define PCINT4_PORT PORTA
-#define PCINT4_BIT 4
-
-#define ADC5_PORT PORTA
-#define ADC5_BIT 5
-#define PCINT5_PORT PORTA
-#define PCINT5_BIT 5
-
-#define ADC6_PORT PORTA
-#define ADC6_BIT 6
-#define PCINT6_PORT PORTA
-#define PCINT6_BIT 6
-
-#define ADC7_PORT PORTA
-#define ADC7_BIT 7
-#define PCINT7_PORT PORTA
-#define PCINT7_BIT 7
-
-#define XCK_PORT PORTB
-#define XCK_BIT 0
-#define T0_PORT PORTB
-#define T0_BIT 0
-#define PCINT9_PORT PORTB
-#define PCINT9_BIT 0
-
-#define T1_PORT PORTB
-#define T1_BIT 1
-#define CLKO_PORT PORTB
-#define CLKO_BIT 1
-#define PCINT9_PORT PORTB
-#define PCINT9_BIT 1
-
-#define AIN0_PORT PORTB
-#define AIN0_BIT 2
-#define INT2_PORT PORTB
-#define INT2_BIT 2
-#define PCINT10_PORT PORTB
-#define PCINT10_BIT 2
-
-#define AIN1_PORT PORTB
-#define AIN1_BIT 3
-#define OC0A_PORT PORTB
-#define OC0A_BIT 3
-#define PCINT11_PORT PORTB
-#define PCINT11_BIT 3
-
-#define SS_PORT PORTB
-#define SS_BIT 4
-#define OC0B_PORT PORTB
-#define OC0B_BIT 4
-#define PCINT12_PORT PORTB
-#define PCINT12_BIT 4
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 5
-#define PCINT13_PORT PORTB
-#define PCINT13_BIT 5
-
-#define MISO_PORT PORTB
-#define MISO_BIT 6
-#define PCINT14_PORT PORTB
-#define PCINT14_BIT 6
-
-#define SCK_PORT PORTB
-#define SCK_BIT 7
-#define PCINT15_PORT PORTB
-#define PCINT15_BIT 7
-
-#define SCL_PORT PORTC
-#define SCL_BIT 0
-#define PCINT16_PORT PORTC
-#define PCINT16_BIT 0
-
-#define SDA_PORT PORTC
-#define SDA_BIT 1
-#define PCINT17_PORT PORTC
-#define PCINT17_BIT 1
-
-#define TCK_PORT PORTC
-#define TCK_BIT 2
-#define PCINT18_PORT PORTC
-#define PCINT18_BIT 2
-
-#define TMS_PORT PORTC
-#define TMS_BIT 3
-#define PCINT19_PORT PORTC
-#define PCINT19_BIT 3
-
-#define TDO_PORT PORTC
-#define TDO_BIT 4
-#define PCINT20_PORT PORTC
-#define PCINT20_BIT 4
-
-#define TDI_PORT PORTC
-#define TDI_BIT 5
-#define PCINT21_PORT PORTC
-#define PCINT21_BIT 5
-
-#define TOSC1_PORT PORTC
-#define TOSC1_BIT 6
-#define PCINT22_PORT PORTC
-#define PCINT22_BIT 6
-
-#define TOSC2_PORT PORTC
-#define TOSC2_BIT 7
-#define PCINT23_PORT PORTC
-#define PCINT23_BIT 7
-
-#define RXD_PORT PORTD
-#define RXD_BIT 0
-#define PCINT24_PORT PORTD
-#define PCINT24_BIT 0
-
-#define TXD_PORT PORTD
-#define TXD_BIT 1
-#define PCINT25_PORT PORTD
-#define PCINT25_BIT 1
-
-#define INT0_PORT PORTD
-#define INT0_BIT 2
-#define PCINT26_PORT PORTD
-#define PCINT26_BIT 2
-
-#define INT1_PORT PORTD
-#define INT1_BIT 3
-#define PCINT27_PORT PORTD
-#define PCINT27_BIT 3
-
-#define OC1B_PORT PORTD
-#define OC1B_BIT 4
-#define PCINT28_PORT PORTD
-#define PCINT28_BIT 4
-
-#define OC1A_PORT PORTD
-#define OC1A_BIT 5
-#define PCINT29_PORT PORTD
-#define PCINT29_BIT 5
-
-#define ICP_PORT PORTD
-#define ICP_BIT 6
-#define OC2B_PORT PORTD
-#define OC2B_BIT 6
-#define PCINT30_PORT PORTD
-#define PCINT30_BIT 6
-
-#define OC2A_PORT PORTD
-#define OC2A_BIT 7
-#define PCINT31_PORT PORTD
-#define PCINT31_BIT 7
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE1A_NUM 1
-#define SIG_OUTPUT_COMPARE1B_NUM 2
-#define SIG_OUTPUT_COMPARE2_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM1A_NUM 1
-#define PWM1B_NUM 2
-#define PWM2_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* OCR2A */
-#define OCR2A0_REG OCR2A
-#define OCR2A1_REG OCR2A
-#define OCR2A2_REG OCR2A
-#define OCR2A3_REG OCR2A
-#define OCR2A4_REG OCR2A
-#define OCR2A5_REG OCR2A
-#define OCR2A6_REG OCR2A
-#define OCR2A7_REG OCR2A
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSART0_REG PRR
-#define PRSPI_REG PRR
-#define PRTIM1_REG PRR
-
-/* PORTF */
-#define PORTF0_REG PORTF
-#define PORTF1_REG PORTF
-#define PORTF2_REG PORTF
-#define PORTF3_REG PORTF
-#define PORTF4_REG PORTF
-#define PORTF5_REG PORTF
-#define PORTF6_REG PORTF
-#define PORTF7_REG PORTF
-
-/* PORTG */
-#define PORTG0_REG PORTG
-#define PORTG1_REG PORTG
-#define PORTG2_REG PORTG
-#define PORTG3_REG PORTG
-#define PORTG4_REG PORTG
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-#define PORTE3_REG PORTE
-#define PORTE4_REG PORTE
-#define PORTE5_REG PORTE
-#define PORTE6_REG PORTE
-#define PORTE7_REG PORTE
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* UDR0 */
-#define UDR00_REG UDR0
-#define UDR01_REG UDR0
-#define UDR02_REG UDR0
-#define UDR03_REG UDR0
-#define UDR04_REG UDR0
-#define UDR05_REG UDR0
-#define UDR06_REG UDR0
-#define UDR07_REG UDR0
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* ASSR */
-#define TCR2UB_REG ASSR
-#define OCR2UB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* DDRG */
-#define DDG0_REG DDRG
-#define DDG1_REG DDRG
-#define DDG2_REG DDRG
-#define DDG3_REG DDRG
-#define DDG4_REG DDRG
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-#define DDE3_REG DDRE
-#define DDE4_REG DDRE
-#define DDE5_REG DDRE
-#define DDE6_REG DDRE
-#define DDE7_REG DDRE
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TCCR0A */
-#define CS00_REG TCCR0A
-#define CS01_REG TCCR0A
-#define CS02_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-#define WGM00_REG TCCR0A
-#define FOC0A_REG TCCR0A
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* GTCCR */
-#define PSR310_REG GTCCR
-#define TSM_REG GTCCR
-#define PSR2_REG GTCCR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* MCUSR */
-#define JTRF_REG MCUSR
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TCCR2A */
-#define CS20_REG TCCR2A
-#define CS21_REG TCCR2A
-#define CS22_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-#define WGM20_REG TCCR2A
-#define FOC2A_REG TCCR2A
-
-/* UBRR0H */
-#define UBRR8_REG UBRR0H
-#define UBRR9_REG UBRR0H
-#define UBRR10_REG UBRR0H
-#define UBRR11_REG UBRR0H
-
-/* UBRR0L */
-#define UBRR0_REG UBRR0L
-#define UBRR1_REG UBRR0L
-#define UBRR2_REG UBRR0L
-#define UBRR3_REG UBRR0L
-#define UBRR4_REG UBRR0L
-#define UBRR5_REG UBRR0L
-#define UBRR6_REG UBRR0L
-#define UBRR7_REG UBRR0L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-
-/* EEARL */
-#define EEAR00_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* MCUCR */
-#define JTD_REG MCUCR
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* USISR */
-#define USICNT0_REG USISR
-#define USICNT1_REG USISR
-#define USICNT2_REG USISR
-#define USICNT3_REG USISR
-#define USIDC_REG USISR
-#define USIPF_REG USISR
-#define USIOIF_REG USISR
-#define USISIF_REG USISR
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ACME_REG ADCSRB
-
-/* DDRF */
-#define DDF0_REG DDRF
-#define DDF1_REG DDRF
-#define DDF2_REG DDRF
-#define DDF3_REG DDRF
-#define DDF4_REG DDRF
-#define DDF5_REG DDRF
-#define DDF6_REG DDRF
-#define DDF7_REG DDRF
-
-/* OCR0A */
-#define OCR0A0_REG OCR0A
-#define OCR0A1_REG OCR0A
-#define OCR0A2_REG OCR0A
-#define OCR0A3_REG OCR0A
-#define OCR0A4_REG OCR0A
-#define OCR0A5_REG OCR0A
-#define OCR0A6_REG OCR0A
-#define OCR0A7_REG OCR0A
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* USICR */
-#define USITC_REG USICR
-#define USICLK_REG USICR
-#define USICS0_REG USICR
-#define USICS1_REG USICR
-#define USIWM0_REG USICR
-#define USIWM1_REG USICR
-#define USIOIE_REG USICR
-#define USISIE_REG USICR
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL0_REG UCSR0C
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define PCIE0_REG EIMSK
-#define PCIE1_REG EIMSK
-#define PCIE2_REG EIMSK
-#define PCIE3_REG EIMSK
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-#define PCINT15_REG PCMSK1
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define PCIF0_REG EIFR
-#define PCIF1_REG EIFR
-#define PCIF2_REG EIFR
-#define PCIF3_REG EIFR
-
-/* PING */
-#define PING0_REG PING
-#define PING1_REG PING
-#define PING2_REG PING
-#define PING3_REG PING
-#define PING4_REG PING
-#define PING5_REG PING
-
-/* PINF */
-#define PINF0_REG PINF
-#define PINF1_REG PINF
-#define PINF2_REG PINF
-#define PINF3_REG PINF
-#define PINF4_REG PINF
-#define PINF5_REG PINF
-#define PINF6_REG PINF
-#define PINF7_REG PINF
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-#define PINE3_REG PINE
-#define PINE4_REG PINE
-#define PINE5_REG PINE
-#define PINE6_REG PINE
-#define PINE7_REG PINE
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* USIDR */
-#define USIDR0_REG USIDR
-#define USIDR1_REG USIDR
-#define USIDR2_REG USIDR
-#define USIDR3_REG USIDR
-#define USIDR4_REG USIDR
-#define USIDR5_REG USIDR
-#define USIDR6_REG USIDR
-#define USIDR7_REG USIDR
-
-/* pins mapping */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE1A_NUM 1
-#define SIG_OUTPUT_COMPARE1B_NUM 2
-#define SIG_OUTPUT_COMPARE2_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM1A_NUM 1
-#define PWM1B_NUM 2
-#define PWM2_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* OCR2A */
-#define OCR2A0_REG OCR2A
-#define OCR2A1_REG OCR2A
-#define OCR2A2_REG OCR2A
-#define OCR2A3_REG OCR2A
-#define OCR2A4_REG OCR2A
-#define OCR2A5_REG OCR2A
-#define OCR2A6_REG OCR2A
-#define OCR2A7_REG OCR2A
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSART0_REG PRR
-#define PRSPI_REG PRR
-#define PRTIM1_REG PRR
-#define PRLCD_REG PRR
-
-/* PORTJ */
-#define PORTJ0_REG PORTJ
-#define PORTJ1_REG PORTJ
-#define PORTJ2_REG PORTJ
-#define PORTJ3_REG PORTJ
-#define PORTJ4_REG PORTJ
-#define PORTJ5_REG PORTJ
-#define PORTJ6_REG PORTJ
-
-/* PORTH */
-#define PORTH0_REG PORTH
-#define PORTH1_REG PORTH
-#define PORTH2_REG PORTH
-#define PORTH3_REG PORTH
-#define PORTH4_REG PORTH
-#define PORTH5_REG PORTH
-#define PORTH6_REG PORTH
-#define PORTH7_REG PORTH
-
-/* PORTF */
-#define PORTF0_REG PORTF
-#define PORTF1_REG PORTF
-#define PORTF2_REG PORTF
-#define PORTF3_REG PORTF
-#define PORTF4_REG PORTF
-#define PORTF5_REG PORTF
-#define PORTF6_REG PORTF
-#define PORTF7_REG PORTF
-
-/* PORTG */
-#define PORTG0_REG PORTG
-#define PORTG1_REG PORTG
-#define PORTG2_REG PORTG
-#define PORTG3_REG PORTG
-#define PORTG4_REG PORTG
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL0_REG UCSR0C
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-#define PORTE3_REG PORTE
-#define PORTE4_REG PORTE
-#define PORTE5_REG PORTE
-#define PORTE6_REG PORTE
-#define PORTE7_REG PORTE
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* UDR0 */
-#define UDR00_REG UDR0
-#define UDR01_REG UDR0
-#define UDR02_REG UDR0
-#define UDR03_REG UDR0
-#define UDR04_REG UDR0
-#define UDR05_REG UDR0
-#define UDR06_REG UDR0
-#define UDR07_REG UDR0
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* ASSR */
-#define TCR2UB_REG ASSR
-#define OCR2UB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRJ */
-#define DDJ0_REG DDRJ
-#define DDJ1_REG DDRJ
-#define DDJ2_REG DDRJ
-#define DDJ3_REG DDRJ
-#define DDJ4_REG DDRJ
-#define DDJ5_REG DDRJ
-#define DDJ6_REG DDRJ
-
-/* DDRH */
-#define DDH0_REG DDRH
-#define DDH1_REG DDRH
-#define DDH2_REG DDRH
-#define DDH3_REG DDRH
-#define DDH4_REG DDRH
-#define DDH5_REG DDRH
-#define DDH6_REG DDRH
-#define DDH7_REG DDRH
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* DDRG */
-#define DDG0_REG DDRG
-#define DDG1_REG DDRG
-#define DDG2_REG DDRG
-#define DDG3_REG DDRG
-#define DDG4_REG DDRG
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-#define DDE3_REG DDRE
-#define DDE4_REG DDRE
-#define DDE5_REG DDRE
-#define DDE6_REG DDRE
-#define DDE7_REG DDRE
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TCCR0A */
-#define CS00_REG TCCR0A
-#define CS01_REG TCCR0A
-#define CS02_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-#define WGM00_REG TCCR0A
-#define FOC0A_REG TCCR0A
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* GTCCR */
-#define PSR310_REG GTCCR
-#define TSM_REG GTCCR
-#define PSR2_REG GTCCR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* MCUSR */
-#define JTRF_REG MCUSR
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TCCR2A */
-#define CS20_REG TCCR2A
-#define CS21_REG TCCR2A
-#define CS22_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-#define WGM20_REG TCCR2A
-#define FOC2A_REG TCCR2A
-
-/* UBRR0H */
-#define UBRR8_REG UBRR0H
-#define UBRR9_REG UBRR0H
-#define UBRR10_REG UBRR0H
-#define UBRR11_REG UBRR0H
-
-/* UBRR0L */
-#define UBRR0_REG UBRR0L
-#define UBRR1_REG UBRR0L
-#define UBRR2_REG UBRR0L
-#define UBRR3_REG UBRR0L
-#define UBRR4_REG UBRR0L
-#define UBRR5_REG UBRR0L
-#define UBRR6_REG UBRR0L
-#define UBRR7_REG UBRR0L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-
-/* EEARL */
-#define EEAR00_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* MCUCR */
-#define JTD_REG MCUCR
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ACME_REG ADCSRB
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-
-/* DDRF */
-#define DDF0_REG DDRF
-#define DDF1_REG DDRF
-#define DDF2_REG DDRF
-#define DDF3_REG DDRF
-#define DDF4_REG DDRF
-#define DDF5_REG DDRF
-#define DDF6_REG DDRF
-#define DDF7_REG DDRF
-
-/* OCR0A */
-#define OCR0A0_REG OCR0A
-#define OCR0A1_REG OCR0A
-#define OCR0A2_REG OCR0A
-#define OCR0A3_REG OCR0A
-#define OCR0A4_REG OCR0A
-#define OCR0A5_REG OCR0A
-#define OCR0A6_REG OCR0A
-#define OCR0A7_REG OCR0A
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* USICR */
-#define USITC_REG USICR
-#define USICLK_REG USICR
-#define USICS0_REG USICR
-#define USICS1_REG USICR
-#define USIWM0_REG USICR
-#define USIWM1_REG USICR
-#define USIOIE_REG USICR
-#define USISIE_REG USICR
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* USISR */
-#define USICNT0_REG USISR
-#define USICNT1_REG USISR
-#define USICNT2_REG USISR
-#define USICNT3_REG USISR
-#define USIDC_REG USISR
-#define USIPF_REG USISR
-#define USIOIF_REG USISR
-#define USISIF_REG USISR
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define PCIE0_REG EIMSK
-#define PCIE1_REG EIMSK
-#define PCIE2_REG EIMSK
-#define PCIE3_REG EIMSK
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* PINJ */
-#define PINJ0_REG PINJ
-#define PINJ1_REG PINJ
-#define PINJ2_REG PINJ
-#define PINJ3_REG PINJ
-#define PINJ4_REG PINJ
-#define PINJ5_REG PINJ
-#define PINJ6_REG PINJ
-
-/* PINH */
-#define PINH0_REG PINH
-#define PINH1_REG PINH
-#define PINH2_REG PINH
-#define PINH3_REG PINH
-#define PINH4_REG PINH
-#define PINH5_REG PINH
-#define PINH6_REG PINH
-#define PINH7_REG PINH
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-#define PCINT15_REG PCMSK1
-
-/* PCMSK2 */
-#define PCINT16_REG PCMSK2
-#define PCINT17_REG PCMSK2
-#define PCINT18_REG PCMSK2
-#define PCINT19_REG PCMSK2
-#define PCINT20_REG PCMSK2
-#define PCINT21_REG PCMSK2
-#define PCINT22_REG PCMSK2
-#define PCINT23_REG PCMSK2
-
-/* PCMSK3 */
-#define PCINT24_REG PCMSK3
-#define PCINT25_REG PCMSK3
-#define PCINT26_REG PCMSK3
-#define PCINT27_REG PCMSK3
-#define PCINT28_REG PCMSK3
-#define PCINT29_REG PCMSK3
-#define PCINT30_REG PCMSK3
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define PCIF0_REG EIFR
-#define PCIF1_REG EIFR
-#define PCIF2_REG EIFR
-#define PCIF3_REG EIFR
-
-/* PING */
-#define PING0_REG PING
-#define PING1_REG PING
-#define PING2_REG PING
-#define PING3_REG PING
-#define PING4_REG PING
-#define PING5_REG PING
-
-/* PINF */
-#define PINF0_REG PINF
-#define PINF1_REG PINF
-#define PINF2_REG PINF
-#define PINF3_REG PINF
-#define PINF4_REG PINF
-#define PINF5_REG PINF
-#define PINF6_REG PINF
-#define PINF7_REG PINF
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-#define PINE3_REG PINE
-#define PINE4_REG PINE
-#define PINE5_REG PINE
-#define PINE6_REG PINE
-#define PINE7_REG PINE
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* USIDR */
-#define USIDR0_REG USIDR
-#define USIDR1_REG USIDR
-#define USIDR2_REG USIDR
-#define USIDR3_REG USIDR
-#define USIDR4_REG USIDR
-#define USIDR5_REG USIDR
-#define USIDR6_REG USIDR
-#define USIDR7_REG USIDR
-
-/* pins mapping */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE1A_NUM 1
-#define SIG_OUTPUT_COMPARE1B_NUM 2
-#define SIG_OUTPUT_COMPARE2_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM1A_NUM 1
-#define PWM1B_NUM 2
-#define PWM2_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* OCR2A */
-#define OCR2A0_REG OCR2A
-#define OCR2A1_REG OCR2A
-#define OCR2A2_REG OCR2A
-#define OCR2A3_REG OCR2A
-#define OCR2A4_REG OCR2A
-#define OCR2A5_REG OCR2A
-#define OCR2A6_REG OCR2A
-#define OCR2A7_REG OCR2A
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSART0_REG PRR
-#define PRSPI_REG PRR
-#define PRTIM1_REG PRR
-#define PRLCD_REG PRR
-
-/* PORTJ */
-#define PORTJ0_REG PORTJ
-#define PORTJ1_REG PORTJ
-#define PORTJ2_REG PORTJ
-#define PORTJ3_REG PORTJ
-#define PORTJ4_REG PORTJ
-#define PORTJ5_REG PORTJ
-#define PORTJ6_REG PORTJ
-
-/* PORTH */
-#define PORTH0_REG PORTH
-#define PORTH1_REG PORTH
-#define PORTH2_REG PORTH
-#define PORTH3_REG PORTH
-#define PORTH4_REG PORTH
-#define PORTH5_REG PORTH
-#define PORTH6_REG PORTH
-#define PORTH7_REG PORTH
-
-/* PORTF */
-#define PORTF0_REG PORTF
-#define PORTF1_REG PORTF
-#define PORTF2_REG PORTF
-#define PORTF3_REG PORTF
-#define PORTF4_REG PORTF
-#define PORTF5_REG PORTF
-#define PORTF6_REG PORTF
-#define PORTF7_REG PORTF
-
-/* PORTG */
-#define PORTG0_REG PORTG
-#define PORTG1_REG PORTG
-#define PORTG2_REG PORTG
-#define PORTG3_REG PORTG
-#define PORTG4_REG PORTG
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL0_REG UCSR0C
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-#define PORTE3_REG PORTE
-#define PORTE4_REG PORTE
-#define PORTE5_REG PORTE
-#define PORTE6_REG PORTE
-#define PORTE7_REG PORTE
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* UDR0 */
-#define UDR00_REG UDR0
-#define UDR01_REG UDR0
-#define UDR02_REG UDR0
-#define UDR03_REG UDR0
-#define UDR04_REG UDR0
-#define UDR05_REG UDR0
-#define UDR06_REG UDR0
-#define UDR07_REG UDR0
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* ASSR */
-#define TCR2UB_REG ASSR
-#define OCR2UB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRJ */
-#define DDJ0_REG DDRJ
-#define DDJ1_REG DDRJ
-#define DDJ2_REG DDRJ
-#define DDJ3_REG DDRJ
-#define DDJ4_REG DDRJ
-#define DDJ5_REG DDRJ
-#define DDJ6_REG DDRJ
-
-/* DDRH */
-#define DDH0_REG DDRH
-#define DDH1_REG DDRH
-#define DDH2_REG DDRH
-#define DDH3_REG DDRH
-#define DDH4_REG DDRH
-#define DDH5_REG DDRH
-#define DDH6_REG DDRH
-#define DDH7_REG DDRH
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* DDRG */
-#define DDG0_REG DDRG
-#define DDG1_REG DDRG
-#define DDG2_REG DDRG
-#define DDG3_REG DDRG
-#define DDG4_REG DDRG
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-#define DDE3_REG DDRE
-#define DDE4_REG DDRE
-#define DDE5_REG DDRE
-#define DDE6_REG DDRE
-#define DDE7_REG DDRE
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TCCR0A */
-#define CS00_REG TCCR0A
-#define CS01_REG TCCR0A
-#define CS02_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-#define WGM00_REG TCCR0A
-#define FOC0A_REG TCCR0A
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* GTCCR */
-#define PSR310_REG GTCCR
-#define TSM_REG GTCCR
-#define PSR2_REG GTCCR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* MCUSR */
-#define JTRF_REG MCUSR
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TCCR2A */
-#define CS20_REG TCCR2A
-#define CS21_REG TCCR2A
-#define CS22_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-#define WGM20_REG TCCR2A
-#define FOC2A_REG TCCR2A
-
-/* UBRR0H */
-#define UBRR8_REG UBRR0H
-#define UBRR9_REG UBRR0H
-#define UBRR10_REG UBRR0H
-#define UBRR11_REG UBRR0H
-
-/* UBRR0L */
-#define UBRR0_REG UBRR0L
-#define UBRR1_REG UBRR0L
-#define UBRR2_REG UBRR0L
-#define UBRR3_REG UBRR0L
-#define UBRR4_REG UBRR0L
-#define UBRR5_REG UBRR0L
-#define UBRR6_REG UBRR0L
-#define UBRR7_REG UBRR0L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-
-/* EEARL */
-#define EEAR00_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* MCUCR */
-#define JTD_REG MCUCR
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-#define BODSE_REG MCUCR
-#define BODS_REG MCUCR
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ACME_REG ADCSRB
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-
-/* DDRF */
-#define DDF0_REG DDRF
-#define DDF1_REG DDRF
-#define DDF2_REG DDRF
-#define DDF3_REG DDRF
-#define DDF4_REG DDRF
-#define DDF5_REG DDRF
-#define DDF6_REG DDRF
-#define DDF7_REG DDRF
-
-/* OCR0A */
-#define OCR0A0_REG OCR0A
-#define OCR0A1_REG OCR0A
-#define OCR0A2_REG OCR0A
-#define OCR0A3_REG OCR0A
-#define OCR0A4_REG OCR0A
-#define OCR0A5_REG OCR0A
-#define OCR0A6_REG OCR0A
-#define OCR0A7_REG OCR0A
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* USICR */
-#define USITC_REG USICR
-#define USICLK_REG USICR
-#define USICS0_REG USICR
-#define USICS1_REG USICR
-#define USIWM0_REG USICR
-#define USIWM1_REG USICR
-#define USIOIE_REG USICR
-#define USISIE_REG USICR
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* USISR */
-#define USICNT0_REG USISR
-#define USICNT1_REG USISR
-#define USICNT2_REG USISR
-#define USICNT3_REG USISR
-#define USIDC_REG USISR
-#define USIPF_REG USISR
-#define USIOIF_REG USISR
-#define USISIF_REG USISR
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define PCIE0_REG EIMSK
-#define PCIE1_REG EIMSK
-#define PCIE2_REG EIMSK
-#define PCIE3_REG EIMSK
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* PINJ */
-#define PINJ0_REG PINJ
-#define PINJ1_REG PINJ
-#define PINJ2_REG PINJ
-#define PINJ3_REG PINJ
-#define PINJ4_REG PINJ
-#define PINJ5_REG PINJ
-#define PINJ6_REG PINJ
-
-/* PINH */
-#define PINH0_REG PINH
-#define PINH1_REG PINH
-#define PINH2_REG PINH
-#define PINH3_REG PINH
-#define PINH4_REG PINH
-#define PINH5_REG PINH
-#define PINH6_REG PINH
-#define PINH7_REG PINH
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-#define PCINT15_REG PCMSK1
-
-/* PCMSK2 */
-#define PCINT16_REG PCMSK2
-#define PCINT17_REG PCMSK2
-#define PCINT18_REG PCMSK2
-#define PCINT19_REG PCMSK2
-#define PCINT20_REG PCMSK2
-#define PCINT21_REG PCMSK2
-#define PCINT22_REG PCMSK2
-#define PCINT23_REG PCMSK2
-
-/* PCMSK3 */
-#define PCINT24_REG PCMSK3
-#define PCINT25_REG PCMSK3
-#define PCINT26_REG PCMSK3
-#define PCINT27_REG PCMSK3
-#define PCINT28_REG PCMSK3
-#define PCINT29_REG PCMSK3
-#define PCINT30_REG PCMSK3
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define PCIF0_REG EIFR
-#define PCIF1_REG EIFR
-#define PCIF2_REG EIFR
-#define PCIF3_REG EIFR
-
-/* PING */
-#define PING0_REG PING
-#define PING1_REG PING
-#define PING2_REG PING
-#define PING3_REG PING
-#define PING4_REG PING
-#define PING5_REG PING
-
-/* PINF */
-#define PINF0_REG PINF
-#define PINF1_REG PINF
-#define PINF2_REG PINF
-#define PINF3_REG PINF
-#define PINF4_REG PINF
-#define PINF5_REG PINF
-#define PINF6_REG PINF
-#define PINF7_REG PINF
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-#define PINE3_REG PINE
-#define PINE4_REG PINE
-#define PINE5_REG PINE
-#define PINE6_REG PINE
-#define PINE7_REG PINE
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* USIDR */
-#define USIDR0_REG USIDR
-#define USIDR1_REG USIDR
-#define USIDR2_REG USIDR
-#define USIDR3_REG USIDR
-#define USIDR4_REG USIDR
-#define USIDR5_REG USIDR
-#define USIDR6_REG USIDR
-#define USIDR7_REG USIDR
-
-/* pins mapping */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE1A_NUM 1
-#define SIG_OUTPUT_COMPARE1B_NUM 2
-#define SIG_OUTPUT_COMPARE2_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM1A_NUM 1
-#define PWM1B_NUM 2
-#define PWM2_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* OCR2A */
-#define OCR2A0_REG OCR2A
-#define OCR2A1_REG OCR2A
-#define OCR2A2_REG OCR2A
-#define OCR2A3_REG OCR2A
-#define OCR2A4_REG OCR2A
-#define OCR2A5_REG OCR2A
-#define OCR2A6_REG OCR2A
-#define OCR2A7_REG OCR2A
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSART0_REG PRR
-#define PRSPI_REG PRR
-#define PRTIM1_REG PRR
-#define PRLCD_REG PRR
-
-/* PORTF */
-#define PORTF0_REG PORTF
-#define PORTF1_REG PORTF
-#define PORTF2_REG PORTF
-#define PORTF3_REG PORTF
-#define PORTF4_REG PORTF
-#define PORTF5_REG PORTF
-#define PORTF6_REG PORTF
-#define PORTF7_REG PORTF
-
-/* PORTG */
-#define PORTG0_REG PORTG
-#define PORTG1_REG PORTG
-#define PORTG2_REG PORTG
-#define PORTG3_REG PORTG
-#define PORTG4_REG PORTG
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-#define PORTE3_REG PORTE
-#define PORTE4_REG PORTE
-#define PORTE5_REG PORTE
-#define PORTE6_REG PORTE
-#define PORTE7_REG PORTE
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* UDR0 */
-#define UDR00_REG UDR0
-#define UDR01_REG UDR0
-#define UDR02_REG UDR0
-#define UDR03_REG UDR0
-#define UDR04_REG UDR0
-#define UDR05_REG UDR0
-#define UDR06_REG UDR0
-#define UDR07_REG UDR0
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* ASSR */
-#define TCR2UB_REG ASSR
-#define OCR2UB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* DDRG */
-#define DDG0_REG DDRG
-#define DDG1_REG DDRG
-#define DDG2_REG DDRG
-#define DDG3_REG DDRG
-#define DDG4_REG DDRG
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-#define DDE3_REG DDRE
-#define DDE4_REG DDRE
-#define DDE5_REG DDRE
-#define DDE6_REG DDRE
-#define DDE7_REG DDRE
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TCCR0A */
-#define CS00_REG TCCR0A
-#define CS01_REG TCCR0A
-#define CS02_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-#define WGM00_REG TCCR0A
-#define FOC0A_REG TCCR0A
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* GTCCR */
-#define PSR310_REG GTCCR
-#define TSM_REG GTCCR
-#define PSR2_REG GTCCR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* MCUSR */
-#define JTRF_REG MCUSR
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TCCR2A */
-#define CS20_REG TCCR2A
-#define CS21_REG TCCR2A
-#define CS22_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-#define WGM20_REG TCCR2A
-#define FOC2A_REG TCCR2A
-
-/* UBRR0H */
-#define UBRR8_REG UBRR0H
-#define UBRR9_REG UBRR0H
-#define UBRR10_REG UBRR0H
-#define UBRR11_REG UBRR0H
-
-/* UBRR0L */
-#define UBRR0_REG UBRR0L
-#define UBRR1_REG UBRR0L
-#define UBRR2_REG UBRR0L
-#define UBRR3_REG UBRR0L
-#define UBRR4_REG UBRR0L
-#define UBRR5_REG UBRR0L
-#define UBRR6_REG UBRR0L
-#define UBRR7_REG UBRR0L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-
-/* EEARL */
-#define EEAR00_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* MCUCR */
-#define JTD_REG MCUCR
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-#define BODSE_REG MCUCR
-#define BODS_REG MCUCR
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* USISR */
-#define USICNT0_REG USISR
-#define USICNT1_REG USISR
-#define USICNT2_REG USISR
-#define USICNT3_REG USISR
-#define USIDC_REG USISR
-#define USIPF_REG USISR
-#define USIOIF_REG USISR
-#define USISIF_REG USISR
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ACME_REG ADCSRB
-
-/* DDRF */
-#define DDF0_REG DDRF
-#define DDF1_REG DDRF
-#define DDF2_REG DDRF
-#define DDF3_REG DDRF
-#define DDF4_REG DDRF
-#define DDF5_REG DDRF
-#define DDF6_REG DDRF
-#define DDF7_REG DDRF
-
-/* OCR0A */
-#define OCR0A0_REG OCR0A
-#define OCR0A1_REG OCR0A
-#define OCR0A2_REG OCR0A
-#define OCR0A3_REG OCR0A
-#define OCR0A4_REG OCR0A
-#define OCR0A5_REG OCR0A
-#define OCR0A6_REG OCR0A
-#define OCR0A7_REG OCR0A
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* USICR */
-#define USITC_REG USICR
-#define USICLK_REG USICR
-#define USICS0_REG USICR
-#define USICS1_REG USICR
-#define USIWM0_REG USICR
-#define USIWM1_REG USICR
-#define USIOIE_REG USICR
-#define USISIE_REG USICR
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL0_REG UCSR0C
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define PCIE0_REG EIMSK
-#define PCIE1_REG EIMSK
-#define PCIE2_REG EIMSK
-#define PCIE3_REG EIMSK
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-#define PCINT15_REG PCMSK1
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define PCIF0_REG EIFR
-#define PCIF1_REG EIFR
-#define PCIF2_REG EIFR
-#define PCIF3_REG EIFR
-
-/* PING */
-#define PING0_REG PING
-#define PING1_REG PING
-#define PING2_REG PING
-#define PING3_REG PING
-#define PING4_REG PING
-#define PING5_REG PING
-
-/* PINF */
-#define PINF0_REG PINF
-#define PINF1_REG PINF
-#define PINF2_REG PINF
-#define PINF3_REG PINF
-#define PINF4_REG PINF
-#define PINF5_REG PINF
-#define PINF6_REG PINF
-#define PINF7_REG PINF
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-#define PINE3_REG PINE
-#define PINE4_REG PINE
-#define PINE5_REG PINE
-#define PINE6_REG PINE
-#define PINE7_REG PINE
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* USIDR */
-#define USIDR0_REG USIDR
-#define USIDR1_REG USIDR
-#define USIDR2_REG USIDR
-#define USIDR3_REG USIDR
-#define USIDR4_REG USIDR
-#define USIDR5_REG USIDR
-#define USIDR6_REG USIDR
-#define USIDR7_REG USIDR
-
-/* pins mapping */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-#define TIMER2A_AVAILABLE
-#define TIMER2B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE2A_NUM 4
-#define SIG_OUTPUT_COMPARE2B_NUM 5
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 6
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM2A_NUM 4
-#define PWM2B_NUM 5
-#define PWM_TOTAL_NUM 6
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* OCR2B */
-#define OCR2B_0_REG OCR2B
-#define OCR2B_1_REG OCR2B
-#define OCR2B_2_REG OCR2B
-#define OCR2B_3_REG OCR2B
-#define OCR2B_4_REG OCR2B
-#define OCR2B_5_REG OCR2B
-#define OCR2B_6_REG OCR2B
-#define OCR2B_7_REG OCR2B
-
-/* OCR2A */
-#define OCR2A_0_REG OCR2A
-#define OCR2A_1_REG OCR2A
-#define OCR2A_2_REG OCR2A
-#define OCR2A_3_REG OCR2A
-#define OCR2A_4_REG OCR2A
-#define OCR2A_5_REG OCR2A
-#define OCR2A_6_REG OCR2A
-#define OCR2A_7_REG OCR2A
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSART0_REG PRR
-#define PRSPI_REG PRR
-#define PRTIM1_REG PRR
-#define PRTIM0_REG PRR
-#define PRTIM2_REG PRR
-#define PRTWI_REG PRR
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-
-/* UDR0 */
-#define UDR0_0_REG UDR0
-#define UDR0_1_REG UDR0
-#define UDR0_2_REG UDR0
-#define UDR0_3_REG UDR0
-#define UDR0_4_REG UDR0
-#define UDR0_5_REG UDR0
-#define UDR0_6_REG UDR0
-#define UDR0_7_REG UDR0
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* ASSR */
-#define TCR2BUB_REG ASSR
-#define TCR2AUB_REG ASSR
-#define OCR2BUB_REG ASSR
-#define OCR2AUB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* PCICR */
-#define PCIE0_REG PCICR
-#define PCIE1_REG PCICR
-#define PCIE2_REG PCICR
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-#define OCF2B_REG TIFR2
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* GTCCR */
-#define PSRSYNC_REG GTCCR
-#define TSM_REG GTCCR
-#define PSRASY_REG GTCCR
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* PCIFR */
-#define PCIF0_REG PCIFR
-#define PCIF1_REG PCIFR
-#define PCIF2_REG PCIFR
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* TCCR2A */
-#define WGM20_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2B0_REG TCCR2A
-#define COM2B1_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-
-/* TCCR2B */
-#define CS20_REG TCCR2B
-#define CS21_REG TCCR2B
-#define CS22_REG TCCR2B
-#define WGM22_REG TCCR2B
-#define FOC2B_REG TCCR2B
-#define FOC2A_REG TCCR2B
-
-/* UBRR0H */
-#define UBRR8_REG UBRR0H
-#define UBRR9_REG UBRR0H
-#define UBRR10_REG UBRR0H
-#define UBRR11_REG UBRR0H
-
-/* UBRR0L */
-#define UBRR0_REG UBRR0L
-#define UBRR1_REG UBRR0L
-#define UBRR2_REG UBRR0L
-#define UBRR3_REG UBRR0L
-#define UBRR4_REG UBRR0L
-#define UBRR5_REG UBRR0L
-#define UBRR6_REG UBRR0L
-#define UBRR7_REG UBRR0L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* MCUCR */
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-#define BODSE_REG MCUCR
-#define BODS_REG MCUCR
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ACME_REG ADCSRB
-
-/* OCR0A */
-#define OCROA_0_REG OCR0A
-#define OCROA_1_REG OCR0A
-#define OCROA_2_REG OCR0A
-#define OCROA_3_REG OCR0A
-#define OCROA_4_REG OCR0A
-#define OCROA_5_REG OCR0A
-#define OCROA_6_REG OCR0A
-#define OCROA_7_REG OCR0A
-
-/* OCR0B */
-#define OCR0B_0_REG OCR0B
-#define OCR0B_1_REG OCR0B
-#define OCR0B_2_REG OCR0B
-#define OCR0B_3_REG OCR0B
-#define OCR0B_4_REG OCR0B
-#define OCR0B_5_REG OCR0B
-#define OCR0B_6_REG OCR0B
-#define OCR0B_7_REG OCR0B
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL00_REG UCSR0C
-#define UMSEL01_REG UCSR0C
-
-/* SPMCSR */
-#define SELFPRGEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-#define OCIE2B_REG TIMSK2
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-
-/* PCMSK2 */
-#define PCINT16_REG PCMSK2
-#define PCINT17_REG PCMSK2
-#define PCINT18_REG PCMSK2
-#define PCINT19_REG PCMSK2
-#define PCINT20_REG PCMSK2
-#define PCINT21_REG PCMSK2
-#define PCINT22_REG PCMSK2
-#define PCINT23_REG PCMSK2
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* TWAMR */
-#define TWAM0_REG TWAMR
-#define TWAM1_REG TWAMR
-#define TWAM2_REG TWAMR
-#define TWAM3_REG TWAMR
-#define TWAM4_REG TWAMR
-#define TWAM5_REG TWAMR
-#define TWAM6_REG TWAMR
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* pins mapping */
-#define ICP1_PORT PORTB
-#define ICP1_BIT 0
-#define CLKO_PORT PORTB
-#define CLKO_BIT 0
-#define PCINT0_PORT PORTB
-#define PCINT0_BIT 0
-
-#define OC1A_PORT PORTB
-#define OC1A_BIT 1
-#define PCINT1_PORT PORTB
-#define PCINT1_BIT 1
-
-#define SS_PORT PORTB
-#define SS_BIT 2
-#define OC1B_PORT PORTB
-#define OC1B_BIT 2
-#define PCINT2_PORT PORTB
-#define PCINT2_BIT 2
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 3
-#define OC2A_PORT PORTB
-#define OC2A_BIT 3
-#define PCINT3_PORT PORTB
-#define PCINT3_BIT 3
-
-#define MISO_PORT PORTB
-#define MISO_BIT 4
-#define PCINT4_PORT PORTB
-#define PCINT4_BIT 4
-
-#define SCK_PORT PORTB
-#define SCK_BIT 5
-#define PCINT5_PORT PORTB
-#define PCINT5_BIT 5
-
-#define XTAL1_PORT PORTB
-#define XTAL1_BIT 6
-#define TOSC1_PORT PORTB
-#define TOSC1_BIT 6
-#define PCINT6_PORT PORTB
-#define PCINT6_BIT 6
-
-#define XTAL2_PORT PORTB
-#define XTAL2_BIT 7
-#define TOSC2_PORT PORTB
-#define TOSC2_BIT 7
-#define PCINT7_PORT PORTB
-#define PCINT7_BIT 7
-
-#define ADC0_PORT PORTC
-#define ADC0_BIT 0
-#define PCINT8_PORT PORTC
-#define PCINT8_BIT 0
-
-#define ADC1_PORT PORTC
-#define ADC1_BIT 1
-#define PCINT9_PORT PORTC
-#define PCINT9_BIT 1
-
-#define ADC2_PORT PORTC
-#define ADC2_BIT 2
-#define PCINT10_PORT PORTC
-#define PCINT10_BIT 2
-
-#define ADC3_PORT PORTC
-#define ADC3_BIT 3
-#define PCINT11_PORT PORTC
-#define PCINT11_BIT 3
-
-#define ADC4_PORT PORTC
-#define ADC4_BIT 4
-#define SDA_PORT PORTC
-#define SDA_BIT 4
-#define PCINT12_PORT PORTC
-#define PCINT12_BIT 4
-
-#define ADC5_PORT PORTC
-#define ADC5_BIT 5
-#define SCL_PORT PORTC
-#define SCL_BIT 5
-#define PCINT13_PORT PORTC
-#define PCINT13_BIT 5
-
-#define RESET_PORT PORTC
-#define RESET_BIT 6
-#define PCINT14_PORT PORTC
-#define PCINT14_BIT 6
-
-#define RXD_PORT PORTD
-#define RXD_BIT 0
-#define PCINT16_PORT PORTD
-#define PCINT16_BIT 0
-
-#define TXD_PORT PORTD
-#define TXD_BIT 1
-#define PCINT17_PORT PORTD
-#define PCINT17_BIT 1
-
-#define INT0_PORT PORTD
-#define INT0_BIT 2
-#define PCINT18_PORT PORTD
-#define PCINT18_BIT 2
-
-#define PCINT19_PORT PORTD
-#define PCINT19_BIT 3
-#define OC2B_PORT PORTD
-#define OC2B_BIT 3
-#define INT1_PORT PORTD
-#define INT1_BIT 3
-
-#define XCK_PORT PORTD
-#define XCK_BIT 4
-#define T0_PORT PORTD
-#define T0_BIT 4
-#define PCINT20_PORT PORTD
-#define PCINT20_BIT 4
-
-#define T1_PORT PORTD
-#define T1_BIT 5
-#define OC0B_PORT PORTD
-#define OC0B_BIT 5
-#define PCINT21_PORT PORTD
-#define PCINT21_BIT 5
-
-#define AIN0_PORT PORTD
-#define AIN0_BIT 6
-#define OC0A_PORT PORTD
-#define OC0A_BIT 6
-#define PCINT22_PORT PORTD
-#define PCINT22_BIT 6
-
-#define AIN1_PORT PORTD
-#define AIN1_BIT 7
-#define PCINT23_PORT PORTD
-#define PCINT23_BIT 7
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE1A_NUM 1
-#define SIG_OUTPUT_COMPARE1B_NUM 2
-#define SIG_OUTPUT_COMPARE2_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM1A_NUM 1
-#define PWM1B_NUM 2
-#define PWM2_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* OCR2A */
-#define OCR2A0_REG OCR2A
-#define OCR2A1_REG OCR2A
-#define OCR2A2_REG OCR2A
-#define OCR2A3_REG OCR2A
-#define OCR2A4_REG OCR2A
-#define OCR2A5_REG OCR2A
-#define OCR2A6_REG OCR2A
-#define OCR2A7_REG OCR2A
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSART0_REG PRR
-#define PRSPI_REG PRR
-#define PRTIM1_REG PRR
-#define PRLCD_REG PRR
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* PORTG */
-#define PORTG0_REG PORTG
-#define PORTG1_REG PORTG
-#define PORTG2_REG PORTG
-#define PORTG3_REG PORTG
-#define PORTG4_REG PORTG
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL0_REG UCSR0C
-
-/* USISR */
-#define USICNT0_REG USISR
-#define USICNT1_REG USISR
-#define USICNT2_REG USISR
-#define USICNT3_REG USISR
-#define USIDC_REG USISR
-#define USIPF_REG USISR
-#define USIOIF_REG USISR
-#define USISIF_REG USISR
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* UDR0 */
-#define UDR00_REG UDR0
-#define UDR01_REG UDR0
-#define UDR02_REG UDR0
-#define UDR03_REG UDR0
-#define UDR04_REG UDR0
-#define UDR05_REG UDR0
-#define UDR06_REG UDR0
-#define UDR07_REG UDR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* ASSR */
-#define TCR2UB_REG ASSR
-#define OCR2UB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* DDRG */
-#define DDG0_REG DDRG
-#define DDG1_REG DDRG
-#define DDG2_REG DDRG
-#define DDG3_REG DDRG
-#define DDG4_REG DDRG
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* LCDDR3 */
-#define SEG024_REG LCDDR3
-
-/* LCDDR2 */
-#define SEG016_REG LCDDR2
-#define SEG017_REG LCDDR2
-#define SEG018_REG LCDDR2
-#define SEG019_REG LCDDR2
-#define SEG020_REG LCDDR2
-#define SEG021_REG LCDDR2
-#define SEG022_REG LCDDR2
-#define SEG023_REG LCDDR2
-
-/* LCDDR1 */
-#define SEG008_REG LCDDR1
-#define SEG009_REG LCDDR1
-#define SEG010_REG LCDDR1
-#define SEG011_REG LCDDR1
-#define SEG012_REG LCDDR1
-#define SEG013_REG LCDDR1
-#define SEG014_REG LCDDR1
-#define SEG015_REG LCDDR1
-
-/* LCDDR0 */
-#define SEG000_REG LCDDR0
-#define SEG001_REG LCDDR0
-#define SEG002_REG LCDDR0
-#define SEG003_REG LCDDR0
-#define SEG004_REG LCDDR0
-#define SEG005_REG LCDDR0
-#define SEG006_REG LCDDR0
-#define SEG007_REG LCDDR0
-
-/* LCDDR7 */
-#define SEG116_REG LCDDR7
-#define SEG117_REG LCDDR7
-#define SEG118_REG LCDDR7
-#define SEG119_REG LCDDR7
-#define SEG120_REG LCDDR7
-#define SEG121_REG LCDDR7
-#define SEG122_REG LCDDR7
-#define SEG123_REG LCDDR7
-
-/* LCDDR6 */
-#define SEG108_REG LCDDR6
-#define SEG109_REG LCDDR6
-#define SEG110_REG LCDDR6
-#define SEG111_REG LCDDR6
-#define SEG112_REG LCDDR6
-#define SEG113_REG LCDDR6
-#define SEG114_REG LCDDR6
-#define SEG115_REG LCDDR6
-
-/* LCDDR5 */
-#define SEG100_REG LCDDR5
-#define SEG101_REG LCDDR5
-#define SEG102_REG LCDDR5
-#define SEG103_REG LCDDR5
-#define SEG104_REG LCDDR5
-#define SEG105_REG LCDDR5
-#define SEG106_REG LCDDR5
-#define SEG107_REG LCDDR5
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* LCDDR8 */
-#define SEG124_REG LCDDR8
-
-/* LCDCRA */
-#define LCDBL_REG LCDCRA
-#define LCDIE_REG LCDCRA
-#define LCDIF_REG LCDCRA
-#define LCDAB_REG LCDCRA
-#define LCDEN_REG LCDCRA
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-#define DDE3_REG DDRE
-#define DDE4_REG DDRE
-#define DDE5_REG DDRE
-#define DDE6_REG DDRE
-#define DDE7_REG DDRE
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TCCR0A */
-#define CS00_REG TCCR0A
-#define CS01_REG TCCR0A
-#define CS02_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-#define WGM00_REG TCCR0A
-#define FOC0A_REG TCCR0A
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* GTCCR */
-#define PSR310_REG GTCCR
-#define TSM_REG GTCCR
-#define PSR2_REG GTCCR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* LCDCRB */
-#define LCDPM0_REG LCDCRB
-#define LCDPM1_REG LCDCRB
-#define LCDPM2_REG LCDCRB
-#define LCDPM3_REG LCDCRB
-#define LCDMUX0_REG LCDCRB
-#define LCDMUX1_REG LCDCRB
-#define LCD2B_REG LCDCRB
-#define LCDCS_REG LCDCRB
-
-/* LCDDR18 */
-#define SEG324_REG LCDDR18
-
-/* LCDDR13 */
-#define SEG224_REG LCDDR13
-
-/* LCDDR12 */
-#define SEG216_REG LCDDR12
-#define SEG217_REG LCDDR12
-#define SEG218_REG LCDDR12
-#define SEG219_REG LCDDR12
-#define SEG220_REG LCDDR12
-#define SEG221_REG LCDDR12
-#define SEG222_REG LCDDR12
-#define SEG223_REG LCDDR12
-
-/* LCDDR11 */
-#define SEG208_REG LCDDR11
-#define SEG209_REG LCDDR11
-#define SEG210_REG LCDDR11
-#define SEG211_REG LCDDR11
-#define SEG212_REG LCDDR11
-#define SEG213_REG LCDDR11
-#define SEG214_REG LCDDR11
-#define SEG215_REG LCDDR11
-
-/* LCDDR10 */
-#define SEG200_REG LCDDR10
-#define SEG201_REG LCDDR10
-#define SEG202_REG LCDDR10
-#define SEG203_REG LCDDR10
-#define SEG204_REG LCDDR10
-#define SEG205_REG LCDDR10
-#define SEG206_REG LCDDR10
-#define SEG207_REG LCDDR10
-
-/* LCDDR17 */
-#define SEG316_REG LCDDR17
-#define SEG317_REG LCDDR17
-#define SEG318_REG LCDDR17
-#define SEG319_REG LCDDR17
-#define SEG320_REG LCDDR17
-#define SEG321_REG LCDDR17
-#define SEG322_REG LCDDR17
-#define SEG323_REG LCDDR17
-
-/* LCDDR16 */
-#define SEG308_REG LCDDR16
-#define SEG309_REG LCDDR16
-#define SEG310_REG LCDDR16
-#define SEG311_REG LCDDR16
-#define SEG312_REG LCDDR16
-#define SEG313_REG LCDDR16
-#define SEG314_REG LCDDR16
-#define SEG315_REG LCDDR16
-
-/* LCDDR15 */
-#define SEG300_REG LCDDR15
-#define SEG301_REG LCDDR15
-#define SEG302_REG LCDDR15
-#define SEG303_REG LCDDR15
-#define SEG304_REG LCDDR15
-#define SEG305_REG LCDDR15
-#define SEG306_REG LCDDR15
-#define SEG307_REG LCDDR15
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* MCUSR */
-#define JTRF_REG MCUSR
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TCCR2A */
-#define CS20_REG TCCR2A
-#define CS21_REG TCCR2A
-#define CS22_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-#define WGM20_REG TCCR2A
-#define FOC2A_REG TCCR2A
-
-/* UBRR0H */
-#define UBRR8_REG UBRR0H
-#define UBRR9_REG UBRR0H
-#define UBRR10_REG UBRR0H
-#define UBRR11_REG UBRR0H
-
-/* UBRR0L */
-#define UBRR0_REG UBRR0L
-#define UBRR1_REG UBRR0L
-#define UBRR2_REG UBRR0L
-#define UBRR3_REG UBRR0L
-#define UBRR4_REG UBRR0L
-#define UBRR5_REG UBRR0L
-#define UBRR6_REG UBRR0L
-#define UBRR7_REG UBRR0L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-
-/* EEARL */
-#define EEAR00_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* MCUCR */
-#define JTD_REG MCUCR
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-#define PORTE3_REG PORTE
-#define PORTE4_REG PORTE
-#define PORTE5_REG PORTE
-#define PORTE6_REG PORTE
-#define PORTE7_REG PORTE
-
-/* LCDCCR */
-#define LCDCC0_REG LCDCCR
-#define LCDCC1_REG LCDCCR
-#define LCDCC2_REG LCDCCR
-#define LCDCC3_REG LCDCCR
-#define LCDDC0_REG LCDCCR
-#define LCDDC1_REG LCDCCR
-#define LCDDC2_REG LCDCCR
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-#define PINE3_REG PINE
-#define PINE4_REG PINE
-#define PINE5_REG PINE
-#define PINE6_REG PINE
-#define PINE7_REG PINE
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ACME_REG ADCSRB
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-
-/* DDRF */
-#define DDF0_REG DDRF
-#define DDF1_REG DDRF
-#define DDF2_REG DDRF
-#define DDF3_REG DDRF
-#define DDF4_REG DDRF
-#define DDF5_REG DDRF
-#define DDF6_REG DDRF
-#define DDF7_REG DDRF
-
-/* OCR0A */
-#define OCR0A0_REG OCR0A
-#define OCR0A1_REG OCR0A
-#define OCR0A2_REG OCR0A
-#define OCR0A3_REG OCR0A
-#define OCR0A4_REG OCR0A
-#define OCR0A5_REG OCR0A
-#define OCR0A6_REG OCR0A
-#define OCR0A7_REG OCR0A
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* USICR */
-#define USITC_REG USICR
-#define USICLK_REG USICR
-#define USICS0_REG USICR
-#define USICS1_REG USICR
-#define USIWM0_REG USICR
-#define USIWM1_REG USICR
-#define USIOIE_REG USICR
-#define USISIE_REG USICR
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* LCDFRR */
-#define LCDCD0_REG LCDFRR
-#define LCDCD1_REG LCDFRR
-#define LCDCD2_REG LCDFRR
-#define LCDPS0_REG LCDFRR
-#define LCDPS1_REG LCDFRR
-#define LCDPS2_REG LCDFRR
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define PCIE0_REG EIMSK
-#define PCIE1_REG EIMSK
-#define PCIE2_REG EIMSK
-#define PCIE3_REG EIMSK
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-#define PCINT15_REG PCMSK1
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define PCIF0_REG EIFR
-#define PCIF1_REG EIFR
-#define PCIF2_REG EIFR
-#define PCIF3_REG EIFR
-
-/* PING */
-#define PING0_REG PING
-#define PING1_REG PING
-#define PING2_REG PING
-#define PING3_REG PING
-#define PING4_REG PING
-#define PING5_REG PING
-
-/* PINF */
-#define PINF0_REG PINF
-#define PINF1_REG PINF
-#define PINF2_REG PINF
-#define PINF3_REG PINF
-#define PINF4_REG PINF
-#define PINF5_REG PINF
-#define PINF6_REG PINF
-#define PINF7_REG PINF
-
-/* PORTF */
-#define PORTF0_REG PORTF
-#define PORTF1_REG PORTF
-#define PORTF2_REG PORTF
-#define PORTF3_REG PORTF
-#define PORTF4_REG PORTF
-#define PORTF5_REG PORTF
-#define PORTF6_REG PORTF
-#define PORTF7_REG PORTF
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-
-/* USIDR */
-#define USIDR0_REG USIDR
-#define USIDR1_REG USIDR
-#define USIDR2_REG USIDR
-#define USIDR3_REG USIDR
-#define USIDR4_REG USIDR
-#define USIDR5_REG USIDR
-#define USIDR6_REG USIDR
-#define USIDR7_REG USIDR
-
-/* pins mapping */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE1A_NUM 1
-#define SIG_OUTPUT_COMPARE1B_NUM 2
-#define SIG_OUTPUT_COMPARE2_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM1A_NUM 1
-#define PWM1B_NUM 2
-#define PWM2_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* OCR2A */
-#define OCR2A0_REG OCR2A
-#define OCR2A1_REG OCR2A
-#define OCR2A2_REG OCR2A
-#define OCR2A3_REG OCR2A
-#define OCR2A4_REG OCR2A
-#define OCR2A5_REG OCR2A
-#define OCR2A6_REG OCR2A
-#define OCR2A7_REG OCR2A
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSART0_REG PRR
-#define PRSPI_REG PRR
-#define PRTIM1_REG PRR
-#define PRLCD_REG PRR
-
-/* PORTJ */
-#define PORTJ0_REG PORTJ
-#define PORTJ1_REG PORTJ
-#define PORTJ2_REG PORTJ
-#define PORTJ3_REG PORTJ
-#define PORTJ4_REG PORTJ
-#define PORTJ5_REG PORTJ
-#define PORTJ6_REG PORTJ
-
-/* PORTH */
-#define PORTH0_REG PORTH
-#define PORTH1_REG PORTH
-#define PORTH2_REG PORTH
-#define PORTH3_REG PORTH
-#define PORTH4_REG PORTH
-#define PORTH5_REG PORTH
-#define PORTH6_REG PORTH
-#define PORTH7_REG PORTH
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* PORTG */
-#define PORTG0_REG PORTG
-#define PORTG1_REG PORTG
-#define PORTG2_REG PORTG
-#define PORTG3_REG PORTG
-#define PORTG4_REG PORTG
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL0_REG UCSR0C
-
-/* USISR */
-#define USICNT0_REG USISR
-#define USICNT1_REG USISR
-#define USICNT2_REG USISR
-#define USICNT3_REG USISR
-#define USIDC_REG USISR
-#define USIPF_REG USISR
-#define USIOIF_REG USISR
-#define USISIF_REG USISR
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* UDR0 */
-#define UDR00_REG UDR0
-#define UDR01_REG UDR0
-#define UDR02_REG UDR0
-#define UDR03_REG UDR0
-#define UDR04_REG UDR0
-#define UDR05_REG UDR0
-#define UDR06_REG UDR0
-#define UDR07_REG UDR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* ASSR */
-#define TCR2UB_REG ASSR
-#define OCR2UB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRJ */
-#define DDJ0_REG DDRJ
-#define DDJ1_REG DDRJ
-#define DDJ2_REG DDRJ
-#define DDJ3_REG DDRJ
-#define DDJ4_REG DDRJ
-#define DDJ5_REG DDRJ
-#define DDJ6_REG DDRJ
-
-/* DDRH */
-#define DDH0_REG DDRH
-#define DDH1_REG DDRH
-#define DDH2_REG DDRH
-#define DDH3_REG DDRH
-#define DDH4_REG DDRH
-#define DDH5_REG DDRH
-#define DDH6_REG DDRH
-#define DDH7_REG DDRH
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* DDRG */
-#define DDG0_REG DDRG
-#define DDG1_REG DDRG
-#define DDG2_REG DDRG
-#define DDG3_REG DDRG
-#define DDG4_REG DDRG
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* LCDDR3 */
-#define SEG024_REG LCDDR3
-#define SEG025_REG LCDDR3
-#define SEG026_REG LCDDR3
-#define SEG027_REG LCDDR3
-#define SEG028_REG LCDDR3
-#define SEG029_REG LCDDR3
-#define SEG030_REG LCDDR3
-#define SEG031_REG LCDDR3
-
-/* LCDDR2 */
-#define SEG016_REG LCDDR2
-#define SEG017_REG LCDDR2
-#define SEG018_REG LCDDR2
-#define SEG019_REG LCDDR2
-#define SEG020_REG LCDDR2
-#define SEG021_REG LCDDR2
-#define SEG022_REG LCDDR2
-#define SEG023_REG LCDDR2
-
-/* LCDDR1 */
-#define SEG008_REG LCDDR1
-#define SEG009_REG LCDDR1
-#define SEG010_REG LCDDR1
-#define SEG011_REG LCDDR1
-#define SEG012_REG LCDDR1
-#define SEG013_REG LCDDR1
-#define SEG014_REG LCDDR1
-#define SEG015_REG LCDDR1
-
-/* LCDDR0 */
-#define SEG000_REG LCDDR0
-#define SEG001_REG LCDDR0
-#define SEG002_REG LCDDR0
-#define SEG003_REG LCDDR0
-#define SEG004_REG LCDDR0
-#define SEG005_REG LCDDR0
-#define SEG006_REG LCDDR0
-#define SEG007_REG LCDDR0
-
-/* LCDDR7 */
-#define SEG116_REG LCDDR7
-#define SEG117_REG LCDDR7
-#define SEG118_REG LCDDR7
-#define SEG119_REG LCDDR7
-#define SEG120_REG LCDDR7
-#define SEG121_REG LCDDR7
-#define SEG122_REG LCDDR7
-#define SEG123_REG LCDDR7
-
-/* LCDDR6 */
-#define SEG108_REG LCDDR6
-#define SEG109_REG LCDDR6
-#define SEG110_REG LCDDR6
-#define SEG111_REG LCDDR6
-#define SEG112_REG LCDDR6
-#define SEG113_REG LCDDR6
-#define SEG114_REG LCDDR6
-#define SEG115_REG LCDDR6
-
-/* LCDDR5 */
-#define SEG100_REG LCDDR5
-#define SEG101_REG LCDDR5
-#define SEG102_REG LCDDR5
-#define SEG103_REG LCDDR5
-#define SEG104_REG LCDDR5
-#define SEG105_REG LCDDR5
-#define SEG106_REG LCDDR5
-#define SEG107_REG LCDDR5
-
-/* LCDDR4 */
-#define SEG032_REG LCDDR4
-#define SEG033_REG LCDDR4
-#define SEG034_REG LCDDR4
-#define SEG035_REG LCDDR4
-#define SEG036_REG LCDDR4
-#define SEG037_REG LCDDR4
-#define SEG038_REG LCDDR4
-#define SEG039_REG LCDDR4
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* LCDDR9 */
-#define SEG132_REG LCDDR9
-#define SEG133_REG LCDDR9
-#define SEG134_REG LCDDR9
-#define SEG135_REG LCDDR9
-#define SEG136_REG LCDDR9
-#define SEG137_REG LCDDR9
-#define SEG138_REG LCDDR9
-#define SEG139_REG LCDDR9
-
-/* LCDDR8 */
-#define SEG124_REG LCDDR8
-#define SEG125_REG LCDDR8
-#define SEG126_REG LCDDR8
-#define SEG127_REG LCDDR8
-#define SEG128_REG LCDDR8
-#define SEG129_REG LCDDR8
-#define SEG130_REG LCDDR8
-#define SEG131_REG LCDDR8
-
-/* LCDCRA */
-#define LCDBL_REG LCDCRA
-#define LCDIE_REG LCDCRA
-#define LCDIF_REG LCDCRA
-#define LCDAB_REG LCDCRA
-#define LCDEN_REG LCDCRA
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-#define DDE3_REG DDRE
-#define DDE4_REG DDRE
-#define DDE5_REG DDRE
-#define DDE6_REG DDRE
-#define DDE7_REG DDRE
-
-/* LCDCRB */
-#define LCDPM0_REG LCDCRB
-#define LCDPM1_REG LCDCRB
-#define LCDPM2_REG LCDCRB
-#define LCDPM3_REG LCDCRB
-#define LCDMUX0_REG LCDCRB
-#define LCDMUX1_REG LCDCRB
-#define LCD2B_REG LCDCRB
-#define LCDCS_REG LCDCRB
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TCCR0A */
-#define CS00_REG TCCR0A
-#define CS01_REG TCCR0A
-#define CS02_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-#define WGM00_REG TCCR0A
-#define FOC0A_REG TCCR0A
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* GTCCR */
-#define PSR310_REG GTCCR
-#define TSM_REG GTCCR
-#define PSR2_REG GTCCR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* LCDDR19 */
-#define SEG332_REG LCDDR19
-#define SEG333_REG LCDDR19
-#define SEG334_REG LCDDR19
-#define SEG335_REG LCDDR19
-#define SEG336_REG LCDDR19
-#define SEG337_REG LCDDR19
-#define SEG338_REG LCDDR19
-#define SEG339_REG LCDDR19
-
-/* LCDDR18 */
-#define SEG324_REG LCDDR18
-#define SEG325_REG LCDDR18
-#define SEG326_REG LCDDR18
-#define SEG327_REG LCDDR18
-#define SEG328_REG LCDDR18
-#define SEG329_REG LCDDR18
-#define SEG330_REG LCDDR18
-#define SEG331_REG LCDDR18
-
-/* LCDDR13 */
-#define SEG224_REG LCDDR13
-#define SEG225_REG LCDDR13
-#define SEG226_REG LCDDR13
-#define SEG227_REG LCDDR13
-#define SEG228_REG LCDDR13
-#define SEG229_REG LCDDR13
-#define SEG230_REG LCDDR13
-#define SEG231_REG LCDDR13
-
-/* LCDDR12 */
-#define SEG216_REG LCDDR12
-#define SEG217_REG LCDDR12
-#define SEG218_REG LCDDR12
-#define SEG219_REG LCDDR12
-#define SEG220_REG LCDDR12
-#define SEG221_REG LCDDR12
-#define SEG222_REG LCDDR12
-#define SEG223_REG LCDDR12
-
-/* LCDDR11 */
-#define SEG208_REG LCDDR11
-#define SEG209_REG LCDDR11
-#define SEG210_REG LCDDR11
-#define SEG211_REG LCDDR11
-#define SEG212_REG LCDDR11
-#define SEG213_REG LCDDR11
-#define SEG214_REG LCDDR11
-#define SEG215_REG LCDDR11
-
-/* LCDDR10 */
-#define SEG200_REG LCDDR10
-#define SEG201_REG LCDDR10
-#define SEG202_REG LCDDR10
-#define SEG203_REG LCDDR10
-#define SEG204_REG LCDDR10
-#define SEG205_REG LCDDR10
-#define SEG206_REG LCDDR10
-#define SEG207_REG LCDDR10
-
-/* LCDDR17 */
-#define SEG316_REG LCDDR17
-#define SEG317_REG LCDDR17
-#define SEG318_REG LCDDR17
-#define SEG319_REG LCDDR17
-#define SEG320_REG LCDDR17
-#define SEG321_REG LCDDR17
-#define SEG322_REG LCDDR17
-#define SEG323_REG LCDDR17
-
-/* LCDDR16 */
-#define SEG308_REG LCDDR16
-#define SEG309_REG LCDDR16
-#define SEG310_REG LCDDR16
-#define SEG311_REG LCDDR16
-#define SEG312_REG LCDDR16
-#define SEG313_REG LCDDR16
-#define SEG314_REG LCDDR16
-#define SEG315_REG LCDDR16
-
-/* LCDDR15 */
-#define SEG300_REG LCDDR15
-#define SEG301_REG LCDDR15
-#define SEG302_REG LCDDR15
-#define SEG303_REG LCDDR15
-#define SEG304_REG LCDDR15
-#define SEG305_REG LCDDR15
-#define SEG306_REG LCDDR15
-#define SEG307_REG LCDDR15
-
-/* LCDDR14 */
-#define SEG232_REG LCDDR14
-#define SEG233_REG LCDDR14
-#define SEG234_REG LCDDR14
-#define SEG235_REG LCDDR14
-#define SEG236_REG LCDDR14
-#define SEG237_REG LCDDR14
-#define SEG238_REG LCDDR14
-#define SEG239_REG LCDDR14
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* MCUSR */
-#define JTRF_REG MCUSR
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TCCR2A */
-#define CS20_REG TCCR2A
-#define CS21_REG TCCR2A
-#define CS22_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-#define WGM20_REG TCCR2A
-#define FOC2A_REG TCCR2A
-
-/* UBRR0H */
-#define UBRR8_REG UBRR0H
-#define UBRR9_REG UBRR0H
-#define UBRR10_REG UBRR0H
-#define UBRR11_REG UBRR0H
-
-/* UBRR0L */
-#define UBRR0_REG UBRR0L
-#define UBRR1_REG UBRR0L
-#define UBRR2_REG UBRR0L
-#define UBRR3_REG UBRR0L
-#define UBRR4_REG UBRR0L
-#define UBRR5_REG UBRR0L
-#define UBRR6_REG UBRR0L
-#define UBRR7_REG UBRR0L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-
-/* EEARL */
-#define EEAR00_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* MCUCR */
-#define JTD_REG MCUCR
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-#define PORTE3_REG PORTE
-#define PORTE4_REG PORTE
-#define PORTE5_REG PORTE
-#define PORTE6_REG PORTE
-#define PORTE7_REG PORTE
-
-/* LCDCCR */
-#define LCDCC0_REG LCDCCR
-#define LCDCC1_REG LCDCCR
-#define LCDCC2_REG LCDCCR
-#define LCDCC3_REG LCDCCR
-#define LCDDC0_REG LCDCCR
-#define LCDDC1_REG LCDCCR
-#define LCDDC2_REG LCDCCR
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-#define PINE3_REG PINE
-#define PINE4_REG PINE
-#define PINE5_REG PINE
-#define PINE6_REG PINE
-#define PINE7_REG PINE
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ACME_REG ADCSRB
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-
-/* DDRF */
-#define DDF0_REG DDRF
-#define DDF1_REG DDRF
-#define DDF2_REG DDRF
-#define DDF3_REG DDRF
-#define DDF4_REG DDRF
-#define DDF5_REG DDRF
-#define DDF6_REG DDRF
-#define DDF7_REG DDRF
-
-/* OCR0A */
-#define OCR0A0_REG OCR0A
-#define OCR0A1_REG OCR0A
-#define OCR0A2_REG OCR0A
-#define OCR0A3_REG OCR0A
-#define OCR0A4_REG OCR0A
-#define OCR0A5_REG OCR0A
-#define OCR0A6_REG OCR0A
-#define OCR0A7_REG OCR0A
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* USICR */
-#define USITC_REG USICR
-#define USICLK_REG USICR
-#define USICS0_REG USICR
-#define USICS1_REG USICR
-#define USIWM0_REG USICR
-#define USIWM1_REG USICR
-#define USIOIE_REG USICR
-#define USISIE_REG USICR
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* LCDFRR */
-#define LCDCD0_REG LCDFRR
-#define LCDCD1_REG LCDFRR
-#define LCDCD2_REG LCDFRR
-#define LCDPS0_REG LCDFRR
-#define LCDPS1_REG LCDFRR
-#define LCDPS2_REG LCDFRR
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define PCIE0_REG EIMSK
-#define PCIE1_REG EIMSK
-#define PCIE2_REG EIMSK
-#define PCIE3_REG EIMSK
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* PINJ */
-#define PINJ0_REG PINJ
-#define PINJ1_REG PINJ
-#define PINJ2_REG PINJ
-#define PINJ3_REG PINJ
-#define PINJ4_REG PINJ
-#define PINJ5_REG PINJ
-#define PINJ6_REG PINJ
-
-/* PINH */
-#define PINH0_REG PINH
-#define PINH1_REG PINH
-#define PINH2_REG PINH
-#define PINH3_REG PINH
-#define PINH4_REG PINH
-#define PINH5_REG PINH
-#define PINH6_REG PINH
-#define PINH7_REG PINH
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-#define PCINT15_REG PCMSK1
-
-/* PCMSK2 */
-#define PCINT16_REG PCMSK2
-#define PCINT17_REG PCMSK2
-#define PCINT18_REG PCMSK2
-#define PCINT19_REG PCMSK2
-#define PCINT20_REG PCMSK2
-#define PCINT21_REG PCMSK2
-#define PCINT22_REG PCMSK2
-#define PCINT23_REG PCMSK2
-
-/* PCMSK3 */
-#define PCINT24_REG PCMSK3
-#define PCINT25_REG PCMSK3
-#define PCINT26_REG PCMSK3
-#define PCINT27_REG PCMSK3
-#define PCINT28_REG PCMSK3
-#define PCINT29_REG PCMSK3
-#define PCINT30_REG PCMSK3
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define PCIF0_REG EIFR
-#define PCIF1_REG EIFR
-#define PCIF2_REG EIFR
-#define PCIF3_REG EIFR
-
-/* PING */
-#define PING0_REG PING
-#define PING1_REG PING
-#define PING2_REG PING
-#define PING3_REG PING
-#define PING4_REG PING
-#define PING5_REG PING
-
-/* PINF */
-#define PINF0_REG PINF
-#define PINF1_REG PINF
-#define PINF2_REG PINF
-#define PINF3_REG PINF
-#define PINF4_REG PINF
-#define PINF5_REG PINF
-#define PINF6_REG PINF
-#define PINF7_REG PINF
-
-/* PORTF */
-#define PORTF0_REG PORTF
-#define PORTF1_REG PORTF
-#define PORTF2_REG PORTF
-#define PORTF3_REG PORTF
-#define PORTF4_REG PORTF
-#define PORTF5_REG PORTF
-#define PORTF6_REG PORTF
-#define PORTF7_REG PORTF
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-
-/* USIDR */
-#define USIDR0_REG USIDR
-#define USIDR1_REG USIDR
-#define USIDR2_REG USIDR
-#define USIDR3_REG USIDR
-#define USIDR4_REG USIDR
-#define USIDR5_REG USIDR
-#define USIDR6_REG USIDR
-#define USIDR7_REG USIDR
-
-/* pins mapping */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE1A_NUM 1
-#define SIG_OUTPUT_COMPARE1B_NUM 2
-#define SIG_OUTPUT_COMPARE2_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM1A_NUM 1
-#define PWM1B_NUM 2
-#define PWM2_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* OCR2A */
-#define OCR2A0_REG OCR2A
-#define OCR2A1_REG OCR2A
-#define OCR2A2_REG OCR2A
-#define OCR2A3_REG OCR2A
-#define OCR2A4_REG OCR2A
-#define OCR2A5_REG OCR2A
-#define OCR2A6_REG OCR2A
-#define OCR2A7_REG OCR2A
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSART0_REG PRR
-#define PRSPI_REG PRR
-#define PRTIM1_REG PRR
-#define PRLCD_REG PRR
-
-/* PORTJ */
-#define PORTJ0_REG PORTJ
-#define PORTJ1_REG PORTJ
-#define PORTJ2_REG PORTJ
-#define PORTJ3_REG PORTJ
-#define PORTJ4_REG PORTJ
-#define PORTJ5_REG PORTJ
-#define PORTJ6_REG PORTJ
-
-/* PORTH */
-#define PORTH0_REG PORTH
-#define PORTH1_REG PORTH
-#define PORTH2_REG PORTH
-#define PORTH3_REG PORTH
-#define PORTH4_REG PORTH
-#define PORTH5_REG PORTH
-#define PORTH6_REG PORTH
-#define PORTH7_REG PORTH
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* PORTG */
-#define PORTG0_REG PORTG
-#define PORTG1_REG PORTG
-#define PORTG2_REG PORTG
-#define PORTG3_REG PORTG
-#define PORTG4_REG PORTG
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL0_REG UCSR0C
-
-/* USISR */
-#define USICNT0_REG USISR
-#define USICNT1_REG USISR
-#define USICNT2_REG USISR
-#define USICNT3_REG USISR
-#define USIDC_REG USISR
-#define USIPF_REG USISR
-#define USIOIF_REG USISR
-#define USISIF_REG USISR
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* UDR0 */
-#define UDR00_REG UDR0
-#define UDR01_REG UDR0
-#define UDR02_REG UDR0
-#define UDR03_REG UDR0
-#define UDR04_REG UDR0
-#define UDR05_REG UDR0
-#define UDR06_REG UDR0
-#define UDR07_REG UDR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* ASSR */
-#define TCR2UB_REG ASSR
-#define OCR2UB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRJ */
-#define DDJ0_REG DDRJ
-#define DDJ1_REG DDRJ
-#define DDJ2_REG DDRJ
-#define DDJ3_REG DDRJ
-#define DDJ4_REG DDRJ
-#define DDJ5_REG DDRJ
-#define DDJ6_REG DDRJ
-
-/* DDRH */
-#define DDH0_REG DDRH
-#define DDH1_REG DDRH
-#define DDH2_REG DDRH
-#define DDH3_REG DDRH
-#define DDH4_REG DDRH
-#define DDH5_REG DDRH
-#define DDH6_REG DDRH
-#define DDH7_REG DDRH
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* DDRG */
-#define DDG0_REG DDRG
-#define DDG1_REG DDRG
-#define DDG2_REG DDRG
-#define DDG3_REG DDRG
-#define DDG4_REG DDRG
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* LCDDR3 */
-#define SEG024_REG LCDDR3
-#define SEG025_REG LCDDR3
-#define SEG026_REG LCDDR3
-#define SEG027_REG LCDDR3
-#define SEG028_REG LCDDR3
-#define SEG029_REG LCDDR3
-#define SEG030_REG LCDDR3
-#define SEG031_REG LCDDR3
-
-/* LCDDR2 */
-#define SEG016_REG LCDDR2
-#define SEG017_REG LCDDR2
-#define SEG018_REG LCDDR2
-#define SEG019_REG LCDDR2
-#define SEG020_REG LCDDR2
-#define SEG021_REG LCDDR2
-#define SEG022_REG LCDDR2
-#define SEG023_REG LCDDR2
-
-/* LCDDR1 */
-#define SEG008_REG LCDDR1
-#define SEG009_REG LCDDR1
-#define SEG010_REG LCDDR1
-#define SEG011_REG LCDDR1
-#define SEG012_REG LCDDR1
-#define SEG013_REG LCDDR1
-#define SEG014_REG LCDDR1
-#define SEG015_REG LCDDR1
-
-/* LCDDR0 */
-#define SEG000_REG LCDDR0
-#define SEG001_REG LCDDR0
-#define SEG002_REG LCDDR0
-#define SEG003_REG LCDDR0
-#define SEG004_REG LCDDR0
-#define SEG005_REG LCDDR0
-#define SEG006_REG LCDDR0
-#define SEG007_REG LCDDR0
-
-/* LCDDR7 */
-#define SEG116_REG LCDDR7
-#define SEG117_REG LCDDR7
-#define SEG118_REG LCDDR7
-#define SEG119_REG LCDDR7
-#define SEG120_REG LCDDR7
-#define SEG121_REG LCDDR7
-#define SEG122_REG LCDDR7
-#define SEG123_REG LCDDR7
-
-/* LCDDR6 */
-#define SEG108_REG LCDDR6
-#define SEG109_REG LCDDR6
-#define SEG110_REG LCDDR6
-#define SEG111_REG LCDDR6
-#define SEG112_REG LCDDR6
-#define SEG113_REG LCDDR6
-#define SEG114_REG LCDDR6
-#define SEG115_REG LCDDR6
-
-/* LCDDR5 */
-#define SEG100_REG LCDDR5
-#define SEG101_REG LCDDR5
-#define SEG102_REG LCDDR5
-#define SEG103_REG LCDDR5
-#define SEG104_REG LCDDR5
-#define SEG105_REG LCDDR5
-#define SEG106_REG LCDDR5
-#define SEG107_REG LCDDR5
-
-/* LCDDR4 */
-#define SEG032_REG LCDDR4
-#define SEG033_REG LCDDR4
-#define SEG034_REG LCDDR4
-#define SEG035_REG LCDDR4
-#define SEG036_REG LCDDR4
-#define SEG037_REG LCDDR4
-#define SEG038_REG LCDDR4
-#define SEG039_REG LCDDR4
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* LCDDR9 */
-#define SEG132_REG LCDDR9
-#define SEG133_REG LCDDR9
-#define SEG134_REG LCDDR9
-#define SEG135_REG LCDDR9
-#define SEG136_REG LCDDR9
-#define SEG137_REG LCDDR9
-#define SEG138_REG LCDDR9
-#define SEG139_REG LCDDR9
-
-/* LCDDR8 */
-#define SEG124_REG LCDDR8
-#define SEG125_REG LCDDR8
-#define SEG126_REG LCDDR8
-#define SEG127_REG LCDDR8
-#define SEG128_REG LCDDR8
-#define SEG129_REG LCDDR8
-#define SEG130_REG LCDDR8
-#define SEG131_REG LCDDR8
-
-/* LCDCRA */
-#define LCDBL_REG LCDCRA
-#define LCDCCD_REG LCDCRA
-#define LCDBD_REG LCDCRA
-#define LCDIE_REG LCDCRA
-#define LCDIF_REG LCDCRA
-#define LCDAB_REG LCDCRA
-#define LCDEN_REG LCDCRA
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-#define DDE3_REG DDRE
-#define DDE4_REG DDRE
-#define DDE5_REG DDRE
-#define DDE6_REG DDRE
-#define DDE7_REG DDRE
-
-/* LCDCRB */
-#define LCDPM0_REG LCDCRB
-#define LCDPM1_REG LCDCRB
-#define LCDPM2_REG LCDCRB
-#define LCDPM3_REG LCDCRB
-#define LCDMUX0_REG LCDCRB
-#define LCDMUX1_REG LCDCRB
-#define LCD2B_REG LCDCRB
-#define LCDCS_REG LCDCRB
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TCCR0A */
-#define CS00_REG TCCR0A
-#define CS01_REG TCCR0A
-#define CS02_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-#define WGM00_REG TCCR0A
-#define FOC0A_REG TCCR0A
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* GTCCR */
-#define PSR310_REG GTCCR
-#define TSM_REG GTCCR
-#define PSR2_REG GTCCR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* LCDDR19 */
-#define SEG332_REG LCDDR19
-#define SEG333_REG LCDDR19
-#define SEG334_REG LCDDR19
-#define SEG335_REG LCDDR19
-#define SEG336_REG LCDDR19
-#define SEG337_REG LCDDR19
-#define SEG338_REG LCDDR19
-#define SEG339_REG LCDDR19
-
-/* LCDDR18 */
-#define SEG324_REG LCDDR18
-#define SEG325_REG LCDDR18
-#define SEG326_REG LCDDR18
-#define SEG327_REG LCDDR18
-#define SEG328_REG LCDDR18
-#define SEG329_REG LCDDR18
-#define SEG330_REG LCDDR18
-#define SEG331_REG LCDDR18
-
-/* LCDDR13 */
-#define SEG224_REG LCDDR13
-#define SEG225_REG LCDDR13
-#define SEG226_REG LCDDR13
-#define SEG227_REG LCDDR13
-#define SEG228_REG LCDDR13
-#define SEG229_REG LCDDR13
-#define SEG230_REG LCDDR13
-#define SEG231_REG LCDDR13
-
-/* LCDDR12 */
-#define SEG216_REG LCDDR12
-#define SEG217_REG LCDDR12
-#define SEG218_REG LCDDR12
-#define SEG219_REG LCDDR12
-#define SEG220_REG LCDDR12
-#define SEG221_REG LCDDR12
-#define SEG222_REG LCDDR12
-#define SEG223_REG LCDDR12
-
-/* LCDDR11 */
-#define SEG208_REG LCDDR11
-#define SEG209_REG LCDDR11
-#define SEG210_REG LCDDR11
-#define SEG211_REG LCDDR11
-#define SEG212_REG LCDDR11
-#define SEG213_REG LCDDR11
-#define SEG214_REG LCDDR11
-#define SEG215_REG LCDDR11
-
-/* LCDDR10 */
-#define SEG200_REG LCDDR10
-#define SEG201_REG LCDDR10
-#define SEG202_REG LCDDR10
-#define SEG203_REG LCDDR10
-#define SEG204_REG LCDDR10
-#define SEG205_REG LCDDR10
-#define SEG206_REG LCDDR10
-#define SEG207_REG LCDDR10
-
-/* LCDDR17 */
-#define SEG316_REG LCDDR17
-#define SEG317_REG LCDDR17
-#define SEG318_REG LCDDR17
-#define SEG319_REG LCDDR17
-#define SEG320_REG LCDDR17
-#define SEG321_REG LCDDR17
-#define SEG322_REG LCDDR17
-#define SEG323_REG LCDDR17
-
-/* LCDDR16 */
-#define SEG308_REG LCDDR16
-#define SEG309_REG LCDDR16
-#define SEG310_REG LCDDR16
-#define SEG311_REG LCDDR16
-#define SEG312_REG LCDDR16
-#define SEG313_REG LCDDR16
-#define SEG314_REG LCDDR16
-#define SEG315_REG LCDDR16
-
-/* LCDDR15 */
-#define SEG300_REG LCDDR15
-#define SEG301_REG LCDDR15
-#define SEG302_REG LCDDR15
-#define SEG303_REG LCDDR15
-#define SEG304_REG LCDDR15
-#define SEG305_REG LCDDR15
-#define SEG306_REG LCDDR15
-#define SEG307_REG LCDDR15
-
-/* LCDDR14 */
-#define SEG232_REG LCDDR14
-#define SEG233_REG LCDDR14
-#define SEG234_REG LCDDR14
-#define SEG235_REG LCDDR14
-#define SEG236_REG LCDDR14
-#define SEG237_REG LCDDR14
-#define SEG238_REG LCDDR14
-#define SEG239_REG LCDDR14
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* MCUSR */
-#define JTRF_REG MCUSR
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TCCR2A */
-#define CS20_REG TCCR2A
-#define CS21_REG TCCR2A
-#define CS22_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-#define WGM20_REG TCCR2A
-#define FOC2A_REG TCCR2A
-
-/* UBRR0H */
-#define UBRR8_REG UBRR0H
-#define UBRR9_REG UBRR0H
-#define UBRR10_REG UBRR0H
-#define UBRR11_REG UBRR0H
-
-/* UBRR0L */
-#define UBRR0_REG UBRR0L
-#define UBRR1_REG UBRR0L
-#define UBRR2_REG UBRR0L
-#define UBRR3_REG UBRR0L
-#define UBRR4_REG UBRR0L
-#define UBRR5_REG UBRR0L
-#define UBRR6_REG UBRR0L
-#define UBRR7_REG UBRR0L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-
-/* EEARL */
-#define EEAR00_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* MCUCR */
-#define JTD_REG MCUCR
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-#define BODSE_REG MCUCR
-#define BODS_REG MCUCR
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-#define PORTE3_REG PORTE
-#define PORTE4_REG PORTE
-#define PORTE5_REG PORTE
-#define PORTE6_REG PORTE
-#define PORTE7_REG PORTE
-
-/* LCDCCR */
-#define LCDCC0_REG LCDCCR
-#define LCDCC1_REG LCDCCR
-#define LCDCC2_REG LCDCCR
-#define LCDCC3_REG LCDCCR
-#define LCDMDT_REG LCDCCR
-#define LCDDC0_REG LCDCCR
-#define LCDDC1_REG LCDCCR
-#define LCDDC2_REG LCDCCR
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-#define PINE3_REG PINE
-#define PINE4_REG PINE
-#define PINE5_REG PINE
-#define PINE6_REG PINE
-#define PINE7_REG PINE
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ACME_REG ADCSRB
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-
-/* DDRF */
-#define DDF0_REG DDRF
-#define DDF1_REG DDRF
-#define DDF2_REG DDRF
-#define DDF3_REG DDRF
-#define DDF4_REG DDRF
-#define DDF5_REG DDRF
-#define DDF6_REG DDRF
-#define DDF7_REG DDRF
-
-/* OCR0A */
-#define OCR0A0_REG OCR0A
-#define OCR0A1_REG OCR0A
-#define OCR0A2_REG OCR0A
-#define OCR0A3_REG OCR0A
-#define OCR0A4_REG OCR0A
-#define OCR0A5_REG OCR0A
-#define OCR0A6_REG OCR0A
-#define OCR0A7_REG OCR0A
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* USICR */
-#define USITC_REG USICR
-#define USICLK_REG USICR
-#define USICS0_REG USICR
-#define USICS1_REG USICR
-#define USIWM0_REG USICR
-#define USIWM1_REG USICR
-#define USIOIE_REG USICR
-#define USISIE_REG USICR
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* LCDFRR */
-#define LCDCD0_REG LCDFRR
-#define LCDCD1_REG LCDFRR
-#define LCDCD2_REG LCDFRR
-#define LCDPS0_REG LCDFRR
-#define LCDPS1_REG LCDFRR
-#define LCDPS2_REG LCDFRR
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define PCIE0_REG EIMSK
-#define PCIE1_REG EIMSK
-#define PCIE2_REG EIMSK
-#define PCIE3_REG EIMSK
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* PINJ */
-#define PINJ0_REG PINJ
-#define PINJ1_REG PINJ
-#define PINJ2_REG PINJ
-#define PINJ3_REG PINJ
-#define PINJ4_REG PINJ
-#define PINJ5_REG PINJ
-#define PINJ6_REG PINJ
-
-/* PINH */
-#define PINH0_REG PINH
-#define PINH1_REG PINH
-#define PINH2_REG PINH
-#define PINH3_REG PINH
-#define PINH4_REG PINH
-#define PINH5_REG PINH
-#define PINH6_REG PINH
-#define PINH7_REG PINH
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-#define PCINT15_REG PCMSK1
-
-/* PCMSK2 */
-#define PCINT16_REG PCMSK2
-#define PCINT17_REG PCMSK2
-#define PCINT18_REG PCMSK2
-#define PCINT19_REG PCMSK2
-#define PCINT20_REG PCMSK2
-#define PCINT21_REG PCMSK2
-#define PCINT22_REG PCMSK2
-#define PCINT23_REG PCMSK2
-
-/* PCMSK3 */
-#define PCINT24_REG PCMSK3
-#define PCINT25_REG PCMSK3
-#define PCINT26_REG PCMSK3
-#define PCINT27_REG PCMSK3
-#define PCINT28_REG PCMSK3
-#define PCINT29_REG PCMSK3
-#define PCINT30_REG PCMSK3
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define PCIF0_REG EIFR
-#define PCIF1_REG EIFR
-#define PCIF2_REG EIFR
-#define PCIF3_REG EIFR
-
-/* PING */
-#define PING0_REG PING
-#define PING1_REG PING
-#define PING2_REG PING
-#define PING3_REG PING
-#define PING4_REG PING
-#define PING5_REG PING
-
-/* PINF */
-#define PINF0_REG PINF
-#define PINF1_REG PINF
-#define PINF2_REG PINF
-#define PINF3_REG PINF
-#define PINF4_REG PINF
-#define PINF5_REG PINF
-#define PINF6_REG PINF
-#define PINF7_REG PINF
-
-/* PORTF */
-#define PORTF0_REG PORTF
-#define PORTF1_REG PORTF
-#define PORTF2_REG PORTF
-#define PORTF3_REG PORTF
-#define PORTF4_REG PORTF
-#define PORTF5_REG PORTF
-#define PORTF6_REG PORTF
-#define PORTF7_REG PORTF
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-
-/* USIDR */
-#define USIDR0_REG USIDR
-#define USIDR1_REG USIDR
-#define USIDR2_REG USIDR
-#define USIDR3_REG USIDR
-#define USIDR4_REG USIDR
-#define USIDR5_REG USIDR
-#define USIDR6_REG USIDR
-#define USIDR7_REG USIDR
-
-/* pins mapping */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE1A_NUM 1
-#define SIG_OUTPUT_COMPARE1B_NUM 2
-#define SIG_OUTPUT_COMPARE2_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM1A_NUM 1
-#define PWM1B_NUM 2
-#define PWM2_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* OCR2A */
-#define OCR2A0_REG OCR2A
-#define OCR2A1_REG OCR2A
-#define OCR2A2_REG OCR2A
-#define OCR2A3_REG OCR2A
-#define OCR2A4_REG OCR2A
-#define OCR2A5_REG OCR2A
-#define OCR2A6_REG OCR2A
-#define OCR2A7_REG OCR2A
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSART0_REG PRR
-#define PRSPI_REG PRR
-#define PRTIM1_REG PRR
-#define PRLCD_REG PRR
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* PORTG */
-#define PORTG0_REG PORTG
-#define PORTG1_REG PORTG
-#define PORTG2_REG PORTG
-#define PORTG3_REG PORTG
-#define PORTG4_REG PORTG
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL0_REG UCSR0C
-
-/* USISR */
-#define USICNT0_REG USISR
-#define USICNT1_REG USISR
-#define USICNT2_REG USISR
-#define USICNT3_REG USISR
-#define USIDC_REG USISR
-#define USIPF_REG USISR
-#define USIOIF_REG USISR
-#define USISIF_REG USISR
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* UDR0 */
-#define UDR00_REG UDR0
-#define UDR01_REG UDR0
-#define UDR02_REG UDR0
-#define UDR03_REG UDR0
-#define UDR04_REG UDR0
-#define UDR05_REG UDR0
-#define UDR06_REG UDR0
-#define UDR07_REG UDR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* ASSR */
-#define TCR2UB_REG ASSR
-#define OCR2UB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* DDRG */
-#define DDG0_REG DDRG
-#define DDG1_REG DDRG
-#define DDG2_REG DDRG
-#define DDG3_REG DDRG
-#define DDG4_REG DDRG
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* LCDDR3 */
-#define SEG024_REG LCDDR3
-
-/* LCDDR2 */
-#define SEG016_REG LCDDR2
-#define SEG017_REG LCDDR2
-#define SEG018_REG LCDDR2
-#define SEG019_REG LCDDR2
-#define SEG020_REG LCDDR2
-#define SEG021_REG LCDDR2
-#define SEG022_REG LCDDR2
-#define SEG023_REG LCDDR2
-
-/* LCDDR1 */
-#define SEG008_REG LCDDR1
-#define SEG009_REG LCDDR1
-#define SEG010_REG LCDDR1
-#define SEG011_REG LCDDR1
-#define SEG012_REG LCDDR1
-#define SEG013_REG LCDDR1
-#define SEG014_REG LCDDR1
-#define SEG015_REG LCDDR1
-
-/* LCDDR0 */
-#define SEG000_REG LCDDR0
-#define SEG001_REG LCDDR0
-#define SEG002_REG LCDDR0
-#define SEG003_REG LCDDR0
-#define SEG004_REG LCDDR0
-#define SEG005_REG LCDDR0
-#define SEG006_REG LCDDR0
-#define SEG007_REG LCDDR0
-
-/* LCDDR7 */
-#define SEG116_REG LCDDR7
-#define SEG117_REG LCDDR7
-#define SEG118_REG LCDDR7
-#define SEG119_REG LCDDR7
-#define SEG120_REG LCDDR7
-#define SEG121_REG LCDDR7
-#define SEG122_REG LCDDR7
-#define SEG123_REG LCDDR7
-
-/* LCDDR6 */
-#define SEG108_REG LCDDR6
-#define SEG109_REG LCDDR6
-#define SEG110_REG LCDDR6
-#define SEG111_REG LCDDR6
-#define SEG112_REG LCDDR6
-#define SEG113_REG LCDDR6
-#define SEG114_REG LCDDR6
-#define SEG115_REG LCDDR6
-
-/* LCDDR5 */
-#define SEG100_REG LCDDR5
-#define SEG101_REG LCDDR5
-#define SEG102_REG LCDDR5
-#define SEG103_REG LCDDR5
-#define SEG104_REG LCDDR5
-#define SEG105_REG LCDDR5
-#define SEG106_REG LCDDR5
-#define SEG107_REG LCDDR5
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* LCDDR8 */
-#define SEG124_REG LCDDR8
-
-/* LCDCRA */
-#define LCDBL_REG LCDCRA
-#define LCDCCD_REG LCDCRA
-#define LCDBD_REG LCDCRA
-#define LCDIE_REG LCDCRA
-#define LCDIF_REG LCDCRA
-#define LCDAB_REG LCDCRA
-#define LCDEN_REG LCDCRA
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-#define DDE3_REG DDRE
-#define DDE4_REG DDRE
-#define DDE5_REG DDRE
-#define DDE6_REG DDRE
-#define DDE7_REG DDRE
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TCCR0A */
-#define CS00_REG TCCR0A
-#define CS01_REG TCCR0A
-#define CS02_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-#define WGM00_REG TCCR0A
-#define FOC0A_REG TCCR0A
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* GTCCR */
-#define PSR310_REG GTCCR
-#define TSM_REG GTCCR
-#define PSR2_REG GTCCR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* LCDCRB */
-#define LCDPM0_REG LCDCRB
-#define LCDPM1_REG LCDCRB
-#define LCDPM2_REG LCDCRB
-#define LCDPM3_REG LCDCRB
-#define LCDMUX0_REG LCDCRB
-#define LCDMUX1_REG LCDCRB
-#define LCD2B_REG LCDCRB
-#define LCDCS_REG LCDCRB
-
-/* LCDDR18 */
-#define SEG324_REG LCDDR18
-
-/* LCDDR13 */
-#define SEG224_REG LCDDR13
-
-/* LCDDR12 */
-#define SEG216_REG LCDDR12
-#define SEG217_REG LCDDR12
-#define SEG218_REG LCDDR12
-#define SEG219_REG LCDDR12
-#define SEG220_REG LCDDR12
-#define SEG221_REG LCDDR12
-#define SEG222_REG LCDDR12
-#define SEG223_REG LCDDR12
-
-/* LCDDR11 */
-#define SEG208_REG LCDDR11
-#define SEG209_REG LCDDR11
-#define SEG210_REG LCDDR11
-#define SEG211_REG LCDDR11
-#define SEG212_REG LCDDR11
-#define SEG213_REG LCDDR11
-#define SEG214_REG LCDDR11
-#define SEG215_REG LCDDR11
-
-/* LCDDR10 */
-#define SEG200_REG LCDDR10
-#define SEG201_REG LCDDR10
-#define SEG202_REG LCDDR10
-#define SEG203_REG LCDDR10
-#define SEG204_REG LCDDR10
-#define SEG205_REG LCDDR10
-#define SEG206_REG LCDDR10
-#define SEG207_REG LCDDR10
-
-/* LCDDR17 */
-#define SEG316_REG LCDDR17
-#define SEG317_REG LCDDR17
-#define SEG318_REG LCDDR17
-#define SEG319_REG LCDDR17
-#define SEG320_REG LCDDR17
-#define SEG321_REG LCDDR17
-#define SEG322_REG LCDDR17
-#define SEG323_REG LCDDR17
-
-/* LCDDR16 */
-#define SEG308_REG LCDDR16
-#define SEG309_REG LCDDR16
-#define SEG310_REG LCDDR16
-#define SEG311_REG LCDDR16
-#define SEG312_REG LCDDR16
-#define SEG313_REG LCDDR16
-#define SEG314_REG LCDDR16
-#define SEG315_REG LCDDR16
-
-/* LCDDR15 */
-#define SEG300_REG LCDDR15
-#define SEG301_REG LCDDR15
-#define SEG302_REG LCDDR15
-#define SEG303_REG LCDDR15
-#define SEG304_REG LCDDR15
-#define SEG305_REG LCDDR15
-#define SEG306_REG LCDDR15
-#define SEG307_REG LCDDR15
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* MCUSR */
-#define JTRF_REG MCUSR
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TCCR2A */
-#define CS20_REG TCCR2A
-#define CS21_REG TCCR2A
-#define CS22_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-#define WGM20_REG TCCR2A
-#define FOC2A_REG TCCR2A
-
-/* UBRR0H */
-#define UBRR8_REG UBRR0H
-#define UBRR9_REG UBRR0H
-#define UBRR10_REG UBRR0H
-#define UBRR11_REG UBRR0H
-
-/* UBRR0L */
-#define UBRR0_REG UBRR0L
-#define UBRR1_REG UBRR0L
-#define UBRR2_REG UBRR0L
-#define UBRR3_REG UBRR0L
-#define UBRR4_REG UBRR0L
-#define UBRR5_REG UBRR0L
-#define UBRR6_REG UBRR0L
-#define UBRR7_REG UBRR0L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-
-/* EEARL */
-#define EEAR00_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* MCUCR */
-#define JTD_REG MCUCR
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-#define BODSE_REG MCUCR
-#define BODS_REG MCUCR
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-#define PORTE3_REG PORTE
-#define PORTE4_REG PORTE
-#define PORTE5_REG PORTE
-#define PORTE6_REG PORTE
-#define PORTE7_REG PORTE
-
-/* LCDCCR */
-#define LCDCC0_REG LCDCCR
-#define LCDCC1_REG LCDCCR
-#define LCDCC2_REG LCDCCR
-#define LCDCC3_REG LCDCCR
-#define LCDMDT_REG LCDCCR
-#define LCDDC0_REG LCDCCR
-#define LCDDC1_REG LCDCCR
-#define LCDDC2_REG LCDCCR
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-#define PINE3_REG PINE
-#define PINE4_REG PINE
-#define PINE5_REG PINE
-#define PINE6_REG PINE
-#define PINE7_REG PINE
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ACME_REG ADCSRB
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-
-/* DDRF */
-#define DDF0_REG DDRF
-#define DDF1_REG DDRF
-#define DDF2_REG DDRF
-#define DDF3_REG DDRF
-#define DDF4_REG DDRF
-#define DDF5_REG DDRF
-#define DDF6_REG DDRF
-#define DDF7_REG DDRF
-
-/* OCR0A */
-#define OCR0A0_REG OCR0A
-#define OCR0A1_REG OCR0A
-#define OCR0A2_REG OCR0A
-#define OCR0A3_REG OCR0A
-#define OCR0A4_REG OCR0A
-#define OCR0A5_REG OCR0A
-#define OCR0A6_REG OCR0A
-#define OCR0A7_REG OCR0A
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* USICR */
-#define USITC_REG USICR
-#define USICLK_REG USICR
-#define USICS0_REG USICR
-#define USICS1_REG USICR
-#define USIWM0_REG USICR
-#define USIWM1_REG USICR
-#define USIOIE_REG USICR
-#define USISIE_REG USICR
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* LCDFRR */
-#define LCDCD0_REG LCDFRR
-#define LCDCD1_REG LCDFRR
-#define LCDCD2_REG LCDFRR
-#define LCDPS0_REG LCDFRR
-#define LCDPS1_REG LCDFRR
-#define LCDPS2_REG LCDFRR
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define PCIE0_REG EIMSK
-#define PCIE1_REG EIMSK
-#define PCIE2_REG EIMSK
-#define PCIE3_REG EIMSK
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-#define PCINT15_REG PCMSK1
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define PCIF0_REG EIFR
-#define PCIF1_REG EIFR
-#define PCIF2_REG EIFR
-#define PCIF3_REG EIFR
-
-/* PING */
-#define PING0_REG PING
-#define PING1_REG PING
-#define PING2_REG PING
-#define PING3_REG PING
-#define PING4_REG PING
-#define PING5_REG PING
-
-/* PINF */
-#define PINF0_REG PINF
-#define PINF1_REG PINF
-#define PINF2_REG PINF
-#define PINF3_REG PINF
-#define PINF4_REG PINF
-#define PINF5_REG PINF
-#define PINF6_REG PINF
-#define PINF7_REG PINF
-
-/* PORTF */
-#define PORTF0_REG PORTF
-#define PORTF1_REG PORTF
-#define PORTF2_REG PORTF
-#define PORTF3_REG PORTF
-#define PORTF4_REG PORTF
-#define PORTF5_REG PORTF
-#define PORTF6_REG PORTF
-#define PORTF7_REG PORTF
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-
-/* USIDR */
-#define USIDR0_REG USIDR
-#define USIDR1_REG USIDR
-#define USIDR2_REG USIDR
-#define USIDR3_REG USIDR
-#define USIDR4_REG USIDR
-#define USIDR5_REG USIDR
-#define USIDR6_REG USIDR
-#define USIDR7_REG USIDR
-
-/* pins mapping */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE1A_NUM 1
-#define SIG_OUTPUT_COMPARE1B_NUM 2
-#define SIG_OUTPUT_COMPARE2_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM1A_NUM 1
-#define PWM1B_NUM 2
-#define PWM2_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDTOE_REG WDTCR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* TCCR0 */
-#define CS00_REG TCCR0
-#define CS01_REG TCCR0
-#define CS02_REG TCCR0
-#define WGM01_REG TCCR0
-#define COM00_REG TCCR0
-#define COM01_REG TCCR0
-#define WGM00_REG TCCR0
-#define FOC0_REG TCCR0
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* GICR */
-#define IVCE_REG GICR
-#define IVSEL_REG GICR
-#define INT2_REG GICR
-#define INT0_REG GICR
-#define INT1_REG GICR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define FOC1B_REG TCCR1A
-#define FOC1A_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* GIFR */
-#define INTF2_REG GIFR
-#define INTF0_REG GIFR
-#define INTF1_REG GIFR
-
-/* TIMSK */
-#define TOIE0_REG TIMSK
-#define OCIE0_REG TIMSK
-#define TOIE2_REG TIMSK
-#define OCIE2_REG TIMSK
-#define TOIE1_REG TIMSK
-#define OCIE1B_REG TIMSK
-#define OCIE1A_REG TIMSK
-#define TICIE1_REG TIMSK
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* UCSRA */
-#define MPCM_REG UCSRA
-#define U2X_REG UCSRA
-#define UPE_REG UCSRA
-#define DOR_REG UCSRA
-#define FE_REG UCSRA
-#define UDRE_REG UCSRA
-#define TXC_REG UCSRA
-#define RXC_REG UCSRA
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SFIOR */
-#define ACME_REG SFIOR
-#define ADTS0_REG SFIOR
-#define ADTS1_REG SFIOR
-#define ADTS2_REG SFIOR
-#define PSR10_REG SFIOR
-#define PSR2_REG SFIOR
-#define PUD_REG SFIOR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* UCSRB */
-#define TXB8_REG UCSRB
-#define RXB8_REG UCSRB
-#define UCSZ2_REG UCSRB
-#define TXEN_REG UCSRB
-#define RXEN_REG UCSRB
-#define UDRIE_REG UCSRB
-#define TXCIE_REG UCSRB
-#define RXCIE_REG UCSRB
-
-/* UCSRC */
-#define UCPOL_REG UCSRC
-#define UCSZ0_REG UCSRC
-#define UCSZ1_REG UCSRC
-#define USBS_REG UCSRC
-#define UPM0_REG UCSRC
-#define UPM1_REG UCSRC
-#define UMSEL_REG UCSRC
-#define URSEL_REG UCSRC
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* UDR */
-#define UDR0_REG UDR
-#define UDR1_REG UDR
-#define UDR2_REG UDR
-#define UDR3_REG UDR
-#define UDR4_REG UDR
-#define UDR5_REG UDR
-#define UDR6_REG UDR
-#define UDR7_REG UDR
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* SPMCR */
-#define SPMEN_REG SPMCR
-#define PGERS_REG SPMCR
-#define PGWRT_REG SPMCR
-#define BLBSET_REG SPMCR
-#define RWWSRE_REG SPMCR
-#define RWWSB_REG SPMCR
-#define SPMIE_REG SPMCR
-
-/* UBRRH */
-#define UBRR8_REG UBRRH
-#define UBRR9_REG UBRRH
-#define UBRR10_REG UBRRH
-#define UBRR11_REG UBRRH
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* UBRRL */
-#define UBRR0_REG UBRRL
-#define UBRR1_REG UBRRL
-#define UBRR2_REG UBRRL
-#define UBRR3_REG UBRRL
-#define UBRR4_REG UBRRL
-#define UBRR5_REG UBRRL
-#define UBRR6_REG UBRRL
-#define UBRR7_REG UBRRL
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* MCUCSR */
-#define ISC2_REG MCUCSR
-#define PORF_REG MCUCSR
-#define EXTRF_REG MCUCSR
-#define BORF_REG MCUCSR
-#define WDRF_REG MCUCSR
-#define JTRF_REG MCUCSR
-#define JTD_REG MCUCSR
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* TCCR2 */
-#define CS20_REG TCCR2
-#define CS21_REG TCCR2
-#define CS22_REG TCCR2
-#define WGM21_REG TCCR2
-#define COM20_REG TCCR2
-#define COM21_REG TCCR2
-#define WGM20_REG TCCR2
-#define FOC2_REG TCCR2
-
-/* TIFR */
-#define TOV0_REG TIFR
-#define OCF0_REG TIFR
-#define TOV2_REG TIFR
-#define OCF2_REG TIFR
-#define TOV1_REG TIFR
-#define OCF1B_REG TIFR
-#define OCF1A_REG TIFR
-#define ICF1_REG TIFR
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* EEARL */
-#define EEAR00_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define ISC10_REG MCUCR
-#define ISC11_REG MCUCR
-#define SM0_REG MCUCR
-#define SM1_REG MCUCR
-#define SM2_REG MCUCR
-#define SE_REG MCUCR
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* ASSR */
-#define TCR2UB_REG ASSR
-#define OCR2UB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-
-/* OCR0 */
-#define OCR0_0_REG OCR0
-#define OCR0_1_REG OCR0
-#define OCR0_2_REG OCR0
-#define OCR0_3_REG OCR0
-#define OCR0_4_REG OCR0
-#define OCR0_5_REG OCR0
-#define OCR0_6_REG OCR0
-#define OCR0_7_REG OCR0
-
-/* OCR2 */
-#define OCR2_0_REG OCR2
-#define OCR2_1_REG OCR2
-#define OCR2_2_REG OCR2
-#define OCR2_3_REG OCR2
-#define OCR2_4_REG OCR2
-#define OCR2_5_REG OCR2
-#define OCR2_6_REG OCR2
-#define OCR2_7_REG OCR2
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* pins mapping */
-#define ADC0_PORT PORTA
-#define ADC0_BIT 0
-
-#define ADC1_PORT PORTA
-#define ADC1_BIT 1
-
-#define ADC2_PORT PORTA
-#define ADC2_BIT 2
-
-#define ADC3_PORT PORTA
-#define ADC3_BIT 3
-
-#define ADC4_PORT PORTA
-#define ADC4_BIT 4
-
-#define ADc5_PORT PORTA
-#define ADc5_BIT 5
-
-#define ADC6_PORT PORTA
-#define ADC6_BIT 6
-
-#define ADC7_PORT PORTA
-#define ADC7_BIT 7
-
-#define XCK_PORT PORTB
-#define XCK_BIT 0
-#define T0_PORT PORTB
-#define T0_BIT 0
-
-#define T1_PORT PORTB
-#define T1_BIT 1
-
-#define AIN0_PORT PORTB
-#define AIN0_BIT 2
-#define INT2_PORT PORTB
-#define INT2_BIT 2
-
-#define AIN1_PORT PORTB
-#define AIN1_BIT 3
-#define OC0_PORT PORTB
-#define OC0_BIT 3
-
-#define SS_PORT PORTB
-#define SS_BIT 4
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 5
-
-#define MISO_PORT PORTB
-#define MISO_BIT 6
-
-
-#define SCL_PORT PORTC
-#define SCL_BIT 0
-
-#define SDA_PORT PORTC
-#define SDA_BIT 1
-
-#define TMS_PORT PORTC
-#define TMS_BIT 2
-
-#define TCK_PORT PORTC
-#define TCK_BIT 3
-
-#define TDO_PORT PORTC
-#define TDO_BIT 4
-
-#define TDI_PORT PORTC
-#define TDI_BIT 5
-
-#define TOSC1_PORT PORTC
-#define TOSC1_BIT 6
-
-#define TOSC2_PORT PORTC
-#define TOSC2_BIT 7
-
-#define RXD_PORT PORTD
-#define RXD_BIT 0
-
-#define TXD_PORT PORTD
-#define TXD_BIT 1
-
-#define INT0_PORT PORTD
-#define INT0_BIT 2
-
-#define INT1_PORT PORTD
-#define INT1_BIT 3
-
-#define OC1B_PORT PORTD
-#define OC1B_BIT 4
-
-#define OC1A_PORT PORTD
-#define OC1A_BIT 5
-
-#define ICP_PORT PORTD
-#define ICP_BIT 6
-
-#define OC2_PORT PORTD
-#define OC2_BIT 7
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW_TOTAL_NUM 2
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* LINBTR */
-#define LBT0_REG LINBTR
-#define LBT1_REG LINBTR
-#define LBT2_REG LINBTR
-#define LBT3_REG LINBTR
-#define LBT4_REG LINBTR
-#define LBT5_REG LINBTR
-#define LDISR_REG LINBTR
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* LINIDR */
-#define LID0_REG LINIDR
-#define LID1_REG LINIDR
-#define LID2_REG LINIDR
-#define LID3_REG LINIDR
-#define LID4_REG LINIDR
-#define LID5_REG LINIDR
-#define LP0_REG LINIDR
-#define LP1_REG LINIDR
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* ACSR */
-#define AC0O_REG ACSR
-#define AC1O_REG ACSR
-#define AC2O_REG ACSR
-#define AC3O_REG ACSR
-#define AC0IF_REG ACSR
-#define AC1IF_REG ACSR
-#define AC2IF_REG ACSR
-#define AC3IF_REG ACSR
-
-/* LINSEL */
-#define LINDX0_REG LINSEL
-#define LINDX1_REG LINSEL
-#define LINDX2_REG LINSEL
-#define LAINC_REG LINSEL
-
-/* LINCR */
-#define LCMD0_REG LINCR
-#define LCMD1_REG LINCR
-#define LCMD2_REG LINCR
-#define LENA_REG LINCR
-#define LCONF0_REG LINCR
-#define LCONF1_REG LINCR
-#define LIN13_REG LINCR
-#define LSWRES_REG LINCR
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* AC1CON */
-#define AC1M0_REG AC1CON
-#define AC1M1_REG AC1CON
-#define AC1M2_REG AC1CON
-#define AC1ICE_REG AC1CON
-#define AC1IS0_REG AC1CON
-#define AC1IS1_REG AC1CON
-#define AC1IE_REG AC1CON
-#define AC1EN_REG AC1CON
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRLIN_REG PRR
-#define PRSPI_REG PRR
-#define PRTIM0_REG PRR
-#define PRTIM1_REG PRR
-#define PRPSC_REG PRR
-#define PRCAN_REG PRR
-
-/* LINBRRL */
-#define LDIV0_REG LINBRRL
-#define LDIV1_REG LINBRRL
-#define LDIV2_REG LINBRRL
-#define LDIV3_REG LINBRRL
-#define LDIV4_REG LINBRRL
-#define LDIV5_REG LINBRRL
-#define LDIV6_REG LINBRRL
-#define LDIV7_REG LINBRRL
-
-/* LINBRRH */
-#define LDIV8_REG LINBRRH
-#define LDIV9_REG LINBRRH
-#define LDIV10_REG LINBRRH
-#define LDIV11_REG LINBRRH
-
-/* CANGSTA */
-#define ERRP_REG CANGSTA
-#define BOFF_REG CANGSTA
-#define ENFG_REG CANGSTA
-#define RXBSY_REG CANGSTA
-#define TXBSY_REG CANGSTA
-#define OVFG_REG CANGSTA
-
-/* CANGCON */
-#define SWRES_REG CANGCON
-#define ENASTB_REG CANGCON
-#define TEST_REG CANGCON
-#define LISTEN_REG CANGCON
-#define SYNTTC_REG CANGCON
-#define TTC_REG CANGCON
-#define OVRQ_REG CANGCON
-#define ABRQ_REG CANGCON
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* AMP1CSR */
-#define AMP1TS0_REG AMP1CSR
-#define AMP1TS1_REG AMP1CSR
-#define AMP1TS2_REG AMP1CSR
-#define AMPCMP1_REG AMP1CSR
-#define AMP1G0_REG AMP1CSR
-#define AMP1G1_REG AMP1CSR
-#define AMP1IS_REG AMP1CSR
-#define AMP1EN_REG AMP1CSR
-
-/* AC2CON */
-#define AC2M0_REG AC2CON
-#define AC2M1_REG AC2CON
-#define AC2M2_REG AC2CON
-#define AC2IS0_REG AC2CON
-#define AC2IS1_REG AC2CON
-#define AC2IE_REG AC2CON
-#define AC2EN_REG AC2CON
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-#define INT3_REG EIMSK
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-#define ISC20_REG EICRA
-#define ISC21_REG EICRA
-#define ISC30_REG EICRA
-#define ISC31_REG EICRA
-
-/* LINSIR */
-#define LRXOK_REG LINSIR
-#define LTXOK_REG LINSIR
-#define LIDOK_REG LINSIR
-#define LERR_REG LINSIR
-#define LBUSY_REG LINSIR
-#define LIDST0_REG LINSIR
-#define LIDST1_REG LINSIR
-#define LIDST2_REG LINSIR
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define ADC8D_REG DIDR1
-#define ADC9D_REG DIDR1
-#define ADC10D_REG DIDR1
-#define AMP0ND_REG DIDR1
-#define AMP0PD_REG DIDR1
-#define ACMP0D_REG DIDR1
-#define AMP2PD_REG DIDR1
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* CANIDM1 */
-#define IDMSK21_REG CANIDM1
-#define IDMSK22_REG CANIDM1
-#define IDMSK23_REG CANIDM1
-#define IDMSK24_REG CANIDM1
-#define IDMSK25_REG CANIDM1
-#define IDMSK26_REG CANIDM1
-#define IDMSK27_REG CANIDM1
-#define IDMSK28_REG CANIDM1
-
-/* CANIDM3 */
-#define IDMSK5_REG CANIDM3
-#define IDMSK6_REG CANIDM3
-#define IDMSK7_REG CANIDM3
-#define IDMSK8_REG CANIDM3
-#define IDMSK9_REG CANIDM3
-#define IDMSK10_REG CANIDM3
-#define IDMSK11_REG CANIDM3
-#define IDMSK12_REG CANIDM3
-
-/* CANIDM2 */
-#define IDMSK13_REG CANIDM2
-#define IDMSK14_REG CANIDM2
-#define IDMSK15_REG CANIDM2
-#define IDMSK16_REG CANIDM2
-#define IDMSK17_REG CANIDM2
-#define IDMSK18_REG CANIDM2
-#define IDMSK19_REG CANIDM2
-#define IDMSK20_REG CANIDM2
-
-/* CANIDM4 */
-#define IDEMSK_REG CANIDM4
-#define RTRMSK_REG CANIDM4
-#define IDMSK0_REG CANIDM4
-#define IDMSK1_REG CANIDM4
-#define IDMSK2_REG CANIDM4
-#define IDMSK3_REG CANIDM4
-#define IDMSK4_REG CANIDM4
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* CANGIT */
-#define AERG_REG CANGIT
-#define FERG_REG CANGIT
-#define CERG_REG CANGIT
-#define SERG_REG CANGIT
-#define BXOK_REG CANGIT
-#define OVRTIM_REG CANGIT
-#define BOFFIT_REG CANGIT
-#define CANIT_REG CANGIT
-
-/* AC3CON */
-#define AC3M0_REG AC3CON
-#define AC3M1_REG AC3CON
-#define AC3M2_REG AC3CON
-#define AC3IS0_REG AC3CON
-#define AC3IS1_REG AC3CON
-#define AC3IE_REG AC3CON
-#define AC3EN_REG AC3CON
-
-/* LINERR */
-#define LBERR_REG LINERR
-#define LCERR_REG LINERR
-#define LPERR_REG LINERR
-#define LSERR_REG LINERR
-#define LFERR_REG LINERR
-#define LOVERR_REG LINERR
-#define LTOERR_REG LINERR
-#define LABORT_REG LINERR
-
-/* PCICR */
-#define PCIE0_REG PCICR
-#define PCIE1_REG PCICR
-#define PCIE2_REG PCICR
-#define PCIE3_REG PCICR
-
-/* CANGIE */
-#define ENOVRT_REG CANGIE
-#define ENERG_REG CANGIE
-#define ENBX_REG CANGIE
-#define ENERR_REG CANGIE
-#define ENTX_REG CANGIE
-#define ENRX_REG CANGIE
-#define ENBOFF_REG CANGIE
-#define ENIT_REG CANGIE
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* CANIE2 */
-#define IEMOB0_REG CANIE2
-#define IEMOB1_REG CANIE2
-#define IEMOB2_REG CANIE2
-#define IEMOB3_REG CANIE2
-#define IEMOB4_REG CANIE2
-#define IEMOB5_REG CANIE2
-
-/* CANSIT2 */
-#define SIT0_REG CANSIT2
-#define SIT1_REG CANSIT2
-#define SIT2_REG CANSIT2
-#define SIT3_REG CANSIT2
-#define SIT4_REG CANSIT2
-#define SIT5_REG CANSIT2
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* CANIDT4 */
-#define RB0TAG_REG CANIDT4
-#define RB1TAG_REG CANIDT4
-#define RTRTAG_REG CANIDT4
-#define IDT0_REG CANIDT4
-#define IDT1_REG CANIDT4
-#define IDT2_REG CANIDT4
-#define IDT3_REG CANIDT4
-#define IDT4_REG CANIDT4
-
-/* CANIDT2 */
-#define IDT13_REG CANIDT2
-#define IDT14_REG CANIDT2
-#define IDT15_REG CANIDT2
-#define IDT16_REG CANIDT2
-#define IDT17_REG CANIDT2
-#define IDT18_REG CANIDT2
-#define IDT19_REG CANIDT2
-#define IDT20_REG CANIDT2
-
-/* CANIDT3 */
-#define IDT5_REG CANIDT3
-#define IDT6_REG CANIDT3
-#define IDT7_REG CANIDT3
-#define IDT8_REG CANIDT3
-#define IDT9_REG CANIDT3
-#define IDT10_REG CANIDT3
-#define IDT11_REG CANIDT3
-#define IDT12_REG CANIDT3
-
-/* CANIDT1 */
-#define IDT21_REG CANIDT1
-#define IDT22_REG CANIDT1
-#define IDT23_REG CANIDT1
-#define IDT24_REG CANIDT1
-#define IDT25_REG CANIDT1
-#define IDT26_REG CANIDT1
-#define IDT27_REG CANIDT1
-#define IDT28_REG CANIDT1
-
-/* GTCCR */
-#define PSR10_REG GTCCR
-#define ICPSEL1_REG GTCCR
-#define TSM_REG GTCCR
-#define PSRSYNC_REG GTCCR
-
-/* CANCDMOB */
-#define DLC0_REG CANCDMOB
-#define DLC1_REG CANCDMOB
-#define DLC2_REG CANCDMOB
-#define DLC3_REG CANCDMOB
-#define IDE_REG CANCDMOB
-#define RPLV_REG CANCDMOB
-#define CONMOB0_REG CANCDMOB
-#define CONMOB1_REG CANCDMOB
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* CANHPMOB */
-#define CGP0_REG CANHPMOB
-#define CGP1_REG CANHPMOB
-#define CGP2_REG CANHPMOB
-#define CGP3_REG CANHPMOB
-#define HPMOB0_REG CANHPMOB
-#define HPMOB1_REG CANHPMOB
-#define HPMOB2_REG CANHPMOB
-#define HPMOB3_REG CANHPMOB
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* LINENIR */
-#define LENRXOK_REG LINENIR
-#define LENTXOK_REG LINENIR
-#define LENIDOK_REG LINENIR
-#define LENERR_REG LINENIR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* DACON */
-#define DAEN_REG DACON
-#define DALA_REG DACON
-#define DATS0_REG DACON
-#define DATS1_REG DACON
-#define DATS2_REG DACON
-#define DAATE_REG DACON
-
-/* PCIFR */
-#define PCIF0_REG PCIFR
-#define PCIF1_REG PCIFR
-#define PCIF2_REG PCIFR
-#define PCIF3_REG PCIFR
-
-/* AMP2CSR */
-#define AMP2TS0_REG AMP2CSR
-#define AMP2TS1_REG AMP2CSR
-#define AMP2TS2_REG AMP2CSR
-#define AMPCMP2_REG AMP2CSR
-#define AMP2G0_REG AMP2CSR
-#define AMP2G1_REG AMP2CSR
-#define AMP2IS_REG AMP2CSR
-#define AMP2EN_REG AMP2CSR
-
-/* LINDAT */
-#define LDATA0_REG LINDAT
-#define LDATA1_REG LINDAT
-#define LDATA2_REG LINDAT
-#define LDATA3_REG LINDAT
-#define LDATA4_REG LINDAT
-#define LDATA5_REG LINDAT
-#define LDATA6_REG LINDAT
-#define LDATA7_REG LINDAT
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-
-/* CANPAGE */
-#define INDX0_REG CANPAGE
-#define INDX1_REG CANPAGE
-#define INDX2_REG CANPAGE
-#define AINC_REG CANPAGE
-#define MOBNB0_REG CANPAGE
-#define MOBNB1_REG CANPAGE
-#define MOBNB2_REG CANPAGE
-#define MOBNB3_REG CANPAGE
-
-/* LINDLR */
-#define LRXDL0_REG LINDLR
-#define LRXDL1_REG LINDLR
-#define LRXDL2_REG LINDLR
-#define LRXDL3_REG LINDLR
-#define LTXDL0_REG LINDLR
-#define LTXDL1_REG LINDLR
-#define LTXDL2_REG LINDLR
-#define LTXDL3_REG LINDLR
-
-/* MCUCR */
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-#define SPIPS_REG MCUCR
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-#define INTF2_REG EIFR
-#define INTF3_REG EIFR
-
-/* CANSTMOB */
-#define AERR_REG CANSTMOB
-#define FERR_REG CANSTMOB
-#define CERR_REG CANSTMOB
-#define SERR_REG CANSTMOB
-#define BERR_REG CANSTMOB
-#define RXOK_REG CANSTMOB
-#define TXOK_REG CANSTMOB
-#define DLCW_REG CANSTMOB
-
-/* DACH */
-#define DACH0_REG DACH
-#define DACH1_REG DACH
-#define DACH2_REG DACH
-#define DACH3_REG DACH
-#define DACH4_REG DACH
-#define DACH5_REG DACH
-#define DACH6_REG DACH
-#define DACH7_REG DACH
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* CANEN2 */
-#define ENMOB0_REG CANEN2
-#define ENMOB1_REG CANEN2
-#define ENMOB2_REG CANEN2
-#define ENMOB3_REG CANEN2
-#define ENMOB4_REG CANEN2
-#define ENMOB5_REG CANEN2
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ADTS3_REG ADCSRB
-#define AREFEN_REG ADCSRB
-#define ISRCEN_REG ADCSRB
-#define ADHSM_REG ADCSRB
-
-/* OCR0A */
-/* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */
-
-/* OCR0B */
-/* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define SIGRD_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* CANBT2 */
-#define PRS0_REG CANBT2
-#define PRS1_REG CANBT2
-#define PRS2_REG CANBT2
-#define SJW0_REG CANBT2
-#define SJW1_REG CANBT2
-
-/* CANBT3 */
-#define SMP_REG CANBT3
-#define PHS10_REG CANBT3
-#define PHS11_REG CANBT3
-#define PHS12_REG CANBT3
-#define PHS20_REG CANBT3
-#define PHS21_REG CANBT3
-#define PHS22_REG CANBT3
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* CANBT1 */
-#define BRP0_REG CANBT1
-#define BRP1_REG CANBT1
-#define BRP2_REG CANBT1
-#define BRP3_REG CANBT1
-#define BRP4_REG CANBT1
-#define BRP5_REG CANBT1
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* DACL */
-#define DACL0_REG DACL
-#define DACL1_REG DACL
-#define DACL2_REG DACL
-#define DACL3_REG DACL
-#define DACL4_REG DACL
-#define DACL5_REG DACL
-#define DACL6_REG DACL
-#define DACL7_REG DACL
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* AMP0CSR */
-#define AMP0TS0_REG AMP0CSR
-#define AMP0TS1_REG AMP0CSR
-#define AMP0TS2_REG AMP0CSR
-#define AMPCMP0_REG AMP0CSR
-#define AMP0G0_REG AMP0CSR
-#define AMP0G1_REG AMP0CSR
-#define AMP0IS_REG AMP0CSR
-#define AMP0EN_REG AMP0CSR
-
-/* PLLCSR */
-#define PLOCK_REG PLLCSR
-#define PLLE_REG PLLCSR
-#define PLLF_REG PLLCSR
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-#define PCINT15_REG PCMSK1
-
-/* PCMSK2 */
-#define PCINT16_REG PCMSK2
-#define PCINT17_REG PCMSK2
-#define PCINT18_REG PCMSK2
-#define PCINT19_REG PCMSK2
-#define PCINT20_REG PCMSK2
-#define PCINT21_REG PCMSK2
-#define PCINT22_REG PCMSK2
-#define PCINT23_REG PCMSK2
-
-/* PCMSK3 */
-#define PCINT24_REG PCMSK3
-#define PCINT25_REG PCMSK3
-#define PCINT26_REG PCMSK3
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* AC0CON */
-#define AC0M0_REG AC0CON
-#define AC0M1_REG AC0CON
-#define AC0M2_REG AC0CON
-#define ACCKSEL_REG AC0CON
-#define AC0IS0_REG AC0CON
-#define AC0IS1_REG AC0CON
-#define AC0IE_REG AC0CON
-#define AC0EN_REG AC0CON
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* pins mapping */
-#define MISO_PORT PORTB
-#define MISO_BIT 0
-#define PCINT0_PORT PORTB
-#define PCINT0_BIT 0
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 1
-#define PCINT1_PORT PORTB
-#define PCINT1_BIT 1
-
-#define ADC5_PORT PORTB
-#define ADC5_BIT 2
-#define INT1_PORT PORTB
-#define INT1_BIT 2
-#define ACMPN0_PORT PORTB
-#define ACMPN0_BIT 2
-#define PCINT2_PORT PORTB
-#define PCINT2_BIT 2
-
-#define AMP0-_PORT PORTB
-#define AMP0-_BIT 3
-#define PCINT3_PORT PORTB
-#define PCINT3_BIT 3
-
-#define AMP0+_PORT PORTB
-#define AMP0+_BIT 4
-#define PCINT4_PORT PORTB
-#define PCINT4_BIT 4
-
-#define ADC6_PORT PORTB
-#define ADC6_BIT 5
-#define INT2_PORT PORTB
-#define INT2_BIT 5
-#define ACMPN1_PORT PORTB
-#define ACMPN1_BIT 5
-#define AMP2-_PORT PORTB
-#define AMP2-_BIT 5
-#define PCINT5_PORT PORTB
-#define PCINT5_BIT 5
-
-#define ADC7_PORT PORTB
-#define ADC7_BIT 6
-#define PCINT6_PORT PORTB
-#define PCINT6_BIT 6
-
-#define ADC4_PORT PORTB
-#define ADC4_BIT 7
-#define SCK_PORT PORTB
-#define SCK_BIT 7
-#define PCINT7_PORT PORTB
-#define PCINT7_BIT 7
-
-#define INT3_PORT PORTC
-#define INT3_BIT 0
-#define PCINT8_PORT PORTC
-#define PCINT8_BIT 0
-
-#define OC1B_PORT PORTC
-#define OC1B_BIT 1
-#define SS_A_PORT PORTC
-#define SS_A_BIT 1
-#define PCINT9_PORT PORTC
-#define PCINT9_BIT 1
-
-#define T0_PORT PORTC
-#define T0_BIT 2
-#define TXCAN_PORT PORTC
-#define TXCAN_BIT 2
-#define PCINT10_PORT PORTC
-#define PCINT10_BIT 2
-
-#define T1_PORT PORTC
-#define T1_BIT 3
-#define RXCAN_PORT PORTC
-#define RXCAN_BIT 3
-#define ICP1B_PORT PORTC
-#define ICP1B_BIT 3
-#define PCINT11_PORT PORTC
-#define PCINT11_BIT 3
-
-#define ADC8_PORT PORTC
-#define ADC8_BIT 4
-#define AMP1-_PORT PORTC
-#define AMP1-_BIT 4
-#define ACMPN3_PORT PORTC
-#define ACMPN3_BIT 4
-#define PCINT12_PORT PORTC
-#define PCINT12_BIT 4
-
-#define ADC9_PORT PORTC
-#define ADC9_BIT 5
-#define AMP1+_PORT PORTC
-#define AMP1+_BIT 5
-#define ACMP3_PORT PORTC
-#define ACMP3_BIT 5
-#define PCINT13_PORT PORTC
-#define PCINT13_BIT 5
-
-#define ADC10_PORT PORTC
-#define ADC10_BIT 6
-#define ACMP1_PORT PORTC
-#define ACMP1_BIT 6
-#define PCINT14_PORT PORTC
-#define PCINT14_BIT 6
-
-#define D2A_PORT PORTC
-#define D2A_BIT 7
-#define AMP2+_PORT PORTC
-#define AMP2+_BIT 7
-#define PCINT15_PORT PORTC
-#define PCINT15_BIT 7
-
-#define PCINT16_PORT PORTD
-#define PCINT16_BIT 0
-
-#define CLK0_PORT PORTD
-#define CLK0_BIT 1
-#define PCINT17_PORT PORTD
-#define PCINT17_BIT 1
-
-#define OC1A_PORT PORTD
-#define OC1A_BIT 2
-#define MISO_A_PORT PORTD
-#define MISO_A_BIT 2
-#define PCINT18_PORT PORTD
-#define PCINT18_BIT 2
-
-#define TXD_PORT PORTD
-#define TXD_BIT 3
-#define TXLIN_PORT PORTD
-#define TXLIN_BIT 3
-#define OC0A_PORT PORTD
-#define OC0A_BIT 3
-#define SS_PORT PORTD
-#define SS_BIT 3
-#define MOSI_A_PORT PORTD
-#define MOSI_A_BIT 3
-#define PCINT19_PORT PORTD
-#define PCINT19_BIT 3
-
-#define ADC1_PORT PORTD
-#define ADC1_BIT 4
-#define RXD_PORT PORTD
-#define RXD_BIT 4
-#define RXLIN_PORT PORTD
-#define RXLIN_BIT 4
-#define ICP1A_PORT PORTD
-#define ICP1A_BIT 4
-#define SCK_A_PORT PORTD
-#define SCK_A_BIT 4
-#define PCINT20_PORT PORTD
-#define PCINT20_BIT 4
-
-#define ADC2_PORT PORTD
-#define ADC2_BIT 5
-#define ACMP2_PORT PORTD
-#define ACMP2_BIT 5
-#define PCINT21_PORT PORTD
-#define PCINT21_BIT 5
-
-#define ADC3_PORT PORTD
-#define ADC3_BIT 6
-#define ACMPN2_PORT PORTD
-#define ACMPN2_BIT 6
-#define INT0_PORT PORTD
-#define INT0_BIT 6
-#define PCINT22_PORT PORTD
-#define PCINT22_BIT 6
-
-#define ACMP0_PORT PORTD
-#define ACMP0_BIT 7
-#define PCINT23_PORT PORTD
-#define PCINT23_BIT 7
-
-#define RESET_PORT PORTE
-#define RESET_BIT 0
-#define OCD_PORT PORTE
-#define OCD_BIT 0
-#define PCINT24_PORT PORTE
-#define PCINT24_BIT 0
-
-#define OC0B_PORT PORTE
-#define OC0B_BIT 1
-#define XTAL1_PORT PORTE
-#define XTAL1_BIT 1
-#define PCINT25_PORT PORTE
-#define PCINT25_BIT 1
-
-#define ADC0_PORT PORTE
-#define ADC0_BIT 2
-#define XTAL2_PORT PORTE
-#define XTAL2_BIT 2
-#define PCINT26_PORT PORTE
-#define PCINT26_BIT 2
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW_TOTAL_NUM 2
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 0
-
-
-/* CADAC2 */
-#define CADAC16_REG CADAC2
-#define CADAC17_REG CADAC2
-#define CADAC18_REG CADAC2
-#define CADAC19_REG CADAC2
-#define CADAC20_REG CADAC2
-#define CADAC21_REG CADAC2
-#define CADAC22_REG CADAC2
-#define CADAC23_REG CADAC2
-
-/* CADAC3 */
-#define CADAC24_REG CADAC3
-#define CADAC25_REG CADAC3
-#define CADAC26_REG CADAC3
-#define CADAC27_REG CADAC3
-#define CADAC28_REG CADAC3
-#define CADAC29_REG CADAC3
-#define CADAC30_REG CADAC3
-#define CADAC31_REG CADAC3
-
-/* CADAC0 */
-#define CADAC00_REG CADAC0
-#define CADAC01_REG CADAC0
-#define CADAC02_REG CADAC0
-#define CADAC03_REG CADAC0
-#define CADAC04_REG CADAC0
-#define CADAC05_REG CADAC0
-#define CADAC06_REG CADAC0
-#define CADAC07_REG CADAC0
-
-/* CADAC1 */
-#define CADAC08_REG CADAC1
-#define CADAC09_REG CADAC1
-#define CADAC10_REG CADAC1
-#define CADAC11_REG CADAC1
-#define CADAC12_REG CADAC1
-#define CADAC13_REG CADAC1
-#define CADAC14_REG CADAC1
-#define CADAC15_REG CADAC1
-
-/* BPIMSK */
-#define CHCIE_REG BPIMSK
-#define DHCIE_REG BPIMSK
-#define COCIE_REG BPIMSK
-#define DOCIE_REG BPIMSK
-#define SCIE_REG BPIMSK
-
-/* TCNT0H */
-#define TCNT0H0_REG TCNT0H
-#define TCNT0H1_REG TCNT0H
-#define TCNT0H2_REG TCNT0H
-#define TCNT0H3_REG TCNT0H
-#define TCNT0H4_REG TCNT0H
-#define TCNT0H5_REG TCNT0H
-#define TCNT0H6_REG TCNT0H
-#define TCNT0H7_REG TCNT0H
-
-/* TCNT0L */
-#define TCNT0L0_REG TCNT0L
-#define TCNT0L1_REG TCNT0L
-#define TCNT0L2_REG TCNT0L
-#define TCNT0L3_REG TCNT0L
-#define TCNT0L4_REG TCNT0L
-#define TCNT0L5_REG TCNT0L
-#define TCNT0L6_REG TCNT0L
-#define TCNT0L7_REG TCNT0L
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* BPCOCD */
-#define COCDL0_REG BPCOCD
-#define COCDL1_REG BPCOCD
-#define COCDL2_REG BPCOCD
-#define COCDL3_REG BPCOCD
-#define COCDL4_REG BPCOCD
-#define COCDL5_REG BPCOCD
-#define COCDL6_REG BPCOCD
-#define COCDL7_REG BPCOCD
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-
-/* BPSCD */
-#define SCDL0_REG BPSCD
-#define SCDL1_REG BPSCD
-#define SCDL2_REG BPSCD
-#define SCDL3_REG BPSCD
-#define SCDL4_REG BPSCD
-#define SCDL5_REG BPSCD
-#define SCDL6_REG BPSCD
-#define SCDL7_REG BPSCD
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* VADCH */
-#define VADC8_REG VADCH
-#define VADC9_REG VADCH
-#define VADC10_REG VADCH
-#define VADC11_REG VADCH
-
-/* VADCL */
-#define VADC0_REG VADCL
-#define VADC1_REG VADCL
-#define VADC2_REG VADCL
-#define VADC3_REG VADCL
-#define VADC4_REG VADCL
-#define VADC5_REG VADCL
-#define VADC6_REG VADCL
-#define VADC7_REG VADCL
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-#define ISC20_REG EICRA
-#define ISC21_REG EICRA
-#define ISC30_REG EICRA
-#define ISC31_REG EICRA
-
-/* FOSCCAL */
-#define FCAL0_REG FOSCCAL
-#define FCAL1_REG FOSCCAL
-#define FCAL2_REG FOSCCAL
-#define FCAL3_REG FOSCCAL
-#define FCAL4_REG FOSCCAL
-#define FCAL5_REG FOSCCAL
-#define FCAL6_REG FOSCCAL
-#define FCAL7_REG FOSCCAL
-
-/* DIDR0 */
-#define PA0DID_REG DIDR0
-#define PA1DID_REG DIDR0
-
-/* OCR1A */
-#define OCR1A0_REG OCR1A
-#define OCR1A1_REG OCR1A
-#define OCR1A2_REG OCR1A
-#define OCR1A3_REG OCR1A
-#define OCR1A4_REG OCR1A
-#define OCR1A5_REG OCR1A
-#define OCR1A6_REG OCR1A
-#define OCR1A7_REG OCR1A
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* OCR1B */
-#define OCR1B0_REG OCR1B
-#define OCR1B1_REG OCR1B
-#define OCR1B2_REG OCR1B
-#define OCR1B3_REG OCR1B
-#define OCR1B4_REG OCR1B
-#define OCR1B5_REG OCR1B
-#define OCR1B6_REG OCR1B
-#define OCR1B7_REG OCR1B
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* BPCR */
-#define CHCD_REG BPCR
-#define DHCD_REG BPCR
-#define COCD_REG BPCR
-#define DOCD_REG BPCR
-#define SCD_REG BPCR
-#define EPID_REG BPCR
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define ICS1_REG TCCR1A
-#define ICES1_REG TCCR1A
-#define ICNC1_REG TCCR1A
-#define ICEN1_REG TCCR1A
-#define TCW1_REG TCCR1A
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-
-/* BPCHCD */
-#define CHCDL0_REG BPCHCD
-#define CHCDL1_REG BPCHCD
-#define CHCDL2_REG BPCHCD
-#define CHCDL3_REG BPCHCD
-#define CHCDL4_REG BPCHCD
-#define CHCDL5_REG BPCHCD
-#define CHCDL6_REG BPCHCD
-#define CHCDL7_REG BPCHCD
-
-/* CADCSRC */
-#define CADVSE_REG CADCSRC
-
-/* CADCSRB */
-#define CADICIF_REG CADCSRB
-#define CADRCIF_REG CADCSRB
-#define CADACIF_REG CADCSRB
-#define CADICIE_REG CADCSRB
-#define CADRCIE_REG CADCSRB
-#define CADACIE_REG CADCSRB
-
-/* CADCSRA */
-#define CADSE_REG CADCSRA
-#define CADSI0_REG CADCSRA
-#define CADSI1_REG CADCSRA
-#define CADAS0_REG CADCSRA
-#define CADAS1_REG CADCSRA
-#define CADUB_REG CADCSRA
-#define CADPOL_REG CADCSRA
-#define CADEN_REG CADCSRA
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* BPPLR */
-#define BPPL_REG BPPLR
-#define BPPLE_REG BPPLR
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* CADRDC */
-#define CADRDC0_REG CADRDC
-#define CADRDC1_REG CADRDC
-#define CADRDC2_REG CADRDC
-#define CADRDC3_REG CADRDC
-#define CADRDC4_REG CADRDC
-#define CADRDC5_REG CADRDC
-#define CADRDC6_REG CADRDC
-#define CADRDC7_REG CADRDC
-
-/* PCICR */
-#define PCIE0_REG PCICR
-#define PCIE1_REG PCICR
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define ICS0_REG TCCR0A
-#define ICES0_REG TCCR0A
-#define ICNC0_REG TCCR0A
-#define ICEN0_REG TCCR0A
-#define TCW0_REG TCCR0A
-
-/* BPDHCD */
-#define DHCDL0_REG BPDHCD
-#define DHCDL1_REG BPDHCD
-#define DHCDL2_REG BPDHCD
-#define DHCDL3_REG BPDHCD
-#define DHCDL4_REG BPDHCD
-#define DHCDL5_REG BPDHCD
-#define DHCDL6_REG BPDHCD
-#define DHCDL7_REG BPDHCD
-
-/* TWBCSR */
-#define TWBCIP_REG TWBCSR
-#define TWBDT0_REG TWBCSR
-#define TWBDT1_REG TWBCSR
-#define TWBCIE_REG TWBCSR
-#define TWBCIF_REG TWBCSR
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* GTCCR */
-#define PSRSYNC_REG GTCCR
-#define TSM_REG GTCCR
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* BGCRR */
-#define BGCR0_REG BGCRR
-#define BGCR1_REG BGCRR
-#define BGCR2_REG BGCRR
-#define BGCR3_REG BGCRR
-#define BGCR4_REG BGCRR
-#define BGCR5_REG BGCRR
-#define BGCR6_REG BGCRR
-#define BGCR7_REG BGCRR
-
-/* PCIFR */
-#define PCIF0_REG PCIFR
-#define PCIF1_REG PCIFR
-
-/* FCSR */
-#define CFE_REG FCSR
-#define DFE_REG FCSR
-#define CPS_REG FCSR
-#define DUVRD_REG FCSR
-
-/* VADMUX */
-#define VADMUX0_REG VADMUX
-#define VADMUX1_REG VADMUX
-#define VADMUX2_REG VADMUX
-#define VADMUX3_REG VADMUX
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BODRF_REG MCUSR
-#define WDRF_REG MCUSR
-#define OCDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-
-/* BPIFR */
-#define CHCIF_REG BPIFR
-#define DHCIF_REG BPIFR
-#define COCIF_REG BPIFR
-#define DOCIF_REG BPIFR
-#define SCIF_REG BPIFR
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* VADCSR */
-#define VADCCIE_REG VADCSR
-#define VADCCIF_REG VADCSR
-#define VADSC_REG VADCSR
-#define VADEN_REG VADCSR
-
-/* MCUCR */
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-#define CKOE_REG MCUCR
-
-/* CBCR */
-#define CBE1_REG CBCR
-#define CBE2_REG CBCR
-#define CBE3_REG CBCR
-#define CBE4_REG CBCR
-
-/* CADRCC */
-#define CADRCC0_REG CADRCC
-#define CADRCC1_REG CADRCC
-#define CADRCC2_REG CADRCC
-#define CADRCC3_REG CADRCC
-#define CADRCC4_REG CADRCC
-#define CADRCC5_REG CADRCC
-#define CADRCC6_REG CADRCC
-#define CADRCC7_REG CADRCC
-
-/* BPOCTR */
-#define OCPT0_REG BPOCTR
-#define OCPT1_REG BPOCTR
-#define OCPT2_REG BPOCTR
-#define OCPT3_REG BPOCTR
-#define OCPT4_REG BPOCTR
-#define OCPT5_REG BPOCTR
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-
-/* BPDOCD */
-#define DOCDL0_REG BPDOCD
-#define DOCDL1_REG BPDOCD
-#define DOCDL2_REG BPDOCD
-#define DOCDL3_REG BPDOCD
-#define DOCDL4_REG BPDOCD
-#define DOCDL5_REG BPDOCD
-#define DOCDL6_REG BPDOCD
-#define DOCDL7_REG BPDOCD
-
-/* BPSCTR */
-#define SCPT0_REG BPSCTR
-#define SCPT1_REG BPSCTR
-#define SCPT2_REG BPSCTR
-#define SCPT3_REG BPSCTR
-#define SCPT4_REG BPSCTR
-#define SCPT5_REG BPSCTR
-#define SCPT6_REG BPSCTR
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* BPHCTR */
-#define HCPT0_REG BPHCTR
-#define HCPT1_REG BPHCTR
-#define HCPT2_REG BPHCTR
-#define HCPT3_REG BPHCTR
-#define HCPT4_REG BPHCTR
-#define HCPT5_REG BPHCTR
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-#define INT3_REG EIMSK
-
-/* PRR0 */
-#define PRVADC_REG PRR0
-#define PRTIM0_REG PRR0
-#define PRTIM1_REG PRR0
-#define PRSPI_REG PRR0
-#define PRVRM_REG PRR0
-#define PRTWI_REG PRR0
-
-/* OCR0A */
-#define OCR0A0_REG OCR0A
-#define OCR0A1_REG OCR0A
-#define OCR0A2_REG OCR0A
-#define OCR0A3_REG OCR0A
-#define OCR0A4_REG OCR0A
-#define OCR0A5_REG OCR0A
-#define OCR0A6_REG OCR0A
-#define OCR0A7_REG OCR0A
-
-/* ROCR */
-#define ROCWIE_REG ROCR
-#define ROCWIF_REG ROCR
-#define ROCD_REG ROCR
-#define ROCS_REG ROCR
-
-/* OCR0B */
-#define OCR0B0_REG OCR0B
-#define OCR0B1_REG OCR0B
-#define OCR0B2_REG OCR0B
-#define OCR0B3_REG OCR0B
-#define OCR0B4_REG OCR0B
-#define OCR0B5_REG OCR0B
-#define OCR0B6_REG OCR0B
-#define OCR0B7_REG OCR0B
-
-/* CADICH */
-#define CADICH0_REG CADICH
-#define CADICH1_REG CADICH
-#define CADICH2_REG CADICH
-#define CADICH3_REG CADICH
-#define CADICH4_REG CADICH
-#define CADICH5_REG CADICH
-#define CADICH6_REG CADICH
-#define CADICH7_REG CADICH
-
-/* CADICL */
-#define CADICL0_REG CADICL
-#define CADICL1_REG CADICL
-#define CADICL2_REG CADICL
-#define CADICL3_REG CADICL
-#define CADICL4_REG CADICL
-#define CADICL5_REG CADICL
-#define CADICL6_REG CADICL
-#define CADICL7_REG CADICL
-
-/* OSICSR */
-#define OSIEN_REG OSICSR
-#define OSIST_REG OSICSR
-#define OSISEL0_REG OSICSR
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define LBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define SIGRD_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* CHGDCSR */
-#define CHGDIE_REG CHGDCSR
-#define CHGDIF_REG CHGDCSR
-#define CHGDISC0_REG CHGDCSR
-#define CHGDISC1_REG CHGDCSR
-#define BATTPVL_REG CHGDCSR
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-#define ICIE0_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* BGCCR */
-#define BGCC0_REG BGCCR
-#define BGCC1_REG BGCCR
-#define BGCC2_REG BGCCR
-#define BGCC3_REG BGCCR
-#define BGCC4_REG BGCCR
-#define BGCC5_REG BGCCR
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT4_REG PCMSK1
-#define PCINT5_REG PCMSK1
-#define PCINT6_REG PCMSK1
-#define PCINT7_REG PCMSK1
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-#define INTF2_REG EIFR
-#define INTF3_REG EIFR
-
-/* BGCSR */
-#define BGSCDIE_REG BGCSR
-#define BGSCDIF_REG BGCSR
-#define BGSCDE_REG BGCSR
-#define BGD_REG BGCSR
-
-/* TWAMR */
-#define TWAM0_REG TWAMR
-#define TWAM1_REG TWAMR
-#define TWAM2_REG TWAMR
-#define TWAM3_REG TWAMR
-#define TWAM4_REG TWAMR
-#define TWAM5_REG TWAMR
-#define TWAM6_REG TWAMR
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-#define ICF0_REG TIFR0
-
-/* pins mapping */
-
-
-
-
-
-
-
-
-
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW_TOTAL_NUM 2
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* LINBTR */
-#define LBT0_REG LINBTR
-#define LBT1_REG LINBTR
-#define LBT2_REG LINBTR
-#define LBT3_REG LINBTR
-#define LBT4_REG LINBTR
-#define LBT5_REG LINBTR
-#define LDISR_REG LINBTR
-
-/* POCR1RAL */
-#define POCR1RA_0_REG POCR1RAL
-#define POCR1RA_1_REG POCR1RAL
-#define POCR1RA_2_REG POCR1RAL
-#define POCR1RA_3_REG POCR1RAL
-#define POCR1RA_4_REG POCR1RAL
-#define POCR1RA_5_REG POCR1RAL
-#define POCR1RA_6_REG POCR1RAL
-#define POCR1RA_7_REG POCR1RAL
-
-/* LINIDR */
-#define LID0_REG LINIDR
-#define LID1_REG LINIDR
-#define LID2_REG LINIDR
-#define LID3_REG LINIDR
-#define LID4_REG LINIDR
-#define LID5_REG LINIDR
-#define LP0_REG LINIDR
-#define LP1_REG LINIDR
-
-/* POCR1RAH */
-#define POCR1RA_8_REG POCR1RAH
-#define POCR1RA_9_REG POCR1RAH
-#define POCR1RA_00_REG POCR1RAH
-#define POCR1RA_01_REG POCR1RAH
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* OCR0B */
-/* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */
-
-/* LINSEL */
-#define LINDX0_REG LINSEL
-#define LINDX1_REG LINSEL
-#define LINDX2_REG LINSEL
-#define LAINC_REG LINSEL
-
-/* LINCR */
-#define LCMD0_REG LINCR
-#define LCMD1_REG LINCR
-#define LCMD2_REG LINCR
-#define LENA_REG LINCR
-#define LCONF0_REG LINCR
-#define LCONF1_REG LINCR
-#define LIN13_REG LINCR
-#define LSWRES_REG LINCR
-
-/* PIM */
-#define PEOPE_REG PIM
-#define PEVE0_REG PIM
-#define PEVE1_REG PIM
-#define PEVE2_REG PIM
-
-/* POCR2SBL */
-#define POCR2SB_0_REG POCR2SBL
-#define POCR2SB_1_REG POCR2SBL
-#define POCR2SB_2_REG POCR2SBL
-#define POCR2SB_3_REG POCR2SBL
-#define POCR2SB_4_REG POCR2SBL
-#define POCR2SB_5_REG POCR2SBL
-#define POCR2SB_6_REG POCR2SBL
-#define POCR2SB_7_REG POCR2SBL
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* POCR2SBH */
-#define POCR2SB_8_REG POCR2SBH
-#define POCR2SB_9_REG POCR2SBH
-#define POCR2SB_00_REG POCR2SBH
-#define POCR2SB_01_REG POCR2SBH
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* AC1CON */
-#define AC1M0_REG AC1CON
-#define AC1M1_REG AC1CON
-#define AC1M2_REG AC1CON
-#define AC1ICE_REG AC1CON
-#define AC1IS0_REG AC1CON
-#define AC1IS1_REG AC1CON
-#define AC1IE_REG AC1CON
-#define AC1EN_REG AC1CON
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRLIN_REG PRR
-#define PRSPI_REG PRR
-#define PRTIM0_REG PRR
-#define PRTIM1_REG PRR
-#define PRPSC_REG PRR
-#define PRCAN_REG PRR
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* LINBRRL */
-#define LDIV0_REG LINBRRL
-#define LDIV1_REG LINBRRL
-#define LDIV2_REG LINBRRL
-#define LDIV3_REG LINBRRL
-#define LDIV4_REG LINBRRL
-#define LDIV5_REG LINBRRL
-#define LDIV6_REG LINBRRL
-#define LDIV7_REG LINBRRL
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-
-/* LINBRRH */
-#define LDIV8_REG LINBRRH
-#define LDIV9_REG LINBRRH
-#define LDIV10_REG LINBRRH
-#define LDIV11_REG LINBRRH
-
-/* CANGSTA */
-#define ERRP_REG CANGSTA
-#define BOFF_REG CANGSTA
-#define ENFG_REG CANGSTA
-#define RXBSY_REG CANGSTA
-#define TXBSY_REG CANGSTA
-#define OVFG_REG CANGSTA
-
-/* CANGCON */
-#define SWRES_REG CANGCON
-#define ENASTB_REG CANGCON
-#define TEST_REG CANGCON
-#define LISTEN_REG CANGCON
-#define SYNTTC_REG CANGCON
-#define TTC_REG CANGCON
-#define OVRQ_REG CANGCON
-#define ABRQ_REG CANGCON
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* AMP1CSR */
-#define AMP1TS0_REG AMP1CSR
-#define AMP1TS1_REG AMP1CSR
-#define AMP1TS2_REG AMP1CSR
-#define AMPCMP1_REG AMP1CSR
-#define AMP1G0_REG AMP1CSR
-#define AMP1G1_REG AMP1CSR
-#define AMP1IS_REG AMP1CSR
-#define AMP1EN_REG AMP1CSR
-
-/* AC2CON */
-#define AC2M0_REG AC2CON
-#define AC2M1_REG AC2CON
-#define AC2M2_REG AC2CON
-#define AC2IS0_REG AC2CON
-#define AC2IS1_REG AC2CON
-#define AC2IE_REG AC2CON
-#define AC2EN_REG AC2CON
-
-/* CANPAGE */
-#define INDX0_REG CANPAGE
-#define INDX1_REG CANPAGE
-#define INDX2_REG CANPAGE
-#define AINC_REG CANPAGE
-#define MOBNB0_REG CANPAGE
-#define MOBNB1_REG CANPAGE
-#define MOBNB2_REG CANPAGE
-#define MOBNB3_REG CANPAGE
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-#define INT3_REG EIMSK
-
-/* LINENIR */
-#define LENRXOK_REG LINENIR
-#define LENTXOK_REG LINENIR
-#define LENIDOK_REG LINENIR
-#define LENERR_REG LINENIR
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-#define ISC20_REG EICRA
-#define ISC21_REG EICRA
-#define ISC30_REG EICRA
-#define ISC31_REG EICRA
-
-/* POCR2RAL */
-#define POCR2RA_0_REG POCR2RAL
-#define POCR2RA_1_REG POCR2RAL
-#define POCR2RA_2_REG POCR2RAL
-#define POCR2RA_3_REG POCR2RAL
-#define POCR2RA_4_REG POCR2RAL
-#define POCR2RA_5_REG POCR2RAL
-#define POCR2RA_6_REG POCR2RAL
-#define POCR2RA_7_REG POCR2RAL
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define ADC8D_REG DIDR1
-#define ADC9D_REG DIDR1
-#define ADC10D_REG DIDR1
-#define AMP0ND_REG DIDR1
-#define AMP0PD_REG DIDR1
-#define ACMP0D_REG DIDR1
-#define AMP2PD_REG DIDR1
-
-/* POCR2RAH */
-#define POCR2RA_8_REG POCR2RAH
-#define POCR2RA_9_REG POCR2RAH
-#define POCR2RA_00_REG POCR2RAH
-#define POCR2RA_01_REG POCR2RAH
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* POCR1SAH */
-#define POCR1SA_8_REG POCR1SAH
-#define POCR1SA_9_REG POCR1SAH
-#define POCR1SA_00_REG POCR1SAH
-#define POCR1SA_01_REG POCR1SAH
-
-/* POCR1SAL */
-#define POCR1SA_0_REG POCR1SAL
-#define POCR1SA_1_REG POCR1SAL
-#define POCR1SA_2_REG POCR1SAL
-#define POCR1SA_3_REG POCR1SAL
-#define POCR1SA_4_REG POCR1SAL
-#define POCR1SA_5_REG POCR1SAL
-#define POCR1SA_6_REG POCR1SAL
-#define POCR1SA_7_REG POCR1SAL
-
-/* CANIDM1 */
-#define IDMSK21_REG CANIDM1
-#define IDMSK22_REG CANIDM1
-#define IDMSK23_REG CANIDM1
-#define IDMSK24_REG CANIDM1
-#define IDMSK25_REG CANIDM1
-#define IDMSK26_REG CANIDM1
-#define IDMSK27_REG CANIDM1
-#define IDMSK28_REG CANIDM1
-
-/* CANIDM3 */
-#define IDMSK5_REG CANIDM3
-#define IDMSK6_REG CANIDM3
-#define IDMSK7_REG CANIDM3
-#define IDMSK8_REG CANIDM3
-#define IDMSK9_REG CANIDM3
-#define IDMSK10_REG CANIDM3
-#define IDMSK11_REG CANIDM3
-#define IDMSK12_REG CANIDM3
-
-/* CANIDM2 */
-#define IDMSK13_REG CANIDM2
-#define IDMSK14_REG CANIDM2
-#define IDMSK15_REG CANIDM2
-#define IDMSK16_REG CANIDM2
-#define IDMSK17_REG CANIDM2
-#define IDMSK18_REG CANIDM2
-#define IDMSK19_REG CANIDM2
-#define IDMSK20_REG CANIDM2
-
-/* CANIDM4 */
-#define IDEMSK_REG CANIDM4
-#define RTRMSK_REG CANIDM4
-#define IDMSK0_REG CANIDM4
-#define IDMSK1_REG CANIDM4
-#define IDMSK2_REG CANIDM4
-#define IDMSK3_REG CANIDM4
-#define IDMSK4_REG CANIDM4
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* PMIC2 */
-#define PRFM20_REG PMIC2
-#define PRFM21_REG PMIC2
-#define PRFM22_REG PMIC2
-#define PAOC2_REG PMIC2
-#define PFLTE2_REG PMIC2
-#define PELEV2_REG PMIC2
-#define PISEL2_REG PMIC2
-#define POVEN2_REG PMIC2
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* PMIC1 */
-#define PRFM10_REG PMIC1
-#define PRFM11_REG PMIC1
-#define PRFM12_REG PMIC1
-#define PAOC1_REG PMIC1
-#define PFLTE1_REG PMIC1
-#define PELEV1_REG PMIC1
-#define PISEL1_REG PMIC1
-#define POVEN1_REG PMIC1
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* PCTL */
-#define PRUN_REG PCTL
-#define PCCYC_REG PCTL
-#define PCLKSEL_REG PCTL
-#define PPRE0_REG PCTL
-#define PPRE1_REG PCTL
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* CANGIT */
-#define AERG_REG CANGIT
-#define FERG_REG CANGIT
-#define CERG_REG CANGIT
-#define SERG_REG CANGIT
-#define BXOK_REG CANGIT
-#define OVRTIM_REG CANGIT
-#define BOFFIT_REG CANGIT
-#define CANIT_REG CANGIT
-
-/* AC3CON */
-#define AC3M0_REG AC3CON
-#define AC3M1_REG AC3CON
-#define AC3M2_REG AC3CON
-#define AC3IS0_REG AC3CON
-#define AC3IS1_REG AC3CON
-#define AC3IE_REG AC3CON
-#define AC3EN_REG AC3CON
-
-/* LINERR */
-#define LBERR_REG LINERR
-#define LCERR_REG LINERR
-#define LPERR_REG LINERR
-#define LSERR_REG LINERR
-#define LFERR_REG LINERR
-#define LOVERR_REG LINERR
-#define LTOERR_REG LINERR
-#define LABORT_REG LINERR
-
-/* PCICR */
-#define PCIE0_REG PCICR
-#define PCIE1_REG PCICR
-#define PCIE2_REG PCICR
-#define PCIE3_REG PCICR
-
-/* CANGIE */
-#define ENOVRT_REG CANGIE
-#define ENERG_REG CANGIE
-#define ENBX_REG CANGIE
-#define ENERR_REG CANGIE
-#define ENTX_REG CANGIE
-#define ENRX_REG CANGIE
-#define ENBOFF_REG CANGIE
-#define ENIT_REG CANGIE
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* CANIE2 */
-#define IEMOB0_REG CANIE2
-#define IEMOB1_REG CANIE2
-#define IEMOB2_REG CANIE2
-#define IEMOB3_REG CANIE2
-#define IEMOB4_REG CANIE2
-#define IEMOB5_REG CANIE2
-
-/* POCR0RAL */
-#define POCR0RA_0_REG POCR0RAL
-#define POCR0RA_1_REG POCR0RAL
-#define POCR0RA_2_REG POCR0RAL
-#define POCR0RA_3_REG POCR0RAL
-#define POCR0RA_4_REG POCR0RAL
-#define POCR0RA_5_REG POCR0RAL
-#define POCR0RA_6_REG POCR0RAL
-#define POCR0RA_7_REG POCR0RAL
-
-/* CANSIT2 */
-#define SIT0_REG CANSIT2
-#define SIT1_REG CANSIT2
-#define SIT2_REG CANSIT2
-#define SIT3_REG CANSIT2
-#define SIT4_REG CANSIT2
-#define SIT5_REG CANSIT2
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* POCR0RAH */
-#define POCR0RA_8_REG POCR0RAH
-#define POCR0RA_9_REG POCR0RAH
-#define POCR0RA_00_REG POCR0RAH
-#define POCR0RA_01_REG POCR0RAH
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* POCR2SAH */
-#define POCR2SA_8_REG POCR2SAH
-#define POCR2SA_9_REG POCR2SAH
-#define POCR2SA_00_REG POCR2SAH
-#define POCR2SA_01_REG POCR2SAH
-
-/* POCR2SAL */
-#define POCR2SA_0_REG POCR2SAL
-#define POCR2SA_1_REG POCR2SAL
-#define POCR2SA_2_REG POCR2SAL
-#define POCR2SA_3_REG POCR2SAL
-#define POCR2SA_4_REG POCR2SAL
-#define POCR2SA_5_REG POCR2SAL
-#define POCR2SA_6_REG POCR2SAL
-#define POCR2SA_7_REG POCR2SAL
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* CANIDT4 */
-#define RB0TAG_REG CANIDT4
-#define RB1TAG_REG CANIDT4
-#define RTRTAG_REG CANIDT4
-#define IDT0_REG CANIDT4
-#define IDT1_REG CANIDT4
-#define IDT2_REG CANIDT4
-#define IDT3_REG CANIDT4
-#define IDT4_REG CANIDT4
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* CANIDT2 */
-#define IDT13_REG CANIDT2
-#define IDT14_REG CANIDT2
-#define IDT15_REG CANIDT2
-#define IDT16_REG CANIDT2
-#define IDT17_REG CANIDT2
-#define IDT18_REG CANIDT2
-#define IDT19_REG CANIDT2
-#define IDT20_REG CANIDT2
-
-/* CANIDT3 */
-#define IDT5_REG CANIDT3
-#define IDT6_REG CANIDT3
-#define IDT7_REG CANIDT3
-#define IDT8_REG CANIDT3
-#define IDT9_REG CANIDT3
-#define IDT10_REG CANIDT3
-#define IDT11_REG CANIDT3
-#define IDT12_REG CANIDT3
-
-/* CANIDT1 */
-#define IDT21_REG CANIDT1
-#define IDT22_REG CANIDT1
-#define IDT23_REG CANIDT1
-#define IDT24_REG CANIDT1
-#define IDT25_REG CANIDT1
-#define IDT26_REG CANIDT1
-#define IDT27_REG CANIDT1
-#define IDT28_REG CANIDT1
-
-/* PSYNC */
-#define PSYNC00_REG PSYNC
-#define PSYNC01_REG PSYNC
-#define PSYNC10_REG PSYNC
-#define PSYNC11_REG PSYNC
-#define PSYNC20_REG PSYNC
-#define PSYNC21_REG PSYNC
-
-/* GTCCR */
-#define PSR10_REG GTCCR
-#define ICPSEL1_REG GTCCR
-#define TSM_REG GTCCR
-#define PSRSYNC_REG GTCCR
-
-/* CANCDMOB */
-#define DLC0_REG CANCDMOB
-#define DLC1_REG CANCDMOB
-#define DLC2_REG CANCDMOB
-#define DLC3_REG CANCDMOB
-#define IDE_REG CANCDMOB
-#define RPLV_REG CANCDMOB
-#define CONMOB0_REG CANCDMOB
-#define CONMOB1_REG CANCDMOB
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* CANHPMOB */
-#define CGP0_REG CANHPMOB
-#define CGP1_REG CANHPMOB
-#define CGP2_REG CANHPMOB
-#define CGP3_REG CANHPMOB
-#define HPMOB0_REG CANHPMOB
-#define HPMOB1_REG CANHPMOB
-#define HPMOB2_REG CANHPMOB
-#define HPMOB3_REG CANHPMOB
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* POCR1SBL */
-#define POCR1SB_0_REG POCR1SBL
-#define POCR1SB_1_REG POCR1SBL
-#define POCR1SB_2_REG POCR1SBL
-#define POCR1SB_3_REG POCR1SBL
-#define POCR1SB_4_REG POCR1SBL
-#define POCR1SB_5_REG POCR1SBL
-#define POCR1SB_6_REG POCR1SBL
-#define POCR1SB_7_REG POCR1SBL
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* PLLCSR */
-#define PLOCK_REG PLLCSR
-#define PLLE_REG PLLCSR
-#define PLLF_REG PLLCSR
-
-/* POCR1SBH */
-#define POCR1SB_8_REG POCR1SBH
-#define POCR1SB_9_REG POCR1SBH
-#define POCR1SB_00_REG POCR1SBH
-#define POCR1SB_01_REG POCR1SBH
-
-/* PCIFR */
-#define PCIF0_REG PCIFR
-#define PCIF1_REG PCIFR
-#define PCIF2_REG PCIFR
-#define PCIF3_REG PCIFR
-
-/* AMP2CSR */
-#define AMP2TS0_REG AMP2CSR
-#define AMP2TS1_REG AMP2CSR
-#define AMP2TS2_REG AMP2CSR
-#define AMPCMP2_REG AMP2CSR
-#define AMP2G0_REG AMP2CSR
-#define AMP2G1_REG AMP2CSR
-#define AMP2IS_REG AMP2CSR
-#define AMP2EN_REG AMP2CSR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* LINDAT */
-#define LDATA0_REG LINDAT
-#define LDATA1_REG LINDAT
-#define LDATA2_REG LINDAT
-#define LDATA3_REG LINDAT
-#define LDATA4_REG LINDAT
-#define LDATA5_REG LINDAT
-#define LDATA6_REG LINDAT
-#define LDATA7_REG LINDAT
-
-/* POCR0SAH */
-#define POCR0SA_8_REG POCR0SAH
-#define POCR0SA_9_REG POCR0SAH
-#define POCR0SA_00_REG POCR0SAH
-#define POCR0SA_01_REG POCR0SAH
-
-/* POCR_RBL */
-#define POCR_RB_0_REG POCR_RBL
-#define POCR_RB_1_REG POCR_RBL
-#define POCR_RB_2_REG POCR_RBL
-#define POCR_RB_3_REG POCR_RBL
-#define POCR_RB_4_REG POCR_RBL
-#define POCR_RB_5_REG POCR_RBL
-#define POCR_RB_6_REG POCR_RBL
-#define POCR_RB_7_REG POCR_RBL
-
-/* POCR0SAL */
-#define POCR0SA_0_REG POCR0SAL
-#define POCR0SA_1_REG POCR0SAL
-#define POCR0SA_2_REG POCR0SAL
-#define POCR0SA_3_REG POCR0SAL
-#define POCR0SA_4_REG POCR0SAL
-#define POCR0SA_5_REG POCR0SAL
-#define POCR0SA_6_REG POCR0SAL
-#define POCR0SA_7_REG POCR0SAL
-
-/* POCR_RBH */
-#define POCR_RB_8_REG POCR_RBH
-#define POCR_RB_9_REG POCR_RBH
-#define POCR_RB_00_REG POCR_RBH
-#define POCR_RB_01_REG POCR_RBH
-
-/* LINDLR */
-#define LRXDL0_REG LINDLR
-#define LRXDL1_REG LINDLR
-#define LRXDL2_REG LINDLR
-#define LRXDL3_REG LINDLR
-#define LTXDL0_REG LINDLR
-#define LTXDL1_REG LINDLR
-#define LTXDL2_REG LINDLR
-#define LTXDL3_REG LINDLR
-
-/* MCUCR */
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-#define SPIPS_REG MCUCR
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-#define INTF2_REG EIFR
-#define INTF3_REG EIFR
-
-/* CANSTMOB */
-#define AERR_REG CANSTMOB
-#define FERR_REG CANSTMOB
-#define CERR_REG CANSTMOB
-#define SERR_REG CANSTMOB
-#define BERR_REG CANSTMOB
-#define RXOK_REG CANSTMOB
-#define TXOK_REG CANSTMOB
-#define DLCW_REG CANSTMOB
-
-/* PIFR */
-#define PEOP_REG PIFR
-#define PEV0_REG PIFR
-#define PEV1_REG PIFR
-#define PEV2_REG PIFR
-
-/* LINSIR */
-#define LRXOK_REG LINSIR
-#define LTXOK_REG LINSIR
-#define LIDOK_REG LINSIR
-#define LERR_REG LINSIR
-#define LBUSY_REG LINSIR
-#define LIDST0_REG LINSIR
-#define LIDST1_REG LINSIR
-#define LIDST2_REG LINSIR
-
-/* DACH */
-#define DACH0_REG DACH
-#define DACH1_REG DACH
-#define DACH2_REG DACH
-#define DACH3_REG DACH
-#define DACH4_REG DACH
-#define DACH5_REG DACH
-#define DACH6_REG DACH
-#define DACH7_REG DACH
-
-/* DACL */
-#define DACL0_REG DACL
-#define DACL1_REG DACL
-#define DACL2_REG DACL
-#define DACL3_REG DACL
-#define DACL4_REG DACL
-#define DACL5_REG DACL
-#define DACL6_REG DACL
-#define DACL7_REG DACL
-
-/* CANEN2 */
-#define ENMOB0_REG CANEN2
-#define ENMOB1_REG CANEN2
-#define ENMOB2_REG CANEN2
-#define ENMOB3_REG CANEN2
-#define ENMOB4_REG CANEN2
-#define ENMOB5_REG CANEN2
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ADTS3_REG ADCSRB
-#define AREFEN_REG ADCSRB
-#define ISRCEN_REG ADCSRB
-#define ADHSM_REG ADCSRB
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* OCR0A */
-/* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */
-
-/* POCR0SBL */
-#define POCR0SB_0_REG POCR0SBL
-#define POCR0SB_1_REG POCR0SBL
-#define POCR0SB_2_REG POCR0SBL
-#define POCR0SB_3_REG POCR0SBL
-#define POCR0SB_4_REG POCR0SBL
-#define POCR0SB_5_REG POCR0SBL
-#define POCR0SB_6_REG POCR0SBL
-#define POCR0SB_7_REG POCR0SBL
-
-/* ACSR */
-#define AC0O_REG ACSR
-#define AC1O_REG ACSR
-#define AC2O_REG ACSR
-#define AC3O_REG ACSR
-#define AC0IF_REG ACSR
-#define AC1IF_REG ACSR
-#define AC2IF_REG ACSR
-#define AC3IF_REG ACSR
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PMIC0 */
-#define PRFM00_REG PMIC0
-#define PRFM01_REG PMIC0
-#define PRFM02_REG PMIC0
-#define PAOC0_REG PMIC0
-#define PFLTE0_REG PMIC0
-#define PELEV0_REG PMIC0
-#define PISEL0_REG PMIC0
-#define POVEN0_REG PMIC0
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* POC */
-#define POEN0A_REG POC
-#define POEN0B_REG POC
-#define POEN1A_REG POC
-#define POEN1B_REG POC
-#define POEN2A_REG POC
-#define POEN2B_REG POC
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define SIGRD_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* PCNF */
-#define POPA_REG PCNF
-#define POPB_REG PCNF
-#define PMODE_REG PCNF
-#define PULOCK_REG PCNF
-
-/* CANBT2 */
-#define PRS0_REG CANBT2
-#define PRS1_REG CANBT2
-#define PRS2_REG CANBT2
-#define SJW0_REG CANBT2
-#define SJW1_REG CANBT2
-
-/* CANBT3 */
-#define SMP_REG CANBT3
-#define PHS10_REG CANBT3
-#define PHS11_REG CANBT3
-#define PHS12_REG CANBT3
-#define PHS20_REG CANBT3
-#define PHS21_REG CANBT3
-#define PHS22_REG CANBT3
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* CANBT1 */
-#define BRP0_REG CANBT1
-#define BRP1_REG CANBT1
-#define BRP2_REG CANBT1
-#define BRP3_REG CANBT1
-#define BRP4_REG CANBT1
-#define BRP5_REG CANBT1
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* AMP0CSR */
-#define AMP0TS0_REG AMP0CSR
-#define AMP0TS1_REG AMP0CSR
-#define AMP0TS2_REG AMP0CSR
-#define AMPCMP0_REG AMP0CSR
-#define AMP0G0_REG AMP0CSR
-#define AMP0G1_REG AMP0CSR
-#define AMP0IS_REG AMP0CSR
-#define AMP0EN_REG AMP0CSR
-
-/* DACON */
-#define DAEN_REG DACON
-#define DALA_REG DACON
-#define DATS0_REG DACON
-#define DATS1_REG DACON
-#define DATS2_REG DACON
-#define DAATE_REG DACON
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-#define PCINT15_REG PCMSK1
-
-/* PCMSK2 */
-#define PCINT16_REG PCMSK2
-#define PCINT17_REG PCMSK2
-#define PCINT18_REG PCMSK2
-#define PCINT19_REG PCMSK2
-#define PCINT20_REG PCMSK2
-#define PCINT21_REG PCMSK2
-#define PCINT22_REG PCMSK2
-#define PCINT23_REG PCMSK2
-
-/* PCMSK3 */
-#define PCINT24_REG PCMSK3
-#define PCINT25_REG PCMSK3
-#define PCINT26_REG PCMSK3
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* AC0CON */
-#define AC0M0_REG AC0CON
-#define AC0M1_REG AC0CON
-#define AC0M2_REG AC0CON
-#define ACCKSEL_REG AC0CON
-#define AC0IS0_REG AC0CON
-#define AC0IS1_REG AC0CON
-#define AC0IE_REG AC0CON
-#define AC0EN_REG AC0CON
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* POCR0SBH */
-#define POCR0SB_8_REG POCR0SBH
-#define POCR0SB_9_REG POCR0SBH
-#define POCR0SB_00_REG POCR0SBH
-#define POCR0SB_01_REG POCR0SBH
-
-/* pins mapping */
-#define MISO_PORT PORTB
-#define MISO_BIT 0
-#define PSCOUT2A_PORT PORTB
-#define PSCOUT2A_BIT 0
-#define PCINT0_PORT PORTB
-#define PCINT0_BIT 0
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 1
-#define PSCOUT2B_PORT PORTB
-#define PSCOUT2B_BIT 1
-#define PCINT1_PORT PORTB
-#define PCINT1_BIT 1
-
-#define ADC5_PORT PORTB
-#define ADC5_BIT 2
-#define INT1_PORT PORTB
-#define INT1_BIT 2
-#define ACMPN0_PORT PORTB
-#define ACMPN0_BIT 2
-#define PCINT2_PORT PORTB
-#define PCINT2_BIT 2
-
-#define AMP0-_PORT PORTB
-#define AMP0-_BIT 3
-#define PCINT3_PORT PORTB
-#define PCINT3_BIT 3
-
-#define AMP0+_PORT PORTB
-#define AMP0+_BIT 4
-#define PCINT4_PORT PORTB
-#define PCINT4_BIT 4
-
-#define ADC6_PORT PORTB
-#define ADC6_BIT 5
-#define INT2_PORT PORTB
-#define INT2_BIT 5
-#define ACMPN1_PORT PORTB
-#define ACMPN1_BIT 5
-#define AMP2-_PORT PORTB
-#define AMP2-_BIT 5
-#define PCINT5_PORT PORTB
-#define PCINT5_BIT 5
-
-#define ADC7_PORT PORTB
-#define ADC7_BIT 6
-#define PSCOUT1B_PORT PORTB
-#define PSCOUT1B_BIT 6
-#define PCINT6_PORT PORTB
-#define PCINT6_BIT 6
-
-#define ADC4_PORT PORTB
-#define ADC4_BIT 7
-#define PSCOUT0B_PORT PORTB
-#define PSCOUT0B_BIT 7
-#define SCK_PORT PORTB
-#define SCK_BIT 7
-#define PCINT7_PORT PORTB
-#define PCINT7_BIT 7
-
-#define INT3_PORT PORTC
-#define INT3_BIT 0
-#define PSCOUT1A_PORT PORTC
-#define PSCOUT1A_BIT 0
-#define PCINT8_PORT PORTC
-#define PCINT8_BIT 0
-
-#define PSCIN1_PORT PORTC
-#define PSCIN1_BIT 1
-#define OC1B_PORT PORTC
-#define OC1B_BIT 1
-#define SS_A_PORT PORTC
-#define SS_A_BIT 1
-#define PCINT9_PORT PORTC
-#define PCINT9_BIT 1
-
-#define T0_PORT PORTC
-#define T0_BIT 2
-#define TXCAN_PORT PORTC
-#define TXCAN_BIT 2
-#define PCINT10_PORT PORTC
-#define PCINT10_BIT 2
-
-#define T1_PORT PORTC
-#define T1_BIT 3
-#define RXCAN_PORT PORTC
-#define RXCAN_BIT 3
-#define ICP1B_PORT PORTC
-#define ICP1B_BIT 3
-#define PCINT11_PORT PORTC
-#define PCINT11_BIT 3
-
-#define ADC8_PORT PORTC
-#define ADC8_BIT 4
-#define AMP1-_PORT PORTC
-#define AMP1-_BIT 4
-#define ACMPN3_PORT PORTC
-#define ACMPN3_BIT 4
-#define PCINT12_PORT PORTC
-#define PCINT12_BIT 4
-
-#define ADC9_PORT PORTC
-#define ADC9_BIT 5
-#define AMP1+_PORT PORTC
-#define AMP1+_BIT 5
-#define ACMP3_PORT PORTC
-#define ACMP3_BIT 5
-#define PCINT13_PORT PORTC
-#define PCINT13_BIT 5
-
-#define ADC10_PORT PORTC
-#define ADC10_BIT 6
-#define ACMP1_PORT PORTC
-#define ACMP1_BIT 6
-#define PCINT14_PORT PORTC
-#define PCINT14_BIT 6
-
-#define D2A_PORT PORTC
-#define D2A_BIT 7
-#define AMP2+_PORT PORTC
-#define AMP2+_BIT 7
-#define PCINT15_PORT PORTC
-#define PCINT15_BIT 7
-
-#define PSCOUT0A_PORT PORTD
-#define PSCOUT0A_BIT 0
-#define PCINT16_PORT PORTD
-#define PCINT16_BIT 0
-
-#define PSCIN0_PORT PORTD
-#define PSCIN0_BIT 1
-#define CLK0_PORT PORTD
-#define CLK0_BIT 1
-#define PCINT17_PORT PORTD
-#define PCINT17_BIT 1
-
-#define PSCIN2_PORT PORTD
-#define PSCIN2_BIT 2
-#define OC1A_PORT PORTD
-#define OC1A_BIT 2
-#define MISO_A_PORT PORTD
-#define MISO_A_BIT 2
-#define PCINT18_PORT PORTD
-#define PCINT18_BIT 2
-
-#define TXD_PORT PORTD
-#define TXD_BIT 3
-#define TXLIN_PORT PORTD
-#define TXLIN_BIT 3
-#define OC0A_PORT PORTD
-#define OC0A_BIT 3
-#define SS_PORT PORTD
-#define SS_BIT 3
-#define MOSI_A_PORT PORTD
-#define MOSI_A_BIT 3
-#define PCINT19_PORT PORTD
-#define PCINT19_BIT 3
-
-#define ADC1_PORT PORTD
-#define ADC1_BIT 4
-#define RXD_PORT PORTD
-#define RXD_BIT 4
-#define RXLIN_PORT PORTD
-#define RXLIN_BIT 4
-#define ICP1A_PORT PORTD
-#define ICP1A_BIT 4
-#define SCK_A_PORT PORTD
-#define SCK_A_BIT 4
-#define PCINT20_PORT PORTD
-#define PCINT20_BIT 4
-
-#define ADC2_PORT PORTD
-#define ADC2_BIT 5
-#define ACMP2_PORT PORTD
-#define ACMP2_BIT 5
-#define PCINT21_PORT PORTD
-#define PCINT21_BIT 5
-
-#define ADC3_PORT PORTD
-#define ADC3_BIT 6
-#define ACMPN2_PORT PORTD
-#define ACMPN2_BIT 6
-#define INT0_PORT PORTD
-#define INT0_BIT 6
-#define PCINT22_PORT PORTD
-#define PCINT22_BIT 6
-
-#define ACMP0_PORT PORTD
-#define ACMP0_BIT 7
-#define PCINT23_PORT PORTD
-#define PCINT23_BIT 7
-
-#define RESET_PORT PORTE
-#define RESET_BIT 0
-#define OCD_PORT PORTE
-#define OCD_BIT 0
-#define PCINT24_PORT PORTE
-#define PCINT24_BIT 0
-
-#define OC0B_PORT PORTE
-#define OC0B_BIT 1
-#define XTAL1_PORT PORTE
-#define XTAL1_BIT 1
-#define PCINT25_PORT PORTE
-#define PCINT25_BIT 1
-
-#define ADC0_PORT PORTE
-#define ADC0_BIT 2
-#define XTAL2_PORT PORTE
-#define XTAL2_BIT 2
-#define PCINT26_PORT PORTE
-#define PCINT26_BIT 2
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 3 */
-#define TIMER3_PRESCALER_DIV_0 0
-#define TIMER3_PRESCALER_DIV_1 1
-#define TIMER3_PRESCALER_DIV_8 2
-#define TIMER3_PRESCALER_DIV_64 3
-#define TIMER3_PRESCALER_DIV_256 4
-#define TIMER3_PRESCALER_DIV_1024 5
-#define TIMER3_PRESCALER_DIV_FALL 6
-#define TIMER3_PRESCALER_DIV_RISE 7
-
-#define TIMER3_PRESCALER_REG_0 0
-#define TIMER3_PRESCALER_REG_1 1
-#define TIMER3_PRESCALER_REG_2 8
-#define TIMER3_PRESCALER_REG_3 64
-#define TIMER3_PRESCALER_REG_4 256
-#define TIMER3_PRESCALER_REG_5 1024
-#define TIMER3_PRESCALER_REG_6 -1
-#define TIMER3_PRESCALER_REG_7 -2
-
-/* prescalers timer 4 */
-
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER1C_AVAILABLE
-#define TIMER3_AVAILABLE
-#define TIMER3A_AVAILABLE
-#define TIMER3B_AVAILABLE
-#define TIMER3C_AVAILABLE
-#define TIMER4_AVAILABLE
-#define TIMER4A_AVAILABLE
-#define TIMER4B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW3_NUM 2
-#define SIG_OVERFLOW4_NUM 3
-#define SIG_OVERFLOW_TOTAL_NUM 4
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE1C_NUM 4
-#define SIG_OUTPUT_COMPARE3A_NUM 5
-#define SIG_OUTPUT_COMPARE3B_NUM 6
-#define SIG_OUTPUT_COMPARE3C_NUM 7
-#define SIG_OUTPUT_COMPARE4_NUM 8
-#define SIG_OUTPUT_COMPARE4A_NUM 9
-#define SIG_OUTPUT_COMPARE4B_NUM 10
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 11
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM1C_NUM 4
-#define PWM3A_NUM 5
-#define PWM3B_NUM 6
-#define PWM3C_NUM 7
-#define PWM4_NUM 8
-#define PWM4A_NUM 9
-#define PWM4B_NUM 10
-#define PWM_TOTAL_NUM 11
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE3_NUM 1
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 2
-
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* UDIEN */
-#define SUSPE_REG UDIEN
-#define SOFE_REG UDIEN
-#define EORSTE_REG UDIEN
-#define WAKEUPE_REG UDIEN
-#define EORSME_REG UDIEN
-#define UPRSME_REG UDIEN
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* OCR0B */
-#define OCR0B_0_REG OCR0B
-#define OCR0B_1_REG OCR0B
-#define OCR0B_2_REG OCR0B
-#define OCR0B_3_REG OCR0B
-#define OCR0B_4_REG OCR0B
-#define OCR0B_5_REG OCR0B
-#define OCR0B_6_REG OCR0B
-#define OCR0B_7_REG OCR0B
-
-/* UDINT */
-#define SUSPI_REG UDINT
-#define SOFI_REG UDINT
-#define EORSTI_REG UDINT
-#define WAKEUPI_REG UDINT
-#define EORSMI_REG UDINT
-#define UPRSMI_REG UDINT
-
-/* UERST */
-#define EPRST0_REG UERST
-#define EPRST1_REG UERST
-#define EPRST2_REG UERST
-#define EPRST3_REG UERST
-#define EPRST4_REG UERST
-#define EPRST5_REG UERST
-#define EPRST6_REG UERST
-
-/* RAMPZ */
-#define RAMPZ0_REG RAMPZ
-
-/* UECFG1X */
-#define ALLOC_REG UECFG1X
-#define EPBK0_REG UECFG1X
-#define EPBK1_REG UECFG1X
-#define EPSIZE0_REG UECFG1X
-#define EPSIZE1_REG UECFG1X
-#define EPSIZE2_REG UECFG1X
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-#define EEAR10_REG EEARH
-#define EEAR11_REG EEARH
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* PORTE */
-#define PORTE2_REG PORTE
-#define PORTE6_REG PORTE
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-#define INT3_REG EIMSK
-#define INT4_REG EIMSK
-#define INT5_REG EIMSK
-#define INT6_REG EIMSK
-#define INT7_REG EIMSK
-
-/* UDR1 */
-#define UDR1_0_REG UDR1
-#define UDR1_1_REG UDR1
-#define UDR1_2_REG UDR1
-#define UDR1_3_REG UDR1
-#define UDR1_4_REG UDR1
-#define UDR1_5_REG UDR1
-#define UDR1_6_REG UDR1
-#define UDR1_7_REG UDR1
-
-/* EICRB */
-#define ISC40_REG EICRB
-#define ISC41_REG EICRB
-#define ISC50_REG EICRB
-#define ISC51_REG EICRB
-#define ISC60_REG EICRB
-#define ISC61_REG EICRB
-#define ISC70_REG EICRB
-#define ISC71_REG EICRB
-
-/* UEDATX */
-#define DAT0_REG UEDATX
-#define DAT1_REG UEDATX
-#define DAT2_REG UEDATX
-#define DAT3_REG UEDATX
-#define DAT4_REG UEDATX
-#define DAT5_REG UEDATX
-#define DAT6_REG UEDATX
-#define DAT7_REG UEDATX
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-#define ISC20_REG EICRA
-#define ISC21_REG EICRA
-#define ISC30_REG EICRA
-#define ISC31_REG EICRA
-
-/* UECFG0X */
-#define EPDIR_REG UECFG0X
-#define EPTYPE0_REG UECFG0X
-#define EPTYPE1_REG UECFG0X
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* DIDR2 */
-#define ADC8D_REG DIDR2
-#define ADC9D_REG DIDR2
-#define ADC10D_REG DIDR2
-#define ADC11D_REG DIDR2
-#define ADC12D_REG DIDR2
-#define ADC13D_REG DIDR2
-
-/* DDRF */
-#define DDF0_REG DDRF
-#define DDF1_REG DDRF
-#define DDF4_REG DDRF
-#define DDF5_REG DDRF
-#define DDF6_REG DDRF
-#define DDF7_REG DDRF
-
-/* CLKSEL1 */
-#define EXCKSEL0_REG CLKSEL1
-#define EXCKSEL1_REG CLKSEL1
-#define EXCKSEL2_REG CLKSEL1
-#define EXCKSEL3_REG CLKSEL1
-#define RCCKSEL0_REG CLKSEL1
-#define RCCKSEL1_REG CLKSEL1
-#define RCCKSEL2_REG CLKSEL1
-#define RCCKSEL3_REG CLKSEL1
-
-/* CLKSEL0 */
-#define CLKS_REG CLKSEL0
-#define EXTE_REG CLKSEL0
-#define RCE_REG CLKSEL0
-#define EXSUT0_REG CLKSEL0
-#define EXSUT1_REG CLKSEL0
-#define RCSUT0_REG CLKSEL0
-#define RCSUT1_REG CLKSEL0
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* UENUM */
-#define UENUM_0_REG UENUM
-#define UENUM_1_REG UENUM
-#define UENUM_2_REG UENUM
-
-/* UBRR1L */
-#define UBRR_0_REG UBRR1L
-#define UBRR_1_REG UBRR1L
-#define UBRR_2_REG UBRR1L
-#define UBRR_3_REG UBRR1L
-#define UBRR_4_REG UBRR1L
-#define UBRR_5_REG UBRR1L
-#define UBRR_6_REG UBRR1L
-#define UBRR_7_REG UBRR1L
-
-/* DDRC */
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* OCR3AL */
-#define OCR3AL0_REG OCR3AL
-#define OCR3AL1_REG OCR3AL
-#define OCR3AL2_REG OCR3AL
-#define OCR3AL3_REG OCR3AL
-#define OCR3AL4_REG OCR3AL
-#define OCR3AL5_REG OCR3AL
-#define OCR3AL6_REG OCR3AL
-#define OCR3AL7_REG OCR3AL
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1C0_REG TCCR1A
-#define COM1C1_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* OCR3AH */
-#define OCR3AH0_REG OCR3AH
-#define OCR3AH1_REG OCR3AH
-#define OCR3AH2_REG OCR3AH
-#define OCR3AH3_REG OCR3AH
-#define OCR3AH4_REG OCR3AH
-#define OCR3AH5_REG OCR3AH
-#define OCR3AH6_REG OCR3AH
-#define OCR3AH7_REG OCR3AH
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* OCR4A */
-#define OCR4A0_REG OCR4A
-#define OCR4A1_REG OCR4A
-#define OCR4A2_REG OCR4A
-#define OCR4A3_REG OCR4A
-#define OCR4A4_REG OCR4A
-#define OCR4A5_REG OCR4A
-#define OCR4A6_REG OCR4A
-#define OCR4A7_REG OCR4A
-
-/* OCR4C */
-#define OCR4C0_REG OCR4C
-#define OCR4C1_REG OCR4C
-#define OCR4C2_REG OCR4C
-#define OCR4C3_REG OCR4C
-#define OCR4C4_REG OCR4C
-#define OCR4C5_REG OCR4C
-#define OCR4C6_REG OCR4C
-#define OCR4C7_REG OCR4C
-
-/* OCR4B */
-#define OCR4B0_REG OCR4B
-#define OCR4B1_REG OCR4B
-#define OCR4B2_REG OCR4B
-#define OCR4B3_REG OCR4B
-#define OCR4B4_REG OCR4B
-#define OCR4B5_REG OCR4B
-#define OCR4B6_REG OCR4B
-#define OCR4B7_REG OCR4B
-
-/* OCR4D */
-#define OCR4D0_REG OCR4D
-#define OCR4D1_REG OCR4D
-#define OCR4D2_REG OCR4D
-#define OCR4D3_REG OCR4D
-#define OCR4D4_REG OCR4D
-#define OCR4D5_REG OCR4D
-#define OCR4D6_REG OCR4D
-#define OCR4D7_REG OCR4D
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* RCCTRL */
-#define RCFREQ_REG RCCTRL
-
-/* UDCON */
-#define DETACH_REG UDCON
-#define RMWKUP_REG UDCON
-#define LSM_REG UDCON
-#define RSTCPU_REG UDCON
-
-/* PCICR */
-#define PCIE0_REG PCICR
-
-/* USBINT */
-#define VBUSTI_REG USBINT
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TCNT4 */
-#define TC40_REG TCNT4
-#define TC41_REG TCNT4
-#define TC42_REG TCNT4
-#define TC43_REG TCNT4
-#define TC44_REG TCNT4
-#define TC45_REG TCNT4
-#define TC46_REG TCNT4
-#define TC47_REG TCNT4
-
-/* TC4H */
-#define TC48_REG TC4H
-#define TC49_REG TC4H
-#define TC410_REG TC4H
-
-/* UHWCON */
-#define UVREGE_REG UHWCON
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* UDMFN */
-#define FNCERR_REG UDMFN
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* TIFR4 */
-#define TOV4_REG TIFR4
-#define OCF4B_REG TIFR4
-#define OCF4A_REG TIFR4
-#define OCF4D_REG TIFR4
-
-/* TIFR3 */
-#define TOV3_REG TIFR3
-#define OCF3A_REG TIFR3
-#define OCF3B_REG TIFR3
-#define OCF3C_REG TIFR3
-#define ICF3_REG TIFR3
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define OCF1C_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* UEBCLX */
-#define BYCT0_REG UEBCLX
-#define BYCT1_REG UEBCLX
-#define BYCT2_REG UEBCLX
-#define BYCT3_REG UEBCLX
-#define BYCT4_REG UEBCLX
-#define BYCT5_REG UEBCLX
-#define BYCT6_REG UEBCLX
-#define BYCT7_REG UEBCLX
-
-/* OCR3CH */
-#define OCR3CH0_REG OCR3CH
-#define OCR3CH1_REG OCR3CH
-#define OCR3CH2_REG OCR3CH
-#define OCR3CH3_REG OCR3CH
-#define OCR3CH4_REG OCR3CH
-#define OCR3CH5_REG OCR3CH
-#define OCR3CH6_REG OCR3CH
-#define OCR3CH7_REG OCR3CH
-
-/* UESTA1X */
-#define CURRBK0_REG UESTA1X
-#define CURRBK1_REG UESTA1X
-#define CTRLDIR_REG UESTA1X
-
-/* OCR3CL */
-#define OCR3CL0_REG OCR3CL
-#define OCR3CL1_REG OCR3CL
-#define OCR3CL2_REG OCR3CL
-#define OCR3CL3_REG OCR3CL
-#define OCR3CL4_REG OCR3CL
-#define OCR3CL5_REG OCR3CL
-#define OCR3CL6_REG OCR3CL
-#define OCR3CL7_REG OCR3CL
-
-/* GTCCR */
-#define PSRSYNC_REG GTCCR
-#define TSM_REG GTCCR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* TCCR3C */
-#define FOC3C_REG TCCR3C
-#define FOC3B_REG TCCR3C
-#define FOC3A_REG TCCR3C
-
-/* TCCR3B */
-#define CS30_REG TCCR3B
-#define CS31_REG TCCR3B
-#define CS32_REG TCCR3B
-#define WGM32_REG TCCR3B
-#define WGM33_REG TCCR3B
-#define ICES3_REG TCCR3B
-#define ICNC3_REG TCCR3B
-
-/* TCCR3A */
-#define WGM30_REG TCCR3A
-#define WGM31_REG TCCR3A
-#define COM3C0_REG TCCR3A
-#define COM3C1_REG TCCR3A
-#define COM3B0_REG TCCR3A
-#define COM3B1_REG TCCR3A
-#define COM3A0_REG TCCR3A
-#define COM3A1_REG TCCR3A
-
-/* UEINTX */
-#define TXINI_REG UEINTX
-#define STALLEDI_REG UEINTX
-#define RXOUTI_REG UEINTX
-#define RXSTPI_REG UEINTX
-#define NAKOUTI_REG UEINTX
-#define RWAL_REG UEINTX
-#define NAKINI_REG UEINTX
-#define FIFOCON_REG UEINTX
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* TCNT3H */
-#define TCNT3H0_REG TCNT3H
-#define TCNT3H1_REG TCNT3H
-#define TCNT3H2_REG TCNT3H
-#define TCNT3H3_REG TCNT3H
-#define TCNT3H4_REG TCNT3H
-#define TCNT3H5_REG TCNT3H
-#define TCNT3H6_REG TCNT3H
-#define TCNT3H7_REG TCNT3H
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* TCNT3L */
-#define TCNT3L0_REG TCNT3L
-#define TCNT3L1_REG TCNT3L
-#define TCNT3L2_REG TCNT3L
-#define TCNT3L3_REG TCNT3L
-#define TCNT3L4_REG TCNT3L
-#define TCNT3L5_REG TCNT3L
-#define TCNT3L6_REG TCNT3L
-#define TCNT3L7_REG TCNT3L
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* USBCON */
-#define VBUSTE_REG USBCON
-#define OTGPADE_REG USBCON
-#define FRZCLK_REG USBCON
-#define USBE_REG USBCON
-
-/* MCUSR */
-#define JTRF_REG MCUSR
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* PCIFR */
-#define PCIF0_REG PCIFR
-
-/* UECONX */
-#define EPEN_REG UECONX
-#define RSTDT_REG UECONX
-#define STALLRQC_REG UECONX
-#define STALLRQ_REG UECONX
-
-/* PLLFRQ */
-#define PDIV0_REG PLLFRQ
-#define PDIV1_REG PLLFRQ
-#define PDIV2_REG PLLFRQ
-#define PDIV3_REG PLLFRQ
-#define PLLTM0_REG PLLFRQ
-#define PLLTM1_REG PLLFRQ
-#define PLLUSB_REG PLLFRQ
-#define PINMUX_REG PLLFRQ
-
-/* UEINT */
-#define EPINT0_REG UEINT
-#define EPINT1_REG UEINT
-#define EPINT2_REG UEINT
-#define EPINT3_REG UEINT
-#define EPINT4_REG UEINT
-#define EPINT5_REG UEINT
-#define EPINT6_REG UEINT
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* MCUCR */
-#define JTD_REG MCUCR
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-
-/* OCR1CL */
-#define OCR1CL0_REG OCR1CL
-#define OCR1CL1_REG OCR1CL
-#define OCR1CL2_REG OCR1CL
-#define OCR1CL3_REG OCR1CL
-#define OCR1CL4_REG OCR1CL
-#define OCR1CL5_REG OCR1CL
-#define OCR1CL6_REG OCR1CL
-#define OCR1CL7_REG OCR1CL
-
-/* OCR1CH */
-#define OCR1CH0_REG OCR1CH
-#define OCR1CH1_REG OCR1CH
-#define OCR1CH2_REG OCR1CH
-#define OCR1CH3_REG OCR1CH
-#define OCR1CH4_REG OCR1CH
-#define OCR1CH5_REG OCR1CH
-#define OCR1CH6_REG OCR1CH
-#define OCR1CH7_REG OCR1CH
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* USBSTA */
-#define VBUS_REG USBSTA
-#define SPEED_REG USBSTA
-
-/* UEIENX */
-#define TXINE_REG UEIENX
-#define STALLEDE_REG UEIENX
-#define RXOUTE_REG UEIENX
-#define RXSTPE_REG UEIENX
-#define NAKOUTE_REG UEIENX
-#define NAKINE_REG UEIENX
-#define FLERRE_REG UEIENX
-
-/* UCSR1B */
-#define TXB81_REG UCSR1B
-#define RXB81_REG UCSR1B
-#define UCSZ12_REG UCSR1B
-#define TXEN1_REG UCSR1B
-#define RXEN1_REG UCSR1B
-#define UDRIE1_REG UCSR1B
-#define TXCIE1_REG UCSR1B
-#define RXCIE1_REG UCSR1B
-
-/* UCSR1C */
-#define UCPOL1_REG UCSR1C
-#define UCSZ10_REG UCSR1C
-#define UCSZ11_REG UCSR1C
-#define USBS1_REG UCSR1C
-#define UPM10_REG UCSR1C
-#define UPM11_REG UCSR1C
-#define UMSEL10_REG UCSR1C
-#define UMSEL11_REG UCSR1C
-
-/* UCSR1A */
-#define MPCM1_REG UCSR1A
-#define U2X1_REG UCSR1A
-#define UPE1_REG UCSR1A
-#define DOR1_REG UCSR1A
-#define FE1_REG UCSR1A
-#define UDRE1_REG UCSR1A
-#define TXC1_REG UCSR1A
-#define RXC1_REG UCSR1A
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* EIND */
-#define EIND0_REG EIND
-
-/* UDFNUML */
-#define FNUM0_REG UDFNUML
-#define FNUM1_REG UDFNUML
-#define FNUM2_REG UDFNUML
-#define FNUM3_REG UDFNUML
-#define FNUM4_REG UDFNUML
-#define FNUM5_REG UDFNUML
-#define FNUM6_REG UDFNUML
-#define FNUM7_REG UDFNUML
-
-/* UDFNUMH */
-#define FNUM8_REG UDFNUMH
-#define FNUM9_REG UDFNUMH
-#define FNUM10_REG UDFNUMH
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ADTS3_REG ADCSRB
-#define MUX5_REG ADCSRB
-#define ADHSM_REG ADCSRB
-#define ACME_REG ADCSRB
-
-/* PRR0 */
-#define PRADC_REG PRR0
-#define PRUSART0_REG PRR0
-#define PRSPI_REG PRR0
-#define PRTIM1_REG PRR0
-#define PRTIM0_REG PRR0
-#define PRTIM2_REG PRR0
-#define PRTWI_REG PRR0
-
-/* UBRR1H */
-#define UBRR_8_REG UBRR1H
-#define UBRR_9_REG UBRR1H
-#define UBRR_10_REG UBRR1H
-#define UBRR_11_REG UBRR1H
-
-/* OCR0A */
-#define OCROA_0_REG OCR0A
-#define OCROA_1_REG OCR0A
-#define OCROA_2_REG OCR0A
-#define OCROA_3_REG OCR0A
-#define OCROA_4_REG OCR0A
-#define OCROA_5_REG OCR0A
-#define OCROA_6_REG OCR0A
-#define OCROA_7_REG OCR0A
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* PORTF */
-#define PORTF0_REG PORTF
-#define PORTF1_REG PORTF
-#define PORTF4_REG PORTF
-#define PORTF5_REG PORTF
-#define PORTF6_REG PORTF
-#define PORTF7_REG PORTF
-
-/* TCCR1C */
-#define FOC1C_REG TCCR1C
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* ICR3H */
-#define ICR3H0_REG ICR3H
-#define ICR3H1_REG ICR3H
-#define ICR3H2_REG ICR3H
-#define ICR3H3_REG ICR3H
-#define ICR3H4_REG ICR3H
-#define ICR3H5_REG ICR3H
-#define ICR3H6_REG ICR3H
-#define ICR3H7_REG ICR3H
-
-/* DDRE */
-#define DDE2_REG DDRE
-#define DDE6_REG DDRE
-
-/* UDADDR */
-#define UADD0_REG UDADDR
-#define UADD1_REG UDADDR
-#define UADD2_REG UDADDR
-#define UADD3_REG UDADDR
-#define UADD4_REG UDADDR
-#define UADD5_REG UDADDR
-#define UADD6_REG UDADDR
-#define ADDEN_REG UDADDR
-
-/* ICR3L */
-#define ICR3L0_REG ICR3L
-#define ICR3L1_REG ICR3L
-#define ICR3L2_REG ICR3L
-#define ICR3L3_REG ICR3L
-#define ICR3L4_REG ICR3L
-#define ICR3L5_REG ICR3L
-#define ICR3L6_REG ICR3L
-#define ICR3L7_REG ICR3L
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define SIGRD_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* UESTA0X */
-#define NBUSYBK0_REG UESTA0X
-#define NBUSYBK1_REG UESTA0X
-#define DTSEQ0_REG UESTA0X
-#define DTSEQ1_REG UESTA0X
-#define UNDERFI_REG UESTA0X
-#define OVERFI_REG UESTA0X
-#define CFGOK_REG UESTA0X
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* OCR3BL */
-#define OCR3BL0_REG OCR3BL
-#define OCR3BL1_REG OCR3BL
-#define OCR3BL2_REG OCR3BL
-#define OCR3BL3_REG OCR3BL
-#define OCR3BL4_REG OCR3BL
-#define OCR3BL5_REG OCR3BL
-#define OCR3BL6_REG OCR3BL
-#define OCR3BL7_REG OCR3BL
-
-/* OCR3BH */
-#define OCR3BH0_REG OCR3BH
-#define OCR3BH1_REG OCR3BH
-#define OCR3BH2_REG OCR3BH
-#define OCR3BH3_REG OCR3BH
-#define OCR3BH4_REG OCR3BH
-#define OCR3BH5_REG OCR3BH
-#define OCR3BH6_REG OCR3BH
-#define OCR3BH7_REG OCR3BH
-
-/* TIMSK3 */
-#define TOIE3_REG TIMSK3
-#define OCIE3A_REG TIMSK3
-#define OCIE3B_REG TIMSK3
-#define OCIE3C_REG TIMSK3
-#define ICIE3_REG TIMSK3
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define OCIE1C_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* CLKSTA */
-#define EXTON_REG CLKSTA
-#define RCON_REG CLKSTA
-
-/* TIMSK4 */
-#define TOIE4_REG TIMSK4
-#define OCIE4B_REG TIMSK4
-#define OCIE4A_REG TIMSK4
-#define OCIE4D_REG TIMSK4
-
-/* TCCR4B */
-#define CS40_REG TCCR4B
-#define CS41_REG TCCR4B
-#define CS42_REG TCCR4B
-#define CS43_REG TCCR4B
-#define DTPS40_REG TCCR4B
-#define DTPS41_REG TCCR4B
-#define PSR4_REG TCCR4B
-#define PWM4X_REG TCCR4B
-
-/* TCCR4C */
-#define PWM4D_REG TCCR4C
-#define FOC4D_REG TCCR4C
-#define COM4D0_REG TCCR4C
-#define COM4D1_REG TCCR4C
-#define COM4B0S_REG TCCR4C
-#define COM4B1S_REG TCCR4C
-#define COM4A0S_REG TCCR4C
-#define COM4A1S_REG TCCR4C
-
-/* PLLCSR */
-#define PLOCK_REG PLLCSR
-#define PLLE_REG PLLCSR
-#define PINDIV_REG PLLCSR
-
-/* TCCR4A */
-#define PWM4B_REG TCCR4A
-#define PWM4A_REG TCCR4A
-#define FOC4B_REG TCCR4A
-#define FOC4A_REG TCCR4A
-#define COM4B0_REG TCCR4A
-#define COM4B1_REG TCCR4A
-#define COM4A0_REG TCCR4A
-#define COM4A1_REG TCCR4A
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* TCCR4D */
-#define WGM40_REG TCCR4D
-#define WGM41_REG TCCR4D
-#define FPF4_REG TCCR4D
-#define FPAC4_REG TCCR4D
-#define FPES4_REG TCCR4D
-#define FPNC4_REG TCCR4D
-#define FPEN4_REG TCCR4D
-#define FPIE4_REG TCCR4D
-
-/* TCCR4E */
-#define OC4OE0_REG TCCR4E
-#define OC4OE1_REG TCCR4E
-#define OC4OE2_REG TCCR4E
-#define OC4OE3_REG TCCR4E
-#define OC4OE4_REG TCCR4E
-#define OC4OE5_REG TCCR4E
-#define ENHC4_REG TCCR4E
-#define TLOCK4_REG TCCR4E
-
-/* PINC */
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-#define INTF2_REG EIFR
-#define INTF3_REG EIFR
-#define INTF4_REG EIFR
-#define INTF5_REG EIFR
-#define INTF6_REG EIFR
-#define INTF7_REG EIFR
-
-/* PINF */
-#define PINF0_REG PINF
-#define PINF1_REG PINF
-#define PINF4_REG PINF
-#define PINF5_REG PINF
-#define PINF6_REG PINF
-#define PINF7_REG PINF
-
-/* PINE */
-#define PINE2_REG PINE
-#define PINE6_REG PINE
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* PRR1 */
-#define PRUSART1_REG PRR1
-#define PRTIM3_REG PRR1
-#define PRUSB_REG PRR1
-
-/* DT4 */
-#define DT4L0_REG DT4
-#define DT4L1_REG DT4
-#define DT4L2_REG DT4
-#define DT4L3_REG DT4
-#define DT4L4_REG DT4
-#define DT4L5_REG DT4
-#define DT4L6_REG DT4
-#define DT4L7_REG DT4
-
-/* pins mapping */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-/* prescalers timer 3 */
-#define TIMER3_PRESCALER_DIV_0 0
-#define TIMER3_PRESCALER_DIV_1 1
-#define TIMER3_PRESCALER_DIV_8 2
-#define TIMER3_PRESCALER_DIV_64 3
-#define TIMER3_PRESCALER_DIV_256 4
-#define TIMER3_PRESCALER_DIV_1024 5
-#define TIMER3_PRESCALER_DIV_FALL 6
-#define TIMER3_PRESCALER_DIV_RISE 7
-
-#define TIMER3_PRESCALER_REG_0 0
-#define TIMER3_PRESCALER_REG_1 1
-#define TIMER3_PRESCALER_REG_2 8
-#define TIMER3_PRESCALER_REG_3 64
-#define TIMER3_PRESCALER_REG_4 256
-#define TIMER3_PRESCALER_REG_5 1024
-#define TIMER3_PRESCALER_REG_6 -1
-#define TIMER3_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER1C_AVAILABLE
-#define TIMER2_AVAILABLE
-#define TIMER2A_AVAILABLE
-#define TIMER2B_AVAILABLE
-#define TIMER3_AVAILABLE
-#define TIMER3A_AVAILABLE
-#define TIMER3B_AVAILABLE
-#define TIMER3C_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW3_NUM 3
-#define SIG_OVERFLOW_TOTAL_NUM 4
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE1C_NUM 4
-#define SIG_OUTPUT_COMPARE2A_NUM 5
-#define SIG_OUTPUT_COMPARE2B_NUM 6
-#define SIG_OUTPUT_COMPARE3A_NUM 7
-#define SIG_OUTPUT_COMPARE3B_NUM 8
-#define SIG_OUTPUT_COMPARE3C_NUM 9
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 10
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM1C_NUM 4
-#define PWM2A_NUM 5
-#define PWM2B_NUM 6
-#define PWM3A_NUM 7
-#define PWM3B_NUM 8
-#define PWM3C_NUM 9
-#define PWM_TOTAL_NUM 10
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE3_NUM 1
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 2
-
-
-/* UEBCHX */
-#define UEBCHX_0_REG UEBCHX
-#define UEBCHX_1_REG UEBCHX
-#define UEBCHX_2_REG UEBCHX
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* UDIEN */
-#define SUSPE_REG UDIEN
-#define SOFE_REG UDIEN
-#define EORSTE_REG UDIEN
-#define WAKEUPE_REG UDIEN
-#define EORSME_REG UDIEN
-#define UPRSME_REG UDIEN
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* OCR0B */
-#define OCR0B_0_REG OCR0B
-#define OCR0B_1_REG OCR0B
-#define OCR0B_2_REG OCR0B
-#define OCR0B_3_REG OCR0B
-#define OCR0B_4_REG OCR0B
-#define OCR0B_5_REG OCR0B
-#define OCR0B_6_REG OCR0B
-#define OCR0B_7_REG OCR0B
-
-/* UDINT */
-#define SUSPI_REG UDINT
-#define SOFI_REG UDINT
-#define EORSTI_REG UDINT
-#define WAKEUPI_REG UDINT
-#define EORSMI_REG UDINT
-#define UPRSMI_REG UDINT
-
-/* UERST */
-#define EPRST0_REG UERST
-#define EPRST1_REG UERST
-#define EPRST2_REG UERST
-#define EPRST3_REG UERST
-#define EPRST4_REG UERST
-#define EPRST5_REG UERST
-#define EPRST6_REG UERST
-
-/* UECFG1X */
-#define ALLOC_REG UECFG1X
-#define EPBK0_REG UECFG1X
-#define EPBK1_REG UECFG1X
-#define EPSIZE0_REG UECFG1X
-#define EPSIZE1_REG UECFG1X
-#define EPSIZE2_REG UECFG1X
-
-/* OCR2B */
-#define OCR2B_0_REG OCR2B
-#define OCR2B_1_REG OCR2B
-#define OCR2B_2_REG OCR2B
-#define OCR2B_3_REG OCR2B
-#define OCR2B_4_REG OCR2B
-#define OCR2B_5_REG OCR2B
-#define OCR2B_6_REG OCR2B
-#define OCR2B_7_REG OCR2B
-
-/* OCR2A */
-#define OCR2A_0_REG OCR2A
-#define OCR2A_1_REG OCR2A
-#define OCR2A_2_REG OCR2A
-#define OCR2A_3_REG OCR2A
-#define OCR2A_4_REG OCR2A
-#define OCR2A_5_REG OCR2A
-#define OCR2A_6_REG OCR2A
-#define OCR2A_7_REG OCR2A
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* UEINT */
-#define EPINT0_REG UEINT
-#define EPINT1_REG UEINT
-#define EPINT2_REG UEINT
-#define EPINT3_REG UEINT
-#define EPINT4_REG UEINT
-#define EPINT5_REG UEINT
-#define EPINT6_REG UEINT
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-#define PORTE3_REG PORTE
-#define PORTE4_REG PORTE
-#define PORTE5_REG PORTE
-#define PORTE6_REG PORTE
-#define PORTE7_REG PORTE
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-#define INT3_REG EIMSK
-#define INT4_REG EIMSK
-#define INT5_REG EIMSK
-#define INT6_REG EIMSK
-#define INT7_REG EIMSK
-
-/* UDR1 */
-#define UDR1_0_REG UDR1
-#define UDR1_1_REG UDR1
-#define UDR1_2_REG UDR1
-#define UDR1_3_REG UDR1
-#define UDR1_4_REG UDR1
-#define UDR1_5_REG UDR1
-#define UDR1_6_REG UDR1
-#define UDR1_7_REG UDR1
-
-/* EICRB */
-#define ISC40_REG EICRB
-#define ISC41_REG EICRB
-#define ISC50_REG EICRB
-#define ISC51_REG EICRB
-#define ISC60_REG EICRB
-#define ISC61_REG EICRB
-#define ISC70_REG EICRB
-#define ISC71_REG EICRB
-
-/* UEDATX */
-#define UEDATX_0_REG UEDATX
-#define UEDATX_1_REG UEDATX
-#define UEDATX_2_REG UEDATX
-#define UEDATX_3_REG UEDATX
-#define UEDATX_4_REG UEDATX
-#define UEDATX_5_REG UEDATX
-#define UEDATX_6_REG UEDATX
-#define UEDATX_7_REG UEDATX
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-#define ISC20_REG EICRA
-#define ISC21_REG EICRA
-#define ISC30_REG EICRA
-#define ISC31_REG EICRA
-
-/* UECFG0X */
-#define EPDIR_REG UECFG0X
-#define EPTYPE0_REG UECFG0X
-#define EPTYPE1_REG UECFG0X
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* DDRF */
-#define DDF0_REG DDRF
-#define DDF1_REG DDRF
-#define DDF2_REG DDRF
-#define DDF3_REG DDRF
-#define DDF4_REG DDRF
-#define DDF5_REG DDRF
-#define DDF6_REG DDRF
-#define DDF7_REG DDRF
-
-/* ASSR */
-#define TCR2BUB_REG ASSR
-#define TCR2AUB_REG ASSR
-#define OCR2BUB_REG ASSR
-#define OCR2AUB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* UENUM */
-#define UENUM_0_REG UENUM
-#define UENUM_1_REG UENUM
-#define UENUM_2_REG UENUM
-
-/* UBRR1L */
-#define UBRR_0_REG UBRR1L
-#define UBRR_1_REG UBRR1L
-#define UBRR_2_REG UBRR1L
-#define UBRR_3_REG UBRR1L
-#define UBRR_4_REG UBRR1L
-#define UBRR_5_REG UBRR1L
-#define UBRR_6_REG UBRR1L
-#define UBRR_7_REG UBRR1L
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* OCR3AL */
-#define OCR3AL0_REG OCR3AL
-#define OCR3AL1_REG OCR3AL
-#define OCR3AL2_REG OCR3AL
-#define OCR3AL3_REG OCR3AL
-#define OCR3AL4_REG OCR3AL
-#define OCR3AL5_REG OCR3AL
-#define OCR3AL6_REG OCR3AL
-#define OCR3AL7_REG OCR3AL
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1C0_REG TCCR1A
-#define COM1C1_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* OCR3AH */
-#define OCR3AH0_REG OCR3AH
-#define OCR3AH1_REG OCR3AH
-#define OCR3AH2_REG OCR3AH
-#define OCR3AH3_REG OCR3AH
-#define OCR3AH4_REG OCR3AH
-#define OCR3AH5_REG OCR3AH
-#define OCR3AH6_REG OCR3AH
-#define OCR3AH7_REG OCR3AH
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* UDCON */
-#define DETACH_REG UDCON
-#define RMWKUP_REG UDCON
-#define LSM_REG UDCON
-
-/* PCICR */
-#define PCIE0_REG PCICR
-
-/* USBINT */
-#define VBUSTI_REG USBINT
-#define IDTI_REG USBINT
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* UHWCON */
-#define UVREGE_REG UHWCON
-#define UVCONE_REG UHWCON
-#define UIDE_REG UHWCON
-#define UIMOD_REG UHWCON
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* UDMFN */
-#define FNCERR_REG UDMFN
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-#define OCF2B_REG TIFR2
-
-/* TIFR3 */
-#define TOV3_REG TIFR3
-#define OCF3A_REG TIFR3
-#define OCF3B_REG TIFR3
-#define OCF3C_REG TIFR3
-#define ICF3_REG TIFR3
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define OCF1C_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-#define EEAR10_REG EEARH
-#define EEAR11_REG EEARH
-
-/* UEBCLX */
-#define UEBCLX_0_REG UEBCLX
-#define UEBCLX_1_REG UEBCLX
-#define UEBCLX_2_REG UEBCLX
-#define UEBCLX_3_REG UEBCLX
-#define UEBCLX_4_REG UEBCLX
-#define UEBCLX_5_REG UEBCLX
-#define UEBCLX_6_REG UEBCLX
-#define UEBCLX_7_REG UEBCLX
-
-/* OCR3CH */
-#define OCR3CH0_REG OCR3CH
-#define OCR3CH1_REG OCR3CH
-#define OCR3CH2_REG OCR3CH
-#define OCR3CH3_REG OCR3CH
-#define OCR3CH4_REG OCR3CH
-#define OCR3CH5_REG OCR3CH
-#define OCR3CH6_REG OCR3CH
-#define OCR3CH7_REG OCR3CH
-
-/* UESTA1X */
-#define CURRBK0_REG UESTA1X
-#define CURRBK1_REG UESTA1X
-#define CTRLDIR_REG UESTA1X
-
-/* OCR3CL */
-#define OCR3CL0_REG OCR3CL
-#define OCR3CL1_REG OCR3CL
-#define OCR3CL2_REG OCR3CL
-#define OCR3CL3_REG OCR3CL
-#define OCR3CL4_REG OCR3CL
-#define OCR3CL5_REG OCR3CL
-#define OCR3CL6_REG OCR3CL
-#define OCR3CL7_REG OCR3CL
-
-/* GTCCR */
-#define PSRSYNC_REG GTCCR
-#define TSM_REG GTCCR
-#define PSRASY_REG GTCCR
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* TCCR3C */
-#define FOC3C_REG TCCR3C
-#define FOC3B_REG TCCR3C
-#define FOC3A_REG TCCR3C
-
-/* TCCR3B */
-#define CS30_REG TCCR3B
-#define CS31_REG TCCR3B
-#define CS32_REG TCCR3B
-#define WGM32_REG TCCR3B
-#define WGM33_REG TCCR3B
-#define ICES3_REG TCCR3B
-#define ICNC3_REG TCCR3B
-
-/* TCCR3A */
-#define WGM30_REG TCCR3A
-#define WGM31_REG TCCR3A
-#define COM3C0_REG TCCR3A
-#define COM3C1_REG TCCR3A
-#define COM3B0_REG TCCR3A
-#define COM3B1_REG TCCR3A
-#define COM3A0_REG TCCR3A
-#define COM3A1_REG TCCR3A
-
-/* UEINTX */
-#define TXINI_REG UEINTX
-#define STALLEDI_REG UEINTX
-#define RXOUTI_REG UEINTX
-#define RXSTPI_REG UEINTX
-#define NAKOUTI_REG UEINTX
-#define RWAL_REG UEINTX
-#define NAKINI_REG UEINTX
-#define FIFOCON_REG UEINTX
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* TCNT3H */
-#define TCNT3H0_REG TCNT3H
-#define TCNT3H1_REG TCNT3H
-#define TCNT3H2_REG TCNT3H
-#define TCNT3H3_REG TCNT3H
-#define TCNT3H4_REG TCNT3H
-#define TCNT3H5_REG TCNT3H
-#define TCNT3H6_REG TCNT3H
-#define TCNT3H7_REG TCNT3H
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* TCNT3L */
-#define TCNT3L0_REG TCNT3L
-#define TCNT3L1_REG TCNT3L
-#define TCNT3L2_REG TCNT3L
-#define TCNT3L3_REG TCNT3L
-#define TCNT3L4_REG TCNT3L
-#define TCNT3L5_REG TCNT3L
-#define TCNT3L6_REG TCNT3L
-#define TCNT3L7_REG TCNT3L
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* USBCON */
-#define VBUSTE_REG USBCON
-#define IDTE_REG USBCON
-#define OTGPADE_REG USBCON
-#define FRZCLK_REG USBCON
-#define HOST_REG USBCON
-#define USBE_REG USBCON
-
-/* MCUSR */
-#define JTRF_REG MCUSR
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* PCIFR */
-#define PCIF0_REG PCIFR
-
-/* TCCR2A */
-#define WGM20_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2B0_REG TCCR2A
-#define COM2B1_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-
-/* TCCR2B */
-#define CS20_REG TCCR2B
-#define CS21_REG TCCR2B
-#define CS22_REG TCCR2B
-#define WGM22_REG TCCR2B
-#define FOC2B_REG TCCR2B
-#define FOC2A_REG TCCR2B
-
-/* UECONX */
-#define EPEN_REG UECONX
-#define RSTDT_REG UECONX
-#define STALLRQC_REG UECONX
-#define STALLRQ_REG UECONX
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* MCUCR */
-#define JTD_REG MCUCR
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-
-/* OCR1CL */
-#define OCR1CL0_REG OCR1CL
-#define OCR1CL1_REG OCR1CL
-#define OCR1CL2_REG OCR1CL
-#define OCR1CL3_REG OCR1CL
-#define OCR1CL4_REG OCR1CL
-#define OCR1CL5_REG OCR1CL
-#define OCR1CL6_REG OCR1CL
-#define OCR1CL7_REG OCR1CL
-
-/* OCR1CH */
-#define OCR1CH0_REG OCR1CH
-#define OCR1CH1_REG OCR1CH
-#define OCR1CH2_REG OCR1CH
-#define OCR1CH3_REG OCR1CH
-#define OCR1CH4_REG OCR1CH
-#define OCR1CH5_REG OCR1CH
-#define OCR1CH6_REG OCR1CH
-#define OCR1CH7_REG OCR1CH
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* USBSTA */
-#define VBUS_REG USBSTA
-#define ID_REG USBSTA
-#define SPEED_REG USBSTA
-
-/* UEIENX */
-#define TXINE_REG UEIENX
-#define STALLEDE_REG UEIENX
-#define RXOUTE_REG UEIENX
-#define RXSTPE_REG UEIENX
-#define NAKOUTE_REG UEIENX
-#define NAKINE_REG UEIENX
-#define FLERRE_REG UEIENX
-
-/* UCSR1B */
-#define TXB81_REG UCSR1B
-#define RXB81_REG UCSR1B
-#define UCSZ12_REG UCSR1B
-#define TXEN1_REG UCSR1B
-#define RXEN1_REG UCSR1B
-#define UDRIE1_REG UCSR1B
-#define TXCIE1_REG UCSR1B
-#define RXCIE1_REG UCSR1B
-
-/* UCSR1C */
-#define UCPOL1_REG UCSR1C
-#define UCSZ10_REG UCSR1C
-#define UCSZ11_REG UCSR1C
-#define USBS1_REG UCSR1C
-#define UPM10_REG UCSR1C
-#define UPM11_REG UCSR1C
-#define UMSEL10_REG UCSR1C
-#define UMSEL11_REG UCSR1C
-
-/* UCSR1A */
-#define MPCM1_REG UCSR1A
-#define U2X1_REG UCSR1A
-#define UPE1_REG UCSR1A
-#define DOR1_REG UCSR1A
-#define FE1_REG UCSR1A
-#define UDRE1_REG UCSR1A
-#define TXC1_REG UCSR1A
-#define RXC1_REG UCSR1A
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* UDFNUML */
-#define UDFNUML_0_REG UDFNUML
-#define UDFNUML_1_REG UDFNUML
-#define UDFNUML_2_REG UDFNUML
-#define UDFNUML_3_REG UDFNUML
-#define UDFNUML_4_REG UDFNUML
-#define UDFNUML_5_REG UDFNUML
-#define UDFNUML_6_REG UDFNUML
-#define UDFNUML_7_REG UDFNUML
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* UDFNUMH */
-#define UDFNUMH_0_REG UDFNUMH
-#define UDFNUMH_1_REG UDFNUMH
-#define UDFNUMH_2_REG UDFNUMH
-
-/* TWAMR */
-#define TWAM0_REG TWAMR
-#define TWAM1_REG TWAMR
-#define TWAM2_REG TWAMR
-#define TWAM3_REG TWAMR
-#define TWAM4_REG TWAMR
-#define TWAM5_REG TWAMR
-#define TWAM6_REG TWAMR
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ADHSM_REG ADCSRB
-#define ACME_REG ADCSRB
-
-/* PRR0 */
-#define PRADC_REG PRR0
-#define PRSPI_REG PRR0
-#define PRTIM1_REG PRR0
-#define PRTIM0_REG PRR0
-#define PRTIM2_REG PRR0
-#define PRTWI_REG PRR0
-
-/* UBRR1H */
-#define UBRR_8_REG UBRR1H
-#define UBRR_9_REG UBRR1H
-#define UBRR_10_REG UBRR1H
-#define UBRR_11_REG UBRR1H
-
-/* OCR0A */
-#define OCROA_0_REG OCR0A
-#define OCROA_1_REG OCR0A
-#define OCROA_2_REG OCR0A
-#define OCROA_3_REG OCR0A
-#define OCROA_4_REG OCR0A
-#define OCROA_5_REG OCR0A
-#define OCROA_6_REG OCR0A
-#define OCROA_7_REG OCR0A
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* PORTF */
-#define PORTF0_REG PORTF
-#define PORTF1_REG PORTF
-#define PORTF2_REG PORTF
-#define PORTF3_REG PORTF
-#define PORTF4_REG PORTF
-#define PORTF5_REG PORTF
-#define PORTF6_REG PORTF
-#define PORTF7_REG PORTF
-
-/* TCCR1C */
-#define FOC1C_REG TCCR1C
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* ICR3H */
-#define ICR3H0_REG ICR3H
-#define ICR3H1_REG ICR3H
-#define ICR3H2_REG ICR3H
-#define ICR3H3_REG ICR3H
-#define ICR3H4_REG ICR3H
-#define ICR3H5_REG ICR3H
-#define ICR3H6_REG ICR3H
-#define ICR3H7_REG ICR3H
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-#define DDE3_REG DDRE
-#define DDE4_REG DDRE
-#define DDE5_REG DDRE
-#define DDE6_REG DDRE
-#define DDE7_REG DDRE
-
-/* UDADDR */
-#define UADD0_REG UDADDR
-#define UADD1_REG UDADDR
-#define UADD2_REG UDADDR
-#define UADD3_REG UDADDR
-#define UADD4_REG UDADDR
-#define UADD5_REG UDADDR
-#define UADD6_REG UDADDR
-#define ADDEN_REG UDADDR
-
-/* ICR3L */
-#define ICR3L0_REG ICR3L
-#define ICR3L1_REG ICR3L
-#define ICR3L2_REG ICR3L
-#define ICR3L3_REG ICR3L
-#define ICR3L4_REG ICR3L
-#define ICR3L5_REG ICR3L
-#define ICR3L6_REG ICR3L
-#define ICR3L7_REG ICR3L
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define SIGRD_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* UESTA0X */
-#define NBUSYBK0_REG UESTA0X
-#define NBUSYBK1_REG UESTA0X
-#define DTSEQ0_REG UESTA0X
-#define DTSEQ1_REG UESTA0X
-#define UNDERFI_REG UESTA0X
-#define OVERFI_REG UESTA0X
-#define CFGOK_REG UESTA0X
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* OCR3BL */
-#define OCR3BL0_REG OCR3BL
-#define OCR3BL1_REG OCR3BL
-#define OCR3BL2_REG OCR3BL
-#define OCR3BL3_REG OCR3BL
-#define OCR3BL4_REG OCR3BL
-#define OCR3BL5_REG OCR3BL
-#define OCR3BL6_REG OCR3BL
-#define OCR3BL7_REG OCR3BL
-
-/* OCR3BH */
-#define OCR3BH0_REG OCR3BH
-#define OCR3BH1_REG OCR3BH
-#define OCR3BH2_REG OCR3BH
-#define OCR3BH3_REG OCR3BH
-#define OCR3BH4_REG OCR3BH
-#define OCR3BH5_REG OCR3BH
-#define OCR3BH6_REG OCR3BH
-#define OCR3BH7_REG OCR3BH
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-#define OCIE2B_REG TIMSK2
-
-/* TIMSK3 */
-#define TOIE3_REG TIMSK3
-#define OCIE3A_REG TIMSK3
-#define OCIE3B_REG TIMSK3
-#define OCIE3C_REG TIMSK3
-#define ICIE3_REG TIMSK3
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define OCIE1C_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* PLLCSR */
-#define PLOCK_REG PLLCSR
-#define PLLE_REG PLLCSR
-#define PLLP0_REG PLLCSR
-#define PLLP1_REG PLLCSR
-#define PLLP2_REG PLLCSR
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* XMCRB */
-#define XMM0_REG XMCRB
-#define XMM1_REG XMCRB
-#define XMM2_REG XMCRB
-#define XMBK_REG XMCRB
-
-/* XMCRA */
-#define SRW00_REG XMCRA
-#define SRW01_REG XMCRA
-#define SRW10_REG XMCRA
-#define SRW11_REG XMCRA
-#define SRL0_REG XMCRA
-#define SRL1_REG XMCRA
-#define SRL2_REG XMCRA
-#define SRE_REG XMCRA
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-#define INTF2_REG EIFR
-#define INTF3_REG EIFR
-#define INTF4_REG EIFR
-#define INTF5_REG EIFR
-#define INTF6_REG EIFR
-#define INTF7_REG EIFR
-
-/* PINF */
-#define PINF0_REG PINF
-#define PINF1_REG PINF
-#define PINF2_REG PINF
-#define PINF3_REG PINF
-#define PINF4_REG PINF
-#define PINF5_REG PINF
-#define PINF6_REG PINF
-#define PINF7_REG PINF
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-#define PINE3_REG PINE
-#define PINE4_REG PINE
-#define PINE5_REG PINE
-#define PINE6_REG PINE
-#define PINE7_REG PINE
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* PRR1 */
-#define PRUSART1_REG PRR1
-#define PRTIM3_REG PRR1
-#define PRUSB_REG PRR1
-
-/* pins mapping */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_32 3
-#define TIMER1_PRESCALER_DIV_64 4
-#define TIMER1_PRESCALER_DIV_128 5
-#define TIMER1_PRESCALER_DIV_256 6
-#define TIMER1_PRESCALER_DIV_1024 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 32
-#define TIMER1_PRESCALER_REG_4 64
-#define TIMER1_PRESCALER_REG_5 128
-#define TIMER1_PRESCALER_REG_6 256
-#define TIMER1_PRESCALER_REG_7 1024
-
-
-/* available timers */
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW_TOTAL_NUM 0
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0
-
-/* Pwm nums */
-#define PWM_TOTAL_NUM 0
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 0
-
-
-/* CADAC2 */
-#define CADAC16_REG CADAC2
-#define CADAC17_REG CADAC2
-#define CADAC18_REG CADAC2
-#define CADAC19_REG CADAC2
-#define CADAC20_REG CADAC2
-#define CADAC21_REG CADAC2
-#define CADAC22_REG CADAC2
-#define CADAC23_REG CADAC2
-
-/* CADAC3 */
-#define CADAC24_REG CADAC3
-#define CADAC25_REG CADAC3
-#define CADAC26_REG CADAC3
-#define CADAC27_REG CADAC3
-#define CADAC28_REG CADAC3
-#define CADAC29_REG CADAC3
-#define CADAC30_REG CADAC3
-#define CADAC31_REG CADAC3
-
-/* CADAC0 */
-#define CADAC00_REG CADAC0
-#define CADAC01_REG CADAC0
-#define CADAC02_REG CADAC0
-#define CADAC03_REG CADAC0
-#define CADAC04_REG CADAC0
-#define CADAC05_REG CADAC0
-#define CADAC06_REG CADAC0
-#define CADAC07_REG CADAC0
-
-/* CADAC1 */
-#define CADAC08_REG CADAC1
-#define CADAC09_REG CADAC1
-#define CADAC10_REG CADAC1
-#define CADAC11_REG CADAC1
-#define CADAC12_REG CADAC1
-#define CADAC13_REG CADAC1
-#define CADAC14_REG CADAC1
-#define CADAC15_REG CADAC1
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* PCIFR */
-#define PCIF0_REG PCIFR
-#define PCIF1_REG PCIFR
-
-/* WUTCSR */
-#define WUTP0_REG WUTCSR
-#define WUTP1_REG WUTCSR
-#define WUTP2_REG WUTCSR
-#define WUTE_REG WUTCSR
-#define WUTR_REG WUTCSR
-#define WUTCF_REG WUTCSR
-#define WUTIE_REG WUTCSR
-#define WUTIF_REG WUTCSR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* PCICR */
-#define PCIE0_REG PCICR
-#define PCIE1_REG PCICR
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* BPCR */
-#define CCD_REG BPCR
-#define DCD_REG BPCR
-#define SCD_REG BPCR
-#define DUVD_REG BPCR
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-
-/* GTCCR */
-#define PSRSYNC_REG GTCCR
-#define TSM_REG GTCCR
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* BGCRR */
-#define BGCR0_REG BGCRR
-#define BGCR1_REG BGCRR
-#define BGCR2_REG BGCRR
-#define BGCR3_REG BGCRR
-#define BGCR4_REG BGCRR
-#define BGCR5_REG BGCRR
-#define BGCR6_REG BGCRR
-#define BGCR7_REG BGCRR
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-#define INT3_REG EIMSK
-
-/* PRR0 */
-#define PRVADC_REG PRR0
-#define PRTIM0_REG PRR0
-#define PRTIM1_REG PRR0
-#define PRTWI_REG PRR0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-#define PCINT15_REG PCMSK1
-
-/* OCR0A */
-#define OCR0A0_REG OCR0A
-#define OCR0A1_REG OCR0A
-#define OCR0A2_REG OCR0A
-#define OCR0A3_REG OCR0A
-#define OCR0A4_REG OCR0A
-#define OCR0A5_REG OCR0A
-#define OCR0A6_REG OCR0A
-#define OCR0A7_REG OCR0A
-
-/* BPOCD */
-#define CCDL0_REG BPOCD
-#define CCDL1_REG BPOCD
-#define CCDL2_REG BPOCD
-#define CCDL3_REG BPOCD
-#define DCDL0_REG BPOCD
-#define DCDL1_REG BPOCD
-#define DCDL2_REG BPOCD
-#define DCDL3_REG BPOCD
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-
-/* OCR0B */
-#define OCR0B0_REG OCR0B
-#define OCR0B1_REG OCR0B
-#define OCR0B2_REG OCR0B
-#define OCR0B3_REG OCR0B
-#define OCR0B4_REG OCR0B
-#define OCR0B5_REG OCR0B
-#define OCR0B6_REG OCR0B
-#define OCR0B7_REG OCR0B
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* CCSR */
-#define ACS_REG CCSR
-#define XOE_REG CCSR
-
-/* CADICH */
-#define CADICH0_REG CADICH
-#define CADICH1_REG CADICH
-#define CADICH2_REG CADICH
-#define CADICH3_REG CADICH
-#define CADICH4_REG CADICH
-#define CADICH5_REG CADICH
-#define CADICH6_REG CADICH
-#define CADICH7_REG CADICH
-
-/* FCSR */
-#define PFD_REG FCSR
-#define CFE_REG FCSR
-#define DFE_REG FCSR
-#define CPS_REG FCSR
-#define PWMOPC_REG FCSR
-#define PWMOC_REG FCSR
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* CADCSRB */
-#define CADICIF_REG CADCSRB
-#define CADRCIF_REG CADCSRB
-#define CADACIF_REG CADCSRB
-#define CADICIE_REG CADCSRB
-#define CADRCIE_REG CADCSRB
-#define CADACIE_REG CADCSRB
-
-/* CADICL */
-#define CADICL0_REG CADICL
-#define CADICL1_REG CADICL
-#define CADICL2_REG CADICL
-#define CADICL3_REG CADICL
-#define CADICL4_REG CADICL
-#define CADICL5_REG CADICL
-#define CADICL6_REG CADICL
-#define CADICL7_REG CADICL
-
-/* BPIR */
-#define SCIE_REG BPIR
-#define DOCIE_REG BPIR
-#define COCIE_REG BPIR
-#define DUVIE_REG BPIR
-#define SCIF_REG BPIR
-#define DOCIF_REG BPIR
-#define COCIF_REG BPIR
-#define DUVIF_REG BPIR
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* BPPLR */
-#define BPPL_REG BPPLR
-#define BPPLE_REG BPPLR
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define CTC1_REG TCCR1B
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BODRF_REG MCUSR
-#define WDRF_REG MCUSR
-#define JTRF_REG MCUSR
-
-/* EEARH */
-#define EEAR8_REG EEARH
-
-/* CBPTR */
-#define OCPT0_REG CBPTR
-#define OCPT1_REG CBPTR
-#define OCPT2_REG CBPTR
-#define OCPT3_REG CBPTR
-#define SCPT0_REG CBPTR
-#define SCPT1_REG CBPTR
-#define SCPT2_REG CBPTR
-#define SCPT3_REG CBPTR
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define SIGRD_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* CADCSRA */
-#define CADSE_REG CADCSRA
-#define CADSI0_REG CADCSRA
-#define CADSI1_REG CADCSRA
-#define CADAS0_REG CADCSRA
-#define CADAS1_REG CADCSRA
-#define CADUB_REG CADCSRA
-#define CADEN_REG CADCSRA
-
-/* BPDUV */
-#define DUDL0_REG BPDUV
-#define DUDL1_REG BPDUV
-#define DUDL2_REG BPDUV
-#define DUDL3_REG BPDUV
-#define DUVT0_REG BPDUV
-#define DUVT1_REG BPDUV
-
-/* CADRDC */
-#define CADRDC0_REG CADRDC
-#define CADRDC1_REG CADRDC
-#define CADRDC2_REG CADRDC
-#define CADRDC3_REG CADRDC
-#define CADRDC4_REG CADRDC
-#define CADRDC5_REG CADRDC
-#define CADRDC6_REG CADRDC
-#define CADRDC7_REG CADRDC
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-
-/* TWAMR */
-#define TWAM0_REG TWAMR
-#define TWAM1_REG TWAMR
-#define TWAM2_REG TWAMR
-#define TWAM3_REG TWAMR
-#define TWAM4_REG TWAMR
-#define TWAM5_REG TWAMR
-#define TWAM6_REG TWAMR
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* BPSCD */
-#define SCDL0_REG BPSCD
-#define SCDL1_REG BPSCD
-#define SCDL2_REG BPSCD
-#define SCDL3_REG BPSCD
-
-/* TCNT0 */
-#define TCNT00_REG TCNT0
-#define TCNT01_REG TCNT0
-#define TCNT02_REG TCNT0
-#define TCNT03_REG TCNT0
-#define TCNT04_REG TCNT0
-#define TCNT05_REG TCNT0
-#define TCNT06_REG TCNT0
-#define TCNT07_REG TCNT0
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* BGCCR */
-#define BGCC0_REG BGCCR
-#define BGCC1_REG BGCCR
-#define BGCC2_REG BGCCR
-#define BGCC3_REG BGCCR
-#define BGCC4_REG BGCCR
-#define BGCC5_REG BGCCR
-#define BGD_REG BGCCR
-
-/* VADMUX */
-#define VADMUX0_REG VADMUX
-#define VADMUX1_REG VADMUX
-#define VADMUX2_REG VADMUX
-#define VADMUX3_REG VADMUX
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* VADCH */
-#define VADC8_REG VADCH
-#define VADC9_REG VADCH
-#define VADC10_REG VADCH
-#define VADC11_REG VADCH
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* VADCL */
-#define VADC0_REG VADCL
-#define VADC1_REG VADCL
-#define VADC2_REG VADCL
-#define VADC3_REG VADCL
-#define VADC4_REG VADCL
-#define VADC5_REG VADCL
-#define VADC6_REG VADCL
-#define VADC7_REG VADCL
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-#define ISC20_REG EICRA
-#define ISC21_REG EICRA
-#define ISC30_REG EICRA
-#define ISC31_REG EICRA
-
-/* VADCSR */
-#define VADCCIE_REG VADCSR
-#define VADCCIF_REG VADCSR
-#define VADSC_REG VADCSR
-#define VADEN_REG VADCSR
-
-/* FOSCCAL */
-#define FCAL0_REG FOSCCAL
-#define FCAL1_REG FOSCCAL
-#define FCAL2_REG FOSCCAL
-#define FCAL3_REG FOSCCAL
-#define FCAL4_REG FOSCCAL
-#define FCAL5_REG FOSCCAL
-#define FCAL6_REG FOSCCAL
-#define FCAL7_REG FOSCCAL
-
-/* DIDR0 */
-#define VADC0D_REG DIDR0
-#define VADC1D_REG DIDR0
-#define VADC2D_REG DIDR0
-#define VADC3D_REG DIDR0
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* MCUCR */
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-#define JTD_REG MCUCR
-
-/* CBCR */
-#define CBE1_REG CBCR
-#define CBE2_REG CBCR
-#define CBE3_REG CBCR
-#define CBE4_REG CBCR
-
-/* TWBCSR */
-#define TWBCIP_REG TWBCSR
-#define TWBDT0_REG TWBCSR
-#define TWBDT1_REG TWBCSR
-#define TWBCIE_REG TWBCSR
-#define TWBCIF_REG TWBCSR
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* CADRCC */
-#define CADRCC0_REG CADRCC
-#define CADRCC1_REG CADRCC
-#define CADRCC2_REG CADRCC
-#define CADRCC3_REG CADRCC
-#define CADRCC4_REG CADRCC
-#define CADRCC5_REG CADRCC
-#define CADRCC6_REG CADRCC
-#define CADRCC7_REG CADRCC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-#define INTF2_REG EIFR
-#define INTF3_REG EIFR
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-
-/* pins mapping */
-#define ADC0_PORT PORTA
-#define ADC0_BIT 0
-#define PCINT0_PORT PORTA
-#define PCINT0_BIT 0
-
-#define ADC1_PORT PORTA
-#define ADC1_BIT 1
-#define PCINT1_PORT PORTA
-#define PCINT1_BIT 1
-
-#define ADC2_PORT PORTA
-#define ADC2_BIT 2
-#define PCINT2_PORT PORTA
-#define PCINT2_BIT 2
-
-#define ADC3_PORT PORTA
-#define ADC3_BIT 3
-#define PCINT3_PORT PORTA
-#define PCINT3_BIT 3
-
-#define ADC4_PORT PORTA
-#define ADC4_BIT 4
-#define INT0_PORT PORTA
-#define INT0_BIT 4
-#define PCINT4_PORT PORTA
-#define PCINT4_BIT 4
-
-#define INT1_PORT PORTA
-#define INT1_BIT 5
-#define PCINT5_PORT PORTA
-#define PCINT5_BIT 5
-
-#define INT2_PORT PORTA
-#define INT2_BIT 6
-#define PCINT6_PORT PORTA
-#define PCINT6_BIT 6
-
-#define INT3_PORT PORTA
-#define INT3_BIT 7
-#define PCINT7_PORT PORTA
-#define PCINT7_BIT 7
-
-#define TDO_PORT PORTB
-#define TDO_BIT 0
-#define PCINT8_PORT PORTB
-#define PCINT8_BIT 0
-
-#define TDI_PORT PORTB
-#define TDI_BIT 1
-#define PCINT9_PORT PORTB
-#define PCINT9_BIT 1
-
-#define TMS_PORT PORTB
-#define TMS_BIT 2
-#define PCINT10_PORT PORTB
-#define PCINT10_BIT 2
-
-#define TCK_PORT PORTB
-#define TCK_BIT 3
-#define PCINT11_PORT PORTB
-#define PCINT11_BIT 3
-
-#define PCINT12_PORT PORTB
-#define PCINT12_BIT 4
-
-#define PCINT13_PORT PORTB
-#define PCINT13_BIT 5
-
-#define OC0A_PORT PORTB
-#define OC0A_BIT 6
-#define PCINT14_PORT PORTB
-#define PCINT14_BIT 6
-
-#define OC0B_PORT PORTB
-#define OC0B_BIT 7
-#define PCINT15_PORT PORTB
-#define PCINT15_BIT 7
-
-
-#define T0_PORT PORTD
-#define T0_BIT 0
-
-
-
-
-
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-#define TIMER2A_AVAILABLE
-#define TIMER2B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE2A_NUM 4
-#define SIG_OUTPUT_COMPARE2B_NUM 5
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 6
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM2A_NUM 4
-#define PWM2B_NUM 5
-#define PWM_TOTAL_NUM 6
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* OCR2B */
-#define OCR2B_0_REG OCR2B
-#define OCR2B_1_REG OCR2B
-#define OCR2B_2_REG OCR2B
-#define OCR2B_3_REG OCR2B
-#define OCR2B_4_REG OCR2B
-#define OCR2B_5_REG OCR2B
-#define OCR2B_6_REG OCR2B
-#define OCR2B_7_REG OCR2B
-
-/* OCR2A */
-#define OCR2A_0_REG OCR2A
-#define OCR2A_1_REG OCR2A
-#define OCR2A_2_REG OCR2A
-#define OCR2A_3_REG OCR2A
-#define OCR2A_4_REG OCR2A
-#define OCR2A_5_REG OCR2A
-#define OCR2A_6_REG OCR2A
-#define OCR2A_7_REG OCR2A
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSART0_REG PRR
-#define PRSPI_REG PRR
-#define PRTIM1_REG PRR
-#define PRTIM0_REG PRR
-#define PRTIM2_REG PRR
-#define PRTWI_REG PRR
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-
-/* UDR0 */
-#define UDR0_0_REG UDR0
-#define UDR0_1_REG UDR0
-#define UDR0_2_REG UDR0
-#define UDR0_3_REG UDR0
-#define UDR0_4_REG UDR0
-#define UDR0_5_REG UDR0
-#define UDR0_6_REG UDR0
-#define UDR0_7_REG UDR0
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* ASSR */
-#define TCR2BUB_REG ASSR
-#define TCR2AUB_REG ASSR
-#define OCR2BUB_REG ASSR
-#define OCR2AUB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* PCICR */
-#define PCIE0_REG PCICR
-#define PCIE1_REG PCICR
-#define PCIE2_REG PCICR
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-#define OCF2B_REG TIFR2
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* GTCCR */
-#define PSRSYNC_REG GTCCR
-#define TSM_REG GTCCR
-#define PSRASY_REG GTCCR
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* PCIFR */
-#define PCIF0_REG PCIFR
-#define PCIF1_REG PCIFR
-#define PCIF2_REG PCIFR
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* TCCR2A */
-#define WGM20_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2B0_REG TCCR2A
-#define COM2B1_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-
-/* TCCR2B */
-#define CS20_REG TCCR2B
-#define CS21_REG TCCR2B
-#define CS22_REG TCCR2B
-#define WGM22_REG TCCR2B
-#define FOC2B_REG TCCR2B
-#define FOC2A_REG TCCR2B
-
-/* UBRR0H */
-#define UBRR8_REG UBRR0H
-#define UBRR9_REG UBRR0H
-#define UBRR10_REG UBRR0H
-#define UBRR11_REG UBRR0H
-
-/* UBRR0L */
-#define UBRR0_REG UBRR0L
-#define UBRR1_REG UBRR0L
-#define UBRR2_REG UBRR0L
-#define UBRR3_REG UBRR0L
-#define UBRR4_REG UBRR0L
-#define UBRR5_REG UBRR0L
-#define UBRR6_REG UBRR0L
-#define UBRR7_REG UBRR0L
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* MCUCR */
-#define PUD_REG MCUCR
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ACME_REG ADCSRB
-
-/* OCR0A */
-#define OCROA_0_REG OCR0A
-#define OCROA_1_REG OCR0A
-#define OCROA_2_REG OCR0A
-#define OCROA_3_REG OCR0A
-#define OCROA_4_REG OCR0A
-#define OCROA_5_REG OCR0A
-#define OCROA_6_REG OCR0A
-#define OCROA_7_REG OCR0A
-
-/* OCR0B */
-#define OCR0B_0_REG OCR0B
-#define OCR0B_1_REG OCR0B
-#define OCR0B_2_REG OCR0B
-#define OCR0B_3_REG OCR0B
-#define OCR0B_4_REG OCR0B
-#define OCR0B_5_REG OCR0B
-#define OCR0B_6_REG OCR0B
-#define OCR0B_7_REG OCR0B
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL00_REG UCSR0C
-#define UMSEL01_REG UCSR0C
-
-/* SPMCSR */
-#define SELFPRGEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-#define OCIE2B_REG TIMSK2
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-
-/* PCMSK2 */
-#define PCINT16_REG PCMSK2
-#define PCINT17_REG PCMSK2
-#define PCINT18_REG PCMSK2
-#define PCINT19_REG PCMSK2
-#define PCINT20_REG PCMSK2
-#define PCINT21_REG PCMSK2
-#define PCINT22_REG PCMSK2
-#define PCINT23_REG PCMSK2
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* TWAMR */
-#define TWAM0_REG TWAMR
-#define TWAM1_REG TWAMR
-#define TWAM2_REG TWAMR
-#define TWAM3_REG TWAMR
-#define TWAM4_REG TWAMR
-#define TWAM5_REG TWAMR
-#define TWAM6_REG TWAMR
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* pins mapping */
-#define ICP1_PORT PORTB
-#define ICP1_BIT 0
-#define CLKO_PORT PORTB
-#define CLKO_BIT 0
-#define PCINT0_PORT PORTB
-#define PCINT0_BIT 0
-
-#define OC1A_PORT PORTB
-#define OC1A_BIT 1
-#define PCINT1_PORT PORTB
-#define PCINT1_BIT 1
-
-#define SS_PORT PORTB
-#define SS_BIT 2
-#define OC1B_PORT PORTB
-#define OC1B_BIT 2
-#define PCINT2_PORT PORTB
-#define PCINT2_BIT 2
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 3
-#define OC2A_PORT PORTB
-#define OC2A_BIT 3
-#define PCINT3_PORT PORTB
-#define PCINT3_BIT 3
-
-#define MISO_PORT PORTB
-#define MISO_BIT 4
-#define PCINT4_PORT PORTB
-#define PCINT4_BIT 4
-
-#define SCK_PORT PORTB
-#define SCK_BIT 5
-#define PCINT5_PORT PORTB
-#define PCINT5_BIT 5
-
-#define XTAL1_PORT PORTB
-#define XTAL1_BIT 6
-#define TOSC1_PORT PORTB
-#define TOSC1_BIT 6
-#define PCINT6_PORT PORTB
-#define PCINT6_BIT 6
-
-#define XTAL2_PORT PORTB
-#define XTAL2_BIT 7
-#define TOSC2_PORT PORTB
-#define TOSC2_BIT 7
-#define PCINT7_PORT PORTB
-#define PCINT7_BIT 7
-
-#define ADC0_PORT PORTC
-#define ADC0_BIT 0
-#define PCINT8_PORT PORTC
-#define PCINT8_BIT 0
-
-#define ADC1_PORT PORTC
-#define ADC1_BIT 1
-#define PCINT9_PORT PORTC
-#define PCINT9_BIT 1
-
-#define ADC2_PORT PORTC
-#define ADC2_BIT 2
-#define PCINT10_PORT PORTC
-#define PCINT10_BIT 2
-
-#define ADC3_PORT PORTC
-#define ADC3_BIT 3
-#define PCINT11_PORT PORTC
-#define PCINT11_BIT 3
-
-#define ADC4_PORT PORTC
-#define ADC4_BIT 4
-#define SDA_PORT PORTC
-#define SDA_BIT 4
-#define PCINT12_PORT PORTC
-#define PCINT12_BIT 4
-
-#define ADC5_PORT PORTC
-#define ADC5_BIT 5
-#define SCL_PORT PORTC
-#define SCL_BIT 5
-#define PCINT13_PORT PORTC
-#define PCINT13_BIT 5
-
-#define RESET_PORT PORTC
-#define RESET_BIT 6
-#define PCINT14_PORT PORTC
-#define PCINT14_BIT 6
-
-#define RXD_PORT PORTD
-#define RXD_BIT 0
-#define PCINT16_PORT PORTD
-#define PCINT16_BIT 0
-
-#define TXD_PORT PORTD
-#define TXD_BIT 1
-#define PCINT17_PORT PORTD
-#define PCINT17_BIT 1
-
-#define INT0_PORT PORTD
-#define INT0_BIT 2
-#define PCINT18_PORT PORTD
-#define PCINT18_BIT 2
-
-#define PCINT19_PORT PORTD
-#define PCINT19_BIT 3
-#define OC2B_PORT PORTD
-#define OC2B_BIT 3
-#define INT1_PORT PORTD
-#define INT1_BIT 3
-
-#define XCK_PORT PORTD
-#define XCK_BIT 4
-#define T0_PORT PORTD
-#define T0_BIT 4
-#define PCINT20_PORT PORTD
-#define PCINT20_BIT 4
-
-#define T1_PORT PORTD
-#define T1_BIT 5
-#define OC0B_PORT PORTD
-#define OC0B_BIT 5
-#define PCINT21_PORT PORTD
-#define PCINT21_BIT 5
-
-#define AIN0_PORT PORTD
-#define AIN0_BIT 6
-#define OC0A_PORT PORTD
-#define OC0A_BIT 6
-#define PCINT22_PORT PORTD
-#define PCINT22_BIT 6
-
-#define AIN1_PORT PORTD
-#define AIN1_BIT 7
-#define PCINT23_PORT PORTD
-#define PCINT23_BIT 7
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-#define TIMER2A_AVAILABLE
-#define TIMER2B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE2A_NUM 4
-#define SIG_OUTPUT_COMPARE2B_NUM 5
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 6
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM2A_NUM 4
-#define PWM2B_NUM 5
-#define PWM_TOTAL_NUM 6
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* OCR2B */
-#define OCR2B_0_REG OCR2B
-#define OCR2B_1_REG OCR2B
-#define OCR2B_2_REG OCR2B
-#define OCR2B_3_REG OCR2B
-#define OCR2B_4_REG OCR2B
-#define OCR2B_5_REG OCR2B
-#define OCR2B_6_REG OCR2B
-#define OCR2B_7_REG OCR2B
-
-/* OCR2A */
-#define OCR2A_0_REG OCR2A
-#define OCR2A_1_REG OCR2A
-#define OCR2A_2_REG OCR2A
-#define OCR2A_3_REG OCR2A
-#define OCR2A_4_REG OCR2A
-#define OCR2A_5_REG OCR2A
-#define OCR2A_6_REG OCR2A
-#define OCR2A_7_REG OCR2A
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSART0_REG PRR
-#define PRSPI_REG PRR
-#define PRTIM1_REG PRR
-#define PRTIM0_REG PRR
-#define PRTIM2_REG PRR
-#define PRTWI_REG PRR
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-
-/* UDR0 */
-#define UDR0_0_REG UDR0
-#define UDR0_1_REG UDR0
-#define UDR0_2_REG UDR0
-#define UDR0_3_REG UDR0
-#define UDR0_4_REG UDR0
-#define UDR0_5_REG UDR0
-#define UDR0_6_REG UDR0
-#define UDR0_7_REG UDR0
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* ASSR */
-#define TCR2BUB_REG ASSR
-#define TCR2AUB_REG ASSR
-#define OCR2BUB_REG ASSR
-#define OCR2AUB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* PCICR */
-#define PCIE0_REG PCICR
-#define PCIE1_REG PCICR
-#define PCIE2_REG PCICR
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-#define OCF2B_REG TIFR2
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* GTCCR */
-#define PSRSYNC_REG GTCCR
-#define TSM_REG GTCCR
-#define PSRASY_REG GTCCR
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* PCIFR */
-#define PCIF0_REG PCIFR
-#define PCIF1_REG PCIFR
-#define PCIF2_REG PCIFR
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* TCCR2A */
-#define WGM20_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2B0_REG TCCR2A
-#define COM2B1_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-
-/* TCCR2B */
-#define CS20_REG TCCR2B
-#define CS21_REG TCCR2B
-#define CS22_REG TCCR2B
-#define WGM22_REG TCCR2B
-#define FOC2B_REG TCCR2B
-#define FOC2A_REG TCCR2B
-
-/* UBRR0H */
-#define UBRR8_REG UBRR0H
-#define UBRR9_REG UBRR0H
-#define UBRR10_REG UBRR0H
-#define UBRR11_REG UBRR0H
-
-/* UBRR0L */
-#define UBRR0_REG UBRR0L
-#define UBRR1_REG UBRR0L
-#define UBRR2_REG UBRR0L
-#define UBRR3_REG UBRR0L
-#define UBRR4_REG UBRR0L
-#define UBRR5_REG UBRR0L
-#define UBRR6_REG UBRR0L
-#define UBRR7_REG UBRR0L
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* MCUCR */
-#define PUD_REG MCUCR
-#define BODSE_REG MCUCR
-#define BODS_REG MCUCR
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ACME_REG ADCSRB
-
-/* OCR0A */
-#define OCROA_0_REG OCR0A
-#define OCROA_1_REG OCR0A
-#define OCROA_2_REG OCR0A
-#define OCROA_3_REG OCR0A
-#define OCROA_4_REG OCR0A
-#define OCROA_5_REG OCR0A
-#define OCROA_6_REG OCR0A
-#define OCROA_7_REG OCR0A
-
-/* OCR0B */
-#define OCR0B_0_REG OCR0B
-#define OCR0B_1_REG OCR0B
-#define OCR0B_2_REG OCR0B
-#define OCR0B_3_REG OCR0B
-#define OCR0B_4_REG OCR0B
-#define OCR0B_5_REG OCR0B
-#define OCR0B_6_REG OCR0B
-#define OCR0B_7_REG OCR0B
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL00_REG UCSR0C
-#define UMSEL01_REG UCSR0C
-
-/* SPMCSR */
-#define SELFPRGEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-#define OCIE2B_REG TIMSK2
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-
-/* PCMSK2 */
-#define PCINT16_REG PCMSK2
-#define PCINT17_REG PCMSK2
-#define PCINT18_REG PCMSK2
-#define PCINT19_REG PCMSK2
-#define PCINT20_REG PCMSK2
-#define PCINT21_REG PCMSK2
-#define PCINT22_REG PCMSK2
-#define PCINT23_REG PCMSK2
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* TWAMR */
-#define TWAM0_REG TWAMR
-#define TWAM1_REG TWAMR
-#define TWAM2_REG TWAMR
-#define TWAM3_REG TWAMR
-#define TWAM4_REG TWAMR
-#define TWAM5_REG TWAMR
-#define TWAM6_REG TWAMR
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* pins mapping */
-#define ICP1_PORT PORTB
-#define ICP1_BIT 0
-#define CLKO_PORT PORTB
-#define CLKO_BIT 0
-#define PCINT0_PORT PORTB
-#define PCINT0_BIT 0
-
-#define OC1A_PORT PORTB
-#define OC1A_BIT 1
-#define PCINT1_PORT PORTB
-#define PCINT1_BIT 1
-
-#define SS_PORT PORTB
-#define SS_BIT 2
-#define OC1B_PORT PORTB
-#define OC1B_BIT 2
-#define PCINT2_PORT PORTB
-#define PCINT2_BIT 2
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 3
-#define OC2A_PORT PORTB
-#define OC2A_BIT 3
-#define PCINT3_PORT PORTB
-#define PCINT3_BIT 3
-
-#define MISO_PORT PORTB
-#define MISO_BIT 4
-#define PCINT4_PORT PORTB
-#define PCINT4_BIT 4
-
-#define SCK_PORT PORTB
-#define SCK_BIT 5
-#define PCINT5_PORT PORTB
-#define PCINT5_BIT 5
-
-#define XTAL1_PORT PORTB
-#define XTAL1_BIT 6
-#define TOSC1_PORT PORTB
-#define TOSC1_BIT 6
-#define PCINT6_PORT PORTB
-#define PCINT6_BIT 6
-
-#define XTAL2_PORT PORTB
-#define XTAL2_BIT 7
-#define TOSC2_PORT PORTB
-#define TOSC2_BIT 7
-#define PCINT7_PORT PORTB
-#define PCINT7_BIT 7
-
-#define ADC0_PORT PORTC
-#define ADC0_BIT 0
-#define PCINT8_PORT PORTC
-#define PCINT8_BIT 0
-
-#define ADC1_PORT PORTC
-#define ADC1_BIT 1
-#define PCINT9_PORT PORTC
-#define PCINT9_BIT 1
-
-#define ADC2_PORT PORTC
-#define ADC2_BIT 2
-#define PCINT10_PORT PORTC
-#define PCINT10_BIT 2
-
-#define ADC3_PORT PORTC
-#define ADC3_BIT 3
-#define PCINT11_PORT PORTC
-#define PCINT11_BIT 3
-
-#define ADC4_PORT PORTC
-#define ADC4_BIT 4
-#define SDA_PORT PORTC
-#define SDA_BIT 4
-#define PCINT12_PORT PORTC
-#define PCINT12_BIT 4
-
-#define ADC5_PORT PORTC
-#define ADC5_BIT 5
-#define SCL_PORT PORTC
-#define SCL_BIT 5
-#define PCINT13_PORT PORTC
-#define PCINT13_BIT 5
-
-#define RESET_PORT PORTC
-#define RESET_BIT 6
-#define PCINT14_PORT PORTC
-#define PCINT14_BIT 6
-
-#define RXD_PORT PORTD
-#define RXD_BIT 0
-#define PCINT16_PORT PORTD
-#define PCINT16_BIT 0
-
-#define TXD_PORT PORTD
-#define TXD_BIT 1
-#define PCINT17_PORT PORTD
-#define PCINT17_BIT 1
-
-#define INT0_PORT PORTD
-#define INT0_BIT 2
-#define PCINT18_PORT PORTD
-#define PCINT18_BIT 2
-
-#define PCINT19_PORT PORTD
-#define PCINT19_BIT 3
-#define OC2B_PORT PORTD
-#define OC2B_BIT 3
-#define INT1_PORT PORTD
-#define INT1_BIT 3
-
-#define XCK_PORT PORTD
-#define XCK_BIT 4
-#define T0_PORT PORTD
-#define T0_BIT 4
-#define PCINT20_PORT PORTD
-#define PCINT20_BIT 4
-
-#define T1_PORT PORTD
-#define T1_BIT 5
-#define OC0B_PORT PORTD
-#define OC0B_BIT 5
-#define PCINT21_PORT PORTD
-#define PCINT21_BIT 5
-
-#define AIN0_PORT PORTD
-#define AIN0_BIT 6
-#define OC0A_PORT PORTD
-#define OC0A_BIT 6
-#define PCINT22_PORT PORTD
-#define PCINT22_BIT 6
-
-#define AIN1_PORT PORTD
-#define AIN1_BIT 7
-#define PCINT23_PORT PORTD
-#define PCINT23_BIT 7
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_32 3
-#define TIMER0_PRESCALER_DIV_64 4
-#define TIMER0_PRESCALER_DIV_128 5
-#define TIMER0_PRESCALER_DIV_256 6
-#define TIMER0_PRESCALER_DIV_1024 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 32
-#define TIMER0_PRESCALER_REG_4 64
-#define TIMER0_PRESCALER_REG_5 128
-#define TIMER0_PRESCALER_REG_6 256
-#define TIMER0_PRESCALER_REG_7 1024
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_64 3
-#define TIMER2_PRESCALER_DIV_256 4
-#define TIMER2_PRESCALER_DIV_1024 5
-#define TIMER2_PRESCALER_DIV_FALL 6
-#define TIMER2_PRESCALER_DIV_RISE 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 64
-#define TIMER2_PRESCALER_REG_4 256
-#define TIMER2_PRESCALER_REG_5 1024
-#define TIMER2_PRESCALER_REG_6 -1
-#define TIMER2_PRESCALER_REG_7 -2
-
-/* prescalers timer 3 */
-#define TIMER3_PRESCALER_DIV_0 0
-#define TIMER3_PRESCALER_DIV_1 1
-#define TIMER3_PRESCALER_DIV_8 2
-#define TIMER3_PRESCALER_DIV_64 3
-#define TIMER3_PRESCALER_DIV_256 4
-#define TIMER3_PRESCALER_DIV_1024 5
-#define TIMER3_PRESCALER_DIV_FALL 6
-#define TIMER3_PRESCALER_DIV_RISE 7
-
-#define TIMER3_PRESCALER_REG_0 0
-#define TIMER3_PRESCALER_REG_1 1
-#define TIMER3_PRESCALER_REG_2 8
-#define TIMER3_PRESCALER_REG_3 64
-#define TIMER3_PRESCALER_REG_4 256
-#define TIMER3_PRESCALER_REG_5 1024
-#define TIMER3_PRESCALER_REG_6 -1
-#define TIMER3_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER1C_AVAILABLE
-#define TIMER2_AVAILABLE
-#define TIMER3_AVAILABLE
-#define TIMER3A_AVAILABLE
-#define TIMER3B_AVAILABLE
-#define TIMER3C_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW3_NUM 3
-#define SIG_OVERFLOW_TOTAL_NUM 4
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE1A_NUM 1
-#define SIG_OUTPUT_COMPARE1B_NUM 2
-#define SIG_OUTPUT_COMPARE1C_NUM 3
-#define SIG_OUTPUT_COMPARE2_NUM 4
-#define SIG_OUTPUT_COMPARE3A_NUM 5
-#define SIG_OUTPUT_COMPARE3B_NUM 6
-#define SIG_OUTPUT_COMPARE3C_NUM 7
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 8
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM1A_NUM 1
-#define PWM1B_NUM 2
-#define PWM1C_NUM 3
-#define PWM2_NUM 4
-#define PWM3A_NUM 5
-#define PWM3B_NUM 6
-#define PWM3C_NUM 7
-#define PWM_TOTAL_NUM 8
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE3_NUM 1
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 2
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTG */
-#define PORTG0_REG PORTG
-#define PORTG1_REG PORTG
-#define PORTG2_REG PORTG
-#define PORTG3_REG PORTG
-#define PORTG4_REG PORTG
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL0_REG UCSR0C
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* UDR1 */
-#define UDR10_REG UDR1
-#define UDR11_REG UDR1
-#define UDR12_REG UDR1
-#define UDR13_REG UDR1
-#define UDR14_REG UDR1
-#define UDR15_REG UDR1
-#define UDR16_REG UDR1
-#define UDR17_REG UDR1
-
-/* UDR0 */
-#define UDR00_REG UDR0
-#define UDR01_REG UDR0
-#define UDR02_REG UDR0
-#define UDR03_REG UDR0
-#define UDR04_REG UDR0
-#define UDR05_REG UDR0
-#define UDR06_REG UDR0
-#define UDR07_REG UDR0
-
-/* EICRB */
-#define ISC40_REG EICRB
-#define ISC41_REG EICRB
-#define ISC50_REG EICRB
-#define ISC51_REG EICRB
-#define ISC60_REG EICRB
-#define ISC61_REG EICRB
-#define ISC70_REG EICRB
-#define ISC71_REG EICRB
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-#define ISC20_REG EICRA
-#define ISC21_REG EICRA
-#define ISC30_REG EICRA
-#define ISC31_REG EICRA
-
-/* ASSR */
-#define TCR0UB_REG ASSR
-#define OCR0UB_REG ASSR
-#define TCN0UB_REG ASSR
-#define AS0_REG ASSR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* UBRR1L */
-/* #define UBRR0_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR1_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR2_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR3_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR4_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR5_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR6_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR7_REG UBRR1L */ /* dup in UBRR0L */
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* OCR3AL */
-#define OCR3AL0_REG OCR3AL
-#define OCR3AL1_REG OCR3AL
-#define OCR3AL2_REG OCR3AL
-#define OCR3AL3_REG OCR3AL
-#define OCR3AL4_REG OCR3AL
-#define OCR3AL5_REG OCR3AL
-#define OCR3AL6_REG OCR3AL
-#define OCR3AL7_REG OCR3AL
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* DDRF */
-#define DDF0_REG DDRF
-#define DDF1_REG DDRF
-#define DDF2_REG DDRF
-#define DDF3_REG DDRF
-#define DDF4_REG DDRF
-#define DDF5_REG DDRF
-#define DDF6_REG DDRF
-#define DDF7_REG DDRF
-
-/* DDRG */
-#define DDG0_REG DDRG
-#define DDG1_REG DDRG
-#define DDG2_REG DDRG
-#define DDG3_REG DDRG
-#define DDG4_REG DDRG
-
-/* OCR3AH */
-#define OCR3AH0_REG OCR3AH
-#define OCR3AH1_REG OCR3AH
-#define OCR3AH2_REG OCR3AH
-#define OCR3AH3_REG OCR3AH
-#define OCR3AH4_REG OCR3AH
-#define OCR3AH5_REG OCR3AH
-#define OCR3AH6_REG OCR3AH
-#define OCR3AH7_REG OCR3AH
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* SFIOR */
-#define ACME_REG SFIOR
-#define PSR321_REG SFIOR
-#define PSR0_REG SFIOR
-#define PUD_REG SFIOR
-#define TSM_REG SFIOR
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* UBRR1H */
-/* #define UBRR8_REG UBRR1H */ /* dup in UBRR0H */
-/* #define UBRR9_REG UBRR1H */ /* dup in UBRR0H */
-/* #define UBRR10_REG UBRR1H */ /* dup in UBRR0H */
-/* #define UBRR11_REG UBRR1H */ /* dup in UBRR0H */
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* TIFR */
-#define TOV0_REG TIFR
-#define OCF0_REG TIFR
-#define TOV1_REG TIFR
-#define OCF1B_REG TIFR
-#define OCF1A_REG TIFR
-#define ICF1_REG TIFR
-#define TOV2_REG TIFR
-#define OCF2_REG TIFR
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* ETIFR */
-#define OCF1C_REG ETIFR
-#define OCF3C_REG ETIFR
-#define TOV3_REG ETIFR
-#define OCF3B_REG ETIFR
-#define OCF3A_REG ETIFR
-#define ICF3_REG ETIFR
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* XDIV */
-#define XDIV0_REG XDIV
-#define XDIV1_REG XDIV
-#define XDIV2_REG XDIV
-#define XDIV3_REG XDIV
-#define XDIV4_REG XDIV
-#define XDIV5_REG XDIV
-#define XDIV6_REG XDIV
-#define XDIVEN_REG XDIV
-
-/* OCR3CH */
-#define OCR3CH0_REG OCR3CH
-#define OCR3CH1_REG OCR3CH
-#define OCR3CH2_REG OCR3CH
-#define OCR3CH3_REG OCR3CH
-#define OCR3CH4_REG OCR3CH
-#define OCR3CH5_REG OCR3CH
-#define OCR3CH6_REG OCR3CH
-#define OCR3CH7_REG OCR3CH
-
-/* ETIMSK */
-#define OCIE1C_REG ETIMSK
-#define OCIE3C_REG ETIMSK
-#define TOIE3_REG ETIMSK
-#define OCIE3B_REG ETIMSK
-#define OCIE3A_REG ETIMSK
-#define TICIE3_REG ETIMSK
-
-/* OCR3CL */
-#define OCR3CL0_REG OCR3CL
-#define OCR3CL1_REG OCR3CL
-#define OCR3CL2_REG OCR3CL
-#define OCR3CL3_REG OCR3CL
-#define OCR3CL4_REG OCR3CL
-#define OCR3CL5_REG OCR3CL
-#define OCR3CL6_REG OCR3CL
-#define OCR3CL7_REG OCR3CL
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* TCCR3C */
-#define FOC3C_REG TCCR3C
-#define FOC3B_REG TCCR3C
-#define FOC3A_REG TCCR3C
-
-/* TCCR3B */
-#define CS30_REG TCCR3B
-#define CS31_REG TCCR3B
-#define CS32_REG TCCR3B
-#define WGM32_REG TCCR3B
-#define WGM33_REG TCCR3B
-#define ICES3_REG TCCR3B
-#define ICNC3_REG TCCR3B
-
-/* TCCR3A */
-#define WGM30_REG TCCR3A
-#define WGM31_REG TCCR3A
-#define COM3C0_REG TCCR3A
-#define COM3C1_REG TCCR3A
-#define COM3B0_REG TCCR3A
-#define COM3B1_REG TCCR3A
-#define COM3A0_REG TCCR3A
-#define COM3A1_REG TCCR3A
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* TCNT3H */
-#define TCNT3H0_REG TCNT3H
-#define TCNT3H1_REG TCNT3H
-#define TCNT3H2_REG TCNT3H
-#define TCNT3H3_REG TCNT3H
-#define TCNT3H4_REG TCNT3H
-#define TCNT3H5_REG TCNT3H
-#define TCNT3H6_REG TCNT3H
-#define TCNT3H7_REG TCNT3H
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* TCNT3L */
-#define TCN3L0_REG TCNT3L
-#define TCN3L1_REG TCNT3L
-#define TCN3L2_REG TCNT3L
-#define TCN3L3_REG TCNT3L
-#define TCN3L4_REG TCNT3L
-#define TCN3L5_REG TCNT3L
-#define TCN3L6_REG TCNT3L
-#define TCN3L7_REG TCNT3L
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* MCUCSR */
-#define PORF_REG MCUCSR
-#define EXTRF_REG MCUCSR
-#define BORF_REG MCUCSR
-#define WDRF_REG MCUCSR
-#define JTRF_REG MCUCSR
-#define JTD_REG MCUCSR
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* UBRR0H */
-/* #define UBRR8_REG UBRR0H */ /* dup in UBRR1H */
-/* #define UBRR9_REG UBRR0H */ /* dup in UBRR1H */
-/* #define UBRR10_REG UBRR0H */ /* dup in UBRR1H */
-/* #define UBRR11_REG UBRR0H */ /* dup in UBRR1H */
-
-/* UBRR0L */
-/* #define UBRR0_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR1_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR2_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR3_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR4_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR5_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR6_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR7_REG UBRR0L */ /* dup in UBRR1L */
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-#define EEAR10_REG EEARH
-
-/* EEARL */
-#define EEARL0_REG EEARL
-#define EEARL1_REG EEARL
-#define EEARL2_REG EEARL
-#define EEARL3_REG EEARL
-#define EEARL4_REG EEARL
-#define EEARL5_REG EEARL
-#define EEARL6_REG EEARL
-#define EEARL7_REG EEARL
-
-/* MCUCR */
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define SM2_REG MCUCR
-#define SM0_REG MCUCR
-#define SM1_REG MCUCR
-#define SE_REG MCUCR
-#define SRW10_REG MCUCR
-#define SRE_REG MCUCR
-
-/* OCR1CL */
-#define OCR1CL0_REG OCR1CL
-#define OCR1CL1_REG OCR1CL
-#define OCR1CL2_REG OCR1CL
-#define OCR1CL3_REG OCR1CL
-#define OCR1CL4_REG OCR1CL
-#define OCR1CL5_REG OCR1CL
-#define OCR1CL6_REG OCR1CL
-#define OCR1CL7_REG OCR1CL
-
-/* OCR1CH */
-#define OCR1CH0_REG OCR1CH
-#define OCR1CH1_REG OCR1CH
-#define OCR1CH2_REG OCR1CH
-#define OCR1CH3_REG OCR1CH
-#define OCR1CH4_REG OCR1CH
-#define OCR1CH5_REG OCR1CH
-#define OCR1CH6_REG OCR1CH
-#define OCR1CH7_REG OCR1CH
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-#define INTF2_REG EIFR
-#define INTF3_REG EIFR
-#define INTF4_REG EIFR
-#define INTF5_REG EIFR
-#define INTF6_REG EIFR
-#define INTF7_REG EIFR
-
-/* UCSR1B */
-#define TXB81_REG UCSR1B
-#define RXB81_REG UCSR1B
-#define UCSZ12_REG UCSR1B
-#define TXEN1_REG UCSR1B
-#define RXEN1_REG UCSR1B
-#define UDRIE1_REG UCSR1B
-#define TXCIE1_REG UCSR1B
-#define RXCIE1_REG UCSR1B
-
-/* UCSR1C */
-#define UCPOL1_REG UCSR1C
-#define UCSZ10_REG UCSR1C
-#define UCSZ11_REG UCSR1C
-#define USBS1_REG UCSR1C
-#define UPM10_REG UCSR1C
-#define UPM11_REG UCSR1C
-#define UMSEL1_REG UCSR1C
-
-/* UCSR1A */
-#define MPCM1_REG UCSR1A
-#define U2X1_REG UCSR1A
-#define UPE1_REG UCSR1A
-#define DOR1_REG UCSR1A
-#define FE1_REG UCSR1A
-#define UDRE1_REG UCSR1A
-#define TXC1_REG UCSR1A
-#define RXC1_REG UCSR1A
-
-/* TCCR0 */
-#define CS00_REG TCCR0
-#define CS01_REG TCCR0
-#define CS02_REG TCCR0
-#define WGM01_REG TCCR0
-#define COM00_REG TCCR0
-#define COM01_REG TCCR0
-#define WGM00_REG TCCR0
-#define FOC0_REG TCCR0
-
-/* TCCR2 */
-#define CS20_REG TCCR2
-#define CS21_REG TCCR2
-#define CS22_REG TCCR2
-#define WGM21_REG TCCR2
-#define COM20_REG TCCR2
-#define COM21_REG TCCR2
-#define WGM20_REG TCCR2
-#define FOC2_REG TCCR2
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* TIMSK */
-#define TOIE0_REG TIMSK
-#define OCIE0_REG TIMSK
-#define TOIE1_REG TIMSK
-#define OCIE1B_REG TIMSK
-#define OCIE1A_REG TIMSK
-#define TICIE1_REG TIMSK
-#define TOIE2_REG TIMSK
-#define OCIE2_REG TIMSK
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-#define INT3_REG EIMSK
-#define INT4_REG EIMSK
-#define INT5_REG EIMSK
-#define INT6_REG EIMSK
-#define INT7_REG EIMSK
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1C0_REG TCCR1A
-#define COM1C1_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* PORTF */
-#define PORTF0_REG PORTF
-#define PORTF1_REG PORTF
-#define PORTF2_REG PORTF
-#define PORTF3_REG PORTF
-#define PORTF4_REG PORTF
-#define PORTF5_REG PORTF
-#define PORTF6_REG PORTF
-#define PORTF7_REG PORTF
-
-/* TCCR1C */
-#define FOC1C_REG TCCR1C
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* ICR3H */
-#define ICR3H0_REG ICR3H
-#define ICR3H1_REG ICR3H
-#define ICR3H2_REG ICR3H
-#define ICR3H3_REG ICR3H
-#define ICR3H4_REG ICR3H
-#define ICR3H5_REG ICR3H
-#define ICR3H6_REG ICR3H
-#define ICR3H7_REG ICR3H
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-#define DDE3_REG DDRE
-#define DDE4_REG DDRE
-#define DDE5_REG DDRE
-#define DDE6_REG DDRE
-#define DDE7_REG DDRE
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* ICR3L */
-#define ICR3L0_REG ICR3L
-#define ICR3L1_REG ICR3L
-#define ICR3L2_REG ICR3L
-#define ICR3L3_REG ICR3L
-#define ICR3L4_REG ICR3L
-#define ICR3L5_REG ICR3L
-#define ICR3L6_REG ICR3L
-#define ICR3L7_REG ICR3L
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-#define PORTE3_REG PORTE
-#define PORTE4_REG PORTE
-#define PORTE5_REG PORTE
-#define PORTE6_REG PORTE
-#define PORTE7_REG PORTE
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* OCR3BL */
-#define OCR3BL0_REG OCR3BL
-#define OCR3BL1_REG OCR3BL
-#define OCR3BL2_REG OCR3BL
-#define OCR3BL3_REG OCR3BL
-#define OCR3BL4_REG OCR3BL
-#define OCR3BL5_REG OCR3BL
-#define OCR3BL6_REG OCR3BL
-#define OCR3BL7_REG OCR3BL
-
-/* OCR3BH */
-#define OCR3BH0_REG OCR3BH
-#define OCR3BH1_REG OCR3BH
-#define OCR3BH2_REG OCR3BH
-#define OCR3BH3_REG OCR3BH
-#define OCR3BH4_REG OCR3BH
-#define OCR3BH5_REG OCR3BH
-#define OCR3BH6_REG OCR3BH
-#define OCR3BH7_REG OCR3BH
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* XMCRB */
-#define XMM0_REG XMCRB
-#define XMM1_REG XMCRB
-#define XMM2_REG XMCRB
-#define XMBK_REG XMCRB
-
-/* XMCRA */
-#define SRW11_REG XMCRA
-#define SRW00_REG XMCRA
-#define SRW01_REG XMCRA
-#define SRL0_REG XMCRA
-#define SRL1_REG XMCRA
-#define SRL2_REG XMCRA
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* PING */
-#define PING0_REG PING
-#define PING1_REG PING
-#define PING2_REG PING
-#define PING3_REG PING
-#define PING4_REG PING
-
-/* PINF */
-#define PINF0_REG PINF
-#define PINF1_REG PINF
-#define PINF2_REG PINF
-#define PINF3_REG PINF
-#define PINF4_REG PINF
-#define PINF5_REG PINF
-#define PINF6_REG PINF
-#define PINF7_REG PINF
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-#define PINE3_REG PINE
-#define PINE4_REG PINE
-#define PINE5_REG PINE
-#define PINE6_REG PINE
-#define PINE7_REG PINE
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* OCR0 */
-#define OCR0_0_REG OCR0
-#define OCR0_1_REG OCR0
-#define OCR0_2_REG OCR0
-#define OCR0_3_REG OCR0
-#define OCR0_4_REG OCR0
-#define OCR0_5_REG OCR0
-#define OCR0_6_REG OCR0
-#define OCR0_7_REG OCR0
-
-/* OCR2 */
-#define OCR2_0_REG OCR2
-#define OCR2_1_REG OCR2
-#define OCR2_2_REG OCR2
-#define OCR2_3_REG OCR2
-#define OCR2_4_REG OCR2
-#define OCR2_5_REG OCR2
-#define OCR2_6_REG OCR2
-#define OCR2_7_REG OCR2
-
-/* pins mapping */
-#define AD0_PORT PORTA
-#define AD0_BIT 0
-
-#define AD1_PORT PORTA
-#define AD1_BIT 1
-
-#define AD2_PORT PORTA
-#define AD2_BIT 2
-
-#define AD3_PORT PORTA
-#define AD3_BIT 3
-
-#define AD4_PORT PORTA
-#define AD4_BIT 4
-
-#define AD5_PORT PORTA
-#define AD5_BIT 5
-
-#define AD6_PORT PORTA
-#define AD6_BIT 6
-
-#define AD7_PORT PORTA
-#define AD7_BIT 7
-
-#define SS_PORT PORTB
-#define SS_BIT 0
-
-#define SCK_PORT PORTB
-#define SCK_BIT 1
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 2
-
-#define MISO_PORT PORTB
-#define MISO_BIT 3
-
-#define OC0_PORT PORTB
-#define OC0_BIT 4
-#define PWM0_PORT PORTB
-#define PWM0_BIT 4
-
-#define OC1A_PORT PORTB
-#define OC1A_BIT 5
-#define PWM1A_PORT PORTB
-#define PWM1A_BIT 5
-
-#define OC1B_PORT PORTB
-#define OC1B_BIT 6
-#define PWM1B_PORT PORTB
-#define PWM1B_BIT 6
-
-#define OC2_PORT PORTB
-#define OC2_BIT 7
-#define PWM2_PORT PORTB
-#define PWM2_BIT 7
-#define OC1C_PORT PORTB
-#define OC1C_BIT 7
-
-#define A8_PORT PORTC
-#define A8_BIT 0
-
-#define A9_PORT PORTC
-#define A9_BIT 1
-
-#define A10_PORT PORTC
-#define A10_BIT 2
-
-#define A11_PORT PORTC
-#define A11_BIT 3
-
-#define A12_PORT PORTC
-#define A12_BIT 4
-
-#define A13_PORT PORTC
-#define A13_BIT 5
-
-#define A14_PORT PORTC
-#define A14_BIT 6
-
-#define A15_PORT PORTC
-#define A15_BIT 7
-
-#define SCL_PORT PORTD
-#define SCL_BIT 0
-#define INT0_PORT PORTD
-#define INT0_BIT 0
-
-#define SDA_PORT PORTD
-#define SDA_BIT 1
-#define INT1_PORT PORTD
-#define INT1_BIT 1
-
-#define RXD1_PORT PORTD
-#define RXD1_BIT 2
-#define INT2_PORT PORTD
-#define INT2_BIT 2
-
-#define TXD1_PORT PORTD
-#define TXD1_BIT 3
-#define INT3_PORT PORTD
-#define INT3_BIT 3
-
-#define IC1_PORT PORTD
-#define IC1_BIT 4
-
-#define XCK1_PORT PORTD
-#define XCK1_BIT 5
-
-#define T1_PORT PORTD
-#define T1_BIT 6
-
-#define T2_PORT PORTD
-#define T2_BIT 7
-
-#define RXD0_PORT PORTE
-#define RXD0_BIT 0
-#define PDI_PORT PORTE
-#define PDI_BIT 0
-
-#define TXD0_PORT PORTE
-#define TXD0_BIT 1
-#define PDO_PORT PORTE
-#define PDO_BIT 1
-
-#define XCK0_PORT PORTE
-#define XCK0_BIT 2
-#define AIN0_PORT PORTE
-#define AIN0_BIT 2
-
-#define OC3A_PORT PORTE
-#define OC3A_BIT 3
-#define AIN1_PORT PORTE
-#define AIN1_BIT 3
-
-#define OC3B_PORT PORTE
-#define OC3B_BIT 4
-#define INT4_PORT PORTE
-#define INT4_BIT 4
-
-#define OC3C_PORT PORTE
-#define OC3C_BIT 5
-#define INT5_PORT PORTE
-#define INT5_BIT 5
-
-#define T3_PORT PORTE
-#define T3_BIT 6
-#define INT6_PORT PORTE
-#define INT6_BIT 6
-
-#define IC3_PORT PORTE
-#define IC3_BIT 7
-#define INT7_PORT PORTE
-#define INT7_BIT 7
-
-#define ADC0_PORT PORTF
-#define ADC0_BIT 0
-
-#define ADC1_PORT PORTF
-#define ADC1_BIT 1
-
-#define ADC2_PORT PORTF
-#define ADC2_BIT 2
-
-#define ADC3_PORT PORTF
-#define ADC3_BIT 3
-
-#define ADC4_PORT PORTF
-#define ADC4_BIT 4
-#define TCK_PORT PORTF
-#define TCK_BIT 4
-
-#define ADC5_PORT PORTF
-#define ADC5_BIT 5
-#define TMS_PORT PORTF
-#define TMS_BIT 5
-
-#define ADC6_PORT PORTF
-#define ADC6_BIT 6
-#define TD0_PORT PORTF
-#define TD0_BIT 6
-
-#define ADC7_PORT PORTF
-#define ADC7_BIT 7
-#define TDI_PORT PORTF
-#define TDI_BIT 7
-
-#define WR_PORT PORTG
-#define WR_BIT 0
-
-#define RD_PORT PORTG
-#define RD_BIT 1
-
-#define ALE_PORT PORTG
-#define ALE_BIT 2
-
-#define TOSC2_PORT PORTG
-#define TOSC2_BIT 3
-
-#define TOSC1_PORT PORTG
-#define TOSC1_BIT 4
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-/* prescalers timer 3 */
-#define TIMER3_PRESCALER_DIV_0 0
-#define TIMER3_PRESCALER_DIV_1 1
-#define TIMER3_PRESCALER_DIV_8 2
-#define TIMER3_PRESCALER_DIV_64 3
-#define TIMER3_PRESCALER_DIV_256 4
-#define TIMER3_PRESCALER_DIV_1024 5
-#define TIMER3_PRESCALER_DIV_FALL 6
-#define TIMER3_PRESCALER_DIV_RISE 7
-
-#define TIMER3_PRESCALER_REG_0 0
-#define TIMER3_PRESCALER_REG_1 1
-#define TIMER3_PRESCALER_REG_2 8
-#define TIMER3_PRESCALER_REG_3 64
-#define TIMER3_PRESCALER_REG_4 256
-#define TIMER3_PRESCALER_REG_5 1024
-#define TIMER3_PRESCALER_REG_6 -1
-#define TIMER3_PRESCALER_REG_7 -2
-
-/* prescalers timer 4 */
-#define TIMER4_PRESCALER_DIV_0 0
-#define TIMER4_PRESCALER_DIV_1 1
-#define TIMER4_PRESCALER_DIV_8 2
-#define TIMER4_PRESCALER_DIV_64 3
-#define TIMER4_PRESCALER_DIV_256 4
-#define TIMER4_PRESCALER_DIV_1024 5
-#define TIMER4_PRESCALER_DIV_FALL 6
-#define TIMER4_PRESCALER_DIV_RISE 7
-
-#define TIMER4_PRESCALER_REG_0 0
-#define TIMER4_PRESCALER_REG_1 1
-#define TIMER4_PRESCALER_REG_2 8
-#define TIMER4_PRESCALER_REG_3 64
-#define TIMER4_PRESCALER_REG_4 256
-#define TIMER4_PRESCALER_REG_5 1024
-#define TIMER4_PRESCALER_REG_6 -1
-#define TIMER4_PRESCALER_REG_7 -2
-
-/* prescalers timer 5 */
-#define TIMER5_PRESCALER_DIV_0 0
-#define TIMER5_PRESCALER_DIV_1 1
-#define TIMER5_PRESCALER_DIV_8 2
-#define TIMER5_PRESCALER_DIV_64 3
-#define TIMER5_PRESCALER_DIV_256 4
-#define TIMER5_PRESCALER_DIV_1024 5
-#define TIMER5_PRESCALER_DIV_FALL 6
-#define TIMER5_PRESCALER_DIV_RISE 7
-
-#define TIMER5_PRESCALER_REG_0 0
-#define TIMER5_PRESCALER_REG_1 1
-#define TIMER5_PRESCALER_REG_2 8
-#define TIMER5_PRESCALER_REG_3 64
-#define TIMER5_PRESCALER_REG_4 256
-#define TIMER5_PRESCALER_REG_5 1024
-#define TIMER5_PRESCALER_REG_6 -1
-#define TIMER5_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER1C_AVAILABLE
-#define TIMER2_AVAILABLE
-#define TIMER2A_AVAILABLE
-#define TIMER2B_AVAILABLE
-#define TIMER3_AVAILABLE
-#define TIMER3A_AVAILABLE
-#define TIMER3B_AVAILABLE
-#define TIMER3C_AVAILABLE
-#define TIMER4_AVAILABLE
-#define TIMER4A_AVAILABLE
-#define TIMER4B_AVAILABLE
-#define TIMER4C_AVAILABLE
-#define TIMER5_AVAILABLE
-#define TIMER5A_AVAILABLE
-#define TIMER5B_AVAILABLE
-#define TIMER5C_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW3_NUM 3
-#define SIG_OVERFLOW4_NUM 4
-#define SIG_OVERFLOW5_NUM 5
-#define SIG_OVERFLOW_TOTAL_NUM 6
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE1C_NUM 4
-#define SIG_OUTPUT_COMPARE2A_NUM 5
-#define SIG_OUTPUT_COMPARE2B_NUM 6
-#define SIG_OUTPUT_COMPARE3A_NUM 7
-#define SIG_OUTPUT_COMPARE3B_NUM 8
-#define SIG_OUTPUT_COMPARE3C_NUM 9
-#define SIG_OUTPUT_COMPARE4A_NUM 10
-#define SIG_OUTPUT_COMPARE4B_NUM 11
-#define SIG_OUTPUT_COMPARE4C_NUM 12
-#define SIG_OUTPUT_COMPARE5A_NUM 13
-#define SIG_OUTPUT_COMPARE5B_NUM 14
-#define SIG_OUTPUT_COMPARE5C_NUM 15
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 16
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM1C_NUM 4
-#define PWM2A_NUM 5
-#define PWM2B_NUM 6
-#define PWM3A_NUM 7
-#define PWM3B_NUM 8
-#define PWM3C_NUM 9
-#define PWM4A_NUM 10
-#define PWM4B_NUM 11
-#define PWM4C_NUM 12
-#define PWM5A_NUM 13
-#define PWM5B_NUM 14
-#define PWM5C_NUM 15
-#define PWM_TOTAL_NUM 16
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE3_NUM 1
-#define SIG_INPUT_CAPTURE4_NUM 2
-#define SIG_INPUT_CAPTURE5_NUM 3
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 4
-
-
-/* UBRR3H */
-/* #define UBRR8_REG UBRR3H */ /* dup in UBRR2H, UBRR0H */
-/* #define UBRR9_REG UBRR3H */ /* dup in UBRR2H, UBRR0H */
-/* #define UBRR10_REG UBRR3H */ /* dup in UBRR2H, UBRR0H */
-/* #define UBRR11_REG UBRR3H */ /* dup in UBRR2H, UBRR0H */
-
-/* UBRR3L */
-/* #define UBRR0_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */
-/* #define UBRR1_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */
-/* #define UBRR2_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */
-/* #define UBRR3_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */
-/* #define UBRR4_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */
-/* #define UBRR5_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */
-/* #define UBRR6_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */
-/* #define UBRR7_REG UBRR3L */ /* dup in UBRR2L, UBRR0L */
-
-/* OCR0A */
-#define OCROA_0_REG OCR0A
-#define OCROA_1_REG OCR0A
-#define OCROA_2_REG OCR0A
-#define OCROA_3_REG OCR0A
-#define OCROA_4_REG OCR0A
-#define OCROA_5_REG OCR0A
-#define OCROA_6_REG OCR0A
-#define OCROA_7_REG OCR0A
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* UCSR3A */
-#define MPCM3_REG UCSR3A
-#define U2X3_REG UCSR3A
-#define UPE3_REG UCSR3A
-#define DOR3_REG UCSR3A
-#define FE3_REG UCSR3A
-#define UDRE3_REG UCSR3A
-#define TXC3_REG UCSR3A
-#define RXC3_REG UCSR3A
-
-/* UCSR3B */
-#define TXB83_REG UCSR3B
-#define RXB83_REG UCSR3B
-#define UCSZ32_REG UCSR3B
-#define TXEN3_REG UCSR3B
-#define RXEN3_REG UCSR3B
-#define UDRIE3_REG UCSR3B
-#define TXCIE3_REG UCSR3B
-#define RXCIE3_REG UCSR3B
-
-/* UCSR3C */
-#define UCPOL3_REG UCSR3C
-#define UCSZ30_REG UCSR3C
-#define UCSZ31_REG UCSR3C
-#define USBS3_REG UCSR3C
-#define UPM30_REG UCSR3C
-#define UPM31_REG UCSR3C
-#define UMSEL30_REG UCSR3C
-#define UMSEL31_REG UCSR3C
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* RAMPZ */
-#define RAMPZ0_REG RAMPZ
-#define RAMPZ1_REG RAMPZ
-
-/* OCR2B */
-#define OCR2B_0_REG OCR2B
-#define OCR2B_1_REG OCR2B
-#define OCR2B_2_REG OCR2B
-#define OCR2B_3_REG OCR2B
-#define OCR2B_4_REG OCR2B
-#define OCR2B_5_REG OCR2B
-#define OCR2B_6_REG OCR2B
-#define OCR2B_7_REG OCR2B
-
-/* OCR2A */
-#define OCR2A_0_REG OCR2A
-#define OCR2A_1_REG OCR2A
-#define OCR2A_2_REG OCR2A
-#define OCR2A_3_REG OCR2A
-#define OCR2A_4_REG OCR2A
-#define OCR2A_5_REG OCR2A
-#define OCR2A_6_REG OCR2A
-#define OCR2A_7_REG OCR2A
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-#define EEAR10_REG EEARH
-#define EEAR11_REG EEARH
-
-/* PORTL */
-#define PORTL0_REG PORTL
-#define PORTL1_REG PORTL
-#define PORTL2_REG PORTL
-#define PORTL3_REG PORTL
-#define PORTL4_REG PORTL
-#define PORTL5_REG PORTL
-#define PORTL6_REG PORTL
-#define PORTL7_REG PORTL
-
-/* PORTJ */
-#define PORTJ0_REG PORTJ
-#define PORTJ1_REG PORTJ
-#define PORTJ2_REG PORTJ
-#define PORTJ3_REG PORTJ
-#define PORTJ4_REG PORTJ
-#define PORTJ5_REG PORTJ
-#define PORTJ6_REG PORTJ
-#define PORTJ7_REG PORTJ
-
-/* PORTK */
-#define PORTK0_REG PORTK
-#define PORTK1_REG PORTK
-#define PORTK2_REG PORTK
-#define PORTK3_REG PORTK
-#define PORTK4_REG PORTK
-#define PORTK5_REG PORTK
-#define PORTK6_REG PORTK
-#define PORTK7_REG PORTK
-
-/* PORTH */
-#define PORTH0_REG PORTH
-#define PORTH1_REG PORTH
-#define PORTH2_REG PORTH
-#define PORTH3_REG PORTH
-#define PORTH4_REG PORTH
-#define PORTH5_REG PORTH
-#define PORTH6_REG PORTH
-#define PORTH7_REG PORTH
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* PORTG */
-#define PORTG0_REG PORTG
-#define PORTG1_REG PORTG
-#define PORTG2_REG PORTG
-#define PORTG3_REG PORTG
-#define PORTG4_REG PORTG
-#define PORTG5_REG PORTG
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL00_REG UCSR0C
-#define UMSEL01_REG UCSR0C
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-#define INT3_REG EIMSK
-#define INT4_REG EIMSK
-#define INT5_REG EIMSK
-#define INT6_REG EIMSK
-#define INT7_REG EIMSK
-
-/* UDR1 */
-#define UDR1_0_REG UDR1
-#define UDR1_1_REG UDR1
-#define UDR1_2_REG UDR1
-#define UDR1_3_REG UDR1
-#define UDR1_4_REG UDR1
-#define UDR1_5_REG UDR1
-#define UDR1_6_REG UDR1
-#define UDR1_7_REG UDR1
-
-/* UDR0 */
-#define UDR0_0_REG UDR0
-#define UDR0_1_REG UDR0
-#define UDR0_2_REG UDR0
-#define UDR0_3_REG UDR0
-#define UDR0_4_REG UDR0
-#define UDR0_5_REG UDR0
-#define UDR0_6_REG UDR0
-#define UDR0_7_REG UDR0
-
-/* UDR3 */
-#define UDR3_0_REG UDR3
-#define UDR3_1_REG UDR3
-#define UDR3_2_REG UDR3
-#define UDR3_3_REG UDR3
-#define UDR3_4_REG UDR3
-#define UDR3_5_REG UDR3
-#define UDR3_6_REG UDR3
-#define UDR3_7_REG UDR3
-
-/* UDR2 */
-#define UDR2_0_REG UDR2
-#define UDR2_1_REG UDR2
-#define UDR2_2_REG UDR2
-#define UDR2_3_REG UDR2
-#define UDR2_4_REG UDR2
-#define UDR2_5_REG UDR2
-#define UDR2_6_REG UDR2
-#define UDR2_7_REG UDR2
-
-/* EICRB */
-#define ISC40_REG EICRB
-#define ISC41_REG EICRB
-#define ISC50_REG EICRB
-#define ISC51_REG EICRB
-#define ISC60_REG EICRB
-#define ISC61_REG EICRB
-#define ISC70_REG EICRB
-#define ISC71_REG EICRB
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-#define ISC20_REG EICRA
-#define ISC21_REG EICRA
-#define ISC30_REG EICRA
-#define ISC31_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* DIDR2 */
-#define ADC8D_REG DIDR2
-#define ADC9D_REG DIDR2
-#define ADC10D_REG DIDR2
-#define ADC11D_REG DIDR2
-#define ADC12D_REG DIDR2
-#define ADC13D_REG DIDR2
-#define ADC14D_REG DIDR2
-#define ADC15D_REG DIDR2
-
-/* DDRF */
-#define DDF0_REG DDRF
-#define DDF1_REG DDRF
-#define DDF2_REG DDRF
-#define DDF3_REG DDRF
-#define DDF4_REG DDRF
-#define DDF5_REG DDRF
-#define DDF6_REG DDRF
-#define DDF7_REG DDRF
-
-/* ASSR */
-#define TCR2BUB_REG ASSR
-#define TCR2AUB_REG ASSR
-#define OCR2BUB_REG ASSR
-#define OCR2AUB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* OCR0B */
-#define OCR0B_0_REG OCR0B
-#define OCR0B_1_REG OCR0B
-#define OCR0B_2_REG OCR0B
-#define OCR0B_3_REG OCR0B
-#define OCR0B_4_REG OCR0B
-#define OCR0B_5_REG OCR0B
-#define OCR0B_6_REG OCR0B
-#define OCR0B_7_REG OCR0B
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRJ */
-#define DDJ0_REG DDRJ
-#define DDJ1_REG DDRJ
-#define DDJ2_REG DDRJ
-#define DDJ3_REG DDRJ
-#define DDJ4_REG DDRJ
-#define DDJ5_REG DDRJ
-#define DDJ6_REG DDRJ
-#define DDJ7_REG DDRJ
-
-/* DDRK */
-#define DDK0_REG DDRK
-#define DDK1_REG DDRK
-#define DDK2_REG DDRK
-#define DDK3_REG DDRK
-#define DDK4_REG DDRK
-#define DDK5_REG DDRK
-#define DDK6_REG DDRK
-#define DDK7_REG DDRK
-
-/* DDRH */
-#define DDH0_REG DDRH
-#define DDH1_REG DDRH
-#define DDH2_REG DDRH
-#define DDH3_REG DDRH
-#define DDH4_REG DDRH
-#define DDH5_REG DDRH
-#define DDH6_REG DDRH
-#define DDH7_REG DDRH
-
-/* DDRL */
-#define DDL0_REG DDRL
-#define DDL1_REG DDRL
-#define DDL2_REG DDRL
-#define DDL3_REG DDRL
-#define DDL4_REG DDRL
-#define DDL5_REG DDRL
-#define DDL6_REG DDRL
-#define DDL7_REG DDRL
-
-/* UBRR1L */
-#define UBRR_0_REG UBRR1L
-#define UBRR_1_REG UBRR1L
-#define UBRR_2_REG UBRR1L
-#define UBRR_3_REG UBRR1L
-#define UBRR_4_REG UBRR1L
-#define UBRR_5_REG UBRR1L
-#define UBRR_6_REG UBRR1L
-#define UBRR_7_REG UBRR1L
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* OCR3AL */
-#define OCR3AL0_REG OCR3AL
-#define OCR3AL1_REG OCR3AL
-#define OCR3AL2_REG OCR3AL
-#define OCR3AL3_REG OCR3AL
-#define OCR3AL4_REG OCR3AL
-#define OCR3AL5_REG OCR3AL
-#define OCR3AL6_REG OCR3AL
-#define OCR3AL7_REG OCR3AL
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* UBRR1H */
-#define UBRR_8_REG UBRR1H
-#define UBRR_9_REG UBRR1H
-#define UBRR_10_REG UBRR1H
-#define UBRR_11_REG UBRR1H
-
-/* DDRG */
-#define DDG0_REG DDRG
-#define DDG1_REG DDRG
-#define DDG2_REG DDRG
-#define DDG3_REG DDRG
-#define DDG4_REG DDRG
-#define DDG5_REG DDRG
-
-/* OCR3AH */
-#define OCR3AH0_REG OCR3AH
-#define OCR3AH1_REG OCR3AH
-#define OCR3AH2_REG OCR3AH
-#define OCR3AH3_REG OCR3AH
-#define OCR3AH4_REG OCR3AH
-#define OCR3AH5_REG OCR3AH
-#define OCR3AH6_REG OCR3AH
-#define OCR3AH7_REG OCR3AH
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* TCNT5H */
-#define TCNT5H0_REG TCNT5H
-#define TCNT5H1_REG TCNT5H
-#define TCNT5H2_REG TCNT5H
-#define TCNT5H3_REG TCNT5H
-#define TCNT5H4_REG TCNT5H
-#define TCNT5H5_REG TCNT5H
-#define TCNT5H6_REG TCNT5H
-#define TCNT5H7_REG TCNT5H
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* TCNT5L */
-#define TCNT5L0_REG TCNT5L
-#define TCNT5L1_REG TCNT5L
-#define TCNT5L2_REG TCNT5L
-#define TCNT5L3_REG TCNT5L
-#define TCNT5L4_REG TCNT5L
-#define TCNT5L5_REG TCNT5L
-#define TCNT5L6_REG TCNT5L
-#define TCNT5L7_REG TCNT5L
-
-/* UBRR2H */
-/* #define UBRR8_REG UBRR2H */ /* dup in UBRR3H, UBRR0H */
-/* #define UBRR9_REG UBRR2H */ /* dup in UBRR3H, UBRR0H */
-/* #define UBRR10_REG UBRR2H */ /* dup in UBRR3H, UBRR0H */
-/* #define UBRR11_REG UBRR2H */ /* dup in UBRR3H, UBRR0H */
-
-/* UBRR2L */
-/* #define UBRR0_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */
-/* #define UBRR1_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */
-/* #define UBRR2_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */
-/* #define UBRR3_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */
-/* #define UBRR4_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */
-/* #define UBRR5_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */
-/* #define UBRR6_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */
-/* #define UBRR7_REG UBRR2L */ /* dup in UBRR3L, UBRR0L */
-
-/* PCICR */
-#define PCIE0_REG PCICR
-#define PCIE1_REG PCICR
-#define PCIE2_REG PCICR
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* UCSR2B */
-#define TXB82_REG UCSR2B
-#define RXB82_REG UCSR2B
-#define UCSZ22_REG UCSR2B
-#define TXEN2_REG UCSR2B
-#define RXEN2_REG UCSR2B
-#define UDRIE2_REG UCSR2B
-#define TXCIE2_REG UCSR2B
-#define RXCIE2_REG UCSR2B
-
-/* UCSR2A */
-#define MPCM2_REG UCSR2A
-#define U2X2_REG UCSR2A
-#define UPE2_REG UCSR2A
-#define DOR2_REG UCSR2A
-#define FE2_REG UCSR2A
-#define UDRE2_REG UCSR2A
-#define TXC2_REG UCSR2A
-#define RXC2_REG UCSR2A
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* UCSR2C */
-#define UCPOL2_REG UCSR2C
-#define UCSZ20_REG UCSR2C
-#define UCSZ21_REG UCSR2C
-#define USBS2_REG UCSR2C
-#define UPM20_REG UCSR2C
-#define UPM21_REG UCSR2C
-#define UMSEL20_REG UCSR2C
-#define UMSEL21_REG UCSR2C
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TIFR4 */
-#define TOV4_REG TIFR4
-#define OCF4A_REG TIFR4
-#define OCF4B_REG TIFR4
-#define OCF4C_REG TIFR4
-#define ICF4_REG TIFR4
-
-/* TIFR5 */
-#define TOV5_REG TIFR5
-#define OCF5A_REG TIFR5
-#define OCF5B_REG TIFR5
-#define OCF5C_REG TIFR5
-#define ICF5_REG TIFR5
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-#define OCF2B_REG TIFR2
-
-/* TIFR3 */
-#define TOV3_REG TIFR3
-#define OCF3A_REG TIFR3
-#define OCF3B_REG TIFR3
-#define OCF3C_REG TIFR3
-#define ICF3_REG TIFR3
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define OCF1C_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* OCR4AH */
-#define OCR4AH0_REG OCR4AH
-#define OCR4AH1_REG OCR4AH
-#define OCR4AH2_REG OCR4AH
-#define OCR4AH3_REG OCR4AH
-#define OCR4AH4_REG OCR4AH
-#define OCR4AH5_REG OCR4AH
-#define OCR4AH6_REG OCR4AH
-#define OCR4AH7_REG OCR4AH
-
-/* OCR5CH */
-#define OCR5CH0_REG OCR5CH
-#define OCR5CH1_REG OCR5CH
-#define OCR5CH2_REG OCR5CH
-#define OCR5CH3_REG OCR5CH
-#define OCR5CH4_REG OCR5CH
-#define OCR5CH5_REG OCR5CH
-#define OCR5CH6_REG OCR5CH
-#define OCR5CH7_REG OCR5CH
-
-/* OCR4AL */
-#define OCR4AL0_REG OCR4AL
-#define OCR4AL1_REG OCR4AL
-#define OCR4AL2_REG OCR4AL
-#define OCR4AL3_REG OCR4AL
-#define OCR4AL4_REG OCR4AL
-#define OCR4AL5_REG OCR4AL
-#define OCR4AL6_REG OCR4AL
-#define OCR4AL7_REG OCR4AL
-
-/* OCR5CL */
-#define OCR5CL0_REG OCR5CL
-#define OCR5CL1_REG OCR5CL
-#define OCR5CL2_REG OCR5CL
-#define OCR5CL3_REG OCR5CL
-#define OCR5CL4_REG OCR5CL
-#define OCR5CL5_REG OCR5CL
-#define OCR5CL6_REG OCR5CL
-#define OCR5CL7_REG OCR5CL
-
-/* OCR3CH */
-#define OCR3CH0_REG OCR3CH
-#define OCR3CH1_REG OCR3CH
-#define OCR3CH2_REG OCR3CH
-#define OCR3CH3_REG OCR3CH
-#define OCR3CH4_REG OCR3CH
-#define OCR3CH5_REG OCR3CH
-#define OCR3CH6_REG OCR3CH
-#define OCR3CH7_REG OCR3CH
-
-/* OCR3CL */
-#define OCR3CL0_REG OCR3CL
-#define OCR3CL1_REG OCR3CL
-#define OCR3CL2_REG OCR3CL
-#define OCR3CL3_REG OCR3CL
-#define OCR3CL4_REG OCR3CL
-#define OCR3CL5_REG OCR3CL
-#define OCR3CL6_REG OCR3CL
-#define OCR3CL7_REG OCR3CL
-
-/* GTCCR */
-#define PSRSYNC_REG GTCCR
-#define TSM_REG GTCCR
-#define PSRASY_REG GTCCR
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* TCCR3C */
-#define FOC3C_REG TCCR3C
-#define FOC3B_REG TCCR3C
-#define FOC3A_REG TCCR3C
-
-/* TCCR3B */
-#define CS30_REG TCCR3B
-#define CS31_REG TCCR3B
-#define CS32_REG TCCR3B
-#define WGM32_REG TCCR3B
-#define WGM33_REG TCCR3B
-#define ICES3_REG TCCR3B
-#define ICNC3_REG TCCR3B
-
-/* TCCR3A */
-#define WGM30_REG TCCR3A
-#define WGM31_REG TCCR3A
-#define COM3C0_REG TCCR3A
-#define COM3C1_REG TCCR3A
-#define COM3B0_REG TCCR3A
-#define COM3B1_REG TCCR3A
-#define COM3A0_REG TCCR3A
-#define COM3A1_REG TCCR3A
-
-/* PORTF */
-#define PORTF0_REG PORTF
-#define PORTF1_REG PORTF
-#define PORTF2_REG PORTF
-#define PORTF3_REG PORTF
-#define PORTF4_REG PORTF
-#define PORTF5_REG PORTF
-#define PORTF6_REG PORTF
-#define PORTF7_REG PORTF
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-#define PCINT15_REG PCMSK1
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* TCNT3H */
-#define TCNT3H0_REG TCNT3H
-#define TCNT3H1_REG TCNT3H
-#define TCNT3H2_REG TCNT3H
-#define TCNT3H3_REG TCNT3H
-#define TCNT3H4_REG TCNT3H
-#define TCNT3H5_REG TCNT3H
-#define TCNT3H6_REG TCNT3H
-#define TCNT3H7_REG TCNT3H
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* TCNT3L */
-#define TCNT3L0_REG TCNT3L
-#define TCNT3L1_REG TCNT3L
-#define TCNT3L2_REG TCNT3L
-#define TCNT3L3_REG TCNT3L
-#define TCNT3L4_REG TCNT3L
-#define TCNT3L5_REG TCNT3L
-#define TCNT3L6_REG TCNT3L
-#define TCNT3L7_REG TCNT3L
-
-/* ICR5L */
-#define ICR5L0_REG ICR5L
-#define ICR5L1_REG ICR5L
-#define ICR5L2_REG ICR5L
-#define ICR5L3_REG ICR5L
-#define ICR5L4_REG ICR5L
-#define ICR5L5_REG ICR5L
-#define ICR5L6_REG ICR5L
-#define ICR5L7_REG ICR5L
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* ICR5H */
-#define ICR5H0_REG ICR5H
-#define ICR5H1_REG ICR5H
-#define ICR5H2_REG ICR5H
-#define ICR5H3_REG ICR5H
-#define ICR5H4_REG ICR5H
-#define ICR5H5_REG ICR5H
-#define ICR5H6_REG ICR5H
-#define ICR5H7_REG ICR5H
-
-/* MCUSR */
-#define JTRF_REG MCUSR
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* PINK */
-#define PINK0_REG PINK
-#define PINK1_REG PINK
-#define PINK2_REG PINK
-#define PINK3_REG PINK
-#define PINK4_REG PINK
-#define PINK5_REG PINK
-#define PINK6_REG PINK
-#define PINK7_REG PINK
-
-/* PINJ */
-#define PINJ0_REG PINJ
-#define PINJ1_REG PINJ
-#define PINJ2_REG PINJ
-#define PINJ3_REG PINJ
-#define PINJ4_REG PINJ
-#define PINJ5_REG PINJ
-#define PINJ6_REG PINJ
-#define PINJ7_REG PINJ
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* PINH */
-#define PINH0_REG PINH
-#define PINH1_REG PINH
-#define PINH2_REG PINH
-#define PINH3_REG PINH
-#define PINH4_REG PINH
-#define PINH5_REG PINH
-#define PINH6_REG PINH
-#define PINH7_REG PINH
-
-/* PCIFR */
-#define PCIF0_REG PCIFR
-#define PCIF1_REG PCIFR
-#define PCIF2_REG PCIFR
-
-/* TCCR2A */
-#define WGM20_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2B0_REG TCCR2A
-#define COM2B1_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-
-/* TCCR2B */
-#define CS20_REG TCCR2B
-#define CS21_REG TCCR2B
-#define CS22_REG TCCR2B
-#define WGM22_REG TCCR2B
-#define FOC2B_REG TCCR2B
-#define FOC2A_REG TCCR2B
-
-/* UBRR0H */
-/* #define UBRR8_REG UBRR0H */ /* dup in UBRR3H, UBRR2H */
-/* #define UBRR9_REG UBRR0H */ /* dup in UBRR3H, UBRR2H */
-/* #define UBRR10_REG UBRR0H */ /* dup in UBRR3H, UBRR2H */
-/* #define UBRR11_REG UBRR0H */ /* dup in UBRR3H, UBRR2H */
-
-/* PING */
-#define PING0_REG PING
-#define PING1_REG PING
-#define PING2_REG PING
-#define PING3_REG PING
-#define PING4_REG PING
-#define PING5_REG PING
-
-/* UBRR0L */
-/* #define UBRR0_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */
-/* #define UBRR1_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */
-/* #define UBRR2_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */
-/* #define UBRR3_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */
-/* #define UBRR4_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */
-/* #define UBRR5_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */
-/* #define UBRR6_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */
-/* #define UBRR7_REG UBRR0L */ /* dup in UBRR3L, UBRR2L */
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* ICR4H */
-#define ICR4H0_REG ICR4H
-#define ICR4H1_REG ICR4H
-#define ICR4H2_REG ICR4H
-#define ICR4H3_REG ICR4H
-#define ICR4H4_REG ICR4H
-#define ICR4H5_REG ICR4H
-#define ICR4H6_REG ICR4H
-#define ICR4H7_REG ICR4H
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* PCMSK2 */
-#define PCINT16_REG PCMSK2
-#define PCINT17_REG PCMSK2
-#define PCINT18_REG PCMSK2
-#define PCINT19_REG PCMSK2
-#define PCINT20_REG PCMSK2
-#define PCINT21_REG PCMSK2
-#define PCINT22_REG PCMSK2
-#define PCINT23_REG PCMSK2
-
-/* ICR4L */
-#define ICR4L0_REG ICR4L
-#define ICR4L1_REG ICR4L
-#define ICR4L2_REG ICR4L
-#define ICR4L3_REG ICR4L
-#define ICR4L4_REG ICR4L
-#define ICR4L5_REG ICR4L
-#define ICR4L6_REG ICR4L
-#define ICR4L7_REG ICR4L
-
-/* MCUCR */
-#define JTD_REG MCUCR
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* OCR1CL */
-#define OCR1CL0_REG OCR1CL
-#define OCR1CL1_REG OCR1CL
-#define OCR1CL2_REG OCR1CL
-#define OCR1CL3_REG OCR1CL
-#define OCR1CL4_REG OCR1CL
-#define OCR1CL5_REG OCR1CL
-#define OCR1CL6_REG OCR1CL
-#define OCR1CL7_REG OCR1CL
-
-/* TCNT4L */
-#define TCNT4L0_REG TCNT4L
-#define TCNT4L1_REG TCNT4L
-#define TCNT4L2_REG TCNT4L
-#define TCNT4L3_REG TCNT4L
-#define TCNT4L4_REG TCNT4L
-#define TCNT4L5_REG TCNT4L
-#define TCNT4L6_REG TCNT4L
-#define TCNT4L7_REG TCNT4L
-
-/* OCR1CH */
-#define OCR1CH0_REG OCR1CH
-#define OCR1CH1_REG OCR1CH
-#define OCR1CH2_REG OCR1CH
-#define OCR1CH3_REG OCR1CH
-#define OCR1CH4_REG OCR1CH
-#define OCR1CH5_REG OCR1CH
-#define OCR1CH6_REG OCR1CH
-#define OCR1CH7_REG OCR1CH
-
-/* TCNT4H */
-#define TCNT4H0_REG TCNT4H
-#define TCNT4H1_REG TCNT4H
-#define TCNT4H2_REG TCNT4H
-#define TCNT4H3_REG TCNT4H
-#define TCNT4H4_REG TCNT4H
-#define TCNT4H5_REG TCNT4H
-#define TCNT4H6_REG TCNT4H
-#define TCNT4H7_REG TCNT4H
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* UCSR1B */
-#define TXB81_REG UCSR1B
-#define RXB81_REG UCSR1B
-#define UCSZ12_REG UCSR1B
-#define TXEN1_REG UCSR1B
-#define RXEN1_REG UCSR1B
-#define UDRIE1_REG UCSR1B
-#define TXCIE1_REG UCSR1B
-#define RXCIE1_REG UCSR1B
-
-/* UCSR1C */
-#define UCPOL1_REG UCSR1C
-#define UCSZ10_REG UCSR1C
-#define UCSZ11_REG UCSR1C
-#define USBS1_REG UCSR1C
-#define UPM10_REG UCSR1C
-#define UPM11_REG UCSR1C
-#define UMSEL10_REG UCSR1C
-#define UMSEL11_REG UCSR1C
-
-/* UCSR1A */
-#define MPCM1_REG UCSR1A
-#define U2X1_REG UCSR1A
-#define UPE1_REG UCSR1A
-#define DOR1_REG UCSR1A
-#define FE1_REG UCSR1A
-#define UDRE1_REG UCSR1A
-#define TXC1_REG UCSR1A
-#define RXC1_REG UCSR1A
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* EIND */
-#define EIND0_REG EIND
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* TCCR5A */
-#define WGM50_REG TCCR5A
-#define WGM51_REG TCCR5A
-#define COM5C0_REG TCCR5A
-#define COM5C1_REG TCCR5A
-#define COM5B0_REG TCCR5A
-#define COM5B1_REG TCCR5A
-#define COM5A0_REG TCCR5A
-#define COM5A1_REG TCCR5A
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* TCCR5C */
-#define FOC5C_REG TCCR5C
-#define FOC5B_REG TCCR5C
-#define FOC5A_REG TCCR5C
-
-/* TCCR5B */
-#define CS50_REG TCCR5B
-#define CS51_REG TCCR5B
-#define CS52_REG TCCR5B
-#define WGM52_REG TCCR5B
-#define WGM53_REG TCCR5B
-#define ICES5_REG TCCR5B
-#define ICNC5_REG TCCR5B
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ACME_REG ADCSRB
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define MUX5_REG ADCSRB
-
-/* OCR5AL */
-#define OCR5AL0_REG OCR5AL
-#define OCR5AL1_REG OCR5AL
-#define OCR5AL2_REG OCR5AL
-#define OCR5AL3_REG OCR5AL
-#define OCR5AL4_REG OCR5AL
-#define OCR5AL5_REG OCR5AL
-#define OCR5AL6_REG OCR5AL
-#define OCR5AL7_REG OCR5AL
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1C0_REG TCCR1A
-#define COM1C1_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* OCR4CH */
-#define OCR4CH0_REG OCR4CH
-#define OCR4CH1_REG OCR4CH
-#define OCR4CH2_REG OCR4CH
-#define OCR4CH3_REG OCR4CH
-#define OCR4CH4_REG OCR4CH
-#define OCR4CH5_REG OCR4CH
-#define OCR4CH6_REG OCR4CH
-#define OCR4CH7_REG OCR4CH
-
-/* OCR5AH */
-#define OCR5AH0_REG OCR5AH
-#define OCR5AH1_REG OCR5AH
-#define OCR5AH2_REG OCR5AH
-#define OCR5AH3_REG OCR5AH
-#define OCR5AH4_REG OCR5AH
-#define OCR5AH5_REG OCR5AH
-#define OCR5AH6_REG OCR5AH
-#define OCR5AH7_REG OCR5AH
-
-/* OCR4CL */
-#define OCR4CL0_REG OCR4CL
-#define OCR4CL1_REG OCR4CL
-#define OCR4CL2_REG OCR4CL
-#define OCR4CL3_REG OCR4CL
-#define OCR4CL4_REG OCR4CL
-#define OCR4CL5_REG OCR4CL
-#define OCR4CL6_REG OCR4CL
-#define OCR4CL7_REG OCR4CL
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* TCCR1C */
-#define FOC1C_REG TCCR1C
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* ICR3H */
-#define ICR3H0_REG ICR3H
-#define ICR3H1_REG ICR3H
-#define ICR3H2_REG ICR3H
-#define ICR3H3_REG ICR3H
-#define ICR3H4_REG ICR3H
-#define ICR3H5_REG ICR3H
-#define ICR3H6_REG ICR3H
-#define ICR3H7_REG ICR3H
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-#define DDE3_REG DDRE
-#define DDE4_REG DDRE
-#define DDE5_REG DDRE
-#define DDE6_REG DDRE
-#define DDE7_REG DDRE
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* ICR3L */
-#define ICR3L0_REG ICR3L
-#define ICR3L1_REG ICR3L
-#define ICR3L2_REG ICR3L
-#define ICR3L3_REG ICR3L
-#define ICR3L4_REG ICR3L
-#define ICR3L5_REG ICR3L
-#define ICR3L6_REG ICR3L
-#define ICR3L7_REG ICR3L
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-#define PORTE3_REG PORTE
-#define PORTE4_REG PORTE
-#define PORTE5_REG PORTE
-#define PORTE6_REG PORTE
-#define PORTE7_REG PORTE
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define SIGRD_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* OCR5BH */
-#define OCR5BH0_REG OCR5BH
-#define OCR5BH1_REG OCR5BH
-#define OCR5BH2_REG OCR5BH
-#define OCR5BH3_REG OCR5BH
-#define OCR5BH4_REG OCR5BH
-#define OCR5BH5_REG OCR5BH
-#define OCR5BH6_REG OCR5BH
-#define OCR5BH7_REG OCR5BH
-
-/* OCR3BL */
-#define OCR3BL0_REG OCR3BL
-#define OCR3BL1_REG OCR3BL
-#define OCR3BL2_REG OCR3BL
-#define OCR3BL3_REG OCR3BL
-#define OCR3BL4_REG OCR3BL
-#define OCR3BL5_REG OCR3BL
-#define OCR3BL6_REG OCR3BL
-#define OCR3BL7_REG OCR3BL
-
-/* OCR5BL */
-#define OCR5BL0_REG OCR5BL
-#define OCR5BL1_REG OCR5BL
-#define OCR5BL2_REG OCR5BL
-#define OCR5BL3_REG OCR5BL
-#define OCR5BL4_REG OCR5BL
-#define OCR5BL5_REG OCR5BL
-#define OCR5BL6_REG OCR5BL
-#define OCR5BL7_REG OCR5BL
-
-/* OCR3BH */
-#define OCR3BH0_REG OCR3BH
-#define OCR3BH1_REG OCR3BH
-#define OCR3BH2_REG OCR3BH
-#define OCR3BH3_REG OCR3BH
-#define OCR3BH4_REG OCR3BH
-#define OCR3BH5_REG OCR3BH
-#define OCR3BH6_REG OCR3BH
-#define OCR3BH7_REG OCR3BH
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-#define OCIE2B_REG TIMSK2
-
-/* TIMSK3 */
-#define TOIE3_REG TIMSK3
-#define OCIE3A_REG TIMSK3
-#define OCIE3B_REG TIMSK3
-#define OCIE3C_REG TIMSK3
-#define ICIE3_REG TIMSK3
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define OCIE1C_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* TIMSK4 */
-#define TOIE4_REG TIMSK4
-#define OCIE4A_REG TIMSK4
-#define OCIE4B_REG TIMSK4
-#define OCIE4C_REG TIMSK4
-#define ICIE4_REG TIMSK4
-
-/* TIMSK5 */
-#define TOIE5_REG TIMSK5
-#define OCIE5A_REG TIMSK5
-#define OCIE5B_REG TIMSK5
-#define OCIE5C_REG TIMSK5
-#define ICIE5_REG TIMSK5
-
-/* TCCR4B */
-#define CS40_REG TCCR4B
-#define CS41_REG TCCR4B
-#define CS42_REG TCCR4B
-#define WGM42_REG TCCR4B
-#define WGM43_REG TCCR4B
-#define ICES4_REG TCCR4B
-#define ICNC4_REG TCCR4B
-
-/* TCCR4C */
-#define FOC4C_REG TCCR4C
-#define FOC4B_REG TCCR4C
-#define FOC4A_REG TCCR4C
-
-/* TCCR4A */
-#define WGM40_REG TCCR4A
-#define WGM41_REG TCCR4A
-#define COM4C0_REG TCCR4A
-#define COM4C1_REG TCCR4A
-#define COM4B0_REG TCCR4A
-#define COM4B1_REG TCCR4A
-#define COM4A0_REG TCCR4A
-#define COM4A1_REG TCCR4A
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* XMCRB */
-#define XMM0_REG XMCRB
-#define XMM1_REG XMCRB
-#define XMM2_REG XMCRB
-#define XMBK_REG XMCRB
-
-/* XMCRA */
-#define SRW00_REG XMCRA
-#define SRW01_REG XMCRA
-#define SRW10_REG XMCRA
-#define SRW11_REG XMCRA
-#define SRL0_REG XMCRA
-#define SRL1_REG XMCRA
-#define SRL2_REG XMCRA
-#define SRE_REG XMCRA
-
-/* PINL */
-#define PINL0_REG PINL
-#define PINL1_REG PINL
-#define PINL2_REG PINL
-#define PINL3_REG PINL
-#define PINL4_REG PINL
-#define PINL5_REG PINL
-#define PINL6_REG PINL
-#define PINL7_REG PINL
-
-/* OCR4BL */
-#define OCR4BL0_REG OCR4BL
-#define OCR4BL1_REG OCR4BL
-#define OCR4BL2_REG OCR4BL
-#define OCR4BL3_REG OCR4BL
-#define OCR4BL4_REG OCR4BL
-#define OCR4BL5_REG OCR4BL
-#define OCR4BL6_REG OCR4BL
-#define OCR4BL7_REG OCR4BL
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-#define INTF2_REG EIFR
-#define INTF3_REG EIFR
-#define INTF4_REG EIFR
-#define INTF5_REG EIFR
-#define INTF6_REG EIFR
-#define INTF7_REG EIFR
-
-/* OCR4BH */
-#define OCR4BH0_REG OCR4BH
-#define OCR4BH1_REG OCR4BH
-#define OCR4BH2_REG OCR4BH
-#define OCR4BH3_REG OCR4BH
-#define OCR4BH4_REG OCR4BH
-#define OCR4BH5_REG OCR4BH
-#define OCR4BH6_REG OCR4BH
-#define OCR4BH7_REG OCR4BH
-
-/* PINF */
-#define PINF0_REG PINF
-#define PINF1_REG PINF
-#define PINF2_REG PINF
-#define PINF3_REG PINF
-#define PINF4_REG PINF
-#define PINF5_REG PINF
-#define PINF6_REG PINF
-#define PINF7_REG PINF
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-#define PINE3_REG PINE
-#define PINE4_REG PINE
-#define PINE5_REG PINE
-#define PINE6_REG PINE
-#define PINE7_REG PINE
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* TWAMR */
-#define TWAM0_REG TWAMR
-#define TWAM1_REG TWAMR
-#define TWAM2_REG TWAMR
-#define TWAM3_REG TWAMR
-#define TWAM4_REG TWAMR
-#define TWAM5_REG TWAMR
-#define TWAM6_REG TWAMR
-
-/* PRR0 */
-#define PRADC_REG PRR0
-#define PRUSART0_REG PRR0
-#define PRSPI_REG PRR0
-#define PRTIM1_REG PRR0
-#define PRTIM0_REG PRR0
-#define PRTIM2_REG PRR0
-#define PRTWI_REG PRR0
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* PRR1 */
-#define PRUSART1_REG PRR1
-#define PRUSART2_REG PRR1
-#define PRUSART3_REG PRR1
-#define PRTIM3_REG PRR1
-#define PRTIM4_REG PRR1
-#define PRTIM5_REG PRR1
-
-/* pins mapping */
-#define AD0_PORT PORTA
-#define AD0_BIT 0
-
-#define AD1_PORT PORTA
-#define AD1_BIT 1
-
-#define AD2_PORT PORTA
-#define AD2_BIT 2
-
-#define AD3_PORT PORTA
-#define AD3_BIT 3
-
-#define AD4_PORT PORTA
-#define AD4_BIT 4
-
-#define AD5_PORT PORTA
-#define AD5_BIT 5
-
-#define AD6_PORT PORTA
-#define AD6_BIT 6
-
-#define AD7_PORT PORTA
-#define AD7_BIT 7
-
-#define SS_PORT PORTB
-#define SS_BIT 0
-#define PCINT0_PORT PORTB
-#define PCINT0_BIT 0
-
-#define SCK_PORT PORTB
-#define SCK_BIT 1
-#define PCINT1_PORT PORTB
-#define PCINT1_BIT 1
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 2
-#define PCINT2_PORT PORTB
-#define PCINT2_BIT 2
-
-#define MISO_PORT PORTB
-#define MISO_BIT 3
-#define PCINT3_PORT PORTB
-#define PCINT3_BIT 3
-
-#define OC0A_PORT PORTB
-#define OC0A_BIT 4
-#define PCINT4_PORT PORTB
-#define PCINT4_BIT 4
-
-#define OC1B_PORT PORTB
-#define OC1B_BIT 6
-#define PCINT6_PORT PORTB
-#define PCINT6_BIT 6
-
-#define OC0A_PORT PORTB
-#define OC0A_BIT 7
-#define OC1C_PORT PORTB
-#define OC1C_BIT 7
-#define PCINT7_PORT PORTB
-#define PCINT7_BIT 7
-
-#define A8_PORT PORTC
-#define A8_BIT 0
-
-#define A9_PORT PORTC
-#define A9_BIT 1
-
-#define A10_PORT PORTC
-#define A10_BIT 2
-
-#define A11_PORT PORTC
-#define A11_BIT 3
-
-#define A12_PORT PORTC
-#define A12_BIT 4
-
-#define A13_PORT PORTC
-#define A13_BIT 5
-
-#define A14_PORT PORTC
-#define A14_BIT 6
-
-#define A15_PORT PORTC
-#define A15_BIT 7
-
-#define SCL_PORT PORTD
-#define SCL_BIT 0
-#define INT0_PORT PORTD
-#define INT0_BIT 0
-
-#define SDA_PORT PORTD
-#define SDA_BIT 1
-#define INT1_PORT PORTD
-#define INT1_BIT 1
-
-#define RXD1_PORT PORTD
-#define RXD1_BIT 2
-#define INT2_PORT PORTD
-#define INT2_BIT 2
-
-#define TXD1_PORT PORTD
-#define TXD1_BIT 3
-#define INT3_PORT PORTD
-#define INT3_BIT 3
-
-#define ICP1_PORT PORTD
-#define ICP1_BIT 4
-
-#define XCK1_PORT PORTD
-#define XCK1_BIT 5
-
-#define T1_PORT PORTD
-#define T1_BIT 6
-
-#define T0_PORT PORTD
-#define T0_BIT 7
-
-#define RXD_PORT PORTE
-#define RXD_BIT 0
-#define PCINT8_PORT PORTE
-#define PCINT8_BIT 0
-
-#define TXD0_PORT PORTE
-#define TXD0_BIT 1
-
-#define XCK_PORT PORTE
-#define XCK_BIT 2
-#define AIN0_PORT PORTE
-#define AIN0_BIT 2
-
-#define OC3A_PORT PORTE
-#define OC3A_BIT 3
-#define AIN1_PORT PORTE
-#define AIN1_BIT 3
-
-#define OC3B_PORT PORTE
-#define OC3B_BIT 4
-#define INT4_PORT PORTE
-#define INT4_BIT 4
-
-#define T3_PORT PORTE
-#define T3_BIT 6
-#define INT6_PORT PORTE
-#define INT6_BIT 6
-
-#define CLKO_PORT PORTE
-#define CLKO_BIT 7
-#define ICP3_PORT PORTE
-#define ICP3_BIT 7
-#define INT7_PORT PORTE
-#define INT7_BIT 7
-
-#define ADC0_PORT PORTF
-#define ADC0_BIT 0
-
-#define ADC1_PORT PORTF
-#define ADC1_BIT 1
-
-#define ADC2_PORT PORTF
-#define ADC2_BIT 2
-
-#define ADC3_PORT PORTF
-#define ADC3_BIT 3
-
-#define ADC4_PORT PORTF
-#define ADC4_BIT 4
-#define TCK_PORT PORTF
-#define TCK_BIT 4
-
-#define ADC6_PORT PORTF
-#define ADC6_BIT 6
-#define TDO_PORT PORTF
-#define TDO_BIT 6
-
-#define ADC7_PORT PORTF
-#define ADC7_BIT 7
-#define TDI_PORT PORTF
-#define TDI_BIT 7
-
-#define WR_PORT PORTG
-#define WR_BIT 0
-
-#define RD_PORT PORTG
-#define RD_BIT 1
-
-#define ALE_PORT PORTG
-#define ALE_BIT 2
-
-#define TOSC2_PORT PORTG
-#define TOSC2_BIT 3
-
-#define TOSC1_PORT PORTG
-#define TOSC1_BIT 4
-
-#define OC0B_PORT PORTG
-#define OC0B_BIT 5
-
-#define RXD2_PORT PORTH
-#define RXD2_BIT 0
-
-#define TXD2_PORT PORTH
-#define TXD2_BIT 1
-
-#define XCK2_PORT PORTH
-#define XCK2_BIT 2
-
-#define OC4A_PORT PORTH
-#define OC4A_BIT 3
-
-#define OC4B_PORT PORTH
-#define OC4B_BIT 4
-
-#define OC2B_PORT PORTH
-#define OC2B_BIT 6
-
-#define T4_PORT PORTH
-#define T4_BIT 7
-
-#define RXD3_PORT PORTJ
-#define RXD3_BIT 0
-#define PCINT9_PORT PORTJ
-#define PCINT9_BIT 0
-
-#define TXD3_PORT PORTJ
-#define TXD3_BIT 1
-#define PCINT10_PORT PORTJ
-#define PCINT10_BIT 1
-
-#define XCK3_PORT PORTJ
-#define XCK3_BIT 2
-#define PCINT11_PORT PORTJ
-#define PCINT11_BIT 2
-
-#define PCINT12_PORT PORTJ
-#define PCINT12_BIT 3
-
-#define PCINT13_PORT PORTJ
-#define PCINT13_BIT 4
-
-#define PCINT15_PORT PORTJ
-#define PCINT15_BIT 6
-
-#define ADC8_PORT PORTK
-#define ADC8_BIT 0
-#define PCINT16_PORT PORTK
-#define PCINT16_BIT 0
-
-#define ADC9_PORT PORTK
-#define ADC9_BIT 1
-#define PCINT17_PORT PORTK
-#define PCINT17_BIT 1
-
-#define ADC10_PORT PORTK
-#define ADC10_BIT 2
-#define PCINT18_PORT PORTK
-#define PCINT18_BIT 2
-
-#define ADC11_PORT PORTK
-#define ADC11_BIT 3
-#define PCINT19_PORT PORTK
-#define PCINT19_BIT 3
-
-#define ADC12_PORT PORTK
-#define ADC12_BIT 4
-#define PCINT20_PORT PORTK
-#define PCINT20_BIT 4
-
-#define ADC13_PORT PORTK
-#define ADC13_BIT 5
-#define PCINT21_PORT PORTK
-#define PCINT21_BIT 5
-
-#define ADC14_PORT PORTK
-#define ADC14_BIT 6
-#define PCINT22_PORT PORTK
-#define PCINT22_BIT 6
-
-#define ADC15_PORT PORTK
-#define ADC15_BIT 7
-#define PCINT23_PORT PORTK
-#define PCINT23_BIT 7
-
-#define ICP4_PORT PORTL
-#define ICP4_BIT 0
-
-#define ICP5_PORT PORTL
-#define ICP5_BIT 1
-
-#define T5_PORT PORTL
-#define T5_BIT 2
-
-#define OC5A_PORT PORTL
-#define OC5A_BIT 3
-
-#define OC5B_PORT PORTL
-#define OC5B_BIT 4
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-#define TIMER2A_AVAILABLE
-#define TIMER2B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE2A_NUM 4
-#define SIG_OUTPUT_COMPARE2B_NUM 5
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 6
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM2A_NUM 4
-#define PWM2B_NUM 5
-#define PWM_TOTAL_NUM 6
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* RAMPZ */
-#define RAMPZ0_REG RAMPZ
-
-/* OCR2B */
-#define OCR2B_0_REG OCR2B
-#define OCR2B_1_REG OCR2B
-#define OCR2B_2_REG OCR2B
-#define OCR2B_3_REG OCR2B
-#define OCR2B_4_REG OCR2B
-#define OCR2B_5_REG OCR2B
-#define OCR2B_6_REG OCR2B
-#define OCR2B_7_REG OCR2B
-
-/* OCR2A */
-#define OCR2A_0_REG OCR2A
-#define OCR2A_1_REG OCR2A
-#define OCR2A_2_REG OCR2A
-#define OCR2A_3_REG OCR2A
-#define OCR2A_4_REG OCR2A
-#define OCR2A_5_REG OCR2A
-#define OCR2A_6_REG OCR2A
-#define OCR2A_7_REG OCR2A
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSART0_REG PRR
-#define PRSPI_REG PRR
-#define PRTIM1_REG PRR
-#define PRTIM0_REG PRR
-#define PRTIM2_REG PRR
-#define PRTWI_REG PRR
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* UDR0 */
-#define UDR0_0_REG UDR0
-#define UDR0_1_REG UDR0
-#define UDR0_2_REG UDR0
-#define UDR0_3_REG UDR0
-#define UDR0_4_REG UDR0
-#define UDR0_5_REG UDR0
-#define UDR0_6_REG UDR0
-#define UDR0_7_REG UDR0
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-#define ISC20_REG EICRA
-#define ISC21_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* ASSR */
-#define TCR2BUB_REG ASSR
-#define TCR2AUB_REG ASSR
-#define OCR2BUB_REG ASSR
-#define OCR2AUB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* PCICR */
-#define PCIE0_REG PCICR
-#define PCIE1_REG PCICR
-#define PCIE2_REG PCICR
-#define PCIE3_REG PCICR
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-#define OCF2B_REG TIFR2
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* GTCCR */
-#define PSRSYNC_REG GTCCR
-#define TSM_REG GTCCR
-#define PSRASY_REG GTCCR
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* OCR1BL */
-/* #define OCR1AL0_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL1_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL2_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL3_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL4_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL5_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL6_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL7_REG OCR1BL */ /* dup in OCR1AL */
-
-/* PCIFR */
-#define PCIF0_REG PCIFR
-#define PCIF1_REG PCIFR
-#define PCIF2_REG PCIFR
-#define PCIF3_REG PCIFR
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* OCR1BH */
-/* #define OCR1AH0_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH1_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH2_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH3_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH4_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH5_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH6_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH7_REG OCR1BH */ /* dup in OCR1AH */
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* TCCR2A */
-#define WGM20_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2B0_REG TCCR2A
-#define COM2B1_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-
-/* TCCR2B */
-#define CS20_REG TCCR2B
-#define CS21_REG TCCR2B
-#define CS22_REG TCCR2B
-#define WGM22_REG TCCR2B
-#define FOC2B_REG TCCR2B
-#define FOC2A_REG TCCR2B
-
-/* UBRR0H */
-#define UBRR8_REG UBRR0H
-#define UBRR9_REG UBRR0H
-#define UBRR10_REG UBRR0H
-#define UBRR11_REG UBRR0H
-
-/* UBRR0L */
-#define UBRR0_REG UBRR0L
-#define UBRR1_REG UBRR0L
-#define UBRR2_REG UBRR0L
-#define UBRR3_REG UBRR0L
-#define UBRR4_REG UBRR0L
-#define UBRR5_REG UBRR0L
-#define UBRR6_REG UBRR0L
-#define UBRR7_REG UBRR0L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-#define EEAR10_REG EEARH
-#define EEAR11_REG EEARH
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* MCUCR */
-#define JTD_REG MCUCR
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-
-/* MCUSR */
-#define JTRF_REG MCUSR
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* OCR1AH */
-/* #define OCR1AH0_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH1_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH2_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH3_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH4_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH5_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH6_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH7_REG OCR1AH */ /* dup in OCR1BH */
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ACME_REG ADCSRB
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-
-/* OCR0A */
-#define OCROA_0_REG OCR0A
-#define OCROA_1_REG OCR0A
-#define OCROA_2_REG OCR0A
-#define OCROA_3_REG OCR0A
-#define OCROA_4_REG OCR0A
-#define OCROA_5_REG OCR0A
-#define OCROA_6_REG OCR0A
-#define OCROA_7_REG OCR0A
-
-/* OCR0B */
-#define OCR0B_0_REG OCR0B
-#define OCR0B_1_REG OCR0B
-#define OCR0B_2_REG OCR0B
-#define OCR0B_3_REG OCR0B
-#define OCR0B_4_REG OCR0B
-#define OCR0B_5_REG OCR0B
-#define OCR0B_6_REG OCR0B
-#define OCR0B_7_REG OCR0B
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL00_REG UCSR0C
-#define UMSEL01_REG UCSR0C
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define SIGRD_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-#define OCIE2B_REG TIMSK2
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-#define PCINT15_REG PCMSK1
-
-/* PCMSK2 */
-#define PCINT16_REG PCMSK2
-#define PCINT17_REG PCMSK2
-#define PCINT18_REG PCMSK2
-#define PCINT19_REG PCMSK2
-#define PCINT20_REG PCMSK2
-#define PCINT21_REG PCMSK2
-#define PCINT22_REG PCMSK2
-#define PCINT23_REG PCMSK2
-
-/* PCMSK3 */
-#define PCINT24_REG PCMSK3
-#define PCINT25_REG PCMSK3
-#define PCINT26_REG PCMSK3
-#define PCINT27_REG PCMSK3
-#define PCINT28_REG PCMSK3
-#define PCINT29_REG PCMSK3
-#define PCINT30_REG PCMSK3
-#define PCINT31_REG PCMSK3
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-#define INTF2_REG EIFR
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* TWAMR */
-#define TWAM0_REG TWAMR
-#define TWAM1_REG TWAMR
-#define TWAM2_REG TWAMR
-#define TWAM3_REG TWAMR
-#define TWAM4_REG TWAMR
-#define TWAM5_REG TWAMR
-#define TWAM6_REG TWAMR
-
-/* OCR1AL */
-/* #define OCR1AL0_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL1_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL2_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL3_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL4_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL5_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL6_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL7_REG OCR1AL */ /* dup in OCR1BL */
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* pins mapping */
-#define ADC0_PORT PORTA
-#define ADC0_BIT 0
-#define PCINT0_PORT PORTA
-#define PCINT0_BIT 0
-
-#define ADC1_PORT PORTA
-#define ADC1_BIT 1
-#define PCINT1_PORT PORTA
-#define PCINT1_BIT 1
-
-#define ADC2_PORT PORTA
-#define ADC2_BIT 2
-#define PCINT2_PORT PORTA
-#define PCINT2_BIT 2
-
-#define ADC3_PORT PORTA
-#define ADC3_BIT 3
-#define PCINT3_PORT PORTA
-#define PCINT3_BIT 3
-
-#define ADC4_PORT PORTA
-#define ADC4_BIT 4
-#define PCINT4_PORT PORTA
-#define PCINT4_BIT 4
-
-#define ADC5_PORT PORTA
-#define ADC5_BIT 5
-#define PCINT5_PORT PORTA
-#define PCINT5_BIT 5
-
-#define ADC6_PORT PORTA
-#define ADC6_BIT 6
-#define PCINT6_PORT PORTA
-#define PCINT6_BIT 6
-
-#define ADC7_PORT PORTA
-#define ADC7_BIT 7
-#define PCINT7_PORT PORTA
-#define PCINT7_BIT 7
-
-#define XCK_PORT PORTB
-#define XCK_BIT 0
-#define T0_PORT PORTB
-#define T0_BIT 0
-#define PCINT9_PORT PORTB
-#define PCINT9_BIT 0
-
-#define T1_PORT PORTB
-#define T1_BIT 1
-#define CLKO_PORT PORTB
-#define CLKO_BIT 1
-#define PCINT9_PORT PORTB
-#define PCINT9_BIT 1
-
-#define AIN0_PORT PORTB
-#define AIN0_BIT 2
-#define INT2_PORT PORTB
-#define INT2_BIT 2
-#define PCINT10_PORT PORTB
-#define PCINT10_BIT 2
-
-#define AIN1_PORT PORTB
-#define AIN1_BIT 3
-#define OC0A_PORT PORTB
-#define OC0A_BIT 3
-#define PCINT11_PORT PORTB
-#define PCINT11_BIT 3
-
-#define SS_PORT PORTB
-#define SS_BIT 4
-#define OC0B_PORT PORTB
-#define OC0B_BIT 4
-#define PCINT12_PORT PORTB
-#define PCINT12_BIT 4
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 5
-#define PCINT13_PORT PORTB
-#define PCINT13_BIT 5
-
-#define MISO_PORT PORTB
-#define MISO_BIT 6
-#define PCINT14_PORT PORTB
-#define PCINT14_BIT 6
-
-#define SCK_PORT PORTB
-#define SCK_BIT 7
-#define PCINT15_PORT PORTB
-#define PCINT15_BIT 7
-
-#define SCL_PORT PORTC
-#define SCL_BIT 0
-#define PCINT16_PORT PORTC
-#define PCINT16_BIT 0
-
-#define SDA_PORT PORTC
-#define SDA_BIT 1
-#define PCINT17_PORT PORTC
-#define PCINT17_BIT 1
-
-#define TCK_PORT PORTC
-#define TCK_BIT 2
-#define PCINT18_PORT PORTC
-#define PCINT18_BIT 2
-
-#define TMS_PORT PORTC
-#define TMS_BIT 3
-#define PCINT19_PORT PORTC
-#define PCINT19_BIT 3
-
-#define TDO_PORT PORTC
-#define TDO_BIT 4
-#define PCINT20_PORT PORTC
-#define PCINT20_BIT 4
-
-#define TDI_PORT PORTC
-#define TDI_BIT 5
-#define PCINT21_PORT PORTC
-#define PCINT21_BIT 5
-
-#define TOSC1_PORT PORTC
-#define TOSC1_BIT 6
-#define PCINT22_PORT PORTC
-#define PCINT22_BIT 6
-
-#define TOSC2_PORT PORTC
-#define TOSC2_BIT 7
-#define PCINT23_PORT PORTC
-#define PCINT23_BIT 7
-
-#define RXD_PORT PORTD
-#define RXD_BIT 0
-#define PCINT24_PORT PORTD
-#define PCINT24_BIT 0
-
-#define TXD_PORT PORTD
-#define TXD_BIT 1
-#define PCINT25_PORT PORTD
-#define PCINT25_BIT 1
-
-#define INT0_PORT PORTD
-#define INT0_BIT 2
-#define PCINT26_PORT PORTD
-#define PCINT26_BIT 2
-
-#define INT1_PORT PORTD
-#define INT1_BIT 3
-#define PCINT27_PORT PORTD
-#define PCINT27_BIT 3
-
-#define OC1B_PORT PORTD
-#define OC1B_BIT 4
-#define PCINT28_PORT PORTD
-#define PCINT28_BIT 4
-
-#define OC1A_PORT PORTD
-#define OC1A_BIT 5
-#define PCINT29_PORT PORTD
-#define PCINT29_BIT 5
-
-#define ICP_PORT PORTD
-#define ICP_BIT 6
-#define OC2B_PORT PORTD
-#define OC2B_BIT 6
-#define PCINT30_PORT PORTD
-#define PCINT30_BIT 6
-
-#define OC2A_PORT PORTD
-#define OC2A_BIT 7
-#define PCINT31_PORT PORTD
-#define PCINT31_BIT 7
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-#define TIMER2A_AVAILABLE
-#define TIMER2B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE2A_NUM 4
-#define SIG_OUTPUT_COMPARE2B_NUM 5
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 6
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM2A_NUM 4
-#define PWM2B_NUM 5
-#define PWM_TOTAL_NUM 6
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* RAMPZ */
-#define RAMPZ0_REG RAMPZ
-
-/* OCR2B */
-#define OCR2B_0_REG OCR2B
-#define OCR2B_1_REG OCR2B
-#define OCR2B_2_REG OCR2B
-#define OCR2B_3_REG OCR2B
-#define OCR2B_4_REG OCR2B
-#define OCR2B_5_REG OCR2B
-#define OCR2B_6_REG OCR2B
-#define OCR2B_7_REG OCR2B
-
-/* OCR2A */
-#define OCR2A_0_REG OCR2A
-#define OCR2A_1_REG OCR2A
-#define OCR2A_2_REG OCR2A
-#define OCR2A_3_REG OCR2A
-#define OCR2A_4_REG OCR2A
-#define OCR2A_5_REG OCR2A
-#define OCR2A_6_REG OCR2A
-#define OCR2A_7_REG OCR2A
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL00_REG UCSR0C
-#define UMSEL01_REG UCSR0C
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* UDR1 */
-#define UDR1_0_REG UDR1
-#define UDR1_1_REG UDR1
-#define UDR1_2_REG UDR1
-#define UDR1_3_REG UDR1
-#define UDR1_4_REG UDR1
-#define UDR1_5_REG UDR1
-#define UDR1_6_REG UDR1
-#define UDR1_7_REG UDR1
-
-/* UDR0 */
-#define UDR0_0_REG UDR0
-#define UDR0_1_REG UDR0
-#define UDR0_2_REG UDR0
-#define UDR0_3_REG UDR0
-#define UDR0_4_REG UDR0
-#define UDR0_5_REG UDR0
-#define UDR0_6_REG UDR0
-#define UDR0_7_REG UDR0
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-#define ISC20_REG EICRA
-#define ISC21_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* ASSR */
-#define TCR2BUB_REG ASSR
-#define TCR2AUB_REG ASSR
-#define OCR2BUB_REG ASSR
-#define OCR2AUB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* UBRR1L */
-#define UBRR_0_REG UBRR1L
-#define UBRR_1_REG UBRR1L
-#define UBRR_2_REG UBRR1L
-#define UBRR_3_REG UBRR1L
-#define UBRR_4_REG UBRR1L
-#define UBRR_5_REG UBRR1L
-#define UBRR_6_REG UBRR1L
-#define UBRR_7_REG UBRR1L
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* UBRR1H */
-#define UBRR_8_REG UBRR1H
-#define UBRR_9_REG UBRR1H
-#define UBRR_10_REG UBRR1H
-#define UBRR_11_REG UBRR1H
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* PCICR */
-#define PCIE0_REG PCICR
-#define PCIE1_REG PCICR
-#define PCIE2_REG PCICR
-#define PCIE3_REG PCICR
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-#define OCF2B_REG TIFR2
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* GTCCR */
-#define PSRSYNC_REG GTCCR
-#define TSM_REG GTCCR
-#define PSRASY_REG GTCCR
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* OCR1BL */
-/* #define OCR1AL0_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL1_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL2_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL3_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL4_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL5_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL6_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL7_REG OCR1BL */ /* dup in OCR1AL */
-
-/* PCIFR */
-#define PCIF0_REG PCIFR
-#define PCIF1_REG PCIFR
-#define PCIF2_REG PCIFR
-#define PCIF3_REG PCIFR
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* OCR1BH */
-/* #define OCR1AH0_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH1_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH2_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH3_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH4_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH5_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH6_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH7_REG OCR1BH */ /* dup in OCR1AH */
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* TCCR2A */
-#define WGM20_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2B0_REG TCCR2A
-#define COM2B1_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-
-/* TCCR2B */
-#define CS20_REG TCCR2B
-#define CS21_REG TCCR2B
-#define CS22_REG TCCR2B
-#define WGM22_REG TCCR2B
-#define FOC2B_REG TCCR2B
-#define FOC2A_REG TCCR2B
-
-/* UBRR0H */
-#define UBRR8_REG UBRR0H
-#define UBRR9_REG UBRR0H
-#define UBRR10_REG UBRR0H
-#define UBRR11_REG UBRR0H
-
-/* UBRR0L */
-#define UBRR0_REG UBRR0L
-#define UBRR1_REG UBRR0L
-#define UBRR2_REG UBRR0L
-#define UBRR3_REG UBRR0L
-#define UBRR4_REG UBRR0L
-#define UBRR5_REG UBRR0L
-#define UBRR6_REG UBRR0L
-#define UBRR7_REG UBRR0L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-#define EEAR10_REG EEARH
-#define EEAR11_REG EEARH
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* MCUCR */
-#define JTD_REG MCUCR
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-#define BODSE_REG MCUCR
-#define BODS_REG MCUCR
-
-/* MCUSR */
-#define JTRF_REG MCUSR
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* UCSR1B */
-#define TXB81_REG UCSR1B
-#define RXB81_REG UCSR1B
-#define UCSZ12_REG UCSR1B
-#define TXEN1_REG UCSR1B
-#define RXEN1_REG UCSR1B
-#define UDRIE1_REG UCSR1B
-#define TXCIE1_REG UCSR1B
-#define RXCIE1_REG UCSR1B
-
-/* UCSR1C */
-#define UCPOL1_REG UCSR1C
-#define UCSZ10_REG UCSR1C
-#define UCSZ11_REG UCSR1C
-#define USBS1_REG UCSR1C
-#define UPM10_REG UCSR1C
-#define UPM11_REG UCSR1C
-#define UMSEL10_REG UCSR1C
-#define UMSEL11_REG UCSR1C
-
-/* UCSR1A */
-#define MPCM1_REG UCSR1A
-#define U2X1_REG UCSR1A
-#define UPE1_REG UCSR1A
-#define DOR1_REG UCSR1A
-#define FE1_REG UCSR1A
-#define UDRE1_REG UCSR1A
-#define TXC1_REG UCSR1A
-#define RXC1_REG UCSR1A
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* TWAMR */
-#define TWAM0_REG TWAMR
-#define TWAM1_REG TWAMR
-#define TWAM2_REG TWAMR
-#define TWAM3_REG TWAMR
-#define TWAM4_REG TWAMR
-#define TWAM5_REG TWAMR
-#define TWAM6_REG TWAMR
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ACME_REG ADCSRB
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-
-/* PRR0 */
-#define PRADC_REG PRR0
-#define PRUSART0_REG PRR0
-#define PRSPI_REG PRR0
-#define PRTIM1_REG PRR0
-#define PRUSART1_REG PRR0
-#define PRTIM0_REG PRR0
-#define PRTIM2_REG PRR0
-#define PRTWI_REG PRR0
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* OCR0A */
-#define OCROA_0_REG OCR0A
-#define OCROA_1_REG OCR0A
-#define OCROA_2_REG OCR0A
-#define OCROA_3_REG OCR0A
-#define OCROA_4_REG OCR0A
-#define OCROA_5_REG OCR0A
-#define OCROA_6_REG OCR0A
-#define OCROA_7_REG OCR0A
-
-/* OCR0B */
-#define OCR0B_0_REG OCR0B
-#define OCR0B_1_REG OCR0B
-#define OCR0B_2_REG OCR0B
-#define OCR0B_3_REG OCR0B
-#define OCR0B_4_REG OCR0B
-#define OCR0B_5_REG OCR0B
-#define OCR0B_6_REG OCR0B
-#define OCR0B_7_REG OCR0B
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define SIGRD_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-#define OCIE2B_REG TIMSK2
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-#define PCINT15_REG PCMSK1
-
-/* PCMSK2 */
-#define PCINT16_REG PCMSK2
-#define PCINT17_REG PCMSK2
-#define PCINT18_REG PCMSK2
-#define PCINT19_REG PCMSK2
-#define PCINT20_REG PCMSK2
-#define PCINT21_REG PCMSK2
-#define PCINT22_REG PCMSK2
-#define PCINT23_REG PCMSK2
-
-/* PCMSK3 */
-#define PCINT24_REG PCMSK3
-#define PCINT25_REG PCMSK3
-#define PCINT26_REG PCMSK3
-#define PCINT27_REG PCMSK3
-#define PCINT28_REG PCMSK3
-#define PCINT29_REG PCMSK3
-#define PCINT30_REG PCMSK3
-#define PCINT31_REG PCMSK3
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-#define INTF2_REG EIFR
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-/* #define OCR1AH0_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH1_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH2_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH3_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH4_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH5_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH6_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH7_REG OCR1AH */ /* dup in OCR1BH */
-
-/* OCR1AL */
-/* #define OCR1AL0_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL1_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL2_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL3_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL4_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL5_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL6_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL7_REG OCR1AL */ /* dup in OCR1BL */
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* pins mapping */
-#define ADC0_PORT PORTA
-#define ADC0_BIT 0
-#define PCINT0_PORT PORTA
-#define PCINT0_BIT 0
-
-#define ADC1_PORT PORTA
-#define ADC1_BIT 1
-#define PCINT1_PORT PORTA
-#define PCINT1_BIT 1
-
-#define ADC2_PORT PORTA
-#define ADC2_BIT 2
-#define PCINT2_PORT PORTA
-#define PCINT2_BIT 2
-
-#define ADC3_PORT PORTA
-#define ADC3_BIT 3
-#define PCINT3_PORT PORTA
-#define PCINT3_BIT 3
-
-#define ADC4_PORT PORTA
-#define ADC4_BIT 4
-#define PCINT4_PORT PORTA
-#define PCINT4_BIT 4
-
-#define ADC5_PORT PORTA
-#define ADC5_BIT 5
-#define PCINT5_PORT PORTA
-#define PCINT5_BIT 5
-
-#define ADC6_PORT PORTA
-#define ADC6_BIT 6
-#define PCINT6_PORT PORTA
-#define PCINT6_BIT 6
-
-#define ADC7_PORT PORTA
-#define ADC7_BIT 7
-#define PCINT7_PORT PORTA
-#define PCINT7_BIT 7
-
-#define XCK_PORT PORTB
-#define XCK_BIT 0
-#define T0_PORT PORTB
-#define T0_BIT 0
-#define PCINT9_PORT PORTB
-#define PCINT9_BIT 0
-
-#define T1_PORT PORTB
-#define T1_BIT 1
-#define CLKO_PORT PORTB
-#define CLKO_BIT 1
-#define PCINT9_PORT PORTB
-#define PCINT9_BIT 1
-
-#define AIN0_PORT PORTB
-#define AIN0_BIT 2
-#define INT2_PORT PORTB
-#define INT2_BIT 2
-#define PCINT10_PORT PORTB
-#define PCINT10_BIT 2
-
-#define AIN1_PORT PORTB
-#define AIN1_BIT 3
-#define OC0A_PORT PORTB
-#define OC0A_BIT 3
-#define PCINT11_PORT PORTB
-#define PCINT11_BIT 3
-
-#define SS_PORT PORTB
-#define SS_BIT 4
-#define OC0B_PORT PORTB
-#define OC0B_BIT 4
-#define PCINT12_PORT PORTB
-#define PCINT12_BIT 4
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 5
-#define PCINT13_PORT PORTB
-#define PCINT13_BIT 5
-
-#define MISO_PORT PORTB
-#define MISO_BIT 6
-#define PCINT14_PORT PORTB
-#define PCINT14_BIT 6
-
-#define SCK_PORT PORTB
-#define SCK_BIT 7
-#define PCINT15_PORT PORTB
-#define PCINT15_BIT 7
-
-#define SCL_PORT PORTC
-#define SCL_BIT 0
-#define PCINT16_PORT PORTC
-#define PCINT16_BIT 0
-
-#define SDA_PORT PORTC
-#define SDA_BIT 1
-#define PCINT17_PORT PORTC
-#define PCINT17_BIT 1
-
-#define TCK_PORT PORTC
-#define TCK_BIT 2
-#define PCINT18_PORT PORTC
-#define PCINT18_BIT 2
-
-#define TMS_PORT PORTC
-#define TMS_BIT 3
-#define PCINT19_PORT PORTC
-#define PCINT19_BIT 3
-
-#define TDO_PORT PORTC
-#define TDO_BIT 4
-#define PCINT20_PORT PORTC
-#define PCINT20_BIT 4
-
-#define TDI_PORT PORTC
-#define TDI_BIT 5
-#define PCINT21_PORT PORTC
-#define PCINT21_BIT 5
-
-#define TOSC1_PORT PORTC
-#define TOSC1_BIT 6
-#define PCINT22_PORT PORTC
-#define PCINT22_BIT 6
-
-#define TOSC2_PORT PORTC
-#define TOSC2_BIT 7
-#define PCINT23_PORT PORTC
-#define PCINT23_BIT 7
-
-#define RXD_PORT PORTD
-#define RXD_BIT 0
-#define PCINT24_PORT PORTD
-#define PCINT24_BIT 0
-
-#define TXD_PORT PORTD
-#define TXD_BIT 1
-#define PCINT25_PORT PORTD
-#define PCINT25_BIT 1
-
-#define INT0_PORT PORTD
-#define INT0_BIT 2
-#define RDX1_PORT PORTD
-#define RDX1_BIT 2
-#define PCINT26_PORT PORTD
-#define PCINT26_BIT 2
-
-#define INT1_PORT PORTD
-#define INT1_BIT 3
-#define TXD1_PORT PORTD
-#define TXD1_BIT 3
-#define PCINT27_PORT PORTD
-#define PCINT27_BIT 3
-
-#define OC1B_PORT PORTD
-#define OC1B_BIT 4
-#define XCK1_PORT PORTD
-#define XCK1_BIT 4
-#define PCINT28_PORT PORTD
-#define PCINT28_BIT 4
-
-#define OC1A_PORT PORTD
-#define OC1A_BIT 5
-#define PCINT29_PORT PORTD
-#define PCINT29_BIT 5
-
-#define ICP_PORT PORTD
-#define ICP_BIT 6
-#define OC2B_PORT PORTD
-#define OC2B_BIT 6
-#define PCINT30_PORT PORTD
-#define PCINT30_BIT 6
-
-#define OC2A_PORT PORTD
-#define OC2A_BIT 7
-#define PCINT31_PORT PORTD
-#define PCINT31_BIT 7
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE1A_NUM 1
-#define SIG_OUTPUT_COMPARE1B_NUM 2
-#define SIG_OUTPUT_COMPARE2_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM1A_NUM 1
-#define PWM1B_NUM 2
-#define PWM2_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* OCR2A */
-#define OCR2A0_REG OCR2A
-#define OCR2A1_REG OCR2A
-#define OCR2A2_REG OCR2A
-#define OCR2A3_REG OCR2A
-#define OCR2A4_REG OCR2A
-#define OCR2A5_REG OCR2A
-#define OCR2A6_REG OCR2A
-#define OCR2A7_REG OCR2A
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSART0_REG PRR
-#define PRSPI_REG PRR
-#define PRTIM1_REG PRR
-#define PRLCD_REG PRR
-
-/* PORTF */
-#define PORTF0_REG PORTF
-#define PORTF1_REG PORTF
-#define PORTF2_REG PORTF
-#define PORTF3_REG PORTF
-#define PORTF4_REG PORTF
-#define PORTF5_REG PORTF
-#define PORTF6_REG PORTF
-#define PORTF7_REG PORTF
-
-/* PORTG */
-#define PORTG0_REG PORTG
-#define PORTG1_REG PORTG
-#define PORTG2_REG PORTG
-#define PORTG3_REG PORTG
-#define PORTG4_REG PORTG
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-#define PORTE3_REG PORTE
-#define PORTE4_REG PORTE
-#define PORTE5_REG PORTE
-#define PORTE6_REG PORTE
-#define PORTE7_REG PORTE
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* UDR0 */
-#define UDR00_REG UDR0
-#define UDR01_REG UDR0
-#define UDR02_REG UDR0
-#define UDR03_REG UDR0
-#define UDR04_REG UDR0
-#define UDR05_REG UDR0
-#define UDR06_REG UDR0
-#define UDR07_REG UDR0
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* ASSR */
-#define TCR2UB_REG ASSR
-#define OCR2UB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* DDRG */
-#define DDG0_REG DDRG
-#define DDG1_REG DDRG
-#define DDG2_REG DDRG
-#define DDG3_REG DDRG
-#define DDG4_REG DDRG
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-#define DDE3_REG DDRE
-#define DDE4_REG DDRE
-#define DDE5_REG DDRE
-#define DDE6_REG DDRE
-#define DDE7_REG DDRE
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TCCR0A */
-#define CS00_REG TCCR0A
-#define CS01_REG TCCR0A
-#define CS02_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-#define WGM00_REG TCCR0A
-#define FOC0A_REG TCCR0A
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* GTCCR */
-#define PSR310_REG GTCCR
-#define TSM_REG GTCCR
-#define PSR2_REG GTCCR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-#define JTRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TCCR2A */
-#define CS20_REG TCCR2A
-#define CS21_REG TCCR2A
-#define CS22_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-#define WGM20_REG TCCR2A
-#define FOC2A_REG TCCR2A
-
-/* UBRR0H */
-#define UBRR8_REG UBRR0H
-#define UBRR9_REG UBRR0H
-#define UBRR10_REG UBRR0H
-#define UBRR11_REG UBRR0H
-
-/* UBRR0L */
-#define UBRR0_REG UBRR0L
-#define UBRR1_REG UBRR0L
-#define UBRR2_REG UBRR0L
-#define UBRR3_REG UBRR0L
-#define UBRR4_REG UBRR0L
-#define UBRR5_REG UBRR0L
-#define UBRR6_REG UBRR0L
-#define UBRR7_REG UBRR0L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-#define EEAR10_REG EEARH
-
-/* EEARL */
-#define EEARL0_REG EEARL
-#define EEARL1_REG EEARL
-#define EEARL2_REG EEARL
-#define EEARL3_REG EEARL
-#define EEARL4_REG EEARL
-#define EEARL5_REG EEARL
-#define EEARL6_REG EEARL
-#define EEARL7_REG EEARL
-
-/* MCUCR */
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-#define JTD_REG MCUCR
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* USISR */
-#define USICNT0_REG USISR
-#define USICNT1_REG USISR
-#define USICNT2_REG USISR
-#define USICNT3_REG USISR
-#define USIDC_REG USISR
-#define USIPF_REG USISR
-#define USIOIF_REG USISR
-#define USISIF_REG USISR
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ACME_REG ADCSRB
-
-/* DDRF */
-#define DDF0_REG DDRF
-#define DDF1_REG DDRF
-#define DDF2_REG DDRF
-#define DDF3_REG DDRF
-#define DDF4_REG DDRF
-#define DDF5_REG DDRF
-#define DDF6_REG DDRF
-#define DDF7_REG DDRF
-
-/* OCR0A */
-#define OCR0A0_REG OCR0A
-#define OCR0A1_REG OCR0A
-#define OCR0A2_REG OCR0A
-#define OCR0A3_REG OCR0A
-#define OCR0A4_REG OCR0A
-#define OCR0A5_REG OCR0A
-#define OCR0A6_REG OCR0A
-#define OCR0A7_REG OCR0A
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* USICR */
-#define USITC_REG USICR
-#define USICLK_REG USICR
-#define USICS0_REG USICR
-#define USICS1_REG USICR
-#define USIWM0_REG USICR
-#define USIWM1_REG USICR
-#define USIOIE_REG USICR
-#define USISIE_REG USICR
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL0_REG UCSR0C
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define PCIE0_REG EIMSK
-#define PCIE1_REG EIMSK
-#define PCIE2_REG EIMSK
-#define PCIE3_REG EIMSK
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-#define PCINT15_REG PCMSK1
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define PCIF0_REG EIFR
-#define PCIF1_REG EIFR
-#define PCIF2_REG EIFR
-#define PCIF3_REG EIFR
-
-/* PING */
-#define PING0_REG PING
-#define PING1_REG PING
-#define PING2_REG PING
-#define PING3_REG PING
-#define PING4_REG PING
-#define PING5_REG PING
-
-/* PINF */
-#define PINF0_REG PINF
-#define PINF1_REG PINF
-#define PINF2_REG PINF
-#define PINF3_REG PINF
-#define PINF4_REG PINF
-#define PINF5_REG PINF
-#define PINF6_REG PINF
-#define PINF7_REG PINF
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-#define PINE3_REG PINE
-#define PINE4_REG PINE
-#define PINE5_REG PINE
-#define PINE6_REG PINE
-#define PINE7_REG PINE
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* USIDR */
-#define USIDR0_REG USIDR
-#define USIDR1_REG USIDR
-#define USIDR2_REG USIDR
-#define USIDR3_REG USIDR
-#define USIDR4_REG USIDR
-#define USIDR5_REG USIDR
-#define USIDR6_REG USIDR
-#define USIDR7_REG USIDR
-
-/* pins mapping */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE1A_NUM 1
-#define SIG_OUTPUT_COMPARE1B_NUM 2
-#define SIG_OUTPUT_COMPARE2_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM1A_NUM 1
-#define PWM1B_NUM 2
-#define PWM2_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* OCR2A */
-#define OCR2A0_REG OCR2A
-#define OCR2A1_REG OCR2A
-#define OCR2A2_REG OCR2A
-#define OCR2A3_REG OCR2A
-#define OCR2A4_REG OCR2A
-#define OCR2A5_REG OCR2A
-#define OCR2A6_REG OCR2A
-#define OCR2A7_REG OCR2A
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSART0_REG PRR
-#define PRSPI_REG PRR
-#define PRTIM1_REG PRR
-#define PRLCD_REG PRR
-
-/* PORTJ */
-#define PORTJ0_REG PORTJ
-#define PORTJ1_REG PORTJ
-#define PORTJ2_REG PORTJ
-#define PORTJ3_REG PORTJ
-#define PORTJ4_REG PORTJ
-#define PORTJ5_REG PORTJ
-#define PORTJ6_REG PORTJ
-
-/* PORTH */
-#define PORTH0_REG PORTH
-#define PORTH1_REG PORTH
-#define PORTH2_REG PORTH
-#define PORTH3_REG PORTH
-#define PORTH4_REG PORTH
-#define PORTH5_REG PORTH
-#define PORTH6_REG PORTH
-#define PORTH7_REG PORTH
-
-/* PORTF */
-#define PORTF0_REG PORTF
-#define PORTF1_REG PORTF
-#define PORTF2_REG PORTF
-#define PORTF3_REG PORTF
-#define PORTF4_REG PORTF
-#define PORTF5_REG PORTF
-#define PORTF6_REG PORTF
-#define PORTF7_REG PORTF
-
-/* PORTG */
-#define PORTG0_REG PORTG
-#define PORTG1_REG PORTG
-#define PORTG2_REG PORTG
-#define PORTG3_REG PORTG
-#define PORTG4_REG PORTG
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL0_REG UCSR0C
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-#define PORTE3_REG PORTE
-#define PORTE4_REG PORTE
-#define PORTE5_REG PORTE
-#define PORTE6_REG PORTE
-#define PORTE7_REG PORTE
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* UDR0 */
-#define UDR00_REG UDR0
-#define UDR01_REG UDR0
-#define UDR02_REG UDR0
-#define UDR03_REG UDR0
-#define UDR04_REG UDR0
-#define UDR05_REG UDR0
-#define UDR06_REG UDR0
-#define UDR07_REG UDR0
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* ASSR */
-#define TCR2UB_REG ASSR
-#define OCR2UB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRJ */
-#define DDJ0_REG DDRJ
-#define DDJ1_REG DDRJ
-#define DDJ2_REG DDRJ
-#define DDJ3_REG DDRJ
-#define DDJ4_REG DDRJ
-#define DDJ5_REG DDRJ
-#define DDJ6_REG DDRJ
-
-/* DDRH */
-#define DDH0_REG DDRH
-#define DDH1_REG DDRH
-#define DDH2_REG DDRH
-#define DDH3_REG DDRH
-#define DDH4_REG DDRH
-#define DDH5_REG DDRH
-#define DDH6_REG DDRH
-#define DDH7_REG DDRH
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* DDRG */
-#define DDG0_REG DDRG
-#define DDG1_REG DDRG
-#define DDG2_REG DDRG
-#define DDG3_REG DDRG
-#define DDG4_REG DDRG
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-#define DDE3_REG DDRE
-#define DDE4_REG DDRE
-#define DDE5_REG DDRE
-#define DDE6_REG DDRE
-#define DDE7_REG DDRE
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TCCR0A */
-#define CS00_REG TCCR0A
-#define CS01_REG TCCR0A
-#define CS02_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-#define WGM00_REG TCCR0A
-#define FOC0A_REG TCCR0A
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* GTCCR */
-#define PSR310_REG GTCCR
-#define TSM_REG GTCCR
-#define PSR2_REG GTCCR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-#define JTRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TCCR2A */
-#define CS20_REG TCCR2A
-#define CS21_REG TCCR2A
-#define CS22_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-#define WGM20_REG TCCR2A
-#define FOC2A_REG TCCR2A
-
-/* UBRR0H */
-#define UBRR8_REG UBRR0H
-#define UBRR9_REG UBRR0H
-#define UBRR10_REG UBRR0H
-#define UBRR11_REG UBRR0H
-
-/* UBRR0L */
-#define UBRR0_REG UBRR0L
-#define UBRR1_REG UBRR0L
-#define UBRR2_REG UBRR0L
-#define UBRR3_REG UBRR0L
-#define UBRR4_REG UBRR0L
-#define UBRR5_REG UBRR0L
-#define UBRR6_REG UBRR0L
-#define UBRR7_REG UBRR0L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-#define EEAR10_REG EEARH
-
-/* EEARL */
-#define EEARL0_REG EEARL
-#define EEARL1_REG EEARL
-#define EEARL2_REG EEARL
-#define EEARL3_REG EEARL
-#define EEARL4_REG EEARL
-#define EEARL5_REG EEARL
-#define EEARL6_REG EEARL
-#define EEARL7_REG EEARL
-
-/* MCUCR */
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-#define JTD_REG MCUCR
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ACME_REG ADCSRB
-
-/* DDRF */
-#define DDF0_REG DDRF
-#define DDF1_REG DDRF
-#define DDF2_REG DDRF
-#define DDF3_REG DDRF
-#define DDF4_REG DDRF
-#define DDF5_REG DDRF
-#define DDF6_REG DDRF
-#define DDF7_REG DDRF
-
-/* OCR0A */
-#define OCR0A0_REG OCR0A
-#define OCR0A1_REG OCR0A
-#define OCR0A2_REG OCR0A
-#define OCR0A3_REG OCR0A
-#define OCR0A4_REG OCR0A
-#define OCR0A5_REG OCR0A
-#define OCR0A6_REG OCR0A
-#define OCR0A7_REG OCR0A
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* USICR */
-#define USITC_REG USICR
-#define USICLK_REG USICR
-#define USICS0_REG USICR
-#define USICS1_REG USICR
-#define USIWM0_REG USICR
-#define USIWM1_REG USICR
-#define USIOIE_REG USICR
-#define USISIE_REG USICR
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* USISR */
-#define USICNT0_REG USISR
-#define USICNT1_REG USISR
-#define USICNT2_REG USISR
-#define USICNT3_REG USISR
-#define USIDC_REG USISR
-#define USIPF_REG USISR
-#define USIOIF_REG USISR
-#define USISIF_REG USISR
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define PCIE0_REG EIMSK
-#define PCIE1_REG EIMSK
-#define PCIE2_REG EIMSK
-#define PCIE3_REG EIMSK
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* PINJ */
-#define PINJ0_REG PINJ
-#define PINJ1_REG PINJ
-#define PINJ2_REG PINJ
-#define PINJ3_REG PINJ
-#define PINJ4_REG PINJ
-#define PINJ5_REG PINJ
-#define PINJ6_REG PINJ
-
-/* PINH */
-#define PINH0_REG PINH
-#define PINH1_REG PINH
-#define PINH2_REG PINH
-#define PINH3_REG PINH
-#define PINH4_REG PINH
-#define PINH5_REG PINH
-#define PINH6_REG PINH
-#define PINH7_REG PINH
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-#define PCINT15_REG PCMSK1
-
-/* PCMSK2 */
-#define PCINT16_REG PCMSK2
-#define PCINT17_REG PCMSK2
-#define PCINT18_REG PCMSK2
-#define PCINT19_REG PCMSK2
-#define PCINT20_REG PCMSK2
-#define PCINT21_REG PCMSK2
-#define PCINT22_REG PCMSK2
-#define PCINT23_REG PCMSK2
-
-/* PCMSK3 */
-#define PCINT24_REG PCMSK3
-#define PCINT25_REG PCMSK3
-#define PCINT26_REG PCMSK3
-#define PCINT27_REG PCMSK3
-#define PCINT28_REG PCMSK3
-#define PCINT29_REG PCMSK3
-#define PCINT30_REG PCMSK3
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define PCIF0_REG EIFR
-#define PCIF1_REG EIFR
-#define PCIF2_REG EIFR
-#define PCIF3_REG EIFR
-
-/* PING */
-#define PING0_REG PING
-#define PING1_REG PING
-#define PING2_REG PING
-#define PING3_REG PING
-#define PING4_REG PING
-#define PING5_REG PING
-
-/* PINF */
-#define PINF0_REG PINF
-#define PINF1_REG PINF
-#define PINF2_REG PINF
-#define PINF3_REG PINF
-#define PINF4_REG PINF
-#define PINF5_REG PINF
-#define PINF6_REG PINF
-#define PINF7_REG PINF
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-#define PINE3_REG PINE
-#define PINE4_REG PINE
-#define PINE5_REG PINE
-#define PINE6_REG PINE
-#define PINE7_REG PINE
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* USIDR */
-#define USIDR0_REG USIDR
-#define USIDR1_REG USIDR
-#define USIDR2_REG USIDR
-#define USIDR3_REG USIDR
-#define USIDR4_REG USIDR
-#define USIDR5_REG USIDR
-#define USIDR6_REG USIDR
-#define USIDR7_REG USIDR
-
-/* pins mapping */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE1A_NUM 1
-#define SIG_OUTPUT_COMPARE1B_NUM 2
-#define SIG_OUTPUT_COMPARE2_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM1A_NUM 1
-#define PWM1B_NUM 2
-#define PWM2_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* OCR2A */
-#define OCR2A0_REG OCR2A
-#define OCR2A1_REG OCR2A
-#define OCR2A2_REG OCR2A
-#define OCR2A3_REG OCR2A
-#define OCR2A4_REG OCR2A
-#define OCR2A5_REG OCR2A
-#define OCR2A6_REG OCR2A
-#define OCR2A7_REG OCR2A
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSART0_REG PRR
-#define PRSPI_REG PRR
-#define PRTIM1_REG PRR
-#define PRLCD_REG PRR
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* PORTG */
-#define PORTG0_REG PORTG
-#define PORTG1_REG PORTG
-#define PORTG2_REG PORTG
-#define PORTG3_REG PORTG
-#define PORTG4_REG PORTG
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL0_REG UCSR0C
-
-/* USISR */
-#define USICNT0_REG USISR
-#define USICNT1_REG USISR
-#define USICNT2_REG USISR
-#define USICNT3_REG USISR
-#define USIDC_REG USISR
-#define USIPF_REG USISR
-#define USIOIF_REG USISR
-#define USISIF_REG USISR
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* UDR0 */
-#define UDR00_REG UDR0
-#define UDR01_REG UDR0
-#define UDR02_REG UDR0
-#define UDR03_REG UDR0
-#define UDR04_REG UDR0
-#define UDR05_REG UDR0
-#define UDR06_REG UDR0
-#define UDR07_REG UDR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* ASSR */
-#define TCR2UB_REG ASSR
-#define OCR2UB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* DDRG */
-#define DDG0_REG DDRG
-#define DDG1_REG DDRG
-#define DDG2_REG DDRG
-#define DDG3_REG DDRG
-#define DDG4_REG DDRG
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* LCDDR3 */
-#define SEG024_REG LCDDR3
-
-/* LCDDR2 */
-#define SEG016_REG LCDDR2
-#define SEG017_REG LCDDR2
-#define SEG018_REG LCDDR2
-#define SEG019_REG LCDDR2
-#define SEG020_REG LCDDR2
-#define SEG021_REG LCDDR2
-#define SEG022_REG LCDDR2
-#define SEG023_REG LCDDR2
-
-/* LCDDR1 */
-#define SEG008_REG LCDDR1
-#define SEG009_REG LCDDR1
-#define SEG010_REG LCDDR1
-#define SEG011_REG LCDDR1
-#define SEG012_REG LCDDR1
-#define SEG013_REG LCDDR1
-#define SEG014_REG LCDDR1
-#define SEG015_REG LCDDR1
-
-/* LCDDR0 */
-#define SEG000_REG LCDDR0
-#define SEG001_REG LCDDR0
-#define SEG002_REG LCDDR0
-#define SEG003_REG LCDDR0
-#define SEG004_REG LCDDR0
-#define SEG005_REG LCDDR0
-#define SEG006_REG LCDDR0
-#define SEG007_REG LCDDR0
-
-/* LCDDR7 */
-#define SEG116_REG LCDDR7
-#define SEG117_REG LCDDR7
-#define SEG118_REG LCDDR7
-#define SEG119_REG LCDDR7
-#define SEG120_REG LCDDR7
-#define SEG121_REG LCDDR7
-#define SEG122_REG LCDDR7
-#define SEG123_REG LCDDR7
-
-/* LCDDR6 */
-#define SEG108_REG LCDDR6
-#define SEG109_REG LCDDR6
-#define SEG110_REG LCDDR6
-#define SEG111_REG LCDDR6
-#define SEG112_REG LCDDR6
-#define SEG113_REG LCDDR6
-#define SEG114_REG LCDDR6
-#define SEG115_REG LCDDR6
-
-/* LCDDR5 */
-#define SEG100_REG LCDDR5
-#define SEG101_REG LCDDR5
-#define SEG102_REG LCDDR5
-#define SEG103_REG LCDDR5
-#define SEG104_REG LCDDR5
-#define SEG105_REG LCDDR5
-#define SEG106_REG LCDDR5
-#define SEG107_REG LCDDR5
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* LCDDR8 */
-#define SEG124_REG LCDDR8
-
-/* LCDCRA */
-#define LCDBL_REG LCDCRA
-#define LCDIE_REG LCDCRA
-#define LCDIF_REG LCDCRA
-#define LCDAB_REG LCDCRA
-#define LCDEN_REG LCDCRA
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-#define DDE3_REG DDRE
-#define DDE4_REG DDRE
-#define DDE5_REG DDRE
-#define DDE6_REG DDRE
-#define DDE7_REG DDRE
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TCCR0A */
-#define CS00_REG TCCR0A
-#define CS01_REG TCCR0A
-#define CS02_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-#define WGM00_REG TCCR0A
-#define FOC0A_REG TCCR0A
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* GTCCR */
-#define PSR310_REG GTCCR
-#define TSM_REG GTCCR
-#define PSR2_REG GTCCR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* LCDCRB */
-#define LCDPM0_REG LCDCRB
-#define LCDPM1_REG LCDCRB
-#define LCDPM2_REG LCDCRB
-#define LCDPM3_REG LCDCRB
-#define LCDMUX0_REG LCDCRB
-#define LCDMUX1_REG LCDCRB
-#define LCD2B_REG LCDCRB
-#define LCDCS_REG LCDCRB
-
-/* LCDDR18 */
-#define SEG324_REG LCDDR18
-
-/* LCDDR13 */
-#define SEG224_REG LCDDR13
-
-/* LCDDR12 */
-#define SEG216_REG LCDDR12
-#define SEG217_REG LCDDR12
-#define SEG218_REG LCDDR12
-#define SEG219_REG LCDDR12
-#define SEG220_REG LCDDR12
-#define SEG221_REG LCDDR12
-#define SEG222_REG LCDDR12
-#define SEG223_REG LCDDR12
-
-/* LCDDR11 */
-#define SEG208_REG LCDDR11
-#define SEG209_REG LCDDR11
-#define SEG210_REG LCDDR11
-#define SEG211_REG LCDDR11
-#define SEG212_REG LCDDR11
-#define SEG213_REG LCDDR11
-#define SEG214_REG LCDDR11
-#define SEG215_REG LCDDR11
-
-/* LCDDR10 */
-#define SEG200_REG LCDDR10
-#define SEG201_REG LCDDR10
-#define SEG202_REG LCDDR10
-#define SEG203_REG LCDDR10
-#define SEG204_REG LCDDR10
-#define SEG205_REG LCDDR10
-#define SEG206_REG LCDDR10
-#define SEG207_REG LCDDR10
-
-/* LCDDR17 */
-#define SEG316_REG LCDDR17
-#define SEG317_REG LCDDR17
-#define SEG318_REG LCDDR17
-#define SEG319_REG LCDDR17
-#define SEG320_REG LCDDR17
-#define SEG321_REG LCDDR17
-#define SEG322_REG LCDDR17
-#define SEG323_REG LCDDR17
-
-/* LCDDR16 */
-#define SEG308_REG LCDDR16
-#define SEG309_REG LCDDR16
-#define SEG310_REG LCDDR16
-#define SEG311_REG LCDDR16
-#define SEG312_REG LCDDR16
-#define SEG313_REG LCDDR16
-#define SEG314_REG LCDDR16
-#define SEG315_REG LCDDR16
-
-/* LCDDR15 */
-#define SEG300_REG LCDDR15
-#define SEG301_REG LCDDR15
-#define SEG302_REG LCDDR15
-#define SEG303_REG LCDDR15
-#define SEG304_REG LCDDR15
-#define SEG305_REG LCDDR15
-#define SEG306_REG LCDDR15
-#define SEG307_REG LCDDR15
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-#define JTRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TCCR2A */
-#define CS20_REG TCCR2A
-#define CS21_REG TCCR2A
-#define CS22_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-#define WGM20_REG TCCR2A
-#define FOC2A_REG TCCR2A
-
-/* UBRR0H */
-#define UBRR8_REG UBRR0H
-#define UBRR9_REG UBRR0H
-#define UBRR10_REG UBRR0H
-#define UBRR11_REG UBRR0H
-
-/* UBRR0L */
-#define UBRR0_REG UBRR0L
-#define UBRR1_REG UBRR0L
-#define UBRR2_REG UBRR0L
-#define UBRR3_REG UBRR0L
-#define UBRR4_REG UBRR0L
-#define UBRR5_REG UBRR0L
-#define UBRR6_REG UBRR0L
-#define UBRR7_REG UBRR0L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-#define EEAR10_REG EEARH
-
-/* EEARL */
-#define EEARL0_REG EEARL
-#define EEARL1_REG EEARL
-#define EEARL2_REG EEARL
-#define EEARL3_REG EEARL
-#define EEARL4_REG EEARL
-#define EEARL5_REG EEARL
-#define EEARL6_REG EEARL
-#define EEARL7_REG EEARL
-
-/* MCUCR */
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-#define JTD_REG MCUCR
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-#define PORTE3_REG PORTE
-#define PORTE4_REG PORTE
-#define PORTE5_REG PORTE
-#define PORTE6_REG PORTE
-#define PORTE7_REG PORTE
-
-/* LCDCCR */
-#define LCDCC0_REG LCDCCR
-#define LCDCC1_REG LCDCCR
-#define LCDCC2_REG LCDCCR
-#define LCDCC3_REG LCDCCR
-#define LCDDC0_REG LCDCCR
-#define LCDDC1_REG LCDCCR
-#define LCDDC2_REG LCDCCR
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-#define PINE3_REG PINE
-#define PINE4_REG PINE
-#define PINE5_REG PINE
-#define PINE6_REG PINE
-#define PINE7_REG PINE
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ACME_REG ADCSRB
-
-/* DDRF */
-#define DDF0_REG DDRF
-#define DDF1_REG DDRF
-#define DDF2_REG DDRF
-#define DDF3_REG DDRF
-#define DDF4_REG DDRF
-#define DDF5_REG DDRF
-#define DDF6_REG DDRF
-#define DDF7_REG DDRF
-
-/* OCR0A */
-#define OCR0A0_REG OCR0A
-#define OCR0A1_REG OCR0A
-#define OCR0A2_REG OCR0A
-#define OCR0A3_REG OCR0A
-#define OCR0A4_REG OCR0A
-#define OCR0A5_REG OCR0A
-#define OCR0A6_REG OCR0A
-#define OCR0A7_REG OCR0A
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* USICR */
-#define USITC_REG USICR
-#define USICLK_REG USICR
-#define USICS0_REG USICR
-#define USICS1_REG USICR
-#define USIWM0_REG USICR
-#define USIWM1_REG USICR
-#define USIOIE_REG USICR
-#define USISIE_REG USICR
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* LCDFRR */
-#define LCDCD0_REG LCDFRR
-#define LCDCD1_REG LCDFRR
-#define LCDCD2_REG LCDFRR
-#define LCDPS0_REG LCDFRR
-#define LCDPS1_REG LCDFRR
-#define LCDPS2_REG LCDFRR
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define PCIE0_REG EIMSK
-#define PCIE1_REG EIMSK
-#define PCIE2_REG EIMSK
-#define PCIE3_REG EIMSK
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-#define PCINT15_REG PCMSK1
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define PCIF0_REG EIFR
-#define PCIF1_REG EIFR
-#define PCIF2_REG EIFR
-#define PCIF3_REG EIFR
-
-/* PING */
-#define PING0_REG PING
-#define PING1_REG PING
-#define PING2_REG PING
-#define PING3_REG PING
-#define PING4_REG PING
-#define PING5_REG PING
-
-/* PINF */
-#define PINF0_REG PINF
-#define PINF1_REG PINF
-#define PINF2_REG PINF
-#define PINF3_REG PINF
-#define PINF4_REG PINF
-#define PINF5_REG PINF
-#define PINF6_REG PINF
-#define PINF7_REG PINF
-
-/* PORTF */
-#define PORTF0_REG PORTF
-#define PORTF1_REG PORTF
-#define PORTF2_REG PORTF
-#define PORTF3_REG PORTF
-#define PORTF4_REG PORTF
-#define PORTF5_REG PORTF
-#define PORTF6_REG PORTF
-#define PORTF7_REG PORTF
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-
-/* USIDR */
-#define USIDR0_REG USIDR
-#define USIDR1_REG USIDR
-#define USIDR2_REG USIDR
-#define USIDR3_REG USIDR
-#define USIDR4_REG USIDR
-#define USIDR5_REG USIDR
-#define USIDR6_REG USIDR
-#define USIDR7_REG USIDR
-
-/* pins mapping */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE1A_NUM 1
-#define SIG_OUTPUT_COMPARE1B_NUM 2
-#define SIG_OUTPUT_COMPARE2_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM1A_NUM 1
-#define PWM1B_NUM 2
-#define PWM2_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* OCR2A */
-#define OCR2A0_REG OCR2A
-#define OCR2A1_REG OCR2A
-#define OCR2A2_REG OCR2A
-#define OCR2A3_REG OCR2A
-#define OCR2A4_REG OCR2A
-#define OCR2A5_REG OCR2A
-#define OCR2A6_REG OCR2A
-#define OCR2A7_REG OCR2A
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSART0_REG PRR
-#define PRSPI_REG PRR
-#define PRTIM1_REG PRR
-#define PRLCD_REG PRR
-
-/* PORTJ */
-#define PORTJ0_REG PORTJ
-#define PORTJ1_REG PORTJ
-#define PORTJ2_REG PORTJ
-#define PORTJ3_REG PORTJ
-#define PORTJ4_REG PORTJ
-#define PORTJ5_REG PORTJ
-#define PORTJ6_REG PORTJ
-
-/* PORTH */
-#define PORTH0_REG PORTH
-#define PORTH1_REG PORTH
-#define PORTH2_REG PORTH
-#define PORTH3_REG PORTH
-#define PORTH4_REG PORTH
-#define PORTH5_REG PORTH
-#define PORTH6_REG PORTH
-#define PORTH7_REG PORTH
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* PORTG */
-#define PORTG0_REG PORTG
-#define PORTG1_REG PORTG
-#define PORTG2_REG PORTG
-#define PORTG3_REG PORTG
-#define PORTG4_REG PORTG
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL0_REG UCSR0C
-
-/* USISR */
-#define USICNT0_REG USISR
-#define USICNT1_REG USISR
-#define USICNT2_REG USISR
-#define USICNT3_REG USISR
-#define USIDC_REG USISR
-#define USIPF_REG USISR
-#define USIOIF_REG USISR
-#define USISIF_REG USISR
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* UDR0 */
-#define UDR00_REG UDR0
-#define UDR01_REG UDR0
-#define UDR02_REG UDR0
-#define UDR03_REG UDR0
-#define UDR04_REG UDR0
-#define UDR05_REG UDR0
-#define UDR06_REG UDR0
-#define UDR07_REG UDR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* ASSR */
-#define TCR2UB_REG ASSR
-#define OCR2UB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRJ */
-#define DDJ0_REG DDRJ
-#define DDJ1_REG DDRJ
-#define DDJ2_REG DDRJ
-#define DDJ3_REG DDRJ
-#define DDJ4_REG DDRJ
-#define DDJ5_REG DDRJ
-#define DDJ6_REG DDRJ
-
-/* DDRH */
-#define DDH0_REG DDRH
-#define DDH1_REG DDRH
-#define DDH2_REG DDRH
-#define DDH3_REG DDRH
-#define DDH4_REG DDRH
-#define DDH5_REG DDRH
-#define DDH6_REG DDRH
-#define DDH7_REG DDRH
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* DDRG */
-#define DDG0_REG DDRG
-#define DDG1_REG DDRG
-#define DDG2_REG DDRG
-#define DDG3_REG DDRG
-#define DDG4_REG DDRG
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* LCDDR3 */
-#define SEG024_REG LCDDR3
-#define SEG025_REG LCDDR3
-#define SEG026_REG LCDDR3
-#define SEG027_REG LCDDR3
-#define SEG028_REG LCDDR3
-#define SEG029_REG LCDDR3
-#define SEG030_REG LCDDR3
-#define SEG031_REG LCDDR3
-
-/* LCDDR2 */
-#define SEG016_REG LCDDR2
-#define SEG017_REG LCDDR2
-#define SEG018_REG LCDDR2
-#define SEG019_REG LCDDR2
-#define SEG020_REG LCDDR2
-#define SEG021_REG LCDDR2
-#define SEG022_REG LCDDR2
-#define SEG023_REG LCDDR2
-
-/* LCDDR1 */
-#define SEG008_REG LCDDR1
-#define SEG009_REG LCDDR1
-#define SEG010_REG LCDDR1
-#define SEG011_REG LCDDR1
-#define SEG012_REG LCDDR1
-#define SEG013_REG LCDDR1
-#define SEG014_REG LCDDR1
-#define SEG015_REG LCDDR1
-
-/* LCDDR0 */
-#define SEG000_REG LCDDR0
-#define SEG001_REG LCDDR0
-#define SEG002_REG LCDDR0
-#define SEG003_REG LCDDR0
-#define SEG004_REG LCDDR0
-#define SEG005_REG LCDDR0
-#define SEG006_REG LCDDR0
-#define SEG007_REG LCDDR0
-
-/* LCDDR7 */
-#define SEG116_REG LCDDR7
-#define SEG117_REG LCDDR7
-#define SEG118_REG LCDDR7
-#define SEG119_REG LCDDR7
-#define SEG120_REG LCDDR7
-#define SEG121_REG LCDDR7
-#define SEG122_REG LCDDR7
-#define SEG123_REG LCDDR7
-
-/* LCDDR6 */
-#define SEG108_REG LCDDR6
-#define SEG109_REG LCDDR6
-#define SEG110_REG LCDDR6
-#define SEG111_REG LCDDR6
-#define SEG112_REG LCDDR6
-#define SEG113_REG LCDDR6
-#define SEG114_REG LCDDR6
-#define SEG115_REG LCDDR6
-
-/* LCDDR5 */
-#define SEG100_REG LCDDR5
-#define SEG101_REG LCDDR5
-#define SEG102_REG LCDDR5
-#define SEG103_REG LCDDR5
-#define SEG104_REG LCDDR5
-#define SEG105_REG LCDDR5
-#define SEG106_REG LCDDR5
-#define SEG107_REG LCDDR5
-
-/* LCDDR4 */
-#define SEG032_REG LCDDR4
-#define SEG033_REG LCDDR4
-#define SEG034_REG LCDDR4
-#define SEG035_REG LCDDR4
-#define SEG036_REG LCDDR4
-#define SEG037_REG LCDDR4
-#define SEG038_REG LCDDR4
-#define SEG039_REG LCDDR4
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* LCDDR9 */
-#define SEG132_REG LCDDR9
-#define SEG133_REG LCDDR9
-#define SEG134_REG LCDDR9
-#define SEG135_REG LCDDR9
-#define SEG136_REG LCDDR9
-#define SEG137_REG LCDDR9
-#define SEG138_REG LCDDR9
-#define SEG139_REG LCDDR9
-
-/* LCDDR8 */
-#define SEG124_REG LCDDR8
-#define SEG125_REG LCDDR8
-#define SEG126_REG LCDDR8
-#define SEG127_REG LCDDR8
-#define SEG128_REG LCDDR8
-#define SEG129_REG LCDDR8
-#define SEG130_REG LCDDR8
-#define SEG131_REG LCDDR8
-
-/* LCDCRA */
-#define LCDBL_REG LCDCRA
-#define LCDIE_REG LCDCRA
-#define LCDIF_REG LCDCRA
-#define LCDAB_REG LCDCRA
-#define LCDEN_REG LCDCRA
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-#define DDE3_REG DDRE
-#define DDE4_REG DDRE
-#define DDE5_REG DDRE
-#define DDE6_REG DDRE
-#define DDE7_REG DDRE
-
-/* LCDCRB */
-#define LCDPM0_REG LCDCRB
-#define LCDPM1_REG LCDCRB
-#define LCDPM2_REG LCDCRB
-#define LCDPM3_REG LCDCRB
-#define LCDMUX0_REG LCDCRB
-#define LCDMUX1_REG LCDCRB
-#define LCD2B_REG LCDCRB
-#define LCDCS_REG LCDCRB
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TCCR0A */
-#define CS00_REG TCCR0A
-#define CS01_REG TCCR0A
-#define CS02_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-#define WGM00_REG TCCR0A
-#define FOC0A_REG TCCR0A
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* GTCCR */
-#define PSR310_REG GTCCR
-#define TSM_REG GTCCR
-#define PSR2_REG GTCCR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* LCDDR19 */
-#define SEG332_REG LCDDR19
-#define SEG333_REG LCDDR19
-#define SEG334_REG LCDDR19
-#define SEG335_REG LCDDR19
-#define SEG336_REG LCDDR19
-#define SEG337_REG LCDDR19
-#define SEG338_REG LCDDR19
-#define SEG339_REG LCDDR19
-
-/* LCDDR18 */
-#define SEG324_REG LCDDR18
-#define SEG325_REG LCDDR18
-#define SEG326_REG LCDDR18
-#define SEG327_REG LCDDR18
-#define SEG328_REG LCDDR18
-#define SEG329_REG LCDDR18
-#define SEG330_REG LCDDR18
-#define SEG331_REG LCDDR18
-
-/* LCDDR13 */
-#define SEG224_REG LCDDR13
-#define SEG225_REG LCDDR13
-#define SEG226_REG LCDDR13
-#define SEG227_REG LCDDR13
-#define SEG228_REG LCDDR13
-#define SEG229_REG LCDDR13
-#define SEG230_REG LCDDR13
-#define SEG231_REG LCDDR13
-
-/* LCDDR12 */
-#define SEG216_REG LCDDR12
-#define SEG217_REG LCDDR12
-#define SEG218_REG LCDDR12
-#define SEG219_REG LCDDR12
-#define SEG220_REG LCDDR12
-#define SEG221_REG LCDDR12
-#define SEG222_REG LCDDR12
-#define SEG223_REG LCDDR12
-
-/* LCDDR11 */
-#define SEG208_REG LCDDR11
-#define SEG209_REG LCDDR11
-#define SEG210_REG LCDDR11
-#define SEG211_REG LCDDR11
-#define SEG212_REG LCDDR11
-#define SEG213_REG LCDDR11
-#define SEG214_REG LCDDR11
-#define SEG215_REG LCDDR11
-
-/* LCDDR10 */
-#define SEG200_REG LCDDR10
-#define SEG201_REG LCDDR10
-#define SEG202_REG LCDDR10
-#define SEG203_REG LCDDR10
-#define SEG204_REG LCDDR10
-#define SEG205_REG LCDDR10
-#define SEG206_REG LCDDR10
-#define SEG207_REG LCDDR10
-
-/* LCDDR17 */
-#define SEG316_REG LCDDR17
-#define SEG317_REG LCDDR17
-#define SEG318_REG LCDDR17
-#define SEG319_REG LCDDR17
-#define SEG320_REG LCDDR17
-#define SEG321_REG LCDDR17
-#define SEG322_REG LCDDR17
-#define SEG323_REG LCDDR17
-
-/* LCDDR16 */
-#define SEG308_REG LCDDR16
-#define SEG309_REG LCDDR16
-#define SEG310_REG LCDDR16
-#define SEG311_REG LCDDR16
-#define SEG312_REG LCDDR16
-#define SEG313_REG LCDDR16
-#define SEG314_REG LCDDR16
-#define SEG315_REG LCDDR16
-
-/* LCDDR15 */
-#define SEG300_REG LCDDR15
-#define SEG301_REG LCDDR15
-#define SEG302_REG LCDDR15
-#define SEG303_REG LCDDR15
-#define SEG304_REG LCDDR15
-#define SEG305_REG LCDDR15
-#define SEG306_REG LCDDR15
-#define SEG307_REG LCDDR15
-
-/* LCDDR14 */
-#define SEG232_REG LCDDR14
-#define SEG233_REG LCDDR14
-#define SEG234_REG LCDDR14
-#define SEG235_REG LCDDR14
-#define SEG236_REG LCDDR14
-#define SEG237_REG LCDDR14
-#define SEG238_REG LCDDR14
-#define SEG239_REG LCDDR14
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-#define JTRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TCCR2A */
-#define CS20_REG TCCR2A
-#define CS21_REG TCCR2A
-#define CS22_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-#define WGM20_REG TCCR2A
-#define FOC2A_REG TCCR2A
-
-/* UBRR0H */
-#define UBRR8_REG UBRR0H
-#define UBRR9_REG UBRR0H
-#define UBRR10_REG UBRR0H
-#define UBRR11_REG UBRR0H
-
-/* UBRR0L */
-#define UBRR0_REG UBRR0L
-#define UBRR1_REG UBRR0L
-#define UBRR2_REG UBRR0L
-#define UBRR3_REG UBRR0L
-#define UBRR4_REG UBRR0L
-#define UBRR5_REG UBRR0L
-#define UBRR6_REG UBRR0L
-#define UBRR7_REG UBRR0L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-#define EEAR10_REG EEARH
-
-/* EEARL */
-#define EEARL0_REG EEARL
-#define EEARL1_REG EEARL
-#define EEARL2_REG EEARL
-#define EEARL3_REG EEARL
-#define EEARL4_REG EEARL
-#define EEARL5_REG EEARL
-#define EEARL6_REG EEARL
-#define EEARL7_REG EEARL
-
-/* MCUCR */
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-#define JTD_REG MCUCR
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-#define PORTE3_REG PORTE
-#define PORTE4_REG PORTE
-#define PORTE5_REG PORTE
-#define PORTE6_REG PORTE
-#define PORTE7_REG PORTE
-
-/* LCDCCR */
-#define LCDCC0_REG LCDCCR
-#define LCDCC1_REG LCDCCR
-#define LCDCC2_REG LCDCCR
-#define LCDCC3_REG LCDCCR
-#define LCDDC0_REG LCDCCR
-#define LCDDC1_REG LCDCCR
-#define LCDDC2_REG LCDCCR
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-#define PINE3_REG PINE
-#define PINE4_REG PINE
-#define PINE5_REG PINE
-#define PINE6_REG PINE
-#define PINE7_REG PINE
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ACME_REG ADCSRB
-
-/* DDRF */
-#define DDF0_REG DDRF
-#define DDF1_REG DDRF
-#define DDF2_REG DDRF
-#define DDF3_REG DDRF
-#define DDF4_REG DDRF
-#define DDF5_REG DDRF
-#define DDF6_REG DDRF
-#define DDF7_REG DDRF
-
-/* OCR0A */
-#define OCR0A0_REG OCR0A
-#define OCR0A1_REG OCR0A
-#define OCR0A2_REG OCR0A
-#define OCR0A3_REG OCR0A
-#define OCR0A4_REG OCR0A
-#define OCR0A5_REG OCR0A
-#define OCR0A6_REG OCR0A
-#define OCR0A7_REG OCR0A
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* USICR */
-#define USITC_REG USICR
-#define USICLK_REG USICR
-#define USICS0_REG USICR
-#define USICS1_REG USICR
-#define USIWM0_REG USICR
-#define USIWM1_REG USICR
-#define USIOIE_REG USICR
-#define USISIE_REG USICR
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* LCDFRR */
-#define LCDCD0_REG LCDFRR
-#define LCDCD1_REG LCDFRR
-#define LCDCD2_REG LCDFRR
-#define LCDPS0_REG LCDFRR
-#define LCDPS1_REG LCDFRR
-#define LCDPS2_REG LCDFRR
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define PCIE0_REG EIMSK
-#define PCIE1_REG EIMSK
-#define PCIE2_REG EIMSK
-#define PCIE3_REG EIMSK
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* PINJ */
-#define PINJ0_REG PINJ
-#define PINJ1_REG PINJ
-#define PINJ2_REG PINJ
-#define PINJ3_REG PINJ
-#define PINJ4_REG PINJ
-#define PINJ5_REG PINJ
-#define PINJ6_REG PINJ
-
-/* PINH */
-#define PINH0_REG PINH
-#define PINH1_REG PINH
-#define PINH2_REG PINH
-#define PINH3_REG PINH
-#define PINH4_REG PINH
-#define PINH5_REG PINH
-#define PINH6_REG PINH
-#define PINH7_REG PINH
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-#define PCINT15_REG PCMSK1
-
-/* PCMSK2 */
-#define PCINT16_REG PCMSK2
-#define PCINT17_REG PCMSK2
-#define PCINT18_REG PCMSK2
-#define PCINT19_REG PCMSK2
-#define PCINT20_REG PCMSK2
-#define PCINT21_REG PCMSK2
-#define PCINT22_REG PCMSK2
-#define PCINT23_REG PCMSK2
-
-/* PCMSK3 */
-#define PCINT24_REG PCMSK3
-#define PCINT25_REG PCMSK3
-#define PCINT26_REG PCMSK3
-#define PCINT27_REG PCMSK3
-#define PCINT28_REG PCMSK3
-#define PCINT29_REG PCMSK3
-#define PCINT30_REG PCMSK3
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define PCIF0_REG EIFR
-#define PCIF1_REG EIFR
-#define PCIF2_REG EIFR
-#define PCIF3_REG EIFR
-
-/* PING */
-#define PING0_REG PING
-#define PING1_REG PING
-#define PING2_REG PING
-#define PING3_REG PING
-#define PING4_REG PING
-#define PING5_REG PING
-
-/* PINF */
-#define PINF0_REG PINF
-#define PINF1_REG PINF
-#define PINF2_REG PINF
-#define PINF3_REG PINF
-#define PINF4_REG PINF
-#define PINF5_REG PINF
-#define PINF6_REG PINF
-#define PINF7_REG PINF
-
-/* PORTF */
-#define PORTF0_REG PORTF
-#define PORTF1_REG PORTF
-#define PORTF2_REG PORTF
-#define PORTF3_REG PORTF
-#define PORTF4_REG PORTF
-#define PORTF5_REG PORTF
-#define PORTF6_REG PORTF
-#define PORTF7_REG PORTF
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-
-/* USIDR */
-#define USIDR0_REG USIDR
-#define USIDR1_REG USIDR
-#define USIDR2_REG USIDR
-#define USIDR3_REG USIDR
-#define USIDR4_REG USIDR
-#define USIDR5_REG USIDR
-#define USIDR6_REG USIDR
-#define USIDR7_REG USIDR
-
-/* pins mapping */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_32 3
-#define TIMER0_PRESCALER_DIV_64 4
-#define TIMER0_PRESCALER_DIV_128 5
-#define TIMER0_PRESCALER_DIV_256 6
-#define TIMER0_PRESCALER_DIV_1024 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 32
-#define TIMER0_PRESCALER_REG_4 64
-#define TIMER0_PRESCALER_REG_5 128
-#define TIMER0_PRESCALER_REG_6 256
-#define TIMER0_PRESCALER_REG_7 1024
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_64 3
-#define TIMER2_PRESCALER_DIV_256 4
-#define TIMER2_PRESCALER_DIV_1024 5
-#define TIMER2_PRESCALER_DIV_FALL 6
-#define TIMER2_PRESCALER_DIV_RISE 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 64
-#define TIMER2_PRESCALER_REG_4 256
-#define TIMER2_PRESCALER_REG_5 1024
-#define TIMER2_PRESCALER_REG_6 -1
-#define TIMER2_PRESCALER_REG_7 -2
-
-/* prescalers timer 3 */
-#define TIMER3_PRESCALER_DIV_0 0
-#define TIMER3_PRESCALER_DIV_1 1
-#define TIMER3_PRESCALER_DIV_8 2
-#define TIMER3_PRESCALER_DIV_64 3
-#define TIMER3_PRESCALER_DIV_256 4
-#define TIMER3_PRESCALER_DIV_1024 5
-#define TIMER3_PRESCALER_DIV_FALL 6
-#define TIMER3_PRESCALER_DIV_RISE 7
-
-#define TIMER3_PRESCALER_REG_0 0
-#define TIMER3_PRESCALER_REG_1 1
-#define TIMER3_PRESCALER_REG_2 8
-#define TIMER3_PRESCALER_REG_3 64
-#define TIMER3_PRESCALER_REG_4 256
-#define TIMER3_PRESCALER_REG_5 1024
-#define TIMER3_PRESCALER_REG_6 -1
-#define TIMER3_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER1C_AVAILABLE
-#define TIMER2_AVAILABLE
-#define TIMER3_AVAILABLE
-#define TIMER3A_AVAILABLE
-#define TIMER3B_AVAILABLE
-#define TIMER3C_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW3_NUM 3
-#define SIG_OVERFLOW_TOTAL_NUM 4
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE1A_NUM 1
-#define SIG_OUTPUT_COMPARE1B_NUM 2
-#define SIG_OUTPUT_COMPARE1C_NUM 3
-#define SIG_OUTPUT_COMPARE2_NUM 4
-#define SIG_OUTPUT_COMPARE3A_NUM 5
-#define SIG_OUTPUT_COMPARE3B_NUM 6
-#define SIG_OUTPUT_COMPARE3C_NUM 7
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 8
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM1A_NUM 1
-#define PWM1B_NUM 2
-#define PWM1C_NUM 3
-#define PWM2_NUM 4
-#define PWM3A_NUM 5
-#define PWM3B_NUM 6
-#define PWM3C_NUM 7
-#define PWM_TOTAL_NUM 8
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE3_NUM 1
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 2
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTG */
-#define PORTG0_REG PORTG
-#define PORTG1_REG PORTG
-#define PORTG2_REG PORTG
-#define PORTG3_REG PORTG
-#define PORTG4_REG PORTG
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL0_REG UCSR0C
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* UDR1 */
-#define UDR10_REG UDR1
-#define UDR11_REG UDR1
-#define UDR12_REG UDR1
-#define UDR13_REG UDR1
-#define UDR14_REG UDR1
-#define UDR15_REG UDR1
-#define UDR16_REG UDR1
-#define UDR17_REG UDR1
-
-/* UDR0 */
-#define UDR00_REG UDR0
-#define UDR01_REG UDR0
-#define UDR02_REG UDR0
-#define UDR03_REG UDR0
-#define UDR04_REG UDR0
-#define UDR05_REG UDR0
-#define UDR06_REG UDR0
-#define UDR07_REG UDR0
-
-/* EICRB */
-#define ISC40_REG EICRB
-#define ISC41_REG EICRB
-#define ISC50_REG EICRB
-#define ISC51_REG EICRB
-#define ISC60_REG EICRB
-#define ISC61_REG EICRB
-#define ISC70_REG EICRB
-#define ISC71_REG EICRB
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-#define ISC20_REG EICRA
-#define ISC21_REG EICRA
-#define ISC30_REG EICRA
-#define ISC31_REG EICRA
-
-/* ASSR */
-#define TCR0UB_REG ASSR
-#define OCR0UB_REG ASSR
-#define TCN0UB_REG ASSR
-#define AS0_REG ASSR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* UBRR1L */
-/* #define UBRR0_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR1_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR2_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR3_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR4_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR5_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR6_REG UBRR1L */ /* dup in UBRR0L */
-/* #define UBRR7_REG UBRR1L */ /* dup in UBRR0L */
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* OCR3AL */
-#define OCR3AL0_REG OCR3AL
-#define OCR3AL1_REG OCR3AL
-#define OCR3AL2_REG OCR3AL
-#define OCR3AL3_REG OCR3AL
-#define OCR3AL4_REG OCR3AL
-#define OCR3AL5_REG OCR3AL
-#define OCR3AL6_REG OCR3AL
-#define OCR3AL7_REG OCR3AL
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* DDRF */
-#define DDF0_REG DDRF
-#define DDF1_REG DDRF
-#define DDF2_REG DDRF
-#define DDF3_REG DDRF
-#define DDF4_REG DDRF
-#define DDF5_REG DDRF
-#define DDF6_REG DDRF
-#define DDF7_REG DDRF
-
-/* DDRG */
-#define DDG0_REG DDRG
-#define DDG1_REG DDRG
-#define DDG2_REG DDRG
-#define DDG3_REG DDRG
-#define DDG4_REG DDRG
-
-/* OCR3AH */
-#define OCR3AH0_REG OCR3AH
-#define OCR3AH1_REG OCR3AH
-#define OCR3AH2_REG OCR3AH
-#define OCR3AH3_REG OCR3AH
-#define OCR3AH4_REG OCR3AH
-#define OCR3AH5_REG OCR3AH
-#define OCR3AH6_REG OCR3AH
-#define OCR3AH7_REG OCR3AH
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* SFIOR */
-#define ACME_REG SFIOR
-#define PSR321_REG SFIOR
-#define PSR0_REG SFIOR
-#define PUD_REG SFIOR
-#define TSM_REG SFIOR
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* UBRR1H */
-/* #define UBRR8_REG UBRR1H */ /* dup in UBRR0H */
-/* #define UBRR9_REG UBRR1H */ /* dup in UBRR0H */
-/* #define UBRR10_REG UBRR1H */ /* dup in UBRR0H */
-/* #define UBRR11_REG UBRR1H */ /* dup in UBRR0H */
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* TIFR */
-#define TOV0_REG TIFR
-#define OCF0_REG TIFR
-#define TOV1_REG TIFR
-#define OCF1B_REG TIFR
-#define OCF1A_REG TIFR
-#define ICF1_REG TIFR
-#define TOV2_REG TIFR
-#define OCF2_REG TIFR
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* ETIFR */
-#define OCF1C_REG ETIFR
-#define OCF3C_REG ETIFR
-#define TOV3_REG ETIFR
-#define OCF3B_REG ETIFR
-#define OCF3A_REG ETIFR
-#define ICF3_REG ETIFR
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* XDIV */
-#define XDIV0_REG XDIV
-#define XDIV1_REG XDIV
-#define XDIV2_REG XDIV
-#define XDIV3_REG XDIV
-#define XDIV4_REG XDIV
-#define XDIV5_REG XDIV
-#define XDIV6_REG XDIV
-#define XDIVEN_REG XDIV
-
-/* OCR3CH */
-#define OCR3CH0_REG OCR3CH
-#define OCR3CH1_REG OCR3CH
-#define OCR3CH2_REG OCR3CH
-#define OCR3CH3_REG OCR3CH
-#define OCR3CH4_REG OCR3CH
-#define OCR3CH5_REG OCR3CH
-#define OCR3CH6_REG OCR3CH
-#define OCR3CH7_REG OCR3CH
-
-/* ETIMSK */
-#define OCIE1C_REG ETIMSK
-#define OCIE3C_REG ETIMSK
-#define TOIE3_REG ETIMSK
-#define OCIE3B_REG ETIMSK
-#define OCIE3A_REG ETIMSK
-#define TICIE3_REG ETIMSK
-
-/* OCR3CL */
-#define OCR3CL0_REG OCR3CL
-#define OCR3CL1_REG OCR3CL
-#define OCR3CL2_REG OCR3CL
-#define OCR3CL3_REG OCR3CL
-#define OCR3CL4_REG OCR3CL
-#define OCR3CL5_REG OCR3CL
-#define OCR3CL6_REG OCR3CL
-#define OCR3CL7_REG OCR3CL
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* TCCR3C */
-#define FOC3C_REG TCCR3C
-#define FOC3B_REG TCCR3C
-#define FOC3A_REG TCCR3C
-
-/* TCCR3B */
-#define CS30_REG TCCR3B
-#define CS31_REG TCCR3B
-#define CS32_REG TCCR3B
-#define WGM32_REG TCCR3B
-#define WGM33_REG TCCR3B
-#define ICES3_REG TCCR3B
-#define ICNC3_REG TCCR3B
-
-/* TCCR3A */
-#define WGM30_REG TCCR3A
-#define WGM31_REG TCCR3A
-#define COM3C0_REG TCCR3A
-#define COM3C1_REG TCCR3A
-#define COM3B0_REG TCCR3A
-#define COM3B1_REG TCCR3A
-#define COM3A0_REG TCCR3A
-#define COM3A1_REG TCCR3A
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* TCNT3H */
-#define TCNT3H0_REG TCNT3H
-#define TCNT3H1_REG TCNT3H
-#define TCNT3H2_REG TCNT3H
-#define TCNT3H3_REG TCNT3H
-#define TCNT3H4_REG TCNT3H
-#define TCNT3H5_REG TCNT3H
-#define TCNT3H6_REG TCNT3H
-#define TCNT3H7_REG TCNT3H
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* TCNT3L */
-#define TCN3L0_REG TCNT3L
-#define TCN3L1_REG TCNT3L
-#define TCN3L2_REG TCNT3L
-#define TCN3L3_REG TCNT3L
-#define TCN3L4_REG TCNT3L
-#define TCN3L5_REG TCNT3L
-#define TCN3L6_REG TCNT3L
-#define TCN3L7_REG TCNT3L
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* MCUCSR */
-#define PORF_REG MCUCSR
-#define EXTRF_REG MCUCSR
-#define BORF_REG MCUCSR
-#define WDRF_REG MCUCSR
-#define JTRF_REG MCUCSR
-#define JTD_REG MCUCSR
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* UBRR0H */
-/* #define UBRR8_REG UBRR0H */ /* dup in UBRR1H */
-/* #define UBRR9_REG UBRR0H */ /* dup in UBRR1H */
-/* #define UBRR10_REG UBRR0H */ /* dup in UBRR1H */
-/* #define UBRR11_REG UBRR0H */ /* dup in UBRR1H */
-
-/* UBRR0L */
-/* #define UBRR0_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR1_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR2_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR3_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR4_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR5_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR6_REG UBRR0L */ /* dup in UBRR1L */
-/* #define UBRR7_REG UBRR0L */ /* dup in UBRR1L */
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-#define EEAR10_REG EEARH
-
-/* EEARL */
-#define EEARL0_REG EEARL
-#define EEARL1_REG EEARL
-#define EEARL2_REG EEARL
-#define EEARL3_REG EEARL
-#define EEARL4_REG EEARL
-#define EEARL5_REG EEARL
-#define EEARL6_REG EEARL
-#define EEARL7_REG EEARL
-
-/* MCUCR */
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define SM2_REG MCUCR
-#define SM0_REG MCUCR
-#define SM1_REG MCUCR
-#define SE_REG MCUCR
-#define SRW10_REG MCUCR
-#define SRE_REG MCUCR
-
-/* OCR1CL */
-#define OCR1CL0_REG OCR1CL
-#define OCR1CL1_REG OCR1CL
-#define OCR1CL2_REG OCR1CL
-#define OCR1CL3_REG OCR1CL
-#define OCR1CL4_REG OCR1CL
-#define OCR1CL5_REG OCR1CL
-#define OCR1CL6_REG OCR1CL
-#define OCR1CL7_REG OCR1CL
-
-/* OCR1CH */
-#define OCR1CH0_REG OCR1CH
-#define OCR1CH1_REG OCR1CH
-#define OCR1CH2_REG OCR1CH
-#define OCR1CH3_REG OCR1CH
-#define OCR1CH4_REG OCR1CH
-#define OCR1CH5_REG OCR1CH
-#define OCR1CH6_REG OCR1CH
-#define OCR1CH7_REG OCR1CH
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-#define INTF2_REG EIFR
-#define INTF3_REG EIFR
-#define INTF4_REG EIFR
-#define INTF5_REG EIFR
-#define INTF6_REG EIFR
-#define INTF7_REG EIFR
-
-/* UCSR1B */
-#define TXB81_REG UCSR1B
-#define RXB81_REG UCSR1B
-#define UCSZ12_REG UCSR1B
-#define TXEN1_REG UCSR1B
-#define RXEN1_REG UCSR1B
-#define UDRIE1_REG UCSR1B
-#define TXCIE1_REG UCSR1B
-#define RXCIE1_REG UCSR1B
-
-/* UCSR1C */
-#define UCPOL1_REG UCSR1C
-#define UCSZ10_REG UCSR1C
-#define UCSZ11_REG UCSR1C
-#define USBS1_REG UCSR1C
-#define UPM10_REG UCSR1C
-#define UPM11_REG UCSR1C
-#define UMSEL1_REG UCSR1C
-
-/* UCSR1A */
-#define MPCM1_REG UCSR1A
-#define U2X1_REG UCSR1A
-#define UPE1_REG UCSR1A
-#define DOR1_REG UCSR1A
-#define FE1_REG UCSR1A
-#define UDRE1_REG UCSR1A
-#define TXC1_REG UCSR1A
-#define RXC1_REG UCSR1A
-
-/* TCCR0 */
-#define CS00_REG TCCR0
-#define CS01_REG TCCR0
-#define CS02_REG TCCR0
-#define WGM01_REG TCCR0
-#define COM00_REG TCCR0
-#define COM01_REG TCCR0
-#define WGM00_REG TCCR0
-#define FOC0_REG TCCR0
-
-/* TCCR2 */
-#define CS20_REG TCCR2
-#define CS21_REG TCCR2
-#define CS22_REG TCCR2
-#define WGM21_REG TCCR2
-#define COM20_REG TCCR2
-#define COM21_REG TCCR2
-#define WGM20_REG TCCR2
-#define FOC2_REG TCCR2
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* TIMSK */
-#define TOIE0_REG TIMSK
-#define OCIE0_REG TIMSK
-#define TOIE1_REG TIMSK
-#define OCIE1B_REG TIMSK
-#define OCIE1A_REG TIMSK
-#define TICIE1_REG TIMSK
-#define TOIE2_REG TIMSK
-#define OCIE2_REG TIMSK
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-#define INT3_REG EIMSK
-#define INT4_REG EIMSK
-#define INT5_REG EIMSK
-#define INT6_REG EIMSK
-#define INT7_REG EIMSK
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1C0_REG TCCR1A
-#define COM1C1_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* PORTF */
-#define PORTF0_REG PORTF
-#define PORTF1_REG PORTF
-#define PORTF2_REG PORTF
-#define PORTF3_REG PORTF
-#define PORTF4_REG PORTF
-#define PORTF5_REG PORTF
-#define PORTF6_REG PORTF
-#define PORTF7_REG PORTF
-
-/* TCCR1C */
-#define FOC1C_REG TCCR1C
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* ICR3H */
-#define ICR3H0_REG ICR3H
-#define ICR3H1_REG ICR3H
-#define ICR3H2_REG ICR3H
-#define ICR3H3_REG ICR3H
-#define ICR3H4_REG ICR3H
-#define ICR3H5_REG ICR3H
-#define ICR3H6_REG ICR3H
-#define ICR3H7_REG ICR3H
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-#define DDE3_REG DDRE
-#define DDE4_REG DDRE
-#define DDE5_REG DDRE
-#define DDE6_REG DDRE
-#define DDE7_REG DDRE
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* ICR3L */
-#define ICR3L0_REG ICR3L
-#define ICR3L1_REG ICR3L
-#define ICR3L2_REG ICR3L
-#define ICR3L3_REG ICR3L
-#define ICR3L4_REG ICR3L
-#define ICR3L5_REG ICR3L
-#define ICR3L6_REG ICR3L
-#define ICR3L7_REG ICR3L
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-#define PORTE3_REG PORTE
-#define PORTE4_REG PORTE
-#define PORTE5_REG PORTE
-#define PORTE6_REG PORTE
-#define PORTE7_REG PORTE
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* OCR3BL */
-#define OCR3BL0_REG OCR3BL
-#define OCR3BL1_REG OCR3BL
-#define OCR3BL2_REG OCR3BL
-#define OCR3BL3_REG OCR3BL
-#define OCR3BL4_REG OCR3BL
-#define OCR3BL5_REG OCR3BL
-#define OCR3BL6_REG OCR3BL
-#define OCR3BL7_REG OCR3BL
-
-/* OCR3BH */
-#define OCR3BH0_REG OCR3BH
-#define OCR3BH1_REG OCR3BH
-#define OCR3BH2_REG OCR3BH
-#define OCR3BH3_REG OCR3BH
-#define OCR3BH4_REG OCR3BH
-#define OCR3BH5_REG OCR3BH
-#define OCR3BH6_REG OCR3BH
-#define OCR3BH7_REG OCR3BH
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* XMCRB */
-#define XMM0_REG XMCRB
-#define XMM1_REG XMCRB
-#define XMM2_REG XMCRB
-#define XMBK_REG XMCRB
-
-/* XMCRA */
-#define SRW11_REG XMCRA
-#define SRW00_REG XMCRA
-#define SRW01_REG XMCRA
-#define SRL0_REG XMCRA
-#define SRL1_REG XMCRA
-#define SRL2_REG XMCRA
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* PING */
-#define PING0_REG PING
-#define PING1_REG PING
-#define PING2_REG PING
-#define PING3_REG PING
-#define PING4_REG PING
-
-/* PINF */
-#define PINF0_REG PINF
-#define PINF1_REG PINF
-#define PINF2_REG PINF
-#define PINF3_REG PINF
-#define PINF4_REG PINF
-#define PINF5_REG PINF
-#define PINF6_REG PINF
-#define PINF7_REG PINF
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-#define PINE3_REG PINE
-#define PINE4_REG PINE
-#define PINE5_REG PINE
-#define PINE6_REG PINE
-#define PINE7_REG PINE
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* OCR0 */
-#define OCR0_0_REG OCR0
-#define OCR0_1_REG OCR0
-#define OCR0_2_REG OCR0
-#define OCR0_3_REG OCR0
-#define OCR0_4_REG OCR0
-#define OCR0_5_REG OCR0
-#define OCR0_6_REG OCR0
-#define OCR0_7_REG OCR0
-
-/* OCR2 */
-#define OCR2_0_REG OCR2
-#define OCR2_1_REG OCR2
-#define OCR2_2_REG OCR2
-#define OCR2_3_REG OCR2
-#define OCR2_4_REG OCR2
-#define OCR2_5_REG OCR2
-#define OCR2_6_REG OCR2
-#define OCR2_7_REG OCR2
-
-/* pins mapping */
-#define AD0_PORT PORTA
-#define AD0_BIT 0
-
-#define AD1_PORT PORTA
-#define AD1_BIT 1
-
-#define AD2_PORT PORTA
-#define AD2_BIT 2
-
-#define AD3_PORT PORTA
-#define AD3_BIT 3
-
-#define AD4_PORT PORTA
-#define AD4_BIT 4
-
-#define AD5_PORT PORTA
-#define AD5_BIT 5
-
-#define AD6_PORT PORTA
-#define AD6_BIT 6
-
-#define AD7_PORT PORTA
-#define AD7_BIT 7
-
-#define SS_PORT PORTB
-#define SS_BIT 0
-
-#define SCK_PORT PORTB
-#define SCK_BIT 1
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 2
-
-#define MISO_PORT PORTB
-#define MISO_BIT 3
-
-#define OC0_PORT PORTB
-#define OC0_BIT 4
-#define PWM0_PORT PORTB
-#define PWM0_BIT 4
-
-#define OC1A_PORT PORTB
-#define OC1A_BIT 5
-#define PWM1A_PORT PORTB
-#define PWM1A_BIT 5
-
-#define OC1B_PORT PORTB
-#define OC1B_BIT 6
-#define PWM1B_PORT PORTB
-#define PWM1B_BIT 6
-
-#define OC2_PORT PORTB
-#define OC2_BIT 7
-#define PWM2_PORT PORTB
-#define PWM2_BIT 7
-#define OC1C_PORT PORTB
-#define OC1C_BIT 7
-
-#define A8_PORT PORTC
-#define A8_BIT 0
-
-#define A9_PORT PORTC
-#define A9_BIT 1
-
-#define A10_PORT PORTC
-#define A10_BIT 2
-
-#define A11_PORT PORTC
-#define A11_BIT 3
-
-#define A12_PORT PORTC
-#define A12_BIT 4
-
-#define A13_PORT PORTC
-#define A13_BIT 5
-
-#define A14_PORT PORTC
-#define A14_BIT 6
-
-#define A15_PORT PORTC
-#define A15_BIT 7
-
-#define SCL_PORT PORTD
-#define SCL_BIT 0
-#define INT0_PORT PORTD
-#define INT0_BIT 0
-
-#define SDA_PORT PORTD
-#define SDA_BIT 1
-#define INT1_PORT PORTD
-#define INT1_BIT 1
-
-#define RXD1_PORT PORTD
-#define RXD1_BIT 2
-#define INT2_PORT PORTD
-#define INT2_BIT 2
-
-#define TXD1_PORT PORTD
-#define TXD1_BIT 3
-#define INT3_PORT PORTD
-#define INT3_BIT 3
-
-#define IC1_PORT PORTD
-#define IC1_BIT 4
-
-#define XCK1_PORT PORTD
-#define XCK1_BIT 5
-
-#define T1_PORT PORTD
-#define T1_BIT 6
-
-#define T2_PORT PORTD
-#define T2_BIT 7
-
-#define RXD0_PORT PORTE
-#define RXD0_BIT 0
-#define PDI_PORT PORTE
-#define PDI_BIT 0
-
-#define TXD0_PORT PORTE
-#define TXD0_BIT 1
-#define PDO_PORT PORTE
-#define PDO_BIT 1
-
-#define XCK0_PORT PORTE
-#define XCK0_BIT 2
-#define AIN0_PORT PORTE
-#define AIN0_BIT 2
-
-#define OC3A_PORT PORTE
-#define OC3A_BIT 3
-#define AIN1_PORT PORTE
-#define AIN1_BIT 3
-
-#define OC3B_PORT PORTE
-#define OC3B_BIT 4
-#define INT4_PORT PORTE
-#define INT4_BIT 4
-
-#define OC3C_PORT PORTE
-#define OC3C_BIT 5
-#define INT5_PORT PORTE
-#define INT5_BIT 5
-
-#define T3_PORT PORTE
-#define T3_BIT 6
-#define INT6_PORT PORTE
-#define INT6_BIT 6
-
-#define IC3_PORT PORTE
-#define IC3_BIT 7
-#define INT7_PORT PORTE
-#define INT7_BIT 7
-
-#define ADC0_PORT PORTF
-#define ADC0_BIT 0
-
-#define ADC1_PORT PORTF
-#define ADC1_BIT 1
-
-#define ADC2_PORT PORTF
-#define ADC2_BIT 2
-
-#define ADC3_PORT PORTF
-#define ADC3_BIT 3
-
-#define ADC4_PORT PORTF
-#define ADC4_BIT 4
-#define TCK_PORT PORTF
-#define TCK_BIT 4
-
-#define ADC5_PORT PORTF
-#define ADC5_BIT 5
-#define TMS_PORT PORTF
-#define TMS_BIT 5
-
-#define ADC6_PORT PORTF
-#define ADC6_BIT 6
-#define TD0_PORT PORTF
-#define TD0_BIT 6
-
-#define ADC7_PORT PORTF
-#define ADC7_BIT 7
-#define TDI_PORT PORTF
-#define TDI_BIT 7
-
-#define WR_PORT PORTG
-#define WR_BIT 0
-
-#define RD_PORT PORTG
-#define RD_BIT 1
-
-#define ALE_PORT PORTG
-#define ALE_BIT 2
-
-#define TOSC2_PORT PORTG
-#define TOSC2_BIT 3
-
-#define TOSC1_PORT PORTG
-#define TOSC1_BIT 4
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE1A_NUM 0
-#define SIG_OUTPUT_COMPARE1B_NUM 1
-#define SIG_OUTPUT_COMPARE2_NUM 2
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 3
-
-/* Pwm nums */
-#define PWM1A_NUM 0
-#define PWM1B_NUM 1
-#define PWM2_NUM 2
-#define PWM_TOTAL_NUM 3
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* TCCR0 */
-#define CS00_REG TCCR0
-#define CS01_REG TCCR0
-#define CS02_REG TCCR0
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* GICR */
-#define IVCE_REG GICR
-#define IVSEL_REG GICR
-#define INT0_REG GICR
-#define INT1_REG GICR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define FOC1B_REG TCCR1A
-#define FOC1A_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* GIFR */
-#define INTF0_REG GIFR
-#define INTF1_REG GIFR
-
-/* TIMSK */
-#define TOIE0_REG TIMSK
-#define TOIE1_REG TIMSK
-#define OCIE1B_REG TIMSK
-#define OCIE1A_REG TIMSK
-#define TICIE1_REG TIMSK
-#define TOIE2_REG TIMSK
-#define OCIE2_REG TIMSK
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADFR_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* UCSRA */
-#define MPCM_REG UCSRA
-#define U2X_REG UCSRA
-#define UPE_REG UCSRA
-#define DOR_REG UCSRA
-#define FE_REG UCSRA
-#define UDRE_REG UCSRA
-#define TXC_REG UCSRA
-#define RXC_REG UCSRA
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SFIOR */
-#define ACME_REG SFIOR
-#define PSR2_REG SFIOR
-#define PSR10_REG SFIOR
-#define PUD_REG SFIOR
-#define ADHSM_REG SFIOR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* UCSRB */
-#define TXB8_REG UCSRB
-#define RXB8_REG UCSRB
-#define UCSZ2_REG UCSRB
-#define TXEN_REG UCSRB
-#define RXEN_REG UCSRB
-#define UDRIE_REG UCSRB
-#define TXCIE_REG UCSRB
-#define RXCIE_REG UCSRB
-
-/* UCSRC */
-#define UCPOL_REG UCSRC
-#define UCSZ0_REG UCSRC
-#define UCSZ1_REG UCSRC
-#define USBS_REG UCSRC
-#define UPM0_REG UCSRC
-#define UPM1_REG UCSRC
-#define UMSEL_REG UCSRC
-#define URSEL_REG UCSRC
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* UDR */
-#define UDR0_REG UDR
-#define UDR1_REG UDR
-#define UDR2_REG UDR
-#define UDR3_REG UDR
-#define UDR4_REG UDR
-#define UDR5_REG UDR
-#define UDR6_REG UDR
-#define UDR7_REG UDR
-
-/* SPMCR */
-#define SPMEN_REG SPMCR
-#define PGERS_REG SPMCR
-#define PGWRT_REG SPMCR
-#define BLBSET_REG SPMCR
-#define RWWSRE_REG SPMCR
-#define RWWSB_REG SPMCR
-#define SPMIE_REG SPMCR
-
-/* UBRRH */
-#define UBRR8_REG UBRRH
-#define UBRR9_REG UBRRH
-#define UBRR10_REG UBRRH
-#define UBRR11_REG UBRRH
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* UBRRL */
-#define UBRR0_REG UBRRL
-#define UBRR1_REG UBRRL
-#define UBRR2_REG UBRRL
-#define UBRR3_REG UBRRL
-#define UBRR4_REG UBRRL
-#define UBRR5_REG UBRRL
-#define UBRR6_REG UBRRL
-#define UBRR7_REG UBRRL
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* TCNT0 */
-#define TCNT00_REG TCNT0
-#define TCNT01_REG TCNT0
-#define TCNT02_REG TCNT0
-#define TCNT03_REG TCNT0
-#define TCNT04_REG TCNT0
-#define TCNT05_REG TCNT0
-#define TCNT06_REG TCNT0
-#define TCNT07_REG TCNT0
-
-/* MCUCSR */
-#define PORF_REG MCUCSR
-#define EXTRF_REG MCUCSR
-#define BORF_REG MCUCSR
-#define WDRF_REG MCUCSR
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* TCCR2 */
-#define CS20_REG TCCR2
-#define CS21_REG TCCR2
-#define CS22_REG TCCR2
-#define WGM21_REG TCCR2
-#define COM20_REG TCCR2
-#define COM21_REG TCCR2
-#define WGM20_REG TCCR2
-#define FOC2_REG TCCR2
-
-/* TIFR */
-#define TOV0_REG TIFR
-#define TOV1_REG TIFR
-#define OCF1B_REG TIFR
-#define OCF1A_REG TIFR
-#define ICF1_REG TIFR
-#define TOV2_REG TIFR
-#define OCF2_REG TIFR
-
-/* EEARH */
-#define EEAR8_REG EEARH
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define ISC10_REG MCUCR
-#define ISC11_REG MCUCR
-#define SM0_REG MCUCR
-#define SM1_REG MCUCR
-#define SM2_REG MCUCR
-#define SE_REG MCUCR
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* ASSR */
-#define TCR2UB_REG ASSR
-#define OCR2UB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-
-/* OCR2 */
-#define OCR2_0_REG OCR2
-#define OCR2_1_REG OCR2
-#define OCR2_2_REG OCR2
-#define OCR2_3_REG OCR2
-#define OCR2_4_REG OCR2
-#define OCR2_5_REG OCR2
-#define OCR2_6_REG OCR2
-#define OCR2_7_REG OCR2
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* pins mapping */
-#define ICP_PORT PORTB
-#define ICP_BIT 0
-
-#define OC1A_PORT PORTB
-#define OC1A_BIT 1
-
-#define SS_PORT PORTB
-#define SS_BIT 2
-#define OC1B_PORT PORTB
-#define OC1B_BIT 2
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 3
-#define OC2_PORT PORTB
-#define OC2_BIT 3
-
-#define MISO_PORT PORTB
-#define MISO_BIT 4
-
-#define SCK_PORT PORTB
-#define SCK_BIT 5
-
-#define XTAL1_PORT PORTB
-#define XTAL1_BIT 6
-#define TOSC1_PORT PORTB
-#define TOSC1_BIT 6
-
-#define XTAL2_PORT PORTB
-#define XTAL2_BIT 7
-#define TOSC2_PORT PORTB
-#define TOSC2_BIT 7
-
-#define ADC0_PORT PORTC
-#define ADC0_BIT 0
-
-#define ADC1_PORT PORTC
-#define ADC1_BIT 1
-
-#define ADC2_PORT PORTC
-#define ADC2_BIT 2
-
-#define ADC3_PORT PORTC
-#define ADC3_BIT 3
-
-#define ADC4_PORT PORTC
-#define ADC4_BIT 4
-#define SDA_PORT PORTC
-#define SDA_BIT 4
-
-#define ADC5_PORT PORTC
-#define ADC5_BIT 5
-#define SCL_PORT PORTC
-#define SCL_BIT 5
-
-#define RESET_PORT PORTC
-#define RESET_BIT 6
-
-#define RXD_PORT PORTD
-#define RXD_BIT 0
-
-#define TXD_PORT PORTD
-#define TXD_BIT 1
-
-#define INT0_PORT PORTD
-#define INT0_BIT 2
-
-#define IN1_PORT PORTD
-#define IN1_BIT 3
-
-#define XCK_PORT PORTD
-#define XCK_BIT 4
-#define T0_PORT PORTD
-#define T0_BIT 4
-
-#define T1_PORT PORTD
-#define T1_BIT 5
-
-#define AIN0_PORT PORTD
-#define AIN0_BIT 6
-
-#define AIN1_PORT PORTD
-#define AIN1_BIT 7
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW_TOTAL_NUM 2
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE1A_NUM 1
-#define SIG_OUTPUT_COMPARE1B_NUM 2
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 3
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM1A_NUM 1
-#define PWM1B_NUM 2
-#define PWM_TOTAL_NUM 3
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* UCSRC */
-#define UCPOL_REG UCSRC
-#define UCSZ0_REG UCSRC
-#define UCSZ1_REG UCSRC
-#define USBS_REG UCSRC
-#define UPM0_REG UCSRC
-#define UPM1_REG UCSRC
-#define UMSEL_REG UCSRC
-/* #define URSEL_REG UCSRC */ /* dup in UBRRH */
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* TCCR0 */
-#define CS00_REG TCCR0
-#define CS01_REG TCCR0
-#define CS02_REG TCCR0
-#define WGM01_REG TCCR0
-#define COM00_REG TCCR0
-#define COM01_REG TCCR0
-#define WGM00_REG TCCR0
-#define FOC0_REG TCCR0
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* GICR */
-#define IVCE_REG GICR
-#define IVSEL_REG GICR
-#define INT2_REG GICR
-#define INT0_REG GICR
-#define INT1_REG GICR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define FOC1B_REG TCCR1A
-#define FOC1A_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* GIFR */
-#define INTF2_REG GIFR
-#define INTF0_REG GIFR
-#define INTF1_REG GIFR
-
-/* TIMSK */
-#define OCIE0_REG TIMSK
-#define TOIE0_REG TIMSK
-#define TICIE1_REG TIMSK
-#define OCIE1B_REG TIMSK
-#define OCIE1A_REG TIMSK
-#define TOIE1_REG TIMSK
-
-/* UCSRA */
-#define MPCM_REG UCSRA
-#define U2X_REG UCSRA
-#define UPE_REG UCSRA
-#define DOR_REG UCSRA
-#define FE_REG UCSRA
-#define UDRE_REG UCSRA
-#define TXC_REG UCSRA
-#define RXC_REG UCSRA
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SFIOR */
-#define PSR10_REG SFIOR
-#define PUD_REG SFIOR
-#define XMM0_REG SFIOR
-#define XMM1_REG SFIOR
-#define XMM2_REG SFIOR
-#define XMBK_REG SFIOR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* UCSRB */
-#define TXB8_REG UCSRB
-#define RXB8_REG UCSRB
-#define UCSZ2_REG UCSRB
-#define TXEN_REG UCSRB
-#define RXEN_REG UCSRB
-#define UDRIE_REG UCSRB
-#define TXCIE_REG UCSRB
-#define RXCIE_REG UCSRB
-
-/* EMCUCR */
-#define ISC2_REG EMCUCR
-#define SRW11_REG EMCUCR
-#define SRW00_REG EMCUCR
-#define SRW01_REG EMCUCR
-#define SRL0_REG EMCUCR
-#define SRL1_REG EMCUCR
-#define SRL2_REG EMCUCR
-#define SM0_REG EMCUCR
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* UDR */
-#define UDR0_REG UDR
-#define UDR1_REG UDR
-#define UDR2_REG UDR
-#define UDR3_REG UDR
-#define UDR4_REG UDR
-#define UDR5_REG UDR
-#define UDR6_REG UDR
-#define UDR7_REG UDR
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* SPMCR */
-#define SPMEN_REG SPMCR
-#define PGERS_REG SPMCR
-#define PGWRT_REG SPMCR
-#define BLBSET_REG SPMCR
-#define RWWSRE_REG SPMCR
-#define RWWSB_REG SPMCR
-#define SPMIE_REG SPMCR
-
-/* UBRRH */
-#define UBRR8_REG UBRRH
-#define UBRR9_REG UBRRH
-#define UBRR10_REG UBRRH
-#define UBRR11_REG UBRRH
-/* #define URSEL_REG UBRRH */ /* dup in UCSRC */
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-
-/* UBRRL */
-#define UBRR0_REG UBRRL
-#define UBRR1_REG UBRRL
-#define UBRR2_REG UBRRL
-#define UBRR3_REG UBRRL
-#define UBRR4_REG UBRRL
-#define UBRR5_REG UBRRL
-#define UBRR6_REG UBRRL
-#define UBRR7_REG UBRRL
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* MCUCSR */
-#define PORF_REG MCUCSR
-#define EXTRF_REG MCUCSR
-#define BORF_REG MCUCSR
-#define WDRF_REG MCUCSR
-#define SM2_REG MCUCSR
-
-/* TIFR */
-#define OCF0_REG TIFR
-#define TOV0_REG TIFR
-#define ICF1_REG TIFR
-#define OCF1B_REG TIFR
-#define OCF1A_REG TIFR
-#define TOV1_REG TIFR
-
-/* EEARH */
-#define EEAR8_REG EEARH
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define ISC10_REG MCUCR
-#define ISC11_REG MCUCR
-#define SM1_REG MCUCR
-#define SE_REG MCUCR
-#define SRW10_REG MCUCR
-#define SRE_REG MCUCR
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* OCR0 */
-#define OCR0_0_REG OCR0
-#define OCR0_1_REG OCR0
-#define OCR0_2_REG OCR0
-#define OCR0_3_REG OCR0
-#define OCR0_4_REG OCR0
-#define OCR0_5_REG OCR0
-#define OCR0_6_REG OCR0
-#define OCR0_7_REG OCR0
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* pins mapping */
-#define AD0_PORT PORTA
-#define AD0_BIT 0
-
-#define AD1_PORT PORTA
-#define AD1_BIT 1
-
-#define AD2_PORT PORTA
-#define AD2_BIT 2
-
-#define AD3_PORT PORTA
-#define AD3_BIT 3
-
-#define AD4_PORT PORTA
-#define AD4_BIT 4
-
-#define AD5_PORT PORTA
-#define AD5_BIT 5
-
-#define AD6_PORT PORTA
-#define AD6_BIT 6
-
-#define AD7_PORT PORTA
-#define AD7_BIT 7
-
-#define OC0_PORT PORTB
-#define OC0_BIT 0
-#define T0_PORT PORTB
-#define T0_BIT 0
-
-#define T1_PORT PORTB
-#define T1_BIT 1
-
-#define AIN0_PORT PORTB
-#define AIN0_BIT 2
-
-#define AIN1_PORT PORTB
-#define AIN1_BIT 3
-
-#define SS_PORT PORTB
-#define SS_BIT 4
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 5
-
-#define MISO_PORT PORTB
-#define MISO_BIT 6
-
-#define SCK_PORT PORTB
-#define SCK_BIT 7
-
-#define A8_PORT PORTC
-#define A8_BIT 0
-
-#define A9_PORT PORTC
-#define A9_BIT 1
-
-#define A10_PORT PORTC
-#define A10_BIT 2
-
-#define A11_PORT PORTC
-#define A11_BIT 3
-
-#define A12_PORT PORTC
-#define A12_BIT 4
-
-#define A13_PORT PORTC
-#define A13_BIT 5
-
-#define A14_PORT PORTC
-#define A14_BIT 6
-
-#define A15_PORT PORTC
-#define A15_BIT 7
-
-#define RXD_PORT PORTD
-#define RXD_BIT 0
-
-#define TXD_PORT PORTD
-#define TXD_BIT 1
-
-#define INT0_PORT PORTD
-#define INT0_BIT 2
-
-#define INT1_PORT PORTD
-#define INT1_BIT 3
-
-#define XCK_PORT PORTD
-#define XCK_BIT 4
-
-#define OC1A_PORT PORTD
-#define OC1A_BIT 5
-
-#define WR_PORT PORTD
-#define WR_BIT 6
-
-#define RD_PORT PORTD
-#define RD_BIT 7
-
-#define ICP_PORT PORTE
-#define ICP_BIT 0
-#define INT2_PORT PORTE
-#define INT2_BIT 0
-
-#define ALE_PORT PORTE
-#define ALE_BIT 1
-
-#define OC1B_PORT PORTE
-#define OC1B_BIT 2
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0_NUM 0
-#define SIG_OUTPUT_COMPARE1A_NUM 1
-#define SIG_OUTPUT_COMPARE1B_NUM 2
-#define SIG_OUTPUT_COMPARE2_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0_NUM 0
-#define PWM1A_NUM 1
-#define PWM1B_NUM 2
-#define PWM2_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* TCCR0 */
-#define CS00_REG TCCR0
-#define CS01_REG TCCR0
-#define CS02_REG TCCR0
-#define WGM01_REG TCCR0
-#define COM00_REG TCCR0
-#define COM01_REG TCCR0
-#define WGM00_REG TCCR0
-#define FOC0_REG TCCR0
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* GICR */
-#define IVCE_REG GICR
-#define IVSEL_REG GICR
-#define INT2_REG GICR
-#define INT0_REG GICR
-#define INT1_REG GICR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define FOC1B_REG TCCR1A
-#define FOC1A_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* GIFR */
-#define INTF2_REG GIFR
-#define INTF0_REG GIFR
-#define INTF1_REG GIFR
-
-/* TIMSK */
-#define TOIE0_REG TIMSK
-#define OCIE0_REG TIMSK
-#define TOIE1_REG TIMSK
-#define OCIE1B_REG TIMSK
-#define OCIE1A_REG TIMSK
-#define TICIE1_REG TIMSK
-#define TOIE2_REG TIMSK
-#define OCIE2_REG TIMSK
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* UCSRA */
-#define MPCM_REG UCSRA
-#define U2X_REG UCSRA
-#define UPE_REG UCSRA
-#define DOR_REG UCSRA
-#define FE_REG UCSRA
-#define UDRE_REG UCSRA
-#define TXC_REG UCSRA
-#define RXC_REG UCSRA
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SFIOR */
-#define ADTS0_REG SFIOR
-#define ADTS1_REG SFIOR
-#define ADTS2_REG SFIOR
-#define PSR10_REG SFIOR
-#define PSR2_REG SFIOR
-#define PUD_REG SFIOR
-#define ACME_REG SFIOR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* UCSRB */
-#define TXB8_REG UCSRB
-#define RXB8_REG UCSRB
-#define UCSZ2_REG UCSRB
-#define TXEN_REG UCSRB
-#define RXEN_REG UCSRB
-#define UDRIE_REG UCSRB
-#define TXCIE_REG UCSRB
-#define RXCIE_REG UCSRB
-
-/* UCSRC */
-#define UCPOL_REG UCSRC
-#define UCSZ0_REG UCSRC
-#define UCSZ1_REG UCSRC
-#define USBS_REG UCSRC
-#define UPM0_REG UCSRC
-#define UPM1_REG UCSRC
-#define UMSEL_REG UCSRC
-/* #define URSEL_REG UCSRC */ /* dup in UBRRH */
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* UDR */
-#define UDR0_REG UDR
-#define UDR1_REG UDR
-#define UDR2_REG UDR
-#define UDR3_REG UDR
-#define UDR4_REG UDR
-#define UDR5_REG UDR
-#define UDR6_REG UDR
-#define UDR7_REG UDR
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* SPMCR */
-#define SPMEN_REG SPMCR
-#define PGERS_REG SPMCR
-#define PGWRT_REG SPMCR
-#define BLBSET_REG SPMCR
-#define RWWSRE_REG SPMCR
-#define RWWSB_REG SPMCR
-#define SPMIE_REG SPMCR
-
-/* UBRRH */
-#define UBRR8_REG UBRRH
-#define UBRR9_REG UBRRH
-#define UBRR10_REG UBRRH
-#define UBRR11_REG UBRRH
-/* #define URSEL_REG UBRRH */ /* dup in UCSRC */
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* UBRRL */
-#define UBRR0_REG UBRRL
-#define UBRR1_REG UBRRL
-#define UBRR2_REG UBRRL
-#define UBRR3_REG UBRRL
-#define UBRR4_REG UBRRL
-#define UBRR5_REG UBRRL
-#define UBRR6_REG UBRRL
-#define UBRR7_REG UBRRL
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* MCUCSR */
-#define ISC2_REG MCUCSR
-#define PORF_REG MCUCSR
-#define EXTRF_REG MCUCSR
-#define BORF_REG MCUCSR
-#define WDRF_REG MCUCSR
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* TCCR2 */
-#define CS20_REG TCCR2
-#define CS21_REG TCCR2
-#define CS22_REG TCCR2
-#define WGM21_REG TCCR2
-#define COM20_REG TCCR2
-#define COM21_REG TCCR2
-#define WGM20_REG TCCR2
-#define FOC2_REG TCCR2
-
-/* TIFR */
-#define TOV0_REG TIFR
-#define OCF0_REG TIFR
-#define TOV1_REG TIFR
-#define OCF1B_REG TIFR
-#define OCF1A_REG TIFR
-#define ICF1_REG TIFR
-#define TOV2_REG TIFR
-#define OCF2_REG TIFR
-
-/* EEARH */
-#define EEAR8_REG EEARH
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define ISC10_REG MCUCR
-#define ISC11_REG MCUCR
-#define SM0_REG MCUCR
-#define SM1_REG MCUCR
-#define SE_REG MCUCR
-#define SM2_REG MCUCR
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* ASSR */
-#define TCR2UB_REG ASSR
-#define OCR2UB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-
-/* OCR0 */
-#define OCR0_0_REG OCR0
-#define OCR0_1_REG OCR0
-#define OCR0_2_REG OCR0
-#define OCR0_3_REG OCR0
-#define OCR0_4_REG OCR0
-#define OCR0_5_REG OCR0
-#define OCR0_6_REG OCR0
-#define OCR0_7_REG OCR0
-
-/* OCR2 */
-#define OCR2_0_REG OCR2
-#define OCR2_1_REG OCR2
-#define OCR2_2_REG OCR2
-#define OCR2_3_REG OCR2
-#define OCR2_4_REG OCR2
-#define OCR2_5_REG OCR2
-#define OCR2_6_REG OCR2
-#define OCR2_7_REG OCR2
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* pins mapping */
-#define ADC0_PORT PORTA
-#define ADC0_BIT 0
-
-#define ADC1_PORT PORTA
-#define ADC1_BIT 1
-
-#define ADC2_PORT PORTA
-#define ADC2_BIT 2
-
-#define ADC3_PORT PORTA
-#define ADC3_BIT 3
-
-#define ADC4_PORT PORTA
-#define ADC4_BIT 4
-
-#define ADc5_PORT PORTA
-#define ADc5_BIT 5
-
-#define ADC6_PORT PORTA
-#define ADC6_BIT 6
-
-#define ADC7_PORT PORTA
-#define ADC7_BIT 7
-
-#define XCK_PORT PORTB
-#define XCK_BIT 0
-#define T0_PORT PORTB
-#define T0_BIT 0
-
-#define T1_PORT PORTB
-#define T1_BIT 1
-
-#define AIN0_PORT PORTB
-#define AIN0_BIT 2
-#define INT2_PORT PORTB
-#define INT2_BIT 2
-
-#define AIN1_PORT PORTB
-#define AIN1_BIT 3
-#define OC0_PORT PORTB
-#define OC0_BIT 3
-
-#define SS_PORT PORTB
-#define SS_BIT 4
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 5
-
-#define MISO_PORT PORTB
-#define MISO_BIT 6
-
-#define SCK_PORT PORTB
-#define SCK_BIT 7
-
-#define SCL_PORT PORTC
-#define SCL_BIT 0
-
-#define SDA_PORT PORTC
-#define SDA_BIT 1
-
-
-
-
-
-#define TOSC1_PORT PORTC
-#define TOSC1_BIT 6
-
-#define TOSC2_PORT PORTC
-#define TOSC2_BIT 7
-
-#define RXD_PORT PORTD
-#define RXD_BIT 0
-
-#define TXD_PORT PORTD
-#define TXD_BIT 1
-
-#define INT0_PORT PORTD
-#define INT0_BIT 2
-
-#define INT1_PORT PORTD
-#define INT1_BIT 3
-
-#define OC1B_PORT PORTD
-#define OC1B_BIT 4
-
-#define OC1A_PORT PORTD
-#define OC1A_BIT 5
-
-#define ICP_PORT PORTD
-#define ICP_BIT 6
-
-#define OC2_PORT PORTD
-#define OC2_BIT 7
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-#define TIMER2A_AVAILABLE
-#define TIMER2B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE2A_NUM 4
-#define SIG_OUTPUT_COMPARE2B_NUM 5
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 6
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM2A_NUM 4
-#define PWM2B_NUM 5
-#define PWM_TOTAL_NUM 6
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* OCR2B */
-#define OCR2B_0_REG OCR2B
-#define OCR2B_1_REG OCR2B
-#define OCR2B_2_REG OCR2B
-#define OCR2B_3_REG OCR2B
-#define OCR2B_4_REG OCR2B
-#define OCR2B_5_REG OCR2B
-#define OCR2B_6_REG OCR2B
-#define OCR2B_7_REG OCR2B
-
-/* OCR2A */
-#define OCR2A_0_REG OCR2A
-#define OCR2A_1_REG OCR2A
-#define OCR2A_2_REG OCR2A
-#define OCR2A_3_REG OCR2A
-#define OCR2A_4_REG OCR2A
-#define OCR2A_5_REG OCR2A
-#define OCR2A_6_REG OCR2A
-#define OCR2A_7_REG OCR2A
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSART0_REG PRR
-#define PRSPI_REG PRR
-#define PRTIM1_REG PRR
-#define PRTIM0_REG PRR
-#define PRTIM2_REG PRR
-#define PRTWI_REG PRR
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-
-/* UDR0 */
-#define UDR0_0_REG UDR0
-#define UDR0_1_REG UDR0
-#define UDR0_2_REG UDR0
-#define UDR0_3_REG UDR0
-#define UDR0_4_REG UDR0
-#define UDR0_5_REG UDR0
-#define UDR0_6_REG UDR0
-#define UDR0_7_REG UDR0
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* ASSR */
-#define TCR2BUB_REG ASSR
-#define TCR2AUB_REG ASSR
-#define OCR2BUB_REG ASSR
-#define OCR2AUB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* PCICR */
-#define PCIE0_REG PCICR
-#define PCIE1_REG PCICR
-#define PCIE2_REG PCICR
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-#define OCF2B_REG TIFR2
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* GTCCR */
-#define PSRSYNC_REG GTCCR
-#define TSM_REG GTCCR
-#define PSRASY_REG GTCCR
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* PCIFR */
-#define PCIF0_REG PCIFR
-#define PCIF1_REG PCIFR
-#define PCIF2_REG PCIFR
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* TCCR2A */
-#define WGM20_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2B0_REG TCCR2A
-#define COM2B1_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-
-/* TCCR2B */
-#define CS20_REG TCCR2B
-#define CS21_REG TCCR2B
-#define CS22_REG TCCR2B
-#define WGM22_REG TCCR2B
-#define FOC2B_REG TCCR2B
-#define FOC2A_REG TCCR2B
-
-/* UBRR0H */
-#define UBRR8_REG UBRR0H
-#define UBRR9_REG UBRR0H
-#define UBRR10_REG UBRR0H
-#define UBRR11_REG UBRR0H
-
-/* UBRR0L */
-#define UBRR0_REG UBRR0L
-#define UBRR1_REG UBRR0L
-#define UBRR2_REG UBRR0L
-#define UBRR3_REG UBRR0L
-#define UBRR4_REG UBRR0L
-#define UBRR5_REG UBRR0L
-#define UBRR6_REG UBRR0L
-#define UBRR7_REG UBRR0L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* MCUCR */
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ACME_REG ADCSRB
-
-/* OCR0A */
-#define OCROA_0_REG OCR0A
-#define OCROA_1_REG OCR0A
-#define OCROA_2_REG OCR0A
-#define OCROA_3_REG OCR0A
-#define OCROA_4_REG OCR0A
-#define OCROA_5_REG OCR0A
-#define OCROA_6_REG OCR0A
-#define OCROA_7_REG OCR0A
-
-/* OCR0B */
-#define OCR0B_0_REG OCR0B
-#define OCR0B_1_REG OCR0B
-#define OCR0B_2_REG OCR0B
-#define OCR0B_3_REG OCR0B
-#define OCR0B_4_REG OCR0B
-#define OCR0B_5_REG OCR0B
-#define OCR0B_6_REG OCR0B
-#define OCR0B_7_REG OCR0B
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL00_REG UCSR0C
-#define UMSEL01_REG UCSR0C
-
-/* SPMCSR */
-#define SELFPRGEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-#define OCIE2B_REG TIMSK2
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-
-/* PCMSK2 */
-#define PCINT16_REG PCMSK2
-#define PCINT17_REG PCMSK2
-#define PCINT18_REG PCMSK2
-#define PCINT19_REG PCMSK2
-#define PCINT20_REG PCMSK2
-#define PCINT21_REG PCMSK2
-#define PCINT22_REG PCMSK2
-#define PCINT23_REG PCMSK2
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* TWAMR */
-#define TWAM0_REG TWAMR
-#define TWAM1_REG TWAMR
-#define TWAM2_REG TWAMR
-#define TWAM3_REG TWAMR
-#define TWAM4_REG TWAMR
-#define TWAM5_REG TWAMR
-#define TWAM6_REG TWAMR
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* pins mapping */
-#define ICP1_PORT PORTB
-#define ICP1_BIT 0
-#define CLKO_PORT PORTB
-#define CLKO_BIT 0
-#define PCINT0_PORT PORTB
-#define PCINT0_BIT 0
-
-#define OC1A_PORT PORTB
-#define OC1A_BIT 1
-#define PCINT1_PORT PORTB
-#define PCINT1_BIT 1
-
-#define SS_PORT PORTB
-#define SS_BIT 2
-#define OC1B_PORT PORTB
-#define OC1B_BIT 2
-#define PCINT2_PORT PORTB
-#define PCINT2_BIT 2
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 3
-#define OC2A_PORT PORTB
-#define OC2A_BIT 3
-#define PCINT3_PORT PORTB
-#define PCINT3_BIT 3
-
-#define MISO_PORT PORTB
-#define MISO_BIT 4
-#define PCINT4_PORT PORTB
-#define PCINT4_BIT 4
-
-#define SCK_PORT PORTB
-#define SCK_BIT 5
-#define PCINT5_PORT PORTB
-#define PCINT5_BIT 5
-
-#define XTAL1_PORT PORTB
-#define XTAL1_BIT 6
-#define TOSC1_PORT PORTB
-#define TOSC1_BIT 6
-#define PCINT6_PORT PORTB
-#define PCINT6_BIT 6
-
-#define XTAL2_PORT PORTB
-#define XTAL2_BIT 7
-#define TOSC2_PORT PORTB
-#define TOSC2_BIT 7
-#define PCINT7_PORT PORTB
-#define PCINT7_BIT 7
-
-#define ADC0_PORT PORTC
-#define ADC0_BIT 0
-#define PCINT8_PORT PORTC
-#define PCINT8_BIT 0
-
-#define ADC1_PORT PORTC
-#define ADC1_BIT 1
-#define PCINT9_PORT PORTC
-#define PCINT9_BIT 1
-
-#define ADC2_PORT PORTC
-#define ADC2_BIT 2
-#define PCINT10_PORT PORTC
-#define PCINT10_BIT 2
-
-#define ADC3_PORT PORTC
-#define ADC3_BIT 3
-#define PCINT11_PORT PORTC
-#define PCINT11_BIT 3
-
-#define ADC4_PORT PORTC
-#define ADC4_BIT 4
-#define SDA_PORT PORTC
-#define SDA_BIT 4
-#define PCINT12_PORT PORTC
-#define PCINT12_BIT 4
-
-#define ADC5_PORT PORTC
-#define ADC5_BIT 5
-#define SCL_PORT PORTC
-#define SCL_BIT 5
-#define PCINT13_PORT PORTC
-#define PCINT13_BIT 5
-
-#define RESET_PORT PORTC
-#define RESET_BIT 6
-#define PCINT14_PORT PORTC
-#define PCINT14_BIT 6
-
-#define RXD_PORT PORTD
-#define RXD_BIT 0
-#define PCINT16_PORT PORTD
-#define PCINT16_BIT 0
-
-#define TXD_PORT PORTD
-#define TXD_BIT 1
-#define PCINT17_PORT PORTD
-#define PCINT17_BIT 1
-
-#define INT0_PORT PORTD
-#define INT0_BIT 2
-#define PCINT18_PORT PORTD
-#define PCINT18_BIT 2
-
-#define PCINT19_PORT PORTD
-#define PCINT19_BIT 3
-#define OC2B_PORT PORTD
-#define OC2B_BIT 3
-#define INT1_PORT PORTD
-#define INT1_BIT 3
-
-#define XCK_PORT PORTD
-#define XCK_BIT 4
-#define T0_PORT PORTD
-#define T0_BIT 4
-#define PCINT20_PORT PORTD
-#define PCINT20_BIT 4
-
-#define T1_PORT PORTD
-#define T1_BIT 5
-#define OC0B_PORT PORTD
-#define OC0B_BIT 5
-#define PCINT21_PORT PORTD
-#define PCINT21_BIT 5
-
-#define AIN0_PORT PORTD
-#define AIN0_BIT 6
-#define OC0A_PORT PORTD
-#define OC0A_BIT 6
-#define PCINT22_PORT PORTD
-#define PCINT22_BIT 6
-
-#define AIN1_PORT PORTD
-#define AIN1_BIT 7
-#define PCINT23_PORT PORTD
-#define PCINT23_BIT 7
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-#define TIMER2A_AVAILABLE
-#define TIMER2B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE2A_NUM 4
-#define SIG_OUTPUT_COMPARE2B_NUM 5
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 6
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM2A_NUM 4
-#define PWM2B_NUM 5
-#define PWM_TOTAL_NUM 6
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* OCR2B */
-#define OCR2B_0_REG OCR2B
-#define OCR2B_1_REG OCR2B
-#define OCR2B_2_REG OCR2B
-#define OCR2B_3_REG OCR2B
-#define OCR2B_4_REG OCR2B
-#define OCR2B_5_REG OCR2B
-#define OCR2B_6_REG OCR2B
-#define OCR2B_7_REG OCR2B
-
-/* OCR2A */
-#define OCR2A_0_REG OCR2A
-#define OCR2A_1_REG OCR2A
-#define OCR2A_2_REG OCR2A
-#define OCR2A_3_REG OCR2A
-#define OCR2A_4_REG OCR2A
-#define OCR2A_5_REG OCR2A
-#define OCR2A_6_REG OCR2A
-#define OCR2A_7_REG OCR2A
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSART0_REG PRR
-#define PRSPI_REG PRR
-#define PRTIM1_REG PRR
-#define PRTIM0_REG PRR
-#define PRTIM2_REG PRR
-#define PRTWI_REG PRR
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-
-/* UDR0 */
-#define UDR0_0_REG UDR0
-#define UDR0_1_REG UDR0
-#define UDR0_2_REG UDR0
-#define UDR0_3_REG UDR0
-#define UDR0_4_REG UDR0
-#define UDR0_5_REG UDR0
-#define UDR0_6_REG UDR0
-#define UDR0_7_REG UDR0
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* ASSR */
-#define TCR2BUB_REG ASSR
-#define TCR2AUB_REG ASSR
-#define OCR2BUB_REG ASSR
-#define OCR2AUB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* PCICR */
-#define PCIE0_REG PCICR
-#define PCIE1_REG PCICR
-#define PCIE2_REG PCICR
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-#define OCF2B_REG TIFR2
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* GTCCR */
-#define PSRSYNC_REG GTCCR
-#define TSM_REG GTCCR
-#define PSRASY_REG GTCCR
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* PCIFR */
-#define PCIF0_REG PCIFR
-#define PCIF1_REG PCIFR
-#define PCIF2_REG PCIFR
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* TCCR2A */
-#define WGM20_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2B0_REG TCCR2A
-#define COM2B1_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-
-/* TCCR2B */
-#define CS20_REG TCCR2B
-#define CS21_REG TCCR2B
-#define CS22_REG TCCR2B
-#define WGM22_REG TCCR2B
-#define FOC2B_REG TCCR2B
-#define FOC2A_REG TCCR2B
-
-/* UBRR0H */
-#define UBRR8_REG UBRR0H
-#define UBRR9_REG UBRR0H
-#define UBRR10_REG UBRR0H
-#define UBRR11_REG UBRR0H
-
-/* UBRR0L */
-#define UBRR0_REG UBRR0L
-#define UBRR1_REG UBRR0L
-#define UBRR2_REG UBRR0L
-#define UBRR3_REG UBRR0L
-#define UBRR4_REG UBRR0L
-#define UBRR5_REG UBRR0L
-#define UBRR6_REG UBRR0L
-#define UBRR7_REG UBRR0L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* MCUCR */
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-#define BODSE_REG MCUCR
-#define BODS_REG MCUCR
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ACME_REG ADCSRB
-
-/* OCR0A */
-#define OCROA_0_REG OCR0A
-#define OCROA_1_REG OCR0A
-#define OCROA_2_REG OCR0A
-#define OCROA_3_REG OCR0A
-#define OCROA_4_REG OCR0A
-#define OCROA_5_REG OCR0A
-#define OCROA_6_REG OCR0A
-#define OCROA_7_REG OCR0A
-
-/* OCR0B */
-#define OCR0B_0_REG OCR0B
-#define OCR0B_1_REG OCR0B
-#define OCR0B_2_REG OCR0B
-#define OCR0B_3_REG OCR0B
-#define OCR0B_4_REG OCR0B
-#define OCR0B_5_REG OCR0B
-#define OCR0B_6_REG OCR0B
-#define OCR0B_7_REG OCR0B
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL00_REG UCSR0C
-#define UMSEL01_REG UCSR0C
-
-/* SPMCSR */
-#define SELFPRGEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-#define OCIE2B_REG TIMSK2
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-
-/* PCMSK2 */
-#define PCINT16_REG PCMSK2
-#define PCINT17_REG PCMSK2
-#define PCINT18_REG PCMSK2
-#define PCINT19_REG PCMSK2
-#define PCINT20_REG PCMSK2
-#define PCINT21_REG PCMSK2
-#define PCINT22_REG PCMSK2
-#define PCINT23_REG PCMSK2
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* TWAMR */
-#define TWAM0_REG TWAMR
-#define TWAM1_REG TWAMR
-#define TWAM2_REG TWAMR
-#define TWAM3_REG TWAMR
-#define TWAM4_REG TWAMR
-#define TWAM5_REG TWAMR
-#define TWAM6_REG TWAMR
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* pins mapping */
-#define ICP1_PORT PORTB
-#define ICP1_BIT 0
-#define CLKO_PORT PORTB
-#define CLKO_BIT 0
-#define PCINT0_PORT PORTB
-#define PCINT0_BIT 0
-
-#define OC1A_PORT PORTB
-#define OC1A_BIT 1
-#define PCINT1_PORT PORTB
-#define PCINT1_BIT 1
-
-#define SS_PORT PORTB
-#define SS_BIT 2
-#define OC1B_PORT PORTB
-#define OC1B_BIT 2
-#define PCINT2_PORT PORTB
-#define PCINT2_BIT 2
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 3
-#define OC2A_PORT PORTB
-#define OC2A_BIT 3
-#define PCINT3_PORT PORTB
-#define PCINT3_BIT 3
-
-#define MISO_PORT PORTB
-#define MISO_BIT 4
-#define PCINT4_PORT PORTB
-#define PCINT4_BIT 4
-
-#define SCK_PORT PORTB
-#define SCK_BIT 5
-#define PCINT5_PORT PORTB
-#define PCINT5_BIT 5
-
-#define XTAL1_PORT PORTB
-#define XTAL1_BIT 6
-#define TOSC1_PORT PORTB
-#define TOSC1_BIT 6
-#define PCINT6_PORT PORTB
-#define PCINT6_BIT 6
-
-#define XTAL2_PORT PORTB
-#define XTAL2_BIT 7
-#define TOSC2_PORT PORTB
-#define TOSC2_BIT 7
-#define PCINT7_PORT PORTB
-#define PCINT7_BIT 7
-
-#define ADC0_PORT PORTC
-#define ADC0_BIT 0
-#define PCINT8_PORT PORTC
-#define PCINT8_BIT 0
-
-#define ADC1_PORT PORTC
-#define ADC1_BIT 1
-#define PCINT9_PORT PORTC
-#define PCINT9_BIT 1
-
-#define ADC2_PORT PORTC
-#define ADC2_BIT 2
-#define PCINT10_PORT PORTC
-#define PCINT10_BIT 2
-
-#define ADC3_PORT PORTC
-#define ADC3_BIT 3
-#define PCINT11_PORT PORTC
-#define PCINT11_BIT 3
-
-#define ADC4_PORT PORTC
-#define ADC4_BIT 4
-#define SDA_PORT PORTC
-#define SDA_BIT 4
-#define PCINT12_PORT PORTC
-#define PCINT12_BIT 4
-
-#define ADC5_PORT PORTC
-#define ADC5_BIT 5
-#define SCL_PORT PORTC
-#define SCL_BIT 5
-#define PCINT13_PORT PORTC
-#define PCINT13_BIT 5
-
-#define RESET_PORT PORTC
-#define RESET_BIT 6
-#define PCINT14_PORT PORTC
-#define PCINT14_BIT 6
-
-#define RXD_PORT PORTD
-#define RXD_BIT 0
-#define PCINT16_PORT PORTD
-#define PCINT16_BIT 0
-
-#define TXD_PORT PORTD
-#define TXD_BIT 1
-#define PCINT17_PORT PORTD
-#define PCINT17_BIT 1
-
-#define INT0_PORT PORTD
-#define INT0_BIT 2
-#define PCINT18_PORT PORTD
-#define PCINT18_BIT 2
-
-#define PCINT19_PORT PORTD
-#define PCINT19_BIT 3
-#define OC2B_PORT PORTD
-#define OC2B_BIT 3
-#define INT1_PORT PORTD
-#define INT1_BIT 3
-
-#define XCK_PORT PORTD
-#define XCK_BIT 4
-#define T0_PORT PORTD
-#define T0_BIT 4
-#define PCINT20_PORT PORTD
-#define PCINT20_BIT 4
-
-#define T1_PORT PORTD
-#define T1_BIT 5
-#define OC0B_PORT PORTD
-#define OC0B_BIT 5
-#define PCINT21_PORT PORTD
-#define PCINT21_BIT 5
-
-#define AIN0_PORT PORTD
-#define AIN0_BIT 6
-#define OC0A_PORT PORTD
-#define OC0A_BIT 6
-#define PCINT22_PORT PORTD
-#define PCINT22_BIT 6
-
-#define AIN1_PORT PORTD
-#define AIN1_BIT 7
-#define PCINT23_PORT PORTD
-#define PCINT23_BIT 7
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-#define TIMER2A_AVAILABLE
-#define TIMER2B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE2A_NUM 4
-#define SIG_OUTPUT_COMPARE2B_NUM 5
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 6
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM2A_NUM 4
-#define PWM2B_NUM 5
-#define PWM_TOTAL_NUM 6
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* OCR2B */
-#define OCR2B_0_REG OCR2B
-#define OCR2B_1_REG OCR2B
-#define OCR2B_2_REG OCR2B
-#define OCR2B_3_REG OCR2B
-#define OCR2B_4_REG OCR2B
-#define OCR2B_5_REG OCR2B
-#define OCR2B_6_REG OCR2B
-#define OCR2B_7_REG OCR2B
-
-/* OCR2A */
-#define OCR2A_0_REG OCR2A
-#define OCR2A_1_REG OCR2A
-#define OCR2A_2_REG OCR2A
-#define OCR2A_3_REG OCR2A
-#define OCR2A_4_REG OCR2A
-#define OCR2A_5_REG OCR2A
-#define OCR2A_6_REG OCR2A
-#define OCR2A_7_REG OCR2A
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSART0_REG PRR
-#define PRSPI_REG PRR
-#define PRTIM1_REG PRR
-#define PRTIM0_REG PRR
-#define PRTIM2_REG PRR
-#define PRTWI_REG PRR
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* UCSR0A */
-#define MPCM0_REG UCSR0A
-#define U2X0_REG UCSR0A
-#define UPE0_REG UCSR0A
-#define DOR0_REG UCSR0A
-#define FE0_REG UCSR0A
-#define UDRE0_REG UCSR0A
-#define TXC0_REG UCSR0A
-#define RXC0_REG UCSR0A
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* UCSR0B */
-#define TXB80_REG UCSR0B
-#define RXB80_REG UCSR0B
-#define UCSZ02_REG UCSR0B
-#define TXEN0_REG UCSR0B
-#define RXEN0_REG UCSR0B
-#define UDRIE0_REG UCSR0B
-#define TXCIE0_REG UCSR0B
-#define RXCIE0_REG UCSR0B
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-
-/* UDR0 */
-#define UDR0_0_REG UDR0
-#define UDR0_1_REG UDR0
-#define UDR0_2_REG UDR0
-#define UDR0_3_REG UDR0
-#define UDR0_4_REG UDR0
-#define UDR0_5_REG UDR0
-#define UDR0_6_REG UDR0
-#define UDR0_7_REG UDR0
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* ASSR */
-#define TCR2BUB_REG ASSR
-#define TCR2AUB_REG ASSR
-#define OCR2BUB_REG ASSR
-#define OCR2AUB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-#define EXCLK_REG ASSR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* PCICR */
-#define PCIE0_REG PCICR
-#define PCIE1_REG PCICR
-#define PCIE2_REG PCICR
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* TIFR2 */
-#define TOV2_REG TIFR2
-#define OCF2A_REG TIFR2
-#define OCF2B_REG TIFR2
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* GTCCR */
-#define PSRSYNC_REG GTCCR
-#define TSM_REG GTCCR
-#define PSRASY_REG GTCCR
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* PCIFR */
-#define PCIF0_REG PCIFR
-#define PCIF1_REG PCIFR
-#define PCIF2_REG PCIFR
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* TCCR2A */
-#define WGM20_REG TCCR2A
-#define WGM21_REG TCCR2A
-#define COM2B0_REG TCCR2A
-#define COM2B1_REG TCCR2A
-#define COM2A0_REG TCCR2A
-#define COM2A1_REG TCCR2A
-
-/* TCCR2B */
-#define CS20_REG TCCR2B
-#define CS21_REG TCCR2B
-#define CS22_REG TCCR2B
-#define WGM22_REG TCCR2B
-#define FOC2B_REG TCCR2B
-#define FOC2A_REG TCCR2B
-
-/* UBRR0H */
-#define UBRR8_REG UBRR0H
-#define UBRR9_REG UBRR0H
-#define UBRR10_REG UBRR0H
-#define UBRR11_REG UBRR0H
-
-/* UBRR0L */
-#define UBRR0_REG UBRR0L
-#define UBRR1_REG UBRR0L
-#define UBRR2_REG UBRR0L
-#define UBRR3_REG UBRR0L
-#define UBRR4_REG UBRR0L
-#define UBRR5_REG UBRR0L
-#define UBRR6_REG UBRR0L
-#define UBRR7_REG UBRR0L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* MCUCR */
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-#define BODSE_REG MCUCR
-#define BODS_REG MCUCR
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ACME_REG ADCSRB
-
-/* OCR0A */
-#define OCROA_0_REG OCR0A
-#define OCROA_1_REG OCR0A
-#define OCROA_2_REG OCR0A
-#define OCROA_3_REG OCR0A
-#define OCROA_4_REG OCR0A
-#define OCROA_5_REG OCR0A
-#define OCROA_6_REG OCR0A
-#define OCROA_7_REG OCR0A
-
-/* OCR0B */
-#define OCR0B_0_REG OCR0B
-#define OCR0B_1_REG OCR0B
-#define OCR0B_2_REG OCR0B
-#define OCR0B_3_REG OCR0B
-#define OCR0B_4_REG OCR0B
-#define OCR0B_5_REG OCR0B
-#define OCR0B_6_REG OCR0B
-#define OCR0B_7_REG OCR0B
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* UCSR0C */
-#define UCPOL0_REG UCSR0C
-#define UCSZ00_REG UCSR0C
-#define UCSZ01_REG UCSR0C
-#define USBS0_REG UCSR0C
-#define UPM00_REG UCSR0C
-#define UPM01_REG UCSR0C
-#define UMSEL00_REG UCSR0C
-#define UMSEL01_REG UCSR0C
-
-/* SPMCSR */
-#define SELFPRGEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* TIMSK2 */
-#define TOIE2_REG TIMSK2
-#define OCIE2A_REG TIMSK2
-#define OCIE2B_REG TIMSK2
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-
-/* PCMSK2 */
-#define PCINT16_REG PCMSK2
-#define PCINT17_REG PCMSK2
-#define PCINT18_REG PCMSK2
-#define PCINT19_REG PCMSK2
-#define PCINT20_REG PCMSK2
-#define PCINT21_REG PCMSK2
-#define PCINT22_REG PCMSK2
-#define PCINT23_REG PCMSK2
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* TWAMR */
-#define TWAM0_REG TWAMR
-#define TWAM1_REG TWAMR
-#define TWAM2_REG TWAMR
-#define TWAM3_REG TWAMR
-#define TWAM4_REG TWAMR
-#define TWAM5_REG TWAMR
-#define TWAM6_REG TWAMR
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* pins mapping */
-#define ICP1_PORT PORTB
-#define ICP1_BIT 0
-#define CLKO_PORT PORTB
-#define CLKO_BIT 0
-#define PCINT0_PORT PORTB
-#define PCINT0_BIT 0
-
-#define OC1A_PORT PORTB
-#define OC1A_BIT 1
-#define PCINT1_PORT PORTB
-#define PCINT1_BIT 1
-
-#define SS_PORT PORTB
-#define SS_BIT 2
-#define OC1B_PORT PORTB
-#define OC1B_BIT 2
-#define PCINT2_PORT PORTB
-#define PCINT2_BIT 2
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 3
-#define OC2A_PORT PORTB
-#define OC2A_BIT 3
-#define PCINT3_PORT PORTB
-#define PCINT3_BIT 3
-
-#define MISO_PORT PORTB
-#define MISO_BIT 4
-#define PCINT4_PORT PORTB
-#define PCINT4_BIT 4
-
-#define SCK_PORT PORTB
-#define SCK_BIT 5
-#define PCINT5_PORT PORTB
-#define PCINT5_BIT 5
-
-#define XTAL1_PORT PORTB
-#define XTAL1_BIT 6
-#define TOSC1_PORT PORTB
-#define TOSC1_BIT 6
-#define PCINT6_PORT PORTB
-#define PCINT6_BIT 6
-
-#define XTAL2_PORT PORTB
-#define XTAL2_BIT 7
-#define TOSC2_PORT PORTB
-#define TOSC2_BIT 7
-#define PCINT7_PORT PORTB
-#define PCINT7_BIT 7
-
-#define ADC0_PORT PORTC
-#define ADC0_BIT 0
-#define PCINT8_PORT PORTC
-#define PCINT8_BIT 0
-
-#define ADC1_PORT PORTC
-#define ADC1_BIT 1
-#define PCINT9_PORT PORTC
-#define PCINT9_BIT 1
-
-#define ADC2_PORT PORTC
-#define ADC2_BIT 2
-#define PCINT10_PORT PORTC
-#define PCINT10_BIT 2
-
-#define ADC3_PORT PORTC
-#define ADC3_BIT 3
-#define PCINT11_PORT PORTC
-#define PCINT11_BIT 3
-
-#define ADC4_PORT PORTC
-#define ADC4_BIT 4
-#define SDA_PORT PORTC
-#define SDA_BIT 4
-#define PCINT12_PORT PORTC
-#define PCINT12_BIT 4
-
-#define ADC5_PORT PORTC
-#define ADC5_BIT 5
-#define SCL_PORT PORTC
-#define SCL_BIT 5
-#define PCINT13_PORT PORTC
-#define PCINT13_BIT 5
-
-#define RESET_PORT PORTC
-#define RESET_BIT 6
-#define PCINT14_PORT PORTC
-#define PCINT14_BIT 6
-
-#define RXD_PORT PORTD
-#define RXD_BIT 0
-#define PCINT16_PORT PORTD
-#define PCINT16_BIT 0
-
-#define TXD_PORT PORTD
-#define TXD_BIT 1
-#define PCINT17_PORT PORTD
-#define PCINT17_BIT 1
-
-#define INT0_PORT PORTD
-#define INT0_BIT 2
-#define PCINT18_PORT PORTD
-#define PCINT18_BIT 2
-
-#define PCINT19_PORT PORTD
-#define PCINT19_BIT 3
-#define OC2B_PORT PORTD
-#define OC2B_BIT 3
-#define INT1_PORT PORTD
-#define INT1_BIT 3
-
-#define XCK_PORT PORTD
-#define XCK_BIT 4
-#define T0_PORT PORTD
-#define T0_BIT 4
-#define PCINT20_PORT PORTD
-#define PCINT20_BIT 4
-
-#define T1_PORT PORTD
-#define T1_BIT 5
-#define OC0B_PORT PORTD
-#define OC0B_BIT 5
-#define PCINT21_PORT PORTD
-#define PCINT21_BIT 5
-
-#define AIN0_PORT PORTD
-#define AIN0_BIT 6
-#define OC0A_PORT PORTD
-#define OC0A_BIT 6
-#define PCINT22_PORT PORTD
-#define PCINT22_BIT 6
-
-#define AIN1_PORT PORTD
-#define AIN1_BIT 7
-#define PCINT23_PORT PORTD
-#define PCINT23_BIT 7
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 2 */
-#define TIMER2_PRESCALER_DIV_0 0
-#define TIMER2_PRESCALER_DIV_1 1
-#define TIMER2_PRESCALER_DIV_8 2
-#define TIMER2_PRESCALER_DIV_32 3
-#define TIMER2_PRESCALER_DIV_64 4
-#define TIMER2_PRESCALER_DIV_128 5
-#define TIMER2_PRESCALER_DIV_256 6
-#define TIMER2_PRESCALER_DIV_1024 7
-
-#define TIMER2_PRESCALER_REG_0 0
-#define TIMER2_PRESCALER_REG_1 1
-#define TIMER2_PRESCALER_REG_2 8
-#define TIMER2_PRESCALER_REG_3 32
-#define TIMER2_PRESCALER_REG_4 64
-#define TIMER2_PRESCALER_REG_5 128
-#define TIMER2_PRESCALER_REG_6 256
-#define TIMER2_PRESCALER_REG_7 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER2_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW2_NUM 2
-#define SIG_OVERFLOW_TOTAL_NUM 3
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE1A_NUM 0
-#define SIG_OUTPUT_COMPARE1B_NUM 1
-#define SIG_OUTPUT_COMPARE2_NUM 2
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 3
-
-/* Pwm nums */
-#define PWM1A_NUM 0
-#define PWM1B_NUM 1
-#define PWM2_NUM 2
-#define PWM_TOTAL_NUM 3
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* TCCR0 */
-#define CS00_REG TCCR0
-#define CS01_REG TCCR0
-#define CS02_REG TCCR0
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* GICR */
-#define IVCE_REG GICR
-#define IVSEL_REG GICR
-#define INT0_REG GICR
-#define INT1_REG GICR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define FOC1B_REG TCCR1A
-#define FOC1A_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* GIFR */
-#define INTF0_REG GIFR
-#define INTF1_REG GIFR
-
-/* TIMSK */
-#define TOIE0_REG TIMSK
-#define TOIE1_REG TIMSK
-#define OCIE1B_REG TIMSK
-#define OCIE1A_REG TIMSK
-#define TICIE1_REG TIMSK
-#define TOIE2_REG TIMSK
-#define OCIE2_REG TIMSK
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADFR_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* UCSRA */
-#define MPCM_REG UCSRA
-#define U2X_REG UCSRA
-#define UPE_REG UCSRA
-#define DOR_REG UCSRA
-#define FE_REG UCSRA
-#define UDRE_REG UCSRA
-#define TXC_REG UCSRA
-#define RXC_REG UCSRA
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SFIOR */
-#define ACME_REG SFIOR
-#define PSR2_REG SFIOR
-#define PSR10_REG SFIOR
-#define PUD_REG SFIOR
-#define ADHSM_REG SFIOR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* UCSRB */
-#define TXB8_REG UCSRB
-#define RXB8_REG UCSRB
-#define UCSZ2_REG UCSRB
-#define TXEN_REG UCSRB
-#define RXEN_REG UCSRB
-#define UDRIE_REG UCSRB
-#define TXCIE_REG UCSRB
-#define RXCIE_REG UCSRB
-
-/* UCSRC */
-#define UCPOL_REG UCSRC
-#define UCSZ0_REG UCSRC
-#define UCSZ1_REG UCSRC
-#define USBS_REG UCSRC
-#define UPM0_REG UCSRC
-#define UPM1_REG UCSRC
-#define UMSEL_REG UCSRC
-#define URSEL_REG UCSRC
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* UDR */
-#define UDR0_REG UDR
-#define UDR1_REG UDR
-#define UDR2_REG UDR
-#define UDR3_REG UDR
-#define UDR4_REG UDR
-#define UDR5_REG UDR
-#define UDR6_REG UDR
-#define UDR7_REG UDR
-
-/* SPMCR */
-#define SPMEN_REG SPMCR
-#define PGERS_REG SPMCR
-#define PGWRT_REG SPMCR
-#define BLBSET_REG SPMCR
-#define RWWSRE_REG SPMCR
-#define RWWSB_REG SPMCR
-#define SPMIE_REG SPMCR
-
-/* UBRRH */
-#define UBRR8_REG UBRRH
-#define UBRR9_REG UBRRH
-#define UBRR10_REG UBRRH
-#define UBRR11_REG UBRRH
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* UBRRL */
-#define UBRR0_REG UBRRL
-#define UBRR1_REG UBRRL
-#define UBRR2_REG UBRRL
-#define UBRR3_REG UBRRL
-#define UBRR4_REG UBRRL
-#define UBRR5_REG UBRRL
-#define UBRR6_REG UBRRL
-#define UBRR7_REG UBRRL
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* TCNT0 */
-#define TCNT00_REG TCNT0
-#define TCNT01_REG TCNT0
-#define TCNT02_REG TCNT0
-#define TCNT03_REG TCNT0
-#define TCNT04_REG TCNT0
-#define TCNT05_REG TCNT0
-#define TCNT06_REG TCNT0
-#define TCNT07_REG TCNT0
-
-/* MCUCSR */
-#define PORF_REG MCUCSR
-#define EXTRF_REG MCUCSR
-#define BORF_REG MCUCSR
-#define WDRF_REG MCUCSR
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* TCCR2 */
-#define CS20_REG TCCR2
-#define CS21_REG TCCR2
-#define CS22_REG TCCR2
-#define WGM21_REG TCCR2
-#define COM20_REG TCCR2
-#define COM21_REG TCCR2
-#define WGM20_REG TCCR2
-#define FOC2_REG TCCR2
-
-/* TIFR */
-#define TOV0_REG TIFR
-#define TOV1_REG TIFR
-#define OCF1B_REG TIFR
-#define OCF1A_REG TIFR
-#define ICF1_REG TIFR
-#define TOV2_REG TIFR
-#define OCF2_REG TIFR
-
-/* EEARH */
-#define EEAR8_REG EEARH
-
-/* TCNT2 */
-#define TCNT2_0_REG TCNT2
-#define TCNT2_1_REG TCNT2
-#define TCNT2_2_REG TCNT2
-#define TCNT2_3_REG TCNT2
-#define TCNT2_4_REG TCNT2
-#define TCNT2_5_REG TCNT2
-#define TCNT2_6_REG TCNT2
-#define TCNT2_7_REG TCNT2
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define ISC10_REG MCUCR
-#define ISC11_REG MCUCR
-#define SM0_REG MCUCR
-#define SM1_REG MCUCR
-#define SM2_REG MCUCR
-#define SE_REG MCUCR
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* ASSR */
-#define TCR2UB_REG ASSR
-#define OCR2UB_REG ASSR
-#define TCN2UB_REG ASSR
-#define AS2_REG ASSR
-
-/* OCR2 */
-#define OCR2_0_REG OCR2
-#define OCR2_1_REG OCR2
-#define OCR2_2_REG OCR2
-#define OCR2_3_REG OCR2
-#define OCR2_4_REG OCR2
-#define OCR2_5_REG OCR2
-#define OCR2_6_REG OCR2
-#define OCR2_7_REG OCR2
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* pins mapping */
-#define ICP_PORT PORTB
-#define ICP_BIT 0
-
-#define OC1A_PORT PORTB
-#define OC1A_BIT 1
-
-#define SS_PORT PORTB
-#define SS_BIT 2
-#define OC1B_PORT PORTB
-#define OC1B_BIT 2
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 3
-#define OC2_PORT PORTB
-#define OC2_BIT 3
-
-#define MISO_PORT PORTB
-#define MISO_BIT 4
-
-#define SCK_PORT PORTB
-#define SCK_BIT 5
-
-#define XTAL1_PORT PORTB
-#define XTAL1_BIT 6
-#define TOSC1_PORT PORTB
-#define TOSC1_BIT 6
-
-#define XTAL2_PORT PORTB
-#define XTAL2_BIT 7
-#define TOSC2_PORT PORTB
-#define TOSC2_BIT 7
-
-#define ADC0_PORT PORTC
-#define ADC0_BIT 0
-
-#define ADC1_PORT PORTC
-#define ADC1_BIT 1
-
-#define ADC2_PORT PORTC
-#define ADC2_BIT 2
-
-#define ADC3_PORT PORTC
-#define ADC3_BIT 3
-
-#define ADC4_PORT PORTC
-#define ADC4_BIT 4
-#define SDA_PORT PORTC
-#define SDA_BIT 4
-
-#define ADC5_PORT PORTC
-#define ADC5_BIT 5
-#define SCL_PORT PORTC
-#define SCL_BIT 5
-
-#define RESET_PORT PORTC
-#define RESET_BIT 6
-
-#define RXD_PORT PORTD
-#define RXD_BIT 0
-
-#define TXD_PORT PORTD
-#define TXD_BIT 1
-
-#define INT0_PORT PORTD
-#define INT0_BIT 2
-
-#define IN1_PORT PORTD
-#define IN1_BIT 3
-
-#define XCK_PORT PORTD
-#define XCK_BIT 4
-#define T0_PORT PORTD
-#define T0_BIT 4
-
-#define T1_PORT PORTD
-#define T1_BIT 5
-
-#define AIN0_PORT PORTD
-#define AIN0_BIT 6
-
-#define AIN1_PORT PORTD
-#define AIN1_BIT 7
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-
-/* available timers */
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW_TOTAL_NUM 0
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0
-
-/* Pwm nums */
-#define PWM_TOTAL_NUM 0
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 0
-
-
-/* CLKPSR */
-#define CLKPS0_REG CLKPSR
-#define CLKPS1_REG CLKPSR
-#define CLKPS2_REG CLKPSR
-#define CLKPS3_REG CLKPSR
-
-/* VLMCSR */
-#define VLM0_REG VLMCSR
-#define VLM1_REG VLMCSR
-#define VLMIE_REG VLMCSR
-#define VLMF_REG VLMCSR
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-
-/* TCNT0H */
-#define TCNT0_8_REG TCNT0H
-#define TCNT0_9_REG TCNT0H
-#define TCNT0_10_REG TCNT0H
-#define TCNT0_11_REG TCNT0H
-#define TCNT0_12_REG TCNT0H
-#define TCNT0_13_REG TCNT0H
-#define TCNT0_14_REG TCNT0H
-#define TCNT0_15_REG TCNT0H
-
-/* PORTCR */
-#define BBMB_REG PORTCR
-
-/* CCP */
-#define CCP0_REG CCP
-#define CCP1_REG CCP
-#define CCP2_REG CCP
-#define CCP3_REG CCP
-#define CCP4_REG CCP
-#define CCP5_REG CCP
-#define CCP6_REG CCP
-#define CCP7_REG CCP
-
-/* TCNT0L */
-#define TCNT0_0_REG TCNT0L
-#define TCNT0_1_REG TCNT0L
-#define TCNT0_2_REG TCNT0L
-#define TCNT0_3_REG TCNT0L
-#define TCNT0_4_REG TCNT0L
-#define TCNT0_5_REG TCNT0L
-#define TCNT0_6_REG TCNT0L
-#define TCNT0_7_REG TCNT0L
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACD_REG ACSR
-
-/* GTCCR */
-#define PSR_REG GTCCR
-#define TSM_REG GTCCR
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-
-/* RSTFLR */
-#define PORF_REG RSTFLR
-#define EXTRF_REG RSTFLR
-#define WDRF_REG RSTFLR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* PCIFR */
-#define PCIF0_REG PCIFR
-
-/* PRR */
-#define PRTIM0_REG PRR
-#define PRADC_REG PRR
-
-/* OCR0BL */
-#define OCR0B0_REG OCR0BL
-#define OCR0B1_REG OCR0BL
-#define OCR0B2_REG OCR0BL
-#define OCR0B3_REG OCR0BL
-#define OCR0B4_REG OCR0BL
-#define OCR0B5_REG OCR0BL
-#define OCR0B6_REG OCR0BL
-#define OCR0B7_REG OCR0BL
-
-/* PCMSK */
-#define PCINT0_REG PCMSK
-#define PCINT1_REG PCMSK
-#define PCINT2_REG PCMSK
-#define PCINT3_REG PCMSK
-
-/* ADCL */
-#define ADC0_REG ADCL
-#define ADC1_REG ADCL
-#define ADC2_REG ADCL
-#define ADC3_REG ADCL
-#define ADC4_REG ADCL
-#define ADC5_REG ADCL
-#define ADC6_REG ADCL
-#define ADC7_REG ADCL
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-
-/* PCICR */
-#define PCIE0_REG PCICR
-
-/* NVMCSR */
-#define NVMBSY_REG NVMCSR
-
-/* EIMSK */
-#define INT0_REG EIMSK
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-#define ICIE0_REG TIMSK0
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define WGM03_REG TCCR0B
-#define ICES0_REG TCCR0B
-#define ICNC0_REG TCCR0B
-
-/* TCCR0C */
-#define FOC0B_REG TCCR0C
-#define FOC0A_REG TCCR0C
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* CLKMSR */
-#define CLKMS0_REG CLKMSR
-#define CLKMS1_REG CLKMSR
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define AIN0D_REG DIDR0
-#define AIN1D_REG DIDR0
-
-/* OCR0AL */
-#define OCR0A0_REG OCR0AL
-#define OCR0A1_REG OCR0AL
-#define OCR0A2_REG OCR0AL
-#define OCR0A3_REG OCR0AL
-#define OCR0A4_REG OCR0AL
-#define OCR0A5_REG OCR0AL
-#define OCR0A6_REG OCR0AL
-#define OCR0A7_REG OCR0AL
-
-/* NVMCMD */
-#define NVMCMD0_REG NVMCMD
-#define NVMCMD1_REG NVMCMD
-#define NVMCMD2_REG NVMCMD
-#define NVMCMD3_REG NVMCMD
-#define NVMCMD4_REG NVMCMD
-#define NVMCMD5_REG NVMCMD
-
-/* ICR0L */
-#define ICR0_0_REG ICR0L
-#define ICR0_1_REG ICR0L
-#define ICR0_2_REG ICR0L
-#define ICR0_3_REG ICR0L
-#define ICR0_4_REG ICR0L
-#define ICR0_5_REG ICR0L
-#define ICR0_6_REG ICR0L
-#define ICR0_7_REG ICR0L
-
-/* OCR0AH */
-#define OCR0A8_REG OCR0AH
-#define OCR0A9_REG OCR0AH
-#define OCR0A10_REG OCR0AH
-#define OCR0A11_REG OCR0AH
-#define OCR0A12_REG OCR0AH
-#define OCR0A13_REG OCR0AH
-#define OCR0A14_REG OCR0AH
-#define OCR0A15_REG OCR0AH
-
-/* ICR0H */
-#define ICR0_8_REG ICR0H
-#define ICR0_9_REG ICR0H
-#define ICR0_10_REG ICR0H
-#define ICR0_11_REG ICR0H
-#define ICR0_12_REG ICR0H
-#define ICR0_13_REG ICR0H
-#define ICR0_14_REG ICR0H
-#define ICR0_15_REG ICR0H
-
-/* PUEB */
-#define PUEB0_REG PUEB
-#define PUEB1_REG PUEB
-#define PUEB2_REG PUEB
-#define PUEB3_REG PUEB
-
-/* OCR0BH */
-#define OCR0B8_REG OCR0BH
-#define OCR0B9_REG OCR0BH
-#define OCR0B10_REG OCR0BH
-#define OCR0B11_REG OCR0BH
-#define OCR0B12_REG OCR0BH
-#define OCR0B13_REG OCR0BH
-#define OCR0B14_REG OCR0BH
-#define OCR0B15_REG OCR0BH
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-#define ICF0_REG TIFR0
-
-/* pins mapping */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW_TOTAL_NUM 1
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0
-
-/* Pwm nums */
-#define PWM_TOTAL_NUM 0
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 0
-
-
-/* GIFR */
-#define PCIF_REG GIFR
-#define INTF0_REG GIFR
-
-/* TIMSK */
-#define TOIE0_REG TIMSK
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDTOE_REG WDTCR
-
-/* GIMSK */
-#define PCIE_REG GIMSK
-#define INT0_REG GIMSK
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-
-/* TCCR0 */
-#define CS00_REG TCCR0
-#define CS01_REG TCCR0
-#define CS02_REG TCCR0
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define SM_REG MCUCR
-#define SE_REG MCUCR
-
-/* TCNT0 */
-#define TCNT00_REG TCNT0
-#define TCNT01_REG TCNT0
-#define TCNT02_REG TCNT0
-#define TCNT03_REG TCNT0
-#define TCNT04_REG TCNT0
-#define TCNT05_REG TCNT0
-#define TCNT06_REG TCNT0
-#define TCNT07_REG TCNT0
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACD_REG ACSR
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* TIFR */
-#define TOV0_REG TIFR
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-
-/* pins mapping */
-#define AIN0_PORT PORTB
-#define AIN0_BIT 0
-
-#define INT0_PORT PORTB
-#define INT0_BIT 1
-#define AIN1_PORT PORTB
-#define AIN1_BIT 1
-
-#define T0_PORT PORTB
-#define T0_BIT 2
-
-#define XTAL1_PORT PORTB
-#define XTAL1_BIT 3
-
-#define XTAL2_PORT PORTB
-#define XTAL2_BIT 4
-
-#define RESET_PORT PORTB
-#define RESET_BIT 5
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW_TOTAL_NUM 1
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0
-
-/* Pwm nums */
-#define PWM_TOTAL_NUM 0
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 0
-
-
-/* GIFR */
-#define PCIF_REG GIFR
-#define INTF0_REG GIFR
-
-/* TIMSK */
-#define TOIE0_REG TIMSK
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDTOE_REG WDTCR
-
-/* GIMSK */
-#define PCIE_REG GIMSK
-#define INT0_REG GIMSK
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-
-/* EEAR */
-#define EEAR0_REG EEAR
-#define EEAR1_REG EEAR
-#define EEAR2_REG EEAR
-#define EEAR3_REG EEAR
-#define EEAR4_REG EEAR
-#define EEAR5_REG EEAR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-
-/* TCCR0 */
-#define CS00_REG TCCR0
-#define CS01_REG TCCR0
-#define CS02_REG TCCR0
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define SM_REG MCUCR
-#define SE_REG MCUCR
-#define PUD_REG MCUCR
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-
-/* TCNT0 */
-#define TCNT00_REG TCNT0
-#define TCNT01_REG TCNT0
-#define TCNT02_REG TCNT0
-#define TCNT03_REG TCNT0
-#define TCNT04_REG TCNT0
-#define TCNT05_REG TCNT0
-#define TCNT06_REG TCNT0
-#define TCNT07_REG TCNT0
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define AINBG_REG ACSR
-#define ACD_REG ACSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* TIFR */
-#define TOV0_REG TIFR
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* pins mapping */
-#define MOSI_PORT PORTB
-#define MOSI_BIT 0
-
-#define MISO_PORT PORTB
-#define MISO_BIT 1
-#define INT0_PORT PORTB
-#define INT0_BIT 1
-
-#define SCK_PORT PORTB
-#define SCK_BIT 2
-#define T0_PORT PORTB
-#define T0_BIT 2
-
-#define CLOCK_PORT PORTB
-#define CLOCK_BIT 3
-
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-
-/* available timers */
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW_TOTAL_NUM 0
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0
-
-/* Pwm nums */
-#define PWM_TOTAL_NUM 0
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 0
-
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-#define WDP3_REG WDTCR
-#define WDTIE_REG WDTCR
-#define WDTIF_REG WDTCR
-
-/* GIMSK */
-#define PCIE_REG GIMSK
-#define INT0_REG GIMSK
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* GTCCR */
-#define PSR10_REG GTCCR
-#define TSM_REG GTCCR
-
-/* GIFR */
-#define PCIF_REG GIFR
-#define INTF0_REG GIFR
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ACME_REG ADCSRB
-
-/* OCR0A */
-#define OCR0A_0_REG OCR0A
-#define OCR0A_1_REG OCR0A
-#define OCR0A_2_REG OCR0A
-#define OCR0A_3_REG OCR0A
-#define OCR0A_4_REG OCR0A
-#define OCR0A_5_REG OCR0A
-#define OCR0A_6_REG OCR0A
-#define OCR0A_7_REG OCR0A
-
-/* OCR0B */
-#define OCR0B_0_REG OCR0B
-#define OCR0B_1_REG OCR0B
-#define OCR0B_2_REG OCR0B
-#define OCR0B_3_REG OCR0B
-#define OCR0B_4_REG OCR0B
-#define OCR0B_5_REG OCR0B
-#define OCR0B_6_REG OCR0B
-#define OCR0B_7_REG OCR0B
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* PCMSK */
-#define PCINT0_REG PCMSK
-#define PCINT1_REG PCMSK
-#define PCINT2_REG PCMSK
-#define PCINT3_REG PCMSK
-#define PCINT4_REG PCMSK
-#define PCINT5_REG PCMSK
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define RFLB_REG SPMCSR
-#define CTPB_REG SPMCSR
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* EEAR */
-#define EEAR0_REG EEAR
-#define EEAR1_REG EEAR
-#define EEAR2_REG EEAR
-#define EEAR3_REG EEAR
-#define EEAR4_REG EEAR
-#define EEAR5_REG EEAR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* DWDR */
-#define DWDR0_REG DWDR
-#define DWDR1_REG DWDR
-#define DWDR2_REG DWDR
-#define DWDR3_REG DWDR
-#define DWDR4_REG DWDR
-#define DWDR5_REG DWDR
-#define DWDR6_REG DWDR
-#define DWDR7_REG DWDR
-
-/* DIDR0 */
-#define ADC1D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC0D_REG DIDR0
-#define AIN0D_REG DIDR0
-#define AIN1D_REG DIDR0
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define SM0_REG MCUCR
-#define SM1_REG MCUCR
-#define SE_REG MCUCR
-#define PUD_REG MCUCR
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* pins mapping */
-#define MOSI_PORT PORTB
-#define MOSI_BIT 0
-#define AIN0_PORT PORTB
-#define AIN0_BIT 0
-#define OC0A_PORT PORTB
-#define OC0A_BIT 0
-#define TXD_PORT PORTB
-#define TXD_BIT 0
-#define PCINT0_PORT PORTB
-#define PCINT0_BIT 0
-
-#define MISO_PORT PORTB
-#define MISO_BIT 1
-#define INT0_PORT PORTB
-#define INT0_BIT 1
-#define AIN1_PORT PORTB
-#define AIN1_BIT 1
-#define OC0B_PORT PORTB
-#define OC0B_BIT 1
-#define INT0_PORT PORTB
-#define INT0_BIT 1
-#define RXD_PORT PORTB
-#define RXD_BIT 1
-#define PCINT1_PORT PORTB
-#define PCINT1_BIT 1
-
-#define SCK_PORT PORTB
-#define SCK_BIT 2
-#define ADC1_PORT PORTB
-#define ADC1_BIT 2
-#define T0_PORT PORTB
-#define T0_BIT 2
-#define PCINT2_PORT PORTB
-#define PCINT2_BIT 2
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-
-/* available timers */
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW_TOTAL_NUM 0
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0
-
-/* Pwm nums */
-#define PWM_TOTAL_NUM 0
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 0
-
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-#define WDP3_REG WDTCR
-#define WDTIE_REG WDTCR
-#define WDTIF_REG WDTCR
-
-/* GIMSK */
-#define PCIE_REG GIMSK
-#define INT0_REG GIMSK
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* GTCCR */
-#define PSR10_REG GTCCR
-#define TSM_REG GTCCR
-
-/* GIFR */
-#define PCIF_REG GIFR
-#define INTF0_REG GIFR
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ACME_REG ADCSRB
-
-/* OCR0A */
-#define OCR0A_0_REG OCR0A
-#define OCR0A_1_REG OCR0A
-#define OCR0A_2_REG OCR0A
-#define OCR0A_3_REG OCR0A
-#define OCR0A_4_REG OCR0A
-#define OCR0A_5_REG OCR0A
-#define OCR0A_6_REG OCR0A
-#define OCR0A_7_REG OCR0A
-
-/* OCR0B */
-#define OCR0B_0_REG OCR0B
-#define OCR0B_1_REG OCR0B
-#define OCR0B_2_REG OCR0B
-#define OCR0B_3_REG OCR0B
-#define OCR0B_4_REG OCR0B
-#define OCR0B_5_REG OCR0B
-#define OCR0B_6_REG OCR0B
-#define OCR0B_7_REG OCR0B
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRTIM0_REG PRR
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* PCMSK */
-#define PCINT0_REG PCMSK
-#define PCINT1_REG PCMSK
-#define PCINT2_REG PCMSK
-#define PCINT3_REG PCMSK
-#define PCINT4_REG PCMSK
-#define PCINT5_REG PCMSK
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define RFLB_REG SPMCSR
-#define CTPB_REG SPMCSR
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* EEAR */
-#define EEAR0_REG EEAR
-#define EEAR1_REG EEAR
-#define EEAR2_REG EEAR
-#define EEAR3_REG EEAR
-#define EEAR4_REG EEAR
-#define EEAR5_REG EEAR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-
-/* BODCR */
-#define BPDSE_REG BODCR
-#define BPDS_REG BODCR
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* DWDR */
-#define DWDR0_REG DWDR
-#define DWDR1_REG DWDR
-#define DWDR2_REG DWDR
-#define DWDR3_REG DWDR
-#define DWDR4_REG DWDR
-#define DWDR5_REG DWDR
-#define DWDR6_REG DWDR
-#define DWDR7_REG DWDR
-
-/* DIDR0 */
-#define ADC1D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC0D_REG DIDR0
-#define AIN0D_REG DIDR0
-#define AIN1D_REG DIDR0
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define SM0_REG MCUCR
-#define SM1_REG MCUCR
-#define SE_REG MCUCR
-#define PUD_REG MCUCR
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* pins mapping */
-#define MOSI_PORT PORTB
-#define MOSI_BIT 0
-#define AIN0_PORT PORTB
-#define AIN0_BIT 0
-#define OC0A_PORT PORTB
-#define OC0A_BIT 0
-#define TXD_PORT PORTB
-#define TXD_BIT 0
-#define PCINT0_PORT PORTB
-#define PCINT0_BIT 0
-
-#define MISO_PORT PORTB
-#define MISO_BIT 1
-#define INT0_PORT PORTB
-#define INT0_BIT 1
-#define AIN1_PORT PORTB
-#define AIN1_BIT 1
-#define OC0B_PORT PORTB
-#define OC0B_BIT 1
-#define INT0_PORT PORTB
-#define INT0_BIT 1
-#define RXD_PORT PORTB
-#define RXD_BIT 1
-#define PCINT1_PORT PORTB
-#define PCINT1_BIT 1
-
-#define SCK_PORT PORTB
-#define SCK_BIT 2
-#define ADC1_PORT PORTB
-#define ADC1_BIT 2
-#define T0_PORT PORTB
-#define T0_BIT 2
-#define PCINT2_PORT PORTB
-#define PCINT2_BIT 2
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_-3 1
-#define TIMER1_PRESCALER_DIV_-3 2
-#define TIMER1_PRESCALER_DIV_-3 3
-#define TIMER1_PRESCALER_DIV_-3 4
-#define TIMER1_PRESCALER_DIV_1 5
-#define TIMER1_PRESCALER_DIV_2 6
-#define TIMER1_PRESCALER_DIV_4 7
-#define TIMER1_PRESCALER_DIV_8 8
-#define TIMER1_PRESCALER_DIV_16 9
-#define TIMER1_PRESCALER_DIV_32 10
-#define TIMER1_PRESCALER_DIV_64 11
-#define TIMER1_PRESCALER_DIV_128 12
-#define TIMER1_PRESCALER_DIV_256 13
-#define TIMER1_PRESCALER_DIV_512 14
-#define TIMER1_PRESCALER_DIV_1024 15
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 -3
-#define TIMER1_PRESCALER_REG_2 -3
-#define TIMER1_PRESCALER_REG_3 -3
-#define TIMER1_PRESCALER_REG_4 -3
-#define TIMER1_PRESCALER_REG_5 1
-#define TIMER1_PRESCALER_REG_6 2
-#define TIMER1_PRESCALER_REG_7 4
-#define TIMER1_PRESCALER_REG_8 8
-#define TIMER1_PRESCALER_REG_9 16
-#define TIMER1_PRESCALER_REG_10 32
-#define TIMER1_PRESCALER_REG_11 64
-#define TIMER1_PRESCALER_REG_12 128
-#define TIMER1_PRESCALER_REG_13 256
-#define TIMER1_PRESCALER_REG_14 512
-#define TIMER1_PRESCALER_REG_15 1024
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW_TOTAL_NUM 2
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE1_NUM 0
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 1
-
-/* Pwm nums */
-#define PWM1_NUM 0
-#define PWM_TOTAL_NUM 1
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 0
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDTOE_REG WDTCR
-
-/* GIMSK */
-#define PCIE_REG GIMSK
-#define INT0_REG GIMSK
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* TCCR1 */
-#define CS10_REG TCCR1
-#define CS11_REG TCCR1
-#define CS12_REG TCCR1
-#define CS13_REG TCCR1
-#define COM1A0_REG TCCR1
-#define COM1A1_REG TCCR1
-#define PWM1_REG TCCR1
-#define CTC1_REG TCCR1
-
-/* TCCR0 */
-#define CS00_REG TCCR0
-#define CS01_REG TCCR0
-#define CS02_REG TCCR0
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* OCR1A */
-#define OCR1A0_REG OCR1A
-#define OCR1A1_REG OCR1A
-#define OCR1A2_REG OCR1A
-#define OCR1A3_REG OCR1A
-#define OCR1A4_REG OCR1A
-#define OCR1A5_REG OCR1A
-#define OCR1A6_REG OCR1A
-#define OCR1A7_REG OCR1A
-
-/* GIFR */
-#define PCIF_REG GIFR
-#define INTF0_REG GIFR
-
-/* TIMSK */
-#define TOIE0_REG TIMSK
-#define TOIE1_REG TIMSK
-#define OCIE1A_REG TIMSK
-
-/* SFIOR */
-#define PSR0_REG SFIOR
-#define PSR1_REG SFIOR
-#define FOC1A_REG SFIOR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* EEAR */
-#define EEAR0_REG EEAR
-#define EEAR1_REG EEAR
-#define EEAR2_REG EEAR
-#define EEAR3_REG EEAR
-#define EEAR4_REG EEAR
-#define EEAR5_REG EEAR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* TCNT0 */
-#define TCNT00_REG TCNT0
-#define TCNT01_REG TCNT0
-#define TCNT02_REG TCNT0
-#define TCNT03_REG TCNT0
-#define TCNT04_REG TCNT0
-#define TCNT05_REG TCNT0
-#define TCNT06_REG TCNT0
-#define TCNT07_REG TCNT0
-
-/* TCNT1 */
-#define TCNT1_0_REG TCNT1
-#define TCNT1_1_REG TCNT1
-#define TCNT1_2_REG TCNT1
-#define TCNT1_3_REG TCNT1
-#define TCNT1_4_REG TCNT1
-#define TCNT1_5_REG TCNT1
-#define TCNT1_6_REG TCNT1
-#define TCNT1_7_REG TCNT1
-
-/* TIFR */
-#define TOV0_REG TIFR
-#define TOV1_REG TIFR
-#define OCF1A_REG TIFR
-
-/* ADCSR */
-#define ADPS0_REG ADCSR
-#define ADPS1_REG ADCSR
-#define ADPS2_REG ADCSR
-#define ADIE_REG ADCSR
-#define ADIF_REG ADCSR
-#define ADFR_REG ADCSR
-#define ADSC_REG ADCSR
-#define ADEN_REG ADCSR
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-
-/* OCR1B */
-#define OCR1B0_REG OCR1B
-#define OCR1B1_REG OCR1B
-#define OCR1B2_REG OCR1B
-#define OCR1B3_REG OCR1B
-#define OCR1B4_REG OCR1B
-#define OCR1B5_REG OCR1B
-#define OCR1B6_REG OCR1B
-#define OCR1B7_REG OCR1B
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define SM0_REG MCUCR
-#define SM1_REG MCUCR
-#define SE_REG MCUCR
-#define PUD_REG MCUCR
-
-/* pins mapping */
-#define MOSI_PORT PORTB
-#define MOSI_BIT 0
-#define AIN0_PORT PORTB
-#define AIN0_BIT 0
-#define AREF_PORT PORTB
-#define AREF_BIT 0
-
-#define MISO_PORT PORTB
-#define MISO_BIT 1
-#define AIN1_PORT PORTB
-#define AIN1_BIT 1
-#define OCP_PORT PORTB
-#define OCP_BIT 1
-
-#define SCK_PORT PORTB
-#define SCK_BIT 2
-#define ADC1_PORT PORTB
-#define ADC1_BIT 2
-#define T0_PORT PORTB
-#define T0_BIT 2
-#define INT0_PORT PORTB
-#define INT0_BIT 2
-
-#define ADC2_PORT PORTB
-#define ADC2_BIT 3
-
-#define ADC3_PORT PORTB
-#define ADC3_BIT 4
-
-#define RESET_PORT PORTB
-#define RESET_BIT 5
-#define ADC0_PORT PORTB
-#define ADC0_BIT 5
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_32 3
-#define TIMER0_PRESCALER_DIV_64 4
-#define TIMER0_PRESCALER_DIV_128 5
-#define TIMER0_PRESCALER_DIV_256 6
-#define TIMER0_PRESCALER_DIV_1024 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 32
-#define TIMER0_PRESCALER_REG_4 64
-#define TIMER0_PRESCALER_REG_5 128
-#define TIMER0_PRESCALER_REG_6 256
-#define TIMER0_PRESCALER_REG_7 1024
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW_TOTAL_NUM 2
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE1A_NUM 1
-#define SIG_OUTPUT_COMPARE1B_NUM 2
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 3
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM1A_NUM 1
-#define PWM1B_NUM 2
-#define PWM_TOTAL_NUM 3
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* LINIDR */
-#define LID0_REG LINIDR
-#define LID1_REG LINIDR
-#define LID2_REG LINIDR
-#define LID3_REG LINIDR
-#define LID4_REG LINIDR
-#define LID5_REG LINIDR
-#define LP0_REG LINIDR
-#define LP1_REG LINIDR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-#define WDP3_REG WDTCR
-#define WDIE_REG WDTCR
-#define WDIF_REG WDTCR
-
-/* PCIFR */
-#define PCIF0_REG PCIFR
-#define PCIF1_REG PCIFR
-
-/* LINBTR */
-#define LBT0_REG LINBTR
-#define LBT1_REG LINBTR
-#define LBT2_REG LINBTR
-#define LBT3_REG LINBTR
-#define LBT4_REG LINBTR
-#define LBT5_REG LINBTR
-#define LDISR_REG LINBTR
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-
-/* PORTCR */
-#define PUDA_REG PORTCR
-#define PUDB_REG PORTCR
-#define BBMA_REG PORTCR
-#define BBMB_REG PORTCR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* AMISCR */
-#define XREFEN_REG AMISCR
-#define AREFEN_REG AMISCR
-#define ISRCEN_REG AMISCR
-
-/* CLKSELR */
-#define CSEL0_REG CLKSELR
-#define CSEL1_REG CLKSELR
-#define CSEL2_REG CLKSELR
-#define CSEL3_REG CLKSELR
-#define CSUT0_REG CLKSELR
-#define CSUT1_REG CLKSELR
-#define COUT_REG CLKSELR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* TCCR1D */
-#define OC1AU_REG TCCR1D
-#define OC1AV_REG TCCR1D
-#define OC1AW_REG TCCR1D
-#define OC1AX_REG TCCR1D
-#define OC1BU_REG TCCR1D
-#define OC1BV_REG TCCR1D
-#define OC1BW_REG TCCR1D
-#define OC1BX_REG TCCR1D
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* LINSEL */
-#define LINDX0_REG LINSEL
-#define LINDX1_REG LINSEL
-#define LINDX2_REG LINSEL
-#define LAINC_REG LINSEL
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* LINCR */
-#define LCMD0_REG LINCR
-#define LCMD1_REG LINCR
-#define LCMD2_REG LINCR
-#define LENA_REG LINCR
-#define LCONF0_REG LINCR
-#define LCONF1_REG LINCR
-#define LIN13_REG LINCR
-#define LSWRES_REG LINCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* GTCCR */
-#define PSR1_REG GTCCR
-#define PSR0_REG GTCCR
-#define TSM_REG GTCCR
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define BIN_REG ADCSRB
-#define ACIR0_REG ADCSRB
-#define ACIR1_REG ADCSRB
-#define ACME_REG ADCSRB
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* OCR0A */
-#define OCR00_REG OCR0A
-#define OCR01_REG OCR0A
-#define OCR02_REG OCR0A
-#define OCR03_REG OCR0A
-#define OCR04_REG OCR0A
-#define OCR05_REG OCR0A
-#define OCR06_REG OCR0A
-#define OCR07_REG OCR0A
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACIRS_REG ACSR
-#define ACD_REG ACSR
-
-/* USIPP */
-#define USIPOS_REG USIPP
-
-/* OCR1BL */
-/* #define OCR1AL0_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL1_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL2_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL3_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL4_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL5_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL6_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL7_REG OCR1BL */ /* dup in OCR1AL */
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* OCR1BH */
-/* #define OCR1AH0_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH1_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH2_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH3_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH4_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH5_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH6_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH7_REG OCR1BH */ /* dup in OCR1AH */
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSI_REG PRR
-#define PRTIM0_REG PRR
-#define PRTIM1_REG PRR
-#define PRSPI_REG PRR
-#define PRLIN_REG PRR
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* USICR */
-#define USITC_REG USICR
-#define USICLK_REG USICR
-#define USICS0_REG USICR
-#define USICS1_REG USICR
-#define USIWM0_REG USICR
-#define USIWM1_REG USICR
-#define USIOIE_REG USICR
-#define USISIE_REG USICR
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define RFLB_REG SPMCSR
-#define CTPB_REG SPMCSR
-#define SIGRD_REG SPMCSR
-#define RWWSB_REG SPMCSR
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* LINBRRL */
-#define LDIV0_REG LINBRRL
-#define LDIV1_REG LINBRRL
-#define LDIV2_REG LINBRRL
-#define LDIV3_REG LINBRRL
-#define LDIV4_REG LINBRRL
-#define LDIV5_REG LINBRRL
-#define LDIV6_REG LINBRRL
-#define LDIV7_REG LINBRRL
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-
-/* LINBRRH */
-#define LDIV8_REG LINBRRH
-#define LDIV9_REG LINBRRH
-#define LDIV10_REG LINBRRH
-#define LDIV11_REG LINBRRH
-
-/* LINDAT */
-#define LDATA0_REG LINDAT
-#define LDATA1_REG LINDAT
-#define LDATA2_REG LINDAT
-#define LDATA3_REG LINDAT
-#define LDATA4_REG LINDAT
-#define LDATA5_REG LINDAT
-#define LDATA6_REG LINDAT
-#define LDATA7_REG LINDAT
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* LINENIR */
-#define LENRXOK_REG LINENIR
-#define LENTXOK_REG LINENIR
-#define LENIDOK_REG LINENIR
-#define LENERR_REG LINENIR
-
-/* USISR */
-#define USICNT0_REG USISR
-#define USICNT1_REG USISR
-#define USICNT2_REG USISR
-#define USICNT3_REG USISR
-#define USIDC_REG USISR
-#define USIPF_REG USISR
-#define USIOIF_REG USISR
-#define USISIF_REG USISR
-
-/* LINERR */
-#define LBERR_REG LINERR
-#define LCERR_REG LINERR
-#define LPERR_REG LINERR
-#define LSERR_REG LINERR
-#define LFERR_REG LINERR
-#define LOVERR_REG LINERR
-#define LTOERR_REG LINERR
-#define LABORT_REG LINERR
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-
-/* TCNT0 */
-#define TCNT00_REG TCNT0
-#define TCNT01_REG TCNT0
-#define TCNT02_REG TCNT0
-#define TCNT03_REG TCNT0
-#define TCNT04_REG TCNT0
-#define TCNT05_REG TCNT0
-#define TCNT06_REG TCNT0
-#define TCNT07_REG TCNT0
-
-/* PCICR */
-#define PCIE0_REG PCICR
-#define PCIE1_REG PCICR
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* EEARH */
-#define EEAR8_REG EEARH
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-#define PCINT15_REG PCMSK1
-
-/* LINDLR */
-#define LRXDL0_REG LINDLR
-#define LRXDL1_REG LINDLR
-#define LRXDL2_REG LINDLR
-#define LRXDL3_REG LINDLR
-#define LTXDL0_REG LINDLR
-#define LTXDL1_REG LINDLR
-#define LTXDL2_REG LINDLR
-#define LTXDL3_REG LINDLR
-
-/* DWDR */
-#define DWDR0_REG DWDR
-#define DWDR1_REG DWDR
-#define DWDR2_REG DWDR
-#define DWDR3_REG DWDR
-#define DWDR4_REG DWDR
-#define DWDR5_REG DWDR
-#define DWDR6_REG DWDR
-#define DWDR7_REG DWDR
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-
-/* LINSIR */
-#define LRXOK_REG LINSIR
-#define LTXOK_REG LINSIR
-#define LIDOK_REG LINSIR
-#define LERR_REG LINSIR
-#define LBUSY_REG LINSIR
-#define LIDST0_REG LINSIR
-#define LIDST1_REG LINSIR
-#define LIDST2_REG LINSIR
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define ADC8D_REG DIDR1
-#define ADC9D_REG DIDR1
-#define ADC10D_REG DIDR1
-
-/* CLKCSR */
-#define CLKC0_REG CLKCSR
-#define CLKC1_REG CLKCSR
-#define CLKC2_REG CLKCSR
-#define CLKC3_REG CLKCSR
-#define CLKRDY_REG CLKCSR
-#define CLKCCE_REG CLKCSR
-
-/* MCUCR */
-#define PUD_REG MCUCR
-#define BODS_REG MCUCR
-#define BODSE_REG MCUCR
-
-/* OCR1AH */
-/* #define OCR1AH0_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH1_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH2_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH3_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH4_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH5_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH6_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH7_REG OCR1AH */ /* dup in OCR1BH */
-
-/* OCR1AL */
-/* #define OCR1AL0_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL1_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL2_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL3_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL4_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL5_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL6_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL7_REG OCR1AL */ /* dup in OCR1BL */
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* USIBR */
-#define USIBR0_REG USIBR
-#define USIBR1_REG USIBR
-#define USIBR2_REG USIBR
-#define USIBR3_REG USIBR
-#define USIBR4_REG USIBR
-#define USIBR5_REG USIBR
-#define USIBR6_REG USIBR
-#define USIBR7_REG USIBR
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* USIDR */
-#define USIDR0_REG USIDR
-#define USIDR1_REG USIDR
-#define USIDR2_REG USIDR
-#define USIDR3_REG USIDR
-#define USIDR4_REG USIDR
-#define USIDR5_REG USIDR
-#define USIDR6_REG USIDR
-#define USIDR7_REG USIDR
-
-/* ASSR */
-#define TCR0BUB_REG ASSR
-#define TCR0AUB_REG ASSR
-#define OCR0AUB_REG ASSR
-#define TCN0UB_REG ASSR
-#define AS0_REG ASSR
-#define EXCLK_REG ASSR
-
-/* pins mapping */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW_TOTAL_NUM 1
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0
-
-/* Pwm nums */
-#define PWM_TOTAL_NUM 0
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 0
-
-
-/* TIMSK */
-#define TOIE0_REG TIMSK
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDTOE_REG WDTCR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-
-/* EEAR */
-#define EEAR0_REG EEAR
-#define EEAR1_REG EEAR
-#define EEAR2_REG EEAR
-#define EEAR3_REG EEAR
-#define EEAR4_REG EEAR
-#define EEAR5_REG EEAR
-#define EEAR6_REG EEAR
-#define EEAR7_REG EEAR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-
-/* TCCR0 */
-#define CS00_REG TCCR0
-#define CS01_REG TCCR0
-#define CS02_REG TCCR0
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define SM_REG MCUCR
-#define SE_REG MCUCR
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-
-/* TCNT0 */
-#define TCNT00_REG TCNT0
-#define TCNT01_REG TCNT0
-#define TCNT02_REG TCNT0
-#define TCNT03_REG TCNT0
-#define TCNT04_REG TCNT0
-#define TCNT05_REG TCNT0
-#define TCNT06_REG TCNT0
-#define TCNT07_REG TCNT0
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* TIFR */
-#define TOV0_REG TIFR
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-
-/* pins mapping */
-#define MOSI_PORT PORTB
-#define MOSI_BIT 0
-
-#define MISO_PORT PORTB
-#define MISO_BIT 1
-#define INT0_PORT PORTB
-#define INT0_BIT 1
-
-#define SCK_PORT PORTB
-#define SCK_BIT 2
-#define T0_PORT PORTB
-#define T0_BIT 2
-
-#define CLOCK_PORT PORTB
-#define CLOCK_BIT 3
-
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW_TOTAL_NUM 2
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* DIDR */
-#define AIN0D_REG DIDR
-#define AIN1D_REG DIDR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-#define WDP3_REG WDTCR
-#define WDIE_REG WDTCR
-#define WDIF_REG WDTCR
-
-/* GIMSK */
-#define PCIE_REG GIMSK
-#define INT0_REG GIMSK
-#define INT1_REG GIMSK
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* USISR */
-#define USICNT0_REG USISR
-#define USICNT1_REG USISR
-#define USICNT2_REG USISR
-#define USICNT3_REG USISR
-#define USIDC_REG USISR
-#define USIPF_REG USISR
-#define USIOIF_REG USISR
-#define USISIF_REG USISR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* GTCCR */
-#define PSR10_REG GTCCR
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* TIMSK */
-#define OCIE0A_REG TIMSK
-#define TOIE0_REG TIMSK
-#define OCIE0B_REG TIMSK
-#define ICIE1_REG TIMSK
-#define OCIE1B_REG TIMSK
-#define OCIE1A_REG TIMSK
-#define TOIE1_REG TIMSK
-
-/* UCSRA */
-#define MPCM_REG UCSRA
-#define U2X_REG UCSRA
-#define UPE_REG UCSRA
-#define DOR_REG UCSRA
-#define FE_REG UCSRA
-#define UDRE_REG UCSRA
-#define TXC_REG UCSRA
-#define RXC_REG UCSRA
-
-/* OCR0A */
-/* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-
-/* OCR0B */
-/* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* OCR1BL */
-/* #define OCR1AL0_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL1_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL2_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL3_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL4_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL5_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL6_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL7_REG OCR1BL */ /* dup in OCR1AL */
-
-/* UCSRB */
-#define TXB8_REG UCSRB
-#define RXB8_REG UCSRB
-#define UCSZ2_REG UCSRB
-#define TXEN_REG UCSRB
-#define RXEN_REG UCSRB
-#define UDRIE_REG UCSRB
-#define TXCIE_REG UCSRB
-#define RXCIE_REG UCSRB
-
-/* UCSRC */
-#define UCPOL_REG UCSRC
-#define UCSZ0_REG UCSRC
-#define UCSZ1_REG UCSRC
-#define USBS_REG UCSRC
-#define UPM0_REG UCSRC
-#define UPM1_REG UCSRC
-#define UMSEL_REG UCSRC
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* OCR1BH */
-/* #define OCR1AH0_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH1_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH2_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH3_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH4_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH5_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH6_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH7_REG OCR1BH */ /* dup in OCR1AH */
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* UBRRH */
-#define UBRR8_REG UBRRH
-#define UBRR9_REG UBRRH
-#define UBRR10_REG UBRRH
-#define UBRR11_REG UBRRH
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* UBRRL */
-#define UBRR0_REG UBRRL
-#define UBRR1_REG UBRRL
-#define UBRR2_REG UBRRL
-#define UBRR3_REG UBRRL
-#define UBRR4_REG UBRRL
-#define UBRR5_REG UBRRL
-#define UBRR6_REG UBRRL
-#define UBRR7_REG UBRRL
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* PCMSK */
-#define PCINT0_REG PCMSK
-#define PCINT1_REG PCMSK
-#define PCINT2_REG PCMSK
-#define PCINT3_REG PCMSK
-#define PCINT4_REG PCMSK
-#define PCINT5_REG PCMSK
-#define PCINT6_REG PCMSK
-#define PCINT7_REG PCMSK
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define RFLB_REG SPMCSR
-#define CTPB_REG SPMCSR
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-
-/* EEAR */
-#define EEAR0_REG EEAR
-#define EEAR1_REG EEAR
-#define EEAR2_REG EEAR
-#define EEAR3_REG EEAR
-#define EEAR4_REG EEAR
-#define EEAR5_REG EEAR
-#define EEAR6_REG EEAR
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* TIFR */
-#define OCF0A_REG TIFR
-#define TOV0_REG TIFR
-#define OCF0B_REG TIFR
-#define ICF1_REG TIFR
-#define OCF1B_REG TIFR
-#define OCF1A_REG TIFR
-#define TOV1_REG TIFR
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* UDR */
-#define UDR0_REG UDR
-#define UDR1_REG UDR
-#define UDR2_REG UDR
-#define UDR3_REG UDR
-#define UDR4_REG UDR
-#define UDR5_REG UDR
-#define UDR6_REG UDR
-#define UDR7_REG UDR
-
-/* USICR */
-#define USITC_REG USICR
-#define USICLK_REG USICR
-#define USICS0_REG USICR
-#define USICS1_REG USICR
-#define USIWM0_REG USICR
-#define USIWM1_REG USICR
-#define USIOIE_REG USICR
-#define USISIE_REG USICR
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define PCIF_REG EIFR
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define ISC10_REG MCUCR
-#define ISC11_REG MCUCR
-#define SM0_REG MCUCR
-#define SE_REG MCUCR
-#define SM1_REG MCUCR
-#define PUD_REG MCUCR
-
-/* OCR1AH */
-/* #define OCR1AH0_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH1_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH2_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH3_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH4_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH5_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH6_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH7_REG OCR1AH */ /* dup in OCR1BH */
-
-/* OCR1AL */
-/* #define OCR1AL0_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL1_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL2_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL3_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL4_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL5_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL6_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL7_REG OCR1AL */ /* dup in OCR1BL */
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-
-/* USIDR */
-#define USIDR0_REG USIDR
-#define USIDR1_REG USIDR
-#define USIDR2_REG USIDR
-#define USIDR3_REG USIDR
-#define USIDR4_REG USIDR
-#define USIDR5_REG USIDR
-#define USIDR6_REG USIDR
-#define USIDR7_REG USIDR
-
-/* pins mapping */
-#define AIN0_PORT PORTB
-#define AIN0_BIT 0
-
-#define AIN1_PORT PORTB
-#define AIN1_BIT 1
-
-#define OC0A_PORT PORTB
-#define OC0A_BIT 2
-
-#define OC1A_PORT PORTB
-#define OC1A_BIT 3
-
-#define OC1B_PORT PORTB
-#define OC1B_BIT 4
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 5
-#define DI_PORT PORTB
-#define DI_BIT 5
-
-#define MISO_PORT PORTB
-#define MISO_BIT 6
-#define DO_PORT PORTB
-#define DO_BIT 6
-
-#define SCK_PORT PORTB
-#define SCK_BIT 7
-#define SCL_PORT PORTB
-#define SCL_BIT 7
-
-#define RXD_PORT PORTD
-#define RXD_BIT 0
-
-#define TXD_PORT PORTD
-#define TXD_BIT 1
-
-#define INT0_PORT PORTD
-#define INT0_BIT 2
-#define XCK_PORT PORTD
-#define XCK_BIT 2
-#define CKOUT_PORT PORTD
-#define CKOUT_BIT 2
-
-#define INT1_PORT PORTD
-#define INT1_BIT 3
-
-#define T0_PORT PORTD
-#define T0_BIT 4
-
-#define T1_PORT PORTD
-#define T1_BIT 5
-#define OC0B_PORT PORTD
-#define OC0B_BIT 5
-
-#define ICP_PORT PORTD
-#define ICP_BIT 6
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-
-/* available timers */
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW_TOTAL_NUM 0
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0
-
-/* Pwm nums */
-#define PWM_TOTAL_NUM 0
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 0
-
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* GIMSK */
-#define PCIE0_REG GIMSK
-#define PCIE1_REG GIMSK
-#define INT0_REG GIMSK
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define MUX5_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* GTCCR */
-#define PSR10_REG GTCCR
-#define TSM_REG GTCCR
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* GIFR */
-#define PCIF0_REG GIFR
-#define PCIF1_REG GIFR
-#define INTF0_REG GIFR
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ACME_REG ADCSRB
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ADLAR_REG ADCSRB
-#define BIN_REG ADCSRB
-
-/* OCR0A */
-/* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */
-
-/* OCR0B */
-/* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* OCR1BL */
-/* #define OCR1AL0_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL1_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL2_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL3_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL4_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL5_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL6_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL7_REG OCR1BL */ /* dup in OCR1AL */
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* OCR1BH */
-/* #define OCR1AH0_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH1_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH2_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH3_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH4_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH5_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH6_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH7_REG OCR1BH */ /* dup in OCR1AH */
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSI_REG PRR
-#define PRTIM0_REG PRR
-#define PRTIM1_REG PRR
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define RFLB_REG SPMCSR
-#define CTPB_REG SPMCSR
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* USISR */
-#define USICNT0_REG USISR
-#define USICNT1_REG USISR
-#define USICNT2_REG USISR
-#define USICNT3_REG USISR
-#define USIDC_REG USISR
-#define USIPF_REG USISR
-#define USIOIF_REG USISR
-#define USISIF_REG USISR
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* EEARH */
-#define EEAR8_REG EEARH
-
-/* USICR */
-#define USITC_REG USICR
-#define USICLK_REG USICR
-#define USICS0_REG USICR
-#define USICS1_REG USICR
-#define USIWM0_REG USICR
-#define USIWM1_REG USICR
-#define USIOIE_REG USICR
-#define USISIE_REG USICR
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define SM0_REG MCUCR
-#define SM1_REG MCUCR
-#define SE_REG MCUCR
-#define PUD_REG MCUCR
-
-/* OCR1AH */
-/* #define OCR1AH0_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH1_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH2_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH3_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH4_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH5_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH6_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH7_REG OCR1AH */ /* dup in OCR1BH */
-
-/* OCR1AL */
-/* #define OCR1AL0_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL1_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL2_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL3_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL4_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL5_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL6_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL7_REG OCR1AL */ /* dup in OCR1BL */
-
-/* USIDR */
-#define USIDR0_REG USIDR
-#define USIDR1_REG USIDR
-#define USIDR2_REG USIDR
-#define USIDR3_REG USIDR
-#define USIDR4_REG USIDR
-#define USIDR5_REG USIDR
-#define USIDR6_REG USIDR
-#define USIDR7_REG USIDR
-
-/* USIBR */
-#define USIBR0_REG USIBR
-#define USIBR1_REG USIBR
-#define USIBR2_REG USIBR
-#define USIBR3_REG USIBR
-#define USIBR4_REG USIBR
-#define USIBR5_REG USIBR
-#define USIBR6_REG USIBR
-#define USIBR7_REG USIBR
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* pins mapping */
-#define ADC0_PORT PORTA
-#define ADC0_BIT 0
-#define AREF_PORT PORTA
-#define AREF_BIT 0
-#define PCINT0_PORT PORTA
-#define PCINT0_BIT 0
-
-#define ADC1_PORT PORTA
-#define ADC1_BIT 1
-#define AIN0_PORT PORTA
-#define AIN0_BIT 1
-#define PCINT1_PORT PORTA
-#define PCINT1_BIT 1
-
-#define ADC2_PORT PORTA
-#define ADC2_BIT 2
-#define AIN1_PORT PORTA
-#define AIN1_BIT 2
-#define PCINT2_PORT PORTA
-#define PCINT2_BIT 2
-
-#define ADC3_PORT PORTA
-#define ADC3_BIT 3
-#define T0_PORT PORTA
-#define T0_BIT 3
-#define PCINT3_PORT PORTA
-#define PCINT3_BIT 3
-
-#define ADC4_PORT PORTA
-#define ADC4_BIT 4
-#define USCK_PORT PORTA
-#define USCK_BIT 4
-#define SCL_PORT PORTA
-#define SCL_BIT 4
-#define T1_PORT PORTA
-#define T1_BIT 4
-#define PCINT4_PORT PORTA
-#define PCINT4_BIT 4
-
-#define ADC5_PORT PORTA
-#define ADC5_BIT 5
-#define DO_PORT PORTA
-#define DO_BIT 5
-#define MISO_PORT PORTA
-#define MISO_BIT 5
-#define OC1B_PORT PORTA
-#define OC1B_BIT 5
-#define PCINT5_PORT PORTA
-#define PCINT5_BIT 5
-
-#define PCINT6_PORT PORTA
-#define PCINT6_BIT 6
-#define OC1A_PORT PORTA
-#define OC1A_BIT 6
-#define DI_PORT PORTA
-#define DI_BIT 6
-#define SDA_PORT PORTA
-#define SDA_BIT 6
-#define MOSI_PORT PORTA
-#define MOSI_BIT 6
-#define ADC6_PORT PORTA
-#define ADC6_BIT 6
-
-#define PCINT7_PORT PORTA
-#define PCINT7_BIT 7
-#define ICP1_PORT PORTA
-#define ICP1_BIT 7
-#define OC0B_PORT PORTA
-#define OC0B_BIT 7
-#define ADC7_PORT PORTA
-#define ADC7_BIT 7
-
-#define PCINT8_PORT PORTB
-#define PCINT8_BIT 0
-#define XTAL1_PORT PORTB
-#define XTAL1_BIT 0
-
-#define PCINT9_PORT PORTB
-#define PCINT9_BIT 1
-#define XTAL2_PORT PORTB
-#define XTAL2_BIT 1
-
-#define PCINT10_PORT PORTB
-#define PCINT10_BIT 2
-#define INT0_PORT PORTB
-#define INT0_BIT 2
-#define OC0A_PORT PORTB
-#define OC0A_BIT 2
-#define CKOUT_PORT PORTB
-#define CKOUT_BIT 2
-
-#define PCINT11_PORT PORTB
-#define PCINT11_BIT 3
-#define RESET_PORT PORTB
-#define RESET_BIT 3
-#define dW_PORT PORTB
-#define dW_BIT 3
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_2 2
-#define TIMER1_PRESCALER_DIV_4 3
-#define TIMER1_PRESCALER_DIV_8 4
-#define TIMER1_PRESCALER_DIV_16 5
-#define TIMER1_PRESCALER_DIV_32 6
-#define TIMER1_PRESCALER_DIV_64 7
-#define TIMER1_PRESCALER_DIV_128 8
-#define TIMER1_PRESCALER_DIV_256 9
-#define TIMER1_PRESCALER_DIV_512 10
-#define TIMER1_PRESCALER_DIV_1024 11
-#define TIMER1_PRESCALER_DIV_2048 12
-#define TIMER1_PRESCALER_DIV_4096 13
-#define TIMER1_PRESCALER_DIV_8192 14
-#define TIMER1_PRESCALER_DIV_16384 15
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 2
-#define TIMER1_PRESCALER_REG_3 4
-#define TIMER1_PRESCALER_REG_4 8
-#define TIMER1_PRESCALER_REG_5 16
-#define TIMER1_PRESCALER_REG_6 32
-#define TIMER1_PRESCALER_REG_7 64
-#define TIMER1_PRESCALER_REG_8 128
-#define TIMER1_PRESCALER_REG_9 256
-#define TIMER1_PRESCALER_REG_10 512
-#define TIMER1_PRESCALER_REG_11 1024
-#define TIMER1_PRESCALER_REG_12 2048
-#define TIMER1_PRESCALER_REG_13 4096
-#define TIMER1_PRESCALER_REG_14 8192
-#define TIMER1_PRESCALER_REG_15 16384
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW_TOTAL_NUM 2
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 0
-
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-#define WDP3_REG WDTCR
-#define WDIE_REG WDTCR
-#define WDIF_REG WDTCR
-
-/* GIMSK */
-#define PCIE_REG GIMSK
-#define INT0_REG GIMSK
-
-/* DIDR0 */
-#define AIN0D_REG DIDR0
-#define AIN1D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC0D_REG DIDR0
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define REFS2_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* TCCR1 */
-#define CS10_REG TCCR1
-#define CS11_REG TCCR1
-#define CS12_REG TCCR1
-#define CS13_REG TCCR1
-#define COM1A0_REG TCCR1
-#define COM1A1_REG TCCR1
-#define PWM1A_REG TCCR1
-#define CTC1_REG TCCR1
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define SM0_REG MCUCR
-#define SM1_REG MCUCR
-#define SE_REG MCUCR
-#define PUD_REG MCUCR
-
-/* GTCCR */
-#define PSR0_REG GTCCR
-#define TSM_REG GTCCR
-#define PSR1_REG GTCCR
-#define FOC1A_REG GTCCR
-#define FOC1B_REG GTCCR
-#define COM1B0_REG GTCCR
-#define COM1B1_REG GTCCR
-#define PWM1B_REG GTCCR
-
-/* DTPS */
-#define DTPS0_REG DTPS
-#define DTPS1_REG DTPS
-
-/* GIFR */
-#define PCIF_REG GIFR
-#define INTF0_REG GIFR
-
-/* TIMSK */
-#define TOIE0_REG TIMSK
-#define OCIE0B_REG TIMSK
-#define OCIE0A_REG TIMSK
-#define TOIE1_REG TIMSK
-#define OCIE1B_REG TIMSK
-#define OCIE1A_REG TIMSK
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* DT1B */
-/* #define DTVL0_REG DT1B */ /* dup in DT1A */
-/* #define DTVL1_REG DT1B */ /* dup in DT1A */
-/* #define DTVL2_REG DT1B */ /* dup in DT1A */
-/* #define DTVL3_REG DT1B */ /* dup in DT1A */
-/* #define DTVH0_REG DT1B */ /* dup in DT1A */
-/* #define DTVH1_REG DT1B */ /* dup in DT1A */
-/* #define DTVH2_REG DT1B */ /* dup in DT1A */
-/* #define DTVH3_REG DT1B */ /* dup in DT1A */
-
-/* OCR0A */
-/* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */
-
-/* OCR0B */
-/* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSI_REG PRR
-#define PRTIM0_REG PRR
-#define PRTIM1_REG PRR
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* PCMSK */
-#define PCINT0_REG PCMSK
-#define PCINT1_REG PCMSK
-#define PCINT2_REG PCMSK
-#define PCINT3_REG PCMSK
-#define PCINT4_REG PCMSK
-#define PCINT5_REG PCMSK
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define RFLB_REG SPMCSR
-#define CTPB_REG SPMCSR
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* USISR */
-#define USICNT0_REG USISR
-#define USICNT1_REG USISR
-#define USICNT2_REG USISR
-#define USICNT3_REG USISR
-#define USIDC_REG USISR
-#define USIPF_REG USISR
-#define USIOIF_REG USISR
-#define USISIF_REG USISR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TCNT1 */
-#define TCNT1_0_REG TCNT1
-#define TCNT1_1_REG TCNT1
-#define TCNT1_2_REG TCNT1
-#define TCNT1_3_REG TCNT1
-#define TCNT1_4_REG TCNT1
-#define TCNT1_5_REG TCNT1
-#define TCNT1_6_REG TCNT1
-#define TCNT1_7_REG TCNT1
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* TIFR */
-#define TOV0_REG TIFR
-#define OCF0B_REG TIFR
-#define OCF0A_REG TIFR
-#define TOV1_REG TIFR
-#define OCF1B_REG TIFR
-#define OCF1A_REG TIFR
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* EEARH */
-#define EEAR8_REG EEARH
-
-/* PLLCSR */
-#define PLOCK_REG PLLCSR
-#define PLLE_REG PLLCSR
-#define PCKE_REG PLLCSR
-#define LSM_REG PLLCSR
-
-/* USICR */
-#define USITC_REG USICR
-#define USICLK_REG USICR
-#define USICS0_REG USICR
-#define USICS1_REG USICR
-#define USIWM0_REG USICR
-#define USIWM1_REG USICR
-#define USIOIE_REG USICR
-#define USISIE_REG USICR
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* DWDR */
-#define DWDR0_REG DWDR
-#define DWDR1_REG DWDR
-#define DWDR2_REG DWDR
-#define DWDR3_REG DWDR
-#define DWDR4_REG DWDR
-#define DWDR5_REG DWDR
-#define DWDR6_REG DWDR
-#define DWDR7_REG DWDR
-
-/* ADCSRB */
-#define ACME_REG ADCSRB
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define IPR_REG ADCSRB
-#define BIN_REG ADCSRB
-
-/* OCR1B */
-#define OCR1B0_REG OCR1B
-#define OCR1B1_REG OCR1B
-#define OCR1B2_REG OCR1B
-#define OCR1B3_REG OCR1B
-#define OCR1B4_REG OCR1B
-#define OCR1B5_REG OCR1B
-#define OCR1B6_REG OCR1B
-#define OCR1B7_REG OCR1B
-
-/* OCR1C */
-#define OCR1C0_REG OCR1C
-#define OCR1C1_REG OCR1C
-#define OCR1C2_REG OCR1C
-#define OCR1C3_REG OCR1C
-#define OCR1C4_REG OCR1C
-#define OCR1C5_REG OCR1C
-#define OCR1C6_REG OCR1C
-#define OCR1C7_REG OCR1C
-
-/* DT1A */
-/* #define DTVL0_REG DT1A */ /* dup in DT1B */
-/* #define DTVL1_REG DT1A */ /* dup in DT1B */
-/* #define DTVL2_REG DT1A */ /* dup in DT1B */
-/* #define DTVL3_REG DT1A */ /* dup in DT1B */
-/* #define DTVH0_REG DT1A */ /* dup in DT1B */
-/* #define DTVH1_REG DT1A */ /* dup in DT1B */
-/* #define DTVH2_REG DT1A */ /* dup in DT1B */
-/* #define DTVH3_REG DT1A */ /* dup in DT1B */
-
-/* OCR1A */
-#define OCR1A0_REG OCR1A
-#define OCR1A1_REG OCR1A
-#define OCR1A2_REG OCR1A
-#define OCR1A3_REG OCR1A
-#define OCR1A4_REG OCR1A
-#define OCR1A5_REG OCR1A
-#define OCR1A6_REG OCR1A
-#define OCR1A7_REG OCR1A
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-
-/* USIBR */
-#define USIBR0_REG USIBR
-#define USIBR1_REG USIBR
-#define USIBR2_REG USIBR
-#define USIBR3_REG USIBR
-#define USIBR4_REG USIBR
-#define USIBR5_REG USIBR
-#define USIBR6_REG USIBR
-#define USIBR7_REG USIBR
-
-/* USIDR */
-#define USIDR0_REG USIDR
-#define USIDR1_REG USIDR
-#define USIDR2_REG USIDR
-#define USIDR3_REG USIDR
-#define USIDR4_REG USIDR
-#define USIDR5_REG USIDR
-#define USIDR6_REG USIDR
-#define USIDR7_REG USIDR
-
-/* pins mapping */
-#define MOSI_PORT PORTB
-#define MOSI_BIT 0
-#define DI_PORT PORTB
-#define DI_BIT 0
-#define SDA_PORT PORTB
-#define SDA_BIT 0
-#define AIN0_PORT PORTB
-#define AIN0_BIT 0
-#define OC0A_PORT PORTB
-#define OC0A_BIT 0
-#define OC1A_PORT PORTB
-#define OC1A_BIT 0
-#define AREF_PORT PORTB
-#define AREF_BIT 0
-#define PCINT0_PORT PORTB
-#define PCINT0_BIT 0
-
-#define MISO_PORT PORTB
-#define MISO_BIT 1
-#define DO_PORT PORTB
-#define DO_BIT 1
-#define AIN1_PORT PORTB
-#define AIN1_BIT 1
-#define OC0B_PORT PORTB
-#define OC0B_BIT 1
-#define OC1A_PORT PORTB
-#define OC1A_BIT 1
-#define PCINT1_PORT PORTB
-#define PCINT1_BIT 1
-
-#define SCK_PORT PORTB
-#define SCK_BIT 2
-#define USCK_PORT PORTB
-#define USCK_BIT 2
-#define SCL_PORT PORTB
-#define SCL_BIT 2
-#define ADC1_PORT PORTB
-#define ADC1_BIT 2
-#define T0_PORT PORTB
-#define T0_BIT 2
-#define INT0_PORT PORTB
-#define INT0_BIT 2
-#define PCINT2_PORT PORTB
-#define PCINT2_BIT 2
-
-#define ADC3_PORT PORTB
-#define ADC3_BIT 3
-#define OC1B_PORT PORTB
-#define OC1B_BIT 3
-#define XTAL1_PORT PORTB
-#define XTAL1_BIT 3
-#define PCINT4_PORT PORTB
-#define PCINT4_BIT 3
-
-#define ADC2_PORT PORTB
-#define ADC2_BIT 4
-#define OC1B_PORT PORTB
-#define OC1B_BIT 4
-#define XTAL2_PORT PORTB
-#define XTAL2_BIT 4
-#define PCINT3_PORT PORTB
-#define PCINT3_BIT 4
-
-#define RESET_PORT PORTB
-#define RESET_BIT 5
-#define ADC0_PORT PORTB
-#define ADC0_BIT 5
-#define PCINT5_PORT PORTB
-#define PCINT5_BIT 5
-#define dW_PORT PORTB
-#define dW_BIT 5
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_2 2
-#define TIMER1_PRESCALER_DIV_4 3
-#define TIMER1_PRESCALER_DIV_8 4
-#define TIMER1_PRESCALER_DIV_16 5
-#define TIMER1_PRESCALER_DIV_32 6
-#define TIMER1_PRESCALER_DIV_64 7
-#define TIMER1_PRESCALER_DIV_128 8
-#define TIMER1_PRESCALER_DIV_256 9
-#define TIMER1_PRESCALER_DIV_512 10
-#define TIMER1_PRESCALER_DIV_1024 11
-#define TIMER1_PRESCALER_DIV_2048 12
-#define TIMER1_PRESCALER_DIV_4096 13
-#define TIMER1_PRESCALER_DIV_8192 14
-#define TIMER1_PRESCALER_DIV_16384 15
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 2
-#define TIMER1_PRESCALER_REG_3 4
-#define TIMER1_PRESCALER_REG_4 8
-#define TIMER1_PRESCALER_REG_5 16
-#define TIMER1_PRESCALER_REG_6 32
-#define TIMER1_PRESCALER_REG_7 64
-#define TIMER1_PRESCALER_REG_8 128
-#define TIMER1_PRESCALER_REG_9 256
-#define TIMER1_PRESCALER_REG_10 512
-#define TIMER1_PRESCALER_REG_11 1024
-#define TIMER1_PRESCALER_REG_12 2048
-#define TIMER1_PRESCALER_REG_13 4096
-#define TIMER1_PRESCALER_REG_14 8192
-#define TIMER1_PRESCALER_REG_15 16384
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER1_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW_TOTAL_NUM 2
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0
-
-/* Pwm nums */
-#define PWM_TOTAL_NUM 0
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 0
-
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-
-/* GIMSK */
-#define PCIE0_REG GIMSK
-#define PCIE1_REG GIMSK
-#define INT0_REG GIMSK
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* TCCR0 */
-#define CS00_REG TCCR0
-#define CS01_REG TCCR0
-#define CS02_REG TCCR0
-#define PSR0_REG TCCR0
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define SM0_REG MCUCR
-#define SM1_REG MCUCR
-#define SE_REG MCUCR
-#define PUD_REG MCUCR
-
-/* TCCR1A */
-#define PWM1B_REG TCCR1A
-#define PWM1A_REG TCCR1A
-#define FOC1B_REG TCCR1A
-#define FOC1A_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define CS13_REG TCCR1B
-#define PSR1_REG TCCR1B
-#define CTC1_REG TCCR1B
-
-/* GIFR */
-#define PCIF_REG GIFR
-#define INTF0_REG GIFR
-
-/* TIMSK */
-#define TOIE0_REG TIMSK
-#define TOIE1_REG TIMSK
-#define OCIE1B_REG TIMSK
-#define OCIE1A_REG TIMSK
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACME_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* USICR */
-#define USITC_REG USICR
-#define USICLK_REG USICR
-#define USICS0_REG USICR
-#define USICS1_REG USICR
-#define USIWM0_REG USICR
-#define USIWM1_REG USICR
-#define USIOIE_REG USICR
-#define USISIE_REG USICR
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-
-/* USISR */
-#define USICNT0_REG USISR
-#define USICNT1_REG USISR
-#define USICNT2_REG USISR
-#define USICNT3_REG USISR
-#define USIDC_REG USISR
-#define USIPF_REG USISR
-#define USIOIF_REG USISR
-#define USISIF_REG USISR
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* EEAR */
-#define EEAR0_REG EEAR
-#define EEAR1_REG EEAR
-#define EEAR2_REG EEAR
-#define EEAR3_REG EEAR
-#define EEAR4_REG EEAR
-#define EEAR5_REG EEAR
-#define EEAR6_REG EEAR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* TCNT0 */
-#define TCNT00_REG TCNT0
-#define TCNT01_REG TCNT0
-#define TCNT02_REG TCNT0
-#define TCNT03_REG TCNT0
-#define TCNT04_REG TCNT0
-#define TCNT05_REG TCNT0
-#define TCNT06_REG TCNT0
-#define TCNT07_REG TCNT0
-
-/* TCNT1 */
-#define TCNT1_0_REG TCNT1
-#define TCNT1_1_REG TCNT1
-#define TCNT1_2_REG TCNT1
-#define TCNT1_3_REG TCNT1
-#define TCNT1_4_REG TCNT1
-#define TCNT1_5_REG TCNT1
-#define TCNT1_6_REG TCNT1
-#define TCNT1_7_REG TCNT1
-
-/* TIFR */
-#define TOV0_REG TIFR
-#define TOV1_REG TIFR
-#define OCF1B_REG TIFR
-#define OCF1A_REG TIFR
-
-/* PLLCSR */
-#define PLOCK_REG PLLCSR
-#define PLLE_REG PLLCSR
-#define PCKE_REG PLLCSR
-
-/* ADCSR */
-#define ADPS0_REG ADCSR
-#define ADPS1_REG ADCSR
-#define ADPS2_REG ADCSR
-#define ADIE_REG ADCSR
-#define ADIF_REG ADCSR
-#define ADFR_REG ADCSR
-#define ADSC_REG ADCSR
-#define ADEN_REG ADCSR
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* SP */
-#define SP0_REG SP
-#define SP1_REG SP
-#define SP2_REG SP
-#define SP3_REG SP
-#define SP4_REG SP
-#define SP5_REG SP
-#define SP6_REG SP
-#define SP7_REG SP
-
-/* OCR1B */
-#define OCR1B0_REG OCR1B
-#define OCR1B1_REG OCR1B
-#define OCR1B2_REG OCR1B
-#define OCR1B3_REG OCR1B
-#define OCR1B4_REG OCR1B
-#define OCR1B5_REG OCR1B
-#define OCR1B6_REG OCR1B
-#define OCR1B7_REG OCR1B
-
-/* OCR1C */
-#define OCR1C0_REG OCR1C
-#define OCR1C1_REG OCR1C
-#define OCR1C2_REG OCR1C
-#define OCR1C3_REG OCR1C
-#define OCR1C4_REG OCR1C
-#define OCR1C5_REG OCR1C
-#define OCR1C6_REG OCR1C
-#define OCR1C7_REG OCR1C
-
-/* OCR1A */
-#define OCR1A0_REG OCR1A
-#define OCR1A1_REG OCR1A
-#define OCR1A2_REG OCR1A
-#define OCR1A3_REG OCR1A
-#define OCR1A4_REG OCR1A
-#define OCR1A5_REG OCR1A
-#define OCR1A6_REG OCR1A
-#define OCR1A7_REG OCR1A
-
-/* USIDR */
-#define USIDR0_REG USIDR
-#define USIDR1_REG USIDR
-#define USIDR2_REG USIDR
-#define USIDR3_REG USIDR
-#define USIDR4_REG USIDR
-#define USIDR5_REG USIDR
-#define USIDR6_REG USIDR
-#define USIDR7_REG USIDR
-
-/* pins mapping */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_2 2
-#define TIMER1_PRESCALER_DIV_4 3
-#define TIMER1_PRESCALER_DIV_8 4
-#define TIMER1_PRESCALER_DIV_16 5
-#define TIMER1_PRESCALER_DIV_32 6
-#define TIMER1_PRESCALER_DIV_64 7
-#define TIMER1_PRESCALER_DIV_128 8
-#define TIMER1_PRESCALER_DIV_256 9
-#define TIMER1_PRESCALER_DIV_512 10
-#define TIMER1_PRESCALER_DIV_1024 11
-#define TIMER1_PRESCALER_DIV_2048 12
-#define TIMER1_PRESCALER_DIV_4096 13
-#define TIMER1_PRESCALER_DIV_8192 14
-#define TIMER1_PRESCALER_DIV_16384 15
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 2
-#define TIMER1_PRESCALER_REG_3 4
-#define TIMER1_PRESCALER_REG_4 8
-#define TIMER1_PRESCALER_REG_5 16
-#define TIMER1_PRESCALER_REG_6 32
-#define TIMER1_PRESCALER_REG_7 64
-#define TIMER1_PRESCALER_REG_8 128
-#define TIMER1_PRESCALER_REG_9 256
-#define TIMER1_PRESCALER_REG_10 512
-#define TIMER1_PRESCALER_REG_11 1024
-#define TIMER1_PRESCALER_REG_12 2048
-#define TIMER1_PRESCALER_REG_13 4096
-#define TIMER1_PRESCALER_REG_14 8192
-#define TIMER1_PRESCALER_REG_15 16384
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW_TOTAL_NUM 2
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1_NUM 2
-#define SIG_OUTPUT_COMPARE1A_NUM 3
-#define SIG_OUTPUT_COMPARE1B_NUM 4
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 5
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1_NUM 2
-#define PWM1A_NUM 3
-#define PWM1B_NUM 4
-#define PWM_TOTAL_NUM 5
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE0_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-#define WDP3_REG WDTCR
-#define WDIE_REG WDTCR
-#define WDIF_REG WDTCR
-
-/* GIMSK */
-#define PCIE0_REG GIMSK
-#define PCIE1_REG GIMSK
-#define INT0_REG GIMSK
-#define INT1_REG GIMSK
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define AREFD_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* TCNT0H */
-/* #define TCNT0_0_REG TCNT0H */ /* dup in TCNT0L */
-/* #define TCNT0_1_REG TCNT0H */ /* dup in TCNT0L */
-/* #define TCNT0_2_REG TCNT0H */ /* dup in TCNT0L */
-/* #define TCNT0_3_REG TCNT0H */ /* dup in TCNT0L */
-/* #define TCNT0_4_REG TCNT0H */ /* dup in TCNT0L */
-/* #define TCNT0_5_REG TCNT0H */ /* dup in TCNT0L */
-/* #define TCNT0_6_REG TCNT0H */ /* dup in TCNT0L */
-/* #define TCNT0_7_REG TCNT0H */ /* dup in TCNT0L */
-
-/* TCNT0L */
-/* #define TCNT0_0_REG TCNT0L */ /* dup in TCNT0H */
-/* #define TCNT0_1_REG TCNT0L */ /* dup in TCNT0H */
-/* #define TCNT0_2_REG TCNT0L */ /* dup in TCNT0H */
-/* #define TCNT0_3_REG TCNT0L */ /* dup in TCNT0H */
-/* #define TCNT0_4_REG TCNT0L */ /* dup in TCNT0H */
-/* #define TCNT0_5_REG TCNT0L */ /* dup in TCNT0H */
-/* #define TCNT0_6_REG TCNT0L */ /* dup in TCNT0H */
-/* #define TCNT0_7_REG TCNT0L */ /* dup in TCNT0H */
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* TCCR1D */
-#define WGM10_REG TCCR1D
-#define WGM11_REG TCCR1D
-#define FPF1_REG TCCR1D
-#define FPAC1_REG TCCR1D
-#define FPES1_REG TCCR1D
-#define FPNC1_REG TCCR1D
-#define FPEN1_REG TCCR1D
-#define FPIE1_REG TCCR1D
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define SM0_REG MCUCR
-#define SM1_REG MCUCR
-#define SE_REG MCUCR
-#define PUD_REG MCUCR
-
-/* TCCR1A */
-#define PWM1B_REG TCCR1A
-#define PWM1A_REG TCCR1A
-#define FOC1B_REG TCCR1A
-#define FOC1A_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* TCCR1C */
-#define PWM1D_REG TCCR1C
-#define FOC1D_REG TCCR1C
-#define COM1D0_REG TCCR1C
-#define COM1D1_REG TCCR1C
-#define COM1B0S_REG TCCR1C
-#define COM1B1S_REG TCCR1C
-#define COM1A0S_REG TCCR1C
-#define COM1A1S_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define CS13_REG TCCR1B
-#define DTPS10_REG TCCR1B
-#define DTPS11_REG TCCR1B
-#define PSR1_REG TCCR1B
-
-/* GIFR */
-#define PCIF_REG GIFR
-#define INTF0_REG GIFR
-#define INTF1_REG GIFR
-
-/* TIMSK */
-#define TICIE0_REG TIMSK
-#define TOIE0_REG TIMSK
-#define OCIE0B_REG TIMSK
-#define OCIE0A_REG TIMSK
-#define TOIE1_REG TIMSK
-#define OCIE1B_REG TIMSK
-#define OCIE1A_REG TIMSK
-#define OCIE1D_REG TIMSK
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ACSRB */
-#define ACM0_REG ACSRB
-#define ACM1_REG ACSRB
-#define ACM2_REG ACSRB
-#define HLEV_REG ACSRB
-#define HSEL_REG ACSRB
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define MUX5_REG ADCSRB
-#define REFS2_REG ADCSRB
-#define IPR_REG ADCSRB
-#define GSEL_REG ADCSRB
-#define BIN_REG ADCSRB
-
-/* TC1H */
-#define TC18_REG TC1H
-#define TC19_REG TC1H
-
-/* TCCR1E */
-#define OC1OE0_REG TCCR1E
-#define OC1OE1_REG TCCR1E
-#define OC1OE2_REG TCCR1E
-#define OC1OE3_REG TCCR1E
-#define OC1OE4_REG TCCR1E
-#define OC1OE5_REG TCCR1E
-
-/* OCR0A */
-/* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */
-
-/* OCR0B */
-/* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */
-
-/* USIPP */
-#define USIPOS_REG USIPP
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSI_REG PRR
-#define PRTIM0_REG PRR
-#define PRTIM1_REG PRR
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* USICR */
-#define USITC_REG USICR
-#define USICLK_REG USICR
-#define USICS0_REG USICR
-#define USICS1_REG USICR
-#define USIWM0_REG USICR
-#define USIWM1_REG USICR
-#define USIOIE_REG USICR
-#define USISIE_REG USICR
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define RFLB_REG SPMCSR
-#define CTPB_REG SPMCSR
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* USISR */
-#define USICNT0_REG USISR
-#define USICNT1_REG USISR
-#define USICNT2_REG USISR
-#define USICNT3_REG USISR
-#define USIDC_REG USISR
-#define USIPF_REG USISR
-#define USIOIF_REG USISR
-#define USISIF_REG USISR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* ACSRA */
-#define ACIS0_REG ACSRA
-#define ACIS1_REG ACSRA
-#define ACME_REG ACSRA
-#define ACIE_REG ACSRA
-#define ACI_REG ACSRA
-#define ACO_REG ACSRA
-#define ACBG_REG ACSRA
-#define ACD_REG ACSRA
-
-/* TCNT1 */
-#define TC1H_0_REG TCNT1
-#define TC1H_1_REG TCNT1
-#define TC1H_2_REG TCNT1
-#define TC1H_3_REG TCNT1
-#define TC1H_4_REG TCNT1
-#define TC1H_5_REG TCNT1
-#define TC1H_6_REG TCNT1
-#define TC1H_7_REG TCNT1
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define PSR0_REG TCCR0B
-#define TSM_REG TCCR0B
-
-/* TIFR */
-#define ICF0_REG TIFR
-#define TOV0_REG TIFR
-#define OCF0B_REG TIFR
-#define OCF0A_REG TIFR
-#define TOV1_REG TIFR
-#define OCF1B_REG TIFR
-#define OCF1A_REG TIFR
-#define OCF1D_REG TIFR
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define ACIC0_REG TCCR0A
-#define ICES0_REG TCCR0A
-#define ICNC0_REG TCCR0A
-#define ICEN0_REG TCCR0A
-#define TCW0_REG TCCR0A
-
-/* EEARH */
-#define EEAR8_REG EEARH
-
-/* PLLCSR */
-#define PLOCK_REG PLLCSR
-#define PLLE_REG PLLCSR
-#define PCKE_REG PLLCSR
-#define LSM_REG PLLCSR
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-#define PCINT15_REG PCMSK1
-
-/* DWDR */
-#define DWDR0_REG DWDR
-#define DWDR1_REG DWDR
-#define DWDR2_REG DWDR
-#define DWDR3_REG DWDR
-#define DWDR4_REG DWDR
-#define DWDR5_REG DWDR
-#define DWDR6_REG DWDR
-#define DWDR7_REG DWDR
-
-/* OCR1D */
-#define OCR1D0_REG OCR1D
-#define OCR1D1_REG OCR1D
-#define OCR1D2_REG OCR1D
-#define OCR1D3_REG OCR1D
-#define OCR1D4_REG OCR1D
-#define OCR1D5_REG OCR1D
-#define OCR1D6_REG OCR1D
-/* #define OCR1C7_REG OCR1D */ /* dup in OCR1C */
-
-/* OCR1B */
-#define OCR1B0_REG OCR1B
-#define OCR1B1_REG OCR1B
-#define OCR1B2_REG OCR1B
-#define OCR1B3_REG OCR1B
-#define OCR1B4_REG OCR1B
-#define OCR1B5_REG OCR1B
-#define OCR1B6_REG OCR1B
-#define OCR1B7_REG OCR1B
-
-/* OCR1C */
-#define OCR1C0_REG OCR1C
-#define OCR1C1_REG OCR1C
-#define OCR1C2_REG OCR1C
-#define OCR1C3_REG OCR1C
-#define OCR1C4_REG OCR1C
-#define OCR1C5_REG OCR1C
-#define OCR1C6_REG OCR1C
-/* #define OCR1C7_REG OCR1C */ /* dup in OCR1D */
-
-/* OCR1A */
-#define OCR1A0_REG OCR1A
-#define OCR1A1_REG OCR1A
-#define OCR1A2_REG OCR1A
-#define OCR1A3_REG OCR1A
-#define OCR1A4_REG OCR1A
-#define OCR1A5_REG OCR1A
-#define OCR1A6_REG OCR1A
-#define OCR1A7_REG OCR1A
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* USIBR */
-#define USIBR0_REG USIBR
-#define USIBR1_REG USIBR
-#define USIBR2_REG USIBR
-#define USIBR3_REG USIBR
-#define USIBR4_REG USIBR
-#define USIBR5_REG USIBR
-#define USIBR6_REG USIBR
-#define USIBR7_REG USIBR
-
-/* DT1 */
-#define DT1L0_REG DT1
-#define DT1L1_REG DT1
-#define DT1L2_REG DT1
-#define DT1L3_REG DT1
-#define DT1H0_REG DT1
-#define DT1H1_REG DT1
-#define DT1H2_REG DT1
-#define DT1H3_REG DT1
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* USIDR */
-#define USIDR0_REG USIDR
-#define USIDR1_REG USIDR
-#define USIDR2_REG USIDR
-#define USIDR3_REG USIDR
-#define USIDR4_REG USIDR
-#define USIDR5_REG USIDR
-#define USIDR6_REG USIDR
-#define USIDR7_REG USIDR
-
-/* DIDR1 */
-#define ADC7D_REG DIDR1
-#define ADC8D_REG DIDR1
-#define ADC9D_REG DIDR1
-#define ADC10D_REG DIDR1
-
-/* pins mapping */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_-3 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 -3
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW_TOTAL_NUM 1
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0
-
-/* Pwm nums */
-#define PWM_TOTAL_NUM 0
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 0
-
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACD_REG ACSR
-
-/* PACR */
-#define DDA0_REG PACR
-#define DDA1_REG PACR
-#define PA2HC_REG PACR
-#define DDA3_REG PACR
-
-/* MODCR */
-#define MCONF0_REG MODCR
-#define MCONF1_REG MODCR
-#define MCONF2_REG MODCR
-#define ONTIM0_REG MODCR
-#define ONTIM1_REG MODCR
-#define ONTIM2_REG MODCR
-#define OTIM3_REG MODCR
-#define ONTIM4_REG MODCR
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA3_REG PINA
-
-/* TCCR0 */
-#define CS00_REG TCCR0
-#define CS01_REG TCCR0
-#define CS02_REG TCCR0
-#define OOM00_REG TCCR0
-#define OOM01_REG TCCR0
-#define FOV0_REG TCCR0
-
-/* MCUCS */
-#define PORF_REG MCUCS
-#define EXTRF_REG MCUCS
-#define WDRF_REG MCUCS
-#define SM_REG MCUCS
-#define SE_REG MCUCS
-#define PLUPB_REG MCUCS
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-
-/* TCNT0 */
-#define TCNT00_REG TCNT0
-#define TCNT01_REG TCNT0
-#define TCNT02_REG TCNT0
-#define TCNT03_REG TCNT0
-#define TCNT04_REG TCNT0
-#define TCNT05_REG TCNT0
-#define TCNT06_REG TCNT0
-#define TCNT07_REG TCNT0
-
-/* IFR */
-#define TOV0_REG IFR
-#define INTF0_REG IFR
-#define INTF1_REG IFR
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* ICR */
-#define ISC00_REG ICR
-#define ISC01_REG ICR
-#define ICS10_REG ICR
-#define ICS11_REG ICR
-#define TOIE0_REG ICR
-#define LLIE_REG ICR
-#define INT0_REG ICR
-#define INT1_REG ICR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDTOE_REG WDTCR
-
-/* pins mapping */
-
-
-#define IR_PORT PORTA
-#define IR_BIT 2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-
-/* available timers */
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW_TOTAL_NUM 0
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0
-
-/* Pwm nums */
-#define PWM_TOTAL_NUM 0
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 0
-
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* GIMSK */
-#define PCIE0_REG GIMSK
-#define PCIE1_REG GIMSK
-#define INT0_REG GIMSK
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define AIN0D_REG DIDR0
-#define AIN1D_REG DIDR0
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define REFS_REG ADMUX
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* OCR1A */
-/* #define OCR1_0_REG OCR1A */ /* dup in OCR1B */
-/* #define OCR1_1_REG OCR1A */ /* dup in OCR1B */
-/* #define OCR1_2_REG OCR1A */ /* dup in OCR1B */
-/* #define OCR1_3_REG OCR1A */ /* dup in OCR1B */
-/* #define OCR1_4_REG OCR1A */ /* dup in OCR1B */
-/* #define OCR1_5_REG OCR1A */ /* dup in OCR1B */
-/* #define OCR1_6_REG OCR1A */ /* dup in OCR1B */
-/* #define OCR1_7_REG OCR1A */ /* dup in OCR1B */
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* GTCCR */
-#define PSR10_REG GTCCR
-#define TSM_REG GTCCR
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define FOC1B_REG TCCR1B
-#define FOC1A_REG TCCR1B
-
-/* GIFR */
-#define PCIF0_REG GIFR
-#define PCIF1_REG GIFR
-#define INTF0_REG GIFR
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ACME_REG ADCSRB
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ADLAR_REG ADCSRB
-#define BVRON_REG ADCSRB
-
-/* OCR0A */
-/* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */
-
-/* OCR0B */
-/* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */
-
-/* SPH */
-#define SP8_REG SPH
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSI_REG PRR
-#define PRTIM0_REG PRR
-#define PRTIM1_REG PRR
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* USISR */
-#define USICNT0_REG USISR
-#define USICNT1_REG USISR
-#define USICNT2_REG USISR
-#define USICNT3_REG USISR
-#define USIDC_REG USISR
-#define USIPF_REG USISR
-#define USIOIF_REG USISR
-#define USISIF_REG USISR
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define RFLB_REG SPMCSR
-#define CTPB_REG SPMCSR
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* EEAR */
-#define EEAR0_REG EEAR
-#define EEAR1_REG EEAR
-#define EEAR2_REG EEAR
-#define EEAR3_REG EEAR
-#define EEAR4_REG EEAR
-#define EEAR5_REG EEAR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TCNT1 */
-#define TCNT1_0_REG TCNT1
-#define TCNT1_1_REG TCNT1
-#define TCNT1_2_REG TCNT1
-#define TCNT1_3_REG TCNT1
-#define TCNT1_4_REG TCNT1
-#define TCNT1_5_REG TCNT1
-#define TCNT1_6_REG TCNT1
-#define TCNT1_7_REG TCNT1
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* USICR */
-#define USITC_REG USICR
-#define USICLK_REG USICR
-#define USICS0_REG USICR
-#define USICS1_REG USICR
-#define USIWM0_REG USICR
-#define USIWM1_REG USICR
-#define USIOIE_REG USICR
-#define USISIE_REG USICR
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-#define PCINT15_REG PCMSK1
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* OCR1B */
-/* #define OCR1_0_REG OCR1B */ /* dup in OCR1A */
-/* #define OCR1_1_REG OCR1B */ /* dup in OCR1A */
-/* #define OCR1_2_REG OCR1B */ /* dup in OCR1A */
-/* #define OCR1_3_REG OCR1B */ /* dup in OCR1A */
-/* #define OCR1_4_REG OCR1B */ /* dup in OCR1A */
-/* #define OCR1_5_REG OCR1B */ /* dup in OCR1A */
-/* #define OCR1_6_REG OCR1B */ /* dup in OCR1A */
-/* #define OCR1_7_REG OCR1B */ /* dup in OCR1A */
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define BODSE_REG MCUCR
-#define SM0_REG MCUCR
-#define SM1_REG MCUCR
-#define SE_REG MCUCR
-#define PUD_REG MCUCR
-#define BODS_REG MCUCR
-
-/* USIDR */
-#define USIDR0_REG USIDR
-#define USIDR1_REG USIDR
-#define USIDR2_REG USIDR
-#define USIDR3_REG USIDR
-#define USIDR4_REG USIDR
-#define USIDR5_REG USIDR
-#define USIDR6_REG USIDR
-#define USIDR7_REG USIDR
-
-/* USIBR */
-#define USIBR0_REG USIBR
-#define USIBR1_REG USIBR
-#define USIBR2_REG USIBR
-#define USIBR3_REG USIBR
-#define USIBR4_REG USIBR
-#define USIBR5_REG USIBR
-#define USIBR6_REG USIBR
-#define USIBR7_REG USIBR
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-
-/* pins mapping */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-
-/* available timers */
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW_TOTAL_NUM 0
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0
-
-/* Pwm nums */
-#define PWM_TOTAL_NUM 0
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 0
-
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* GIMSK */
-#define PCIE0_REG GIMSK
-#define PCIE1_REG GIMSK
-#define INT0_REG GIMSK
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define MUX5_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* GTCCR */
-#define PSR10_REG GTCCR
-#define TSM_REG GTCCR
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* GIFR */
-#define PCIF0_REG GIFR
-#define PCIF1_REG GIFR
-#define INTF0_REG GIFR
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ACME_REG ADCSRB
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ADLAR_REG ADCSRB
-#define BIN_REG ADCSRB
-
-/* OCR0A */
-/* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */
-
-/* OCR0B */
-/* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */
-
-/* SPH */
-#define SP8_REG SPH
-
-/* OCR1BL */
-/* #define OCR1AL0_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL1_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL2_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL3_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL4_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL5_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL6_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL7_REG OCR1BL */ /* dup in OCR1AL */
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* OCR1BH */
-/* #define OCR1AH0_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH1_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH2_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH3_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH4_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH5_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH6_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH7_REG OCR1BH */ /* dup in OCR1AH */
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSI_REG PRR
-#define PRTIM0_REG PRR
-#define PRTIM1_REG PRR
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define RFLB_REG SPMCSR
-#define CTPB_REG SPMCSR
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* USISR */
-#define USICNT0_REG USISR
-#define USICNT1_REG USISR
-#define USICNT2_REG USISR
-#define USICNT3_REG USISR
-#define USIDC_REG USISR
-#define USIPF_REG USISR
-#define USIOIF_REG USISR
-#define USISIF_REG USISR
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* EEARH */
-#define EEAR8_REG EEARH
-
-/* USICR */
-#define USITC_REG USICR
-#define USICLK_REG USICR
-#define USICS0_REG USICR
-#define USICS1_REG USICR
-#define USIWM0_REG USICR
-#define USIWM1_REG USICR
-#define USIOIE_REG USICR
-#define USISIE_REG USICR
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define SM0_REG MCUCR
-#define SM1_REG MCUCR
-#define SE_REG MCUCR
-#define PUD_REG MCUCR
-
-/* OCR1AH */
-/* #define OCR1AH0_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH1_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH2_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH3_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH4_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH5_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH6_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH7_REG OCR1AH */ /* dup in OCR1BH */
-
-/* OCR1AL */
-/* #define OCR1AL0_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL1_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL2_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL3_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL4_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL5_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL6_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL7_REG OCR1AL */ /* dup in OCR1BL */
-
-/* USIDR */
-#define USIDR0_REG USIDR
-#define USIDR1_REG USIDR
-#define USIDR2_REG USIDR
-#define USIDR3_REG USIDR
-#define USIDR4_REG USIDR
-#define USIDR5_REG USIDR
-#define USIDR6_REG USIDR
-#define USIDR7_REG USIDR
-
-/* USIBR */
-#define USIBR0_REG USIBR
-#define USIBR1_REG USIBR
-#define USIBR2_REG USIBR
-#define USIBR3_REG USIBR
-#define USIBR4_REG USIBR
-#define USIBR5_REG USIBR
-#define USIBR6_REG USIBR
-#define USIBR7_REG USIBR
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* pins mapping */
-#define ADC0_PORT PORTA
-#define ADC0_BIT 0
-#define AREF_PORT PORTA
-#define AREF_BIT 0
-#define PCINT0_PORT PORTA
-#define PCINT0_BIT 0
-
-#define ADC1_PORT PORTA
-#define ADC1_BIT 1
-#define AIN0_PORT PORTA
-#define AIN0_BIT 1
-#define PCINT1_PORT PORTA
-#define PCINT1_BIT 1
-
-#define ADC2_PORT PORTA
-#define ADC2_BIT 2
-#define AIN1_PORT PORTA
-#define AIN1_BIT 2
-#define PCINT2_PORT PORTA
-#define PCINT2_BIT 2
-
-#define ADC3_PORT PORTA
-#define ADC3_BIT 3
-#define T0_PORT PORTA
-#define T0_BIT 3
-#define PCINT3_PORT PORTA
-#define PCINT3_BIT 3
-
-#define ADC4_PORT PORTA
-#define ADC4_BIT 4
-#define USCK_PORT PORTA
-#define USCK_BIT 4
-#define SCL_PORT PORTA
-#define SCL_BIT 4
-#define T1_PORT PORTA
-#define T1_BIT 4
-#define PCINT4_PORT PORTA
-#define PCINT4_BIT 4
-
-#define ADC5_PORT PORTA
-#define ADC5_BIT 5
-#define DO_PORT PORTA
-#define DO_BIT 5
-#define MISO_PORT PORTA
-#define MISO_BIT 5
-#define OC1B_PORT PORTA
-#define OC1B_BIT 5
-#define PCINT5_PORT PORTA
-#define PCINT5_BIT 5
-
-#define PCINT6_PORT PORTA
-#define PCINT6_BIT 6
-#define OC1A_PORT PORTA
-#define OC1A_BIT 6
-#define DI_PORT PORTA
-#define DI_BIT 6
-#define SDA_PORT PORTA
-#define SDA_BIT 6
-#define MOSI_PORT PORTA
-#define MOSI_BIT 6
-#define ADC6_PORT PORTA
-#define ADC6_BIT 6
-
-#define PCINT7_PORT PORTA
-#define PCINT7_BIT 7
-#define ICP1_PORT PORTA
-#define ICP1_BIT 7
-#define OC0B_PORT PORTA
-#define OC0B_BIT 7
-#define ADC7_PORT PORTA
-#define ADC7_BIT 7
-
-#define PCINT8_PORT PORTB
-#define PCINT8_BIT 0
-#define XTAL1_PORT PORTB
-#define XTAL1_BIT 0
-
-#define PCINT9_PORT PORTB
-#define PCINT9_BIT 1
-#define XTAL2_PORT PORTB
-#define XTAL2_BIT 1
-
-#define PCINT10_PORT PORTB
-#define PCINT10_BIT 2
-#define INT0_PORT PORTB
-#define INT0_BIT 2
-#define OC0A_PORT PORTB
-#define OC0A_BIT 2
-#define CKOUT_PORT PORTB
-#define CKOUT_BIT 2
-
-#define PCINT11_PORT PORTB
-#define PCINT11_BIT 3
-#define RESET_PORT PORTB
-#define RESET_BIT 3
-#define dW_PORT PORTB
-#define dW_BIT 3
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_2 2
-#define TIMER1_PRESCALER_DIV_4 3
-#define TIMER1_PRESCALER_DIV_8 4
-#define TIMER1_PRESCALER_DIV_16 5
-#define TIMER1_PRESCALER_DIV_32 6
-#define TIMER1_PRESCALER_DIV_64 7
-#define TIMER1_PRESCALER_DIV_128 8
-#define TIMER1_PRESCALER_DIV_256 9
-#define TIMER1_PRESCALER_DIV_512 10
-#define TIMER1_PRESCALER_DIV_1024 11
-#define TIMER1_PRESCALER_DIV_2048 12
-#define TIMER1_PRESCALER_DIV_4096 13
-#define TIMER1_PRESCALER_DIV_8192 14
-#define TIMER1_PRESCALER_DIV_16384 15
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 2
-#define TIMER1_PRESCALER_REG_3 4
-#define TIMER1_PRESCALER_REG_4 8
-#define TIMER1_PRESCALER_REG_5 16
-#define TIMER1_PRESCALER_REG_6 32
-#define TIMER1_PRESCALER_REG_7 64
-#define TIMER1_PRESCALER_REG_8 128
-#define TIMER1_PRESCALER_REG_9 256
-#define TIMER1_PRESCALER_REG_10 512
-#define TIMER1_PRESCALER_REG_11 1024
-#define TIMER1_PRESCALER_REG_12 2048
-#define TIMER1_PRESCALER_REG_13 4096
-#define TIMER1_PRESCALER_REG_14 8192
-#define TIMER1_PRESCALER_REG_15 16384
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW_TOTAL_NUM 2
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 0
-
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-#define WDP3_REG WDTCR
-#define WDIE_REG WDTCR
-#define WDIF_REG WDTCR
-
-/* GIMSK */
-#define PCIE_REG GIMSK
-#define INT0_REG GIMSK
-
-/* DIDR0 */
-#define AIN0D_REG DIDR0
-#define AIN1D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC0D_REG DIDR0
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define REFS2_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* TCCR1 */
-#define CS10_REG TCCR1
-#define CS11_REG TCCR1
-#define CS12_REG TCCR1
-#define CS13_REG TCCR1
-#define COM1A0_REG TCCR1
-#define COM1A1_REG TCCR1
-#define PWM1A_REG TCCR1
-#define CTC1_REG TCCR1
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define BODSE_REG MCUCR
-#define SM0_REG MCUCR
-#define SM1_REG MCUCR
-#define SE_REG MCUCR
-#define PUD_REG MCUCR
-#define BODS_REG MCUCR
-
-/* GTCCR */
-#define PSR0_REG GTCCR
-#define TSM_REG GTCCR
-#define PSR1_REG GTCCR
-#define FOC1A_REG GTCCR
-#define FOC1B_REG GTCCR
-#define COM1B0_REG GTCCR
-#define COM1B1_REG GTCCR
-#define PWM1B_REG GTCCR
-
-/* DTPS */
-#define DTPS0_REG DTPS
-#define DTPS1_REG DTPS
-
-/* GIFR */
-#define PCIF_REG GIFR
-#define INTF0_REG GIFR
-
-/* TIMSK */
-#define TOIE0_REG TIMSK
-#define OCIE0B_REG TIMSK
-#define OCIE0A_REG TIMSK
-#define TOIE1_REG TIMSK
-#define OCIE1B_REG TIMSK
-#define OCIE1A_REG TIMSK
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* DT1B */
-/* #define DTVL0_REG DT1B */ /* dup in DT1A */
-/* #define DTVL1_REG DT1B */ /* dup in DT1A */
-/* #define DTVL2_REG DT1B */ /* dup in DT1A */
-/* #define DTVL3_REG DT1B */ /* dup in DT1A */
-/* #define DTVH0_REG DT1B */ /* dup in DT1A */
-/* #define DTVH1_REG DT1B */ /* dup in DT1A */
-/* #define DTVH2_REG DT1B */ /* dup in DT1A */
-/* #define DTVH3_REG DT1B */ /* dup in DT1A */
-
-/* OCR0A */
-/* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */
-
-/* OCR0B */
-/* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSI_REG PRR
-#define PRTIM0_REG PRR
-#define PRTIM1_REG PRR
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* PCMSK */
-#define PCINT0_REG PCMSK
-#define PCINT1_REG PCMSK
-#define PCINT2_REG PCMSK
-#define PCINT3_REG PCMSK
-#define PCINT4_REG PCMSK
-#define PCINT5_REG PCMSK
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define RFLB_REG SPMCSR
-#define CTPB_REG SPMCSR
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* USISR */
-#define USICNT0_REG USISR
-#define USICNT1_REG USISR
-#define USICNT2_REG USISR
-#define USICNT3_REG USISR
-#define USIDC_REG USISR
-#define USIPF_REG USISR
-#define USIOIF_REG USISR
-#define USISIF_REG USISR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TCNT1 */
-#define TCNT1_0_REG TCNT1
-#define TCNT1_1_REG TCNT1
-#define TCNT1_2_REG TCNT1
-#define TCNT1_3_REG TCNT1
-#define TCNT1_4_REG TCNT1
-#define TCNT1_5_REG TCNT1
-#define TCNT1_6_REG TCNT1
-#define TCNT1_7_REG TCNT1
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* TIFR */
-#define TOV0_REG TIFR
-#define OCF0B_REG TIFR
-#define OCF0A_REG TIFR
-#define TOV1_REG TIFR
-#define OCF1B_REG TIFR
-#define OCF1A_REG TIFR
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* EEARH */
-#define EEAR8_REG EEARH
-
-/* PLLCSR */
-#define PLOCK_REG PLLCSR
-#define PLLE_REG PLLCSR
-#define PCKE_REG PLLCSR
-#define LSM_REG PLLCSR
-
-/* USICR */
-#define USITC_REG USICR
-#define USICLK_REG USICR
-#define USICS0_REG USICR
-#define USICS1_REG USICR
-#define USIWM0_REG USICR
-#define USIWM1_REG USICR
-#define USIOIE_REG USICR
-#define USISIE_REG USICR
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* DWDR */
-#define DWDR0_REG DWDR
-#define DWDR1_REG DWDR
-#define DWDR2_REG DWDR
-#define DWDR3_REG DWDR
-#define DWDR4_REG DWDR
-#define DWDR5_REG DWDR
-#define DWDR6_REG DWDR
-#define DWDR7_REG DWDR
-
-/* ADCSRB */
-#define ACME_REG ADCSRB
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define IPR_REG ADCSRB
-#define BIN_REG ADCSRB
-
-/* OCR1B */
-#define OCR1B0_REG OCR1B
-#define OCR1B1_REG OCR1B
-#define OCR1B2_REG OCR1B
-#define OCR1B3_REG OCR1B
-#define OCR1B4_REG OCR1B
-#define OCR1B5_REG OCR1B
-#define OCR1B6_REG OCR1B
-#define OCR1B7_REG OCR1B
-
-/* OCR1C */
-#define OCR1C0_REG OCR1C
-#define OCR1C1_REG OCR1C
-#define OCR1C2_REG OCR1C
-#define OCR1C3_REG OCR1C
-#define OCR1C4_REG OCR1C
-#define OCR1C5_REG OCR1C
-#define OCR1C6_REG OCR1C
-#define OCR1C7_REG OCR1C
-
-/* DT1A */
-/* #define DTVL0_REG DT1A */ /* dup in DT1B */
-/* #define DTVL1_REG DT1A */ /* dup in DT1B */
-/* #define DTVL2_REG DT1A */ /* dup in DT1B */
-/* #define DTVL3_REG DT1A */ /* dup in DT1B */
-/* #define DTVH0_REG DT1A */ /* dup in DT1B */
-/* #define DTVH1_REG DT1A */ /* dup in DT1B */
-/* #define DTVH2_REG DT1A */ /* dup in DT1B */
-/* #define DTVH3_REG DT1A */ /* dup in DT1B */
-
-/* OCR1A */
-#define OCR1A0_REG OCR1A
-#define OCR1A1_REG OCR1A
-#define OCR1A2_REG OCR1A
-#define OCR1A3_REG OCR1A
-#define OCR1A4_REG OCR1A
-#define OCR1A5_REG OCR1A
-#define OCR1A6_REG OCR1A
-#define OCR1A7_REG OCR1A
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-
-/* USIBR */
-#define USIBR0_REG USIBR
-#define USIBR1_REG USIBR
-#define USIBR2_REG USIBR
-#define USIBR3_REG USIBR
-#define USIBR4_REG USIBR
-#define USIBR5_REG USIBR
-#define USIBR6_REG USIBR
-#define USIBR7_REG USIBR
-
-/* USIDR */
-#define USIDR0_REG USIDR
-#define USIDR1_REG USIDR
-#define USIDR2_REG USIDR
-#define USIDR3_REG USIDR
-#define USIDR4_REG USIDR
-#define USIDR5_REG USIDR
-#define USIDR6_REG USIDR
-#define USIDR7_REG USIDR
-
-/* pins mapping */
-#define MOSI_PORT PORTB
-#define MOSI_BIT 0
-#define DI_PORT PORTB
-#define DI_BIT 0
-#define SDA_PORT PORTB
-#define SDA_BIT 0
-#define AIN0_PORT PORTB
-#define AIN0_BIT 0
-#define OC0A_PORT PORTB
-#define OC0A_BIT 0
-#define OC1A_PORT PORTB
-#define OC1A_BIT 0
-#define AREF_PORT PORTB
-#define AREF_BIT 0
-#define PCINT0_PORT PORTB
-#define PCINT0_BIT 0
-
-#define MISO_PORT PORTB
-#define MISO_BIT 1
-#define DO_PORT PORTB
-#define DO_BIT 1
-#define AIN1_PORT PORTB
-#define AIN1_BIT 1
-#define OC0B_PORT PORTB
-#define OC0B_BIT 1
-#define OC1A_PORT PORTB
-#define OC1A_BIT 1
-#define PCINT1_PORT PORTB
-#define PCINT1_BIT 1
-
-#define SCK_PORT PORTB
-#define SCK_BIT 2
-#define USCK_PORT PORTB
-#define USCK_BIT 2
-#define SCL_PORT PORTB
-#define SCL_BIT 2
-#define ADC1_PORT PORTB
-#define ADC1_BIT 2
-#define T0_PORT PORTB
-#define T0_BIT 2
-#define INT0_PORT PORTB
-#define INT0_BIT 2
-#define PCINT2_PORT PORTB
-#define PCINT2_BIT 2
-
-#define ADC3_PORT PORTB
-#define ADC3_BIT 3
-#define OC1B_PORT PORTB
-#define OC1B_BIT 3
-#define XTAL1_PORT PORTB
-#define XTAL1_BIT 3
-#define PCINT4_PORT PORTB
-#define PCINT4_BIT 3
-
-#define ADC2_PORT PORTB
-#define ADC2_BIT 4
-#define OC1B_PORT PORTB
-#define OC1B_BIT 4
-#define XTAL2_PORT PORTB
-#define XTAL2_BIT 4
-#define PCINT3_PORT PORTB
-#define PCINT3_BIT 4
-
-#define RESET_PORT PORTB
-#define RESET_BIT 5
-#define ADC0_PORT PORTB
-#define ADC0_BIT 5
-#define PCINT5_PORT PORTB
-#define PCINT5_BIT 5
-#define dW_PORT PORTB
-#define dW_BIT 5
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_2 2
-#define TIMER1_PRESCALER_DIV_4 3
-#define TIMER1_PRESCALER_DIV_8 4
-#define TIMER1_PRESCALER_DIV_16 5
-#define TIMER1_PRESCALER_DIV_32 6
-#define TIMER1_PRESCALER_DIV_64 7
-#define TIMER1_PRESCALER_DIV_128 8
-#define TIMER1_PRESCALER_DIV_256 9
-#define TIMER1_PRESCALER_DIV_512 10
-#define TIMER1_PRESCALER_DIV_1024 11
-#define TIMER1_PRESCALER_DIV_2048 12
-#define TIMER1_PRESCALER_DIV_4096 13
-#define TIMER1_PRESCALER_DIV_8192 14
-#define TIMER1_PRESCALER_DIV_16384 15
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 2
-#define TIMER1_PRESCALER_REG_3 4
-#define TIMER1_PRESCALER_REG_4 8
-#define TIMER1_PRESCALER_REG_5 16
-#define TIMER1_PRESCALER_REG_6 32
-#define TIMER1_PRESCALER_REG_7 64
-#define TIMER1_PRESCALER_REG_8 128
-#define TIMER1_PRESCALER_REG_9 256
-#define TIMER1_PRESCALER_REG_10 512
-#define TIMER1_PRESCALER_REG_11 1024
-#define TIMER1_PRESCALER_REG_12 2048
-#define TIMER1_PRESCALER_REG_13 4096
-#define TIMER1_PRESCALER_REG_14 8192
-#define TIMER1_PRESCALER_REG_15 16384
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW_TOTAL_NUM 2
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1_NUM 2
-#define SIG_OUTPUT_COMPARE1A_NUM 3
-#define SIG_OUTPUT_COMPARE1B_NUM 4
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 5
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1_NUM 2
-#define PWM1A_NUM 3
-#define PWM1B_NUM 4
-#define PWM_TOTAL_NUM 5
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE0_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-#define WDP3_REG WDTCR
-#define WDIE_REG WDTCR
-#define WDIF_REG WDTCR
-
-/* GIMSK */
-#define PCIE0_REG GIMSK
-#define PCIE1_REG GIMSK
-#define INT0_REG GIMSK
-#define INT1_REG GIMSK
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define AREFD_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* TCNT0H */
-/* #define TCNT0_0_REG TCNT0H */ /* dup in TCNT0L */
-/* #define TCNT0_1_REG TCNT0H */ /* dup in TCNT0L */
-/* #define TCNT0_2_REG TCNT0H */ /* dup in TCNT0L */
-/* #define TCNT0_3_REG TCNT0H */ /* dup in TCNT0L */
-/* #define TCNT0_4_REG TCNT0H */ /* dup in TCNT0L */
-/* #define TCNT0_5_REG TCNT0H */ /* dup in TCNT0L */
-/* #define TCNT0_6_REG TCNT0H */ /* dup in TCNT0L */
-/* #define TCNT0_7_REG TCNT0H */ /* dup in TCNT0L */
-
-/* TCNT0L */
-/* #define TCNT0_0_REG TCNT0L */ /* dup in TCNT0H */
-/* #define TCNT0_1_REG TCNT0L */ /* dup in TCNT0H */
-/* #define TCNT0_2_REG TCNT0L */ /* dup in TCNT0H */
-/* #define TCNT0_3_REG TCNT0L */ /* dup in TCNT0H */
-/* #define TCNT0_4_REG TCNT0L */ /* dup in TCNT0H */
-/* #define TCNT0_5_REG TCNT0L */ /* dup in TCNT0H */
-/* #define TCNT0_6_REG TCNT0L */ /* dup in TCNT0H */
-/* #define TCNT0_7_REG TCNT0L */ /* dup in TCNT0H */
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* TCCR1D */
-#define WGM10_REG TCCR1D
-#define WGM11_REG TCCR1D
-#define FPF1_REG TCCR1D
-#define FPAC1_REG TCCR1D
-#define FPES1_REG TCCR1D
-#define FPNC1_REG TCCR1D
-#define FPEN1_REG TCCR1D
-#define FPIE1_REG TCCR1D
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define SM0_REG MCUCR
-#define SM1_REG MCUCR
-#define SE_REG MCUCR
-#define PUD_REG MCUCR
-
-/* TCCR1A */
-#define PWM1B_REG TCCR1A
-#define PWM1A_REG TCCR1A
-#define FOC1B_REG TCCR1A
-#define FOC1A_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* TCCR1C */
-#define PWM1D_REG TCCR1C
-#define FOC1D_REG TCCR1C
-#define COM1D0_REG TCCR1C
-#define COM1D1_REG TCCR1C
-#define COM1B0S_REG TCCR1C
-#define COM1B1S_REG TCCR1C
-#define COM1A0S_REG TCCR1C
-#define COM1A1S_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define CS13_REG TCCR1B
-#define DTPS10_REG TCCR1B
-#define DTPS11_REG TCCR1B
-#define PSR1_REG TCCR1B
-
-/* GIFR */
-#define PCIF_REG GIFR
-#define INTF0_REG GIFR
-#define INTF1_REG GIFR
-
-/* TIMSK */
-#define TICIE0_REG TIMSK
-#define TOIE0_REG TIMSK
-#define OCIE0B_REG TIMSK
-#define OCIE0A_REG TIMSK
-#define TOIE1_REG TIMSK
-#define OCIE1B_REG TIMSK
-#define OCIE1A_REG TIMSK
-#define OCIE1D_REG TIMSK
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ACSRB */
-#define ACM0_REG ACSRB
-#define ACM1_REG ACSRB
-#define ACM2_REG ACSRB
-#define HLEV_REG ACSRB
-#define HSEL_REG ACSRB
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define MUX5_REG ADCSRB
-#define REFS2_REG ADCSRB
-#define IPR_REG ADCSRB
-#define GSEL_REG ADCSRB
-#define BIN_REG ADCSRB
-
-/* TC1H */
-#define TC18_REG TC1H
-#define TC19_REG TC1H
-
-/* TCCR1E */
-#define OC1OE0_REG TCCR1E
-#define OC1OE1_REG TCCR1E
-#define OC1OE2_REG TCCR1E
-#define OC1OE3_REG TCCR1E
-#define OC1OE4_REG TCCR1E
-#define OC1OE5_REG TCCR1E
-
-/* OCR0A */
-/* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */
-
-/* OCR0B */
-/* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */
-
-/* SPH */
-#define SP8_REG SPH
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSI_REG PRR
-#define PRTIM0_REG PRR
-#define PRTIM1_REG PRR
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* USICR */
-#define USITC_REG USICR
-#define USICLK_REG USICR
-#define USICS0_REG USICR
-#define USICS1_REG USICR
-#define USIWM0_REG USICR
-#define USIWM1_REG USICR
-#define USIOIE_REG USICR
-#define USISIE_REG USICR
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define RFLB_REG SPMCSR
-#define CTPB_REG SPMCSR
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* USISR */
-#define USICNT0_REG USISR
-#define USICNT1_REG USISR
-#define USICNT2_REG USISR
-#define USICNT3_REG USISR
-#define USIDC_REG USISR
-#define USIPF_REG USISR
-#define USIOIF_REG USISR
-#define USISIF_REG USISR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* ACSRA */
-#define ACIS0_REG ACSRA
-#define ACIS1_REG ACSRA
-#define ACME_REG ACSRA
-#define ACIE_REG ACSRA
-#define ACI_REG ACSRA
-#define ACO_REG ACSRA
-#define ACBG_REG ACSRA
-#define ACD_REG ACSRA
-
-/* TCNT1 */
-#define TC1H_0_REG TCNT1
-#define TC1H_1_REG TCNT1
-#define TC1H_2_REG TCNT1
-#define TC1H_3_REG TCNT1
-#define TC1H_4_REG TCNT1
-#define TC1H_5_REG TCNT1
-#define TC1H_6_REG TCNT1
-#define TC1H_7_REG TCNT1
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define PSR0_REG TCCR0B
-#define TSM_REG TCCR0B
-
-/* TIFR */
-#define ICF0_REG TIFR
-#define TOV0_REG TIFR
-#define OCF0B_REG TIFR
-#define OCF0A_REG TIFR
-#define TOV1_REG TIFR
-#define OCF1B_REG TIFR
-#define OCF1A_REG TIFR
-#define OCF1D_REG TIFR
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define ACIC0_REG TCCR0A
-#define ICES0_REG TCCR0A
-#define ICNC0_REG TCCR0A
-#define ICEN0_REG TCCR0A
-#define TCW0_REG TCCR0A
-
-/* EEARH */
-#define EEAR8_REG EEARH
-
-/* PLLCSR */
-#define PLOCK_REG PLLCSR
-#define PLLE_REG PLLCSR
-#define PCKE_REG PLLCSR
-#define LSM_REG PLLCSR
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-#define PCINT15_REG PCMSK1
-
-/* DWDR */
-#define DWDR0_REG DWDR
-#define DWDR1_REG DWDR
-#define DWDR2_REG DWDR
-#define DWDR3_REG DWDR
-#define DWDR4_REG DWDR
-#define DWDR5_REG DWDR
-#define DWDR6_REG DWDR
-#define DWDR7_REG DWDR
-
-/* OCR1D */
-#define OCR1D0_REG OCR1D
-#define OCR1D1_REG OCR1D
-#define OCR1D2_REG OCR1D
-#define OCR1D3_REG OCR1D
-#define OCR1D4_REG OCR1D
-#define OCR1D5_REG OCR1D
-#define OCR1D6_REG OCR1D
-/* #define OCR1C7_REG OCR1D */ /* dup in OCR1C */
-
-/* OCR1B */
-#define OCR1B0_REG OCR1B
-#define OCR1B1_REG OCR1B
-#define OCR1B2_REG OCR1B
-#define OCR1B3_REG OCR1B
-#define OCR1B4_REG OCR1B
-#define OCR1B5_REG OCR1B
-#define OCR1B6_REG OCR1B
-#define OCR1B7_REG OCR1B
-
-/* OCR1C */
-#define OCR1C0_REG OCR1C
-#define OCR1C1_REG OCR1C
-#define OCR1C2_REG OCR1C
-#define OCR1C3_REG OCR1C
-#define OCR1C4_REG OCR1C
-#define OCR1C5_REG OCR1C
-#define OCR1C6_REG OCR1C
-/* #define OCR1C7_REG OCR1C */ /* dup in OCR1D */
-
-/* OCR1A */
-#define OCR1A0_REG OCR1A
-#define OCR1A1_REG OCR1A
-#define OCR1A2_REG OCR1A
-#define OCR1A3_REG OCR1A
-#define OCR1A4_REG OCR1A
-#define OCR1A5_REG OCR1A
-#define OCR1A6_REG OCR1A
-#define OCR1A7_REG OCR1A
-
-/* USIPP */
-#define USIPOS_REG USIPP
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* USIBR */
-#define USIBR0_REG USIBR
-#define USIBR1_REG USIBR
-#define USIBR2_REG USIBR
-#define USIBR3_REG USIBR
-#define USIBR4_REG USIBR
-#define USIBR5_REG USIBR
-#define USIBR6_REG USIBR
-#define USIBR7_REG USIBR
-
-/* DT1 */
-#define DT1L0_REG DT1
-#define DT1L1_REG DT1
-#define DT1L2_REG DT1
-#define DT1L3_REG DT1
-#define DT1H0_REG DT1
-#define DT1H1_REG DT1
-#define DT1H2_REG DT1
-#define DT1H3_REG DT1
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* USIDR */
-#define USIDR0_REG USIDR
-#define USIDR1_REG USIDR
-#define USIDR2_REG USIDR
-#define USIDR3_REG USIDR
-#define USIDR4_REG USIDR
-#define USIDR5_REG USIDR
-#define USIDR6_REG USIDR
-#define USIDR7_REG USIDR
-
-/* DIDR1 */
-#define ADC7D_REG DIDR1
-#define ADC8D_REG DIDR1
-#define ADC9D_REG DIDR1
-#define ADC10D_REG DIDR1
-
-/* pins mapping */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW_TOTAL_NUM 2
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SPH */
-#define SP8_REG SPH
-
-/* PCIFR */
-#define PCIF0_REG PCIFR
-#define PCIF1_REG PCIFR
-#define PCIF2_REG PCIFR
-#define PCIF3_REG PCIFR
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* PORTCR */
-#define PUDA_REG PORTCR
-#define PUDB_REG PORTCR
-#define PUDC_REG PORTCR
-#define PUDD_REG PORTCR
-#define BBMA_REG PORTCR
-#define BBMB_REG PORTCR
-#define BBMC_REG PORTCR
-#define BBMD_REG PORTCR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* OCR0B */
-#define OCR0B_0_REG OCR0B
-#define OCR0B_1_REG OCR0B
-#define OCR0B_2_REG OCR0B
-#define OCR0B_3_REG OCR0B
-#define OCR0B_4_REG OCR0B
-#define OCR0B_5_REG OCR0B
-#define OCR0B_6_REG OCR0B
-#define OCR0B_7_REG OCR0B
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* GTCCR */
-#define PSRSYNC_REG GTCCR
-#define TSM_REG GTCCR
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ACME_REG ADCSRB
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* OCR0A */
-#define OCR0A_0_REG OCR0A
-#define OCR0A_1_REG OCR0A
-#define OCR0A_2_REG OCR0A
-#define OCR0A_3_REG OCR0A
-#define OCR0A_4_REG OCR0A
-#define OCR0A_5_REG OCR0A
-#define OCR0A_6_REG OCR0A
-#define OCR0A_7_REG OCR0A
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRSPI_REG PRR
-#define PRTIM1_REG PRR
-#define PRTIM0_REG PRR
-#define PRTWI_REG PRR
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* SPMCSR */
-#define SELFPRGEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define RFLB_REG SPMCSR
-#define CTPB_REG SPMCSR
-#define RWWSB_REG SPMCSR
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* TWHSR */
-#define TWIHS_REG TWHSR
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* PCICR */
-#define PCIE0_REG PCICR
-#define PCIE1_REG PCICR
-#define PCIE2_REG PCICR
-#define PCIE3_REG PCICR
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* TCCR0A */
-#define CS00_REG TCCR0A
-#define CS01_REG TCCR0A
-#define CS02_REG TCCR0A
-#define CTC0_REG TCCR0A
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-#define PCINT15_REG PCMSK1
-
-/* PCMSK2 */
-#define PCINT16_REG PCMSK2
-#define PCINT17_REG PCMSK2
-#define PCINT18_REG PCMSK2
-#define PCINT19_REG PCMSK2
-#define PCINT20_REG PCMSK2
-#define PCINT21_REG PCMSK2
-#define PCINT22_REG PCMSK2
-#define PCINT23_REG PCMSK2
-
-/* PCMSK3 */
-#define PCINT24_REG PCMSK3
-#define PCINT25_REG PCMSK3
-#define PCINT26_REG PCMSK3
-#define PCINT27_REG PCMSK3
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-#define AREFD_REG DIDR1
-
-/* MCUCR */
-#define PUD_REG MCUCR
-#define BODSE_REG MCUCR
-#define BODS_REG MCUCR
-
-/* TWAMR */
-#define TWAM0_REG TWAMR
-#define TWAM1_REG TWAMR
-#define TWAM2_REG TWAMR
-#define TWAM3_REG TWAMR
-#define TWAM4_REG TWAMR
-#define TWAM5_REG TWAMR
-#define TWAM6_REG TWAMR
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* pins mapping */
-#define ICP1_PORT PORTB
-#define ICP1_BIT 0
-#define CLKO_PORT PORTB
-#define CLKO_BIT 0
-#define PCINT0_PORT PORTB
-#define PCINT0_BIT 0
-
-#define OC1A_PORT PORTB
-#define OC1A_BIT 1
-#define PCINT1_PORT PORTB
-#define PCINT1_BIT 1
-
-#define SS_PORT PORTB
-#define SS_BIT 2
-#define OC1B_PORT PORTB
-#define OC1B_BIT 2
-#define PCINT2_PORT PORTB
-#define PCINT2_BIT 2
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 3
-#define OC2A_PORT PORTB
-#define OC2A_BIT 3
-#define PCINT3_PORT PORTB
-#define PCINT3_BIT 3
-
-#define MISO_PORT PORTB
-#define MISO_BIT 4
-#define PCINT4_PORT PORTB
-#define PCINT4_BIT 4
-
-#define SCK_PORT PORTB
-#define SCK_BIT 5
-#define PCINT5_PORT PORTB
-#define PCINT5_BIT 5
-
-#define XTAL1_PORT PORTB
-#define XTAL1_BIT 6
-#define TOSC1_PORT PORTB
-#define TOSC1_BIT 6
-#define PCINT6_PORT PORTB
-#define PCINT6_BIT 6
-
-#define XTAL2_PORT PORTB
-#define XTAL2_BIT 7
-#define TOSC2_PORT PORTB
-#define TOSC2_BIT 7
-#define PCINT7_PORT PORTB
-#define PCINT7_BIT 7
-
-#define ADC0_PORT PORTC
-#define ADC0_BIT 0
-#define PCINT8_PORT PORTC
-#define PCINT8_BIT 0
-
-#define ADC1_PORT PORTC
-#define ADC1_BIT 1
-#define PCINT9_PORT PORTC
-#define PCINT9_BIT 1
-
-#define ADC2_PORT PORTC
-#define ADC2_BIT 2
-#define PCINT10_PORT PORTC
-#define PCINT10_BIT 2
-
-#define ADC3_PORT PORTC
-#define ADC3_BIT 3
-#define PCINT11_PORT PORTC
-#define PCINT11_BIT 3
-
-#define ADC4_PORT PORTC
-#define ADC4_BIT 4
-#define SDA_PORT PORTC
-#define SDA_BIT 4
-#define PCINT12_PORT PORTC
-#define PCINT12_BIT 4
-
-#define ADC5_PORT PORTC
-#define ADC5_BIT 5
-#define SCL_PORT PORTC
-#define SCL_BIT 5
-#define PCINT13_PORT PORTC
-#define PCINT13_BIT 5
-
-#define RESET_PORT PORTC
-#define RESET_BIT 6
-#define PCINT14_PORT PORTC
-#define PCINT14_BIT 6
-
-#define RXD_PORT PORTD
-#define RXD_BIT 0
-#define PCINT16_PORT PORTD
-#define PCINT16_BIT 0
-
-#define TXD_PORT PORTD
-#define TXD_BIT 1
-#define PCINT17_PORT PORTD
-#define PCINT17_BIT 1
-
-#define INT0_PORT PORTD
-#define INT0_BIT 2
-#define PCINT18_PORT PORTD
-#define PCINT18_BIT 2
-
-#define PCINT19_PORT PORTD
-#define PCINT19_BIT 3
-#define OC2B_PORT PORTD
-#define OC2B_BIT 3
-#define INT1_PORT PORTD
-#define INT1_BIT 3
-
-#define XCK_PORT PORTD
-#define XCK_BIT 4
-#define T0_PORT PORTD
-#define T0_BIT 4
-#define PCINT20_PORT PORTD
-#define PCINT20_BIT 4
-
-#define T1_PORT PORTD
-#define T1_BIT 5
-#define OC0B_PORT PORTD
-#define OC0B_BIT 5
-#define PCINT21_PORT PORTD
-#define PCINT21_BIT 5
-
-#define AIN0_PORT PORTD
-#define AIN0_BIT 6
-#define OC0A_PORT PORTD
-#define OC0A_BIT 6
-#define PCINT22_PORT PORTD
-#define PCINT22_BIT 6
-
-#define AIN1_PORT PORTD
-#define AIN1_BIT 7
-#define PCINT23_PORT PORTD
-#define PCINT23_BIT 7
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-
-/* available timers */
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW_TOTAL_NUM 0
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0
-
-/* Pwm nums */
-#define PWM_TOTAL_NUM 0
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 0
-
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* GIMSK */
-#define PCIE0_REG GIMSK
-#define PCIE1_REG GIMSK
-#define INT0_REG GIMSK
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define MUX5_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* GTCCR */
-#define PSR10_REG GTCCR
-#define TSM_REG GTCCR
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* GIFR */
-#define PCIF0_REG GIFR
-#define PCIF1_REG GIFR
-#define INTF0_REG GIFR
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ACME_REG ADCSRB
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ADLAR_REG ADCSRB
-#define BIN_REG ADCSRB
-
-/* OCR0A */
-/* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */
-
-/* OCR0B */
-/* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-
-/* OCR1BL */
-/* #define OCR1AL0_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL1_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL2_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL3_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL4_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL5_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL6_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL7_REG OCR1BL */ /* dup in OCR1AL */
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* OCR1BH */
-/* #define OCR1AH0_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH1_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH2_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH3_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH4_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH5_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH6_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH7_REG OCR1BH */ /* dup in OCR1AH */
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSI_REG PRR
-#define PRTIM0_REG PRR
-#define PRTIM1_REG PRR
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define RFLB_REG SPMCSR
-#define CTPB_REG SPMCSR
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* USISR */
-#define USICNT0_REG USISR
-#define USICNT1_REG USISR
-#define USICNT2_REG USISR
-#define USICNT3_REG USISR
-#define USIDC_REG USISR
-#define USIPF_REG USISR
-#define USIOIF_REG USISR
-#define USISIF_REG USISR
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* EEARH */
-#define EEAR8_REG EEARH
-
-/* USICR */
-#define USITC_REG USICR
-#define USICLK_REG USICR
-#define USICS0_REG USICR
-#define USICS1_REG USICR
-#define USIWM0_REG USICR
-#define USIWM1_REG USICR
-#define USIOIE_REG USICR
-#define USISIE_REG USICR
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define SM0_REG MCUCR
-#define SM1_REG MCUCR
-#define SE_REG MCUCR
-#define PUD_REG MCUCR
-
-/* OCR1AH */
-/* #define OCR1AH0_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH1_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH2_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH3_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH4_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH5_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH6_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH7_REG OCR1AH */ /* dup in OCR1BH */
-
-/* OCR1AL */
-/* #define OCR1AL0_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL1_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL2_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL3_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL4_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL5_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL6_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL7_REG OCR1AL */ /* dup in OCR1BL */
-
-/* USIDR */
-#define USIDR0_REG USIDR
-#define USIDR1_REG USIDR
-#define USIDR2_REG USIDR
-#define USIDR3_REG USIDR
-#define USIDR4_REG USIDR
-#define USIDR5_REG USIDR
-#define USIDR6_REG USIDR
-#define USIDR7_REG USIDR
-
-/* USIBR */
-#define USIBR0_REG USIBR
-#define USIBR1_REG USIBR
-#define USIBR2_REG USIBR
-#define USIBR3_REG USIBR
-#define USIBR4_REG USIBR
-#define USIBR5_REG USIBR
-#define USIBR6_REG USIBR
-#define USIBR7_REG USIBR
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* pins mapping */
-#define ADC0_PORT PORTA
-#define ADC0_BIT 0
-#define AREF_PORT PORTA
-#define AREF_BIT 0
-#define PCINT0_PORT PORTA
-#define PCINT0_BIT 0
-
-#define ADC1_PORT PORTA
-#define ADC1_BIT 1
-#define AIN0_PORT PORTA
-#define AIN0_BIT 1
-#define PCINT1_PORT PORTA
-#define PCINT1_BIT 1
-
-#define ADC2_PORT PORTA
-#define ADC2_BIT 2
-#define AIN1_PORT PORTA
-#define AIN1_BIT 2
-#define PCINT2_PORT PORTA
-#define PCINT2_BIT 2
-
-#define ADC3_PORT PORTA
-#define ADC3_BIT 3
-#define T0_PORT PORTA
-#define T0_BIT 3
-#define PCINT3_PORT PORTA
-#define PCINT3_BIT 3
-
-#define ADC4_PORT PORTA
-#define ADC4_BIT 4
-#define USCK_PORT PORTA
-#define USCK_BIT 4
-#define SCL_PORT PORTA
-#define SCL_BIT 4
-#define T1_PORT PORTA
-#define T1_BIT 4
-#define PCINT4_PORT PORTA
-#define PCINT4_BIT 4
-
-#define ADC5_PORT PORTA
-#define ADC5_BIT 5
-#define DO_PORT PORTA
-#define DO_BIT 5
-#define MISO_PORT PORTA
-#define MISO_BIT 5
-#define OC1B_PORT PORTA
-#define OC1B_BIT 5
-#define PCINT5_PORT PORTA
-#define PCINT5_BIT 5
-
-#define PCINT6_PORT PORTA
-#define PCINT6_BIT 6
-#define OC1A_PORT PORTA
-#define OC1A_BIT 6
-#define DI_PORT PORTA
-#define DI_BIT 6
-#define SDA_PORT PORTA
-#define SDA_BIT 6
-#define MOSI_PORT PORTA
-#define MOSI_BIT 6
-#define ADC6_PORT PORTA
-#define ADC6_BIT 6
-
-#define PCINT7_PORT PORTA
-#define PCINT7_BIT 7
-#define ICP1_PORT PORTA
-#define ICP1_BIT 7
-#define OC0B_PORT PORTA
-#define OC0B_BIT 7
-#define ADC7_PORT PORTA
-#define ADC7_BIT 7
-
-#define PCINT8_PORT PORTB
-#define PCINT8_BIT 0
-#define XTAL1_PORT PORTB
-#define XTAL1_BIT 0
-
-#define PCINT9_PORT PORTB
-#define PCINT9_BIT 1
-#define XTAL2_PORT PORTB
-#define XTAL2_BIT 1
-
-#define PCINT10_PORT PORTB
-#define PCINT10_BIT 2
-#define INT0_PORT PORTB
-#define INT0_BIT 2
-#define OC0A_PORT PORTB
-#define OC0A_BIT 2
-#define CKOUT_PORT PORTB
-#define CKOUT_BIT 2
-
-#define PCINT11_PORT PORTB
-#define PCINT11_BIT 3
-#define RESET_PORT PORTB
-#define RESET_BIT 3
-#define dW_PORT PORTB
-#define dW_BIT 3
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_2 2
-#define TIMER1_PRESCALER_DIV_4 3
-#define TIMER1_PRESCALER_DIV_8 4
-#define TIMER1_PRESCALER_DIV_16 5
-#define TIMER1_PRESCALER_DIV_32 6
-#define TIMER1_PRESCALER_DIV_64 7
-#define TIMER1_PRESCALER_DIV_128 8
-#define TIMER1_PRESCALER_DIV_256 9
-#define TIMER1_PRESCALER_DIV_512 10
-#define TIMER1_PRESCALER_DIV_1024 11
-#define TIMER1_PRESCALER_DIV_2048 12
-#define TIMER1_PRESCALER_DIV_4096 13
-#define TIMER1_PRESCALER_DIV_8192 14
-#define TIMER1_PRESCALER_DIV_16384 15
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 2
-#define TIMER1_PRESCALER_REG_3 4
-#define TIMER1_PRESCALER_REG_4 8
-#define TIMER1_PRESCALER_REG_5 16
-#define TIMER1_PRESCALER_REG_6 32
-#define TIMER1_PRESCALER_REG_7 64
-#define TIMER1_PRESCALER_REG_8 128
-#define TIMER1_PRESCALER_REG_9 256
-#define TIMER1_PRESCALER_REG_10 512
-#define TIMER1_PRESCALER_REG_11 1024
-#define TIMER1_PRESCALER_REG_12 2048
-#define TIMER1_PRESCALER_REG_13 4096
-#define TIMER1_PRESCALER_REG_14 8192
-#define TIMER1_PRESCALER_REG_15 16384
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW_TOTAL_NUM 2
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 0
-
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-#define WDP3_REG WDTCR
-#define WDIE_REG WDTCR
-#define WDIF_REG WDTCR
-
-/* GIMSK */
-#define PCIE_REG GIMSK
-#define INT0_REG GIMSK
-
-/* DIDR0 */
-#define AIN0D_REG DIDR0
-#define AIN1D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC0D_REG DIDR0
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define REFS2_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* TCCR1 */
-#define CS10_REG TCCR1
-#define CS11_REG TCCR1
-#define CS12_REG TCCR1
-#define CS13_REG TCCR1
-#define COM1A0_REG TCCR1
-#define COM1A1_REG TCCR1
-#define PWM1A_REG TCCR1
-#define CTC1_REG TCCR1
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define SM0_REG MCUCR
-#define SM1_REG MCUCR
-#define SE_REG MCUCR
-#define PUD_REG MCUCR
-
-/* GTCCR */
-#define PSR0_REG GTCCR
-#define TSM_REG GTCCR
-#define PSR1_REG GTCCR
-#define FOC1A_REG GTCCR
-#define FOC1B_REG GTCCR
-#define COM1B0_REG GTCCR
-#define COM1B1_REG GTCCR
-#define PWM1B_REG GTCCR
-
-/* DTPS */
-#define DTPS0_REG DTPS
-#define DTPS1_REG DTPS
-
-/* GIFR */
-#define PCIF_REG GIFR
-#define INTF0_REG GIFR
-
-/* TIMSK */
-#define TOIE0_REG TIMSK
-#define OCIE0B_REG TIMSK
-#define OCIE0A_REG TIMSK
-#define TOIE1_REG TIMSK
-#define OCIE1B_REG TIMSK
-#define OCIE1A_REG TIMSK
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* DT1B */
-/* #define DTVL0_REG DT1B */ /* dup in DT1A */
-/* #define DTVL1_REG DT1B */ /* dup in DT1A */
-/* #define DTVL2_REG DT1B */ /* dup in DT1A */
-/* #define DTVL3_REG DT1B */ /* dup in DT1A */
-/* #define DTVH0_REG DT1B */ /* dup in DT1A */
-/* #define DTVH1_REG DT1B */ /* dup in DT1A */
-/* #define DTVH2_REG DT1B */ /* dup in DT1A */
-/* #define DTVH3_REG DT1B */ /* dup in DT1A */
-
-/* OCR0A */
-/* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */
-
-/* OCR0B */
-/* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSI_REG PRR
-#define PRTIM0_REG PRR
-#define PRTIM1_REG PRR
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* PCMSK */
-#define PCINT0_REG PCMSK
-#define PCINT1_REG PCMSK
-#define PCINT2_REG PCMSK
-#define PCINT3_REG PCMSK
-#define PCINT4_REG PCMSK
-#define PCINT5_REG PCMSK
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define RFLB_REG SPMCSR
-#define CTPB_REG SPMCSR
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* USISR */
-#define USICNT0_REG USISR
-#define USICNT1_REG USISR
-#define USICNT2_REG USISR
-#define USICNT3_REG USISR
-#define USIDC_REG USISR
-#define USIPF_REG USISR
-#define USIOIF_REG USISR
-#define USISIF_REG USISR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TCNT1 */
-#define TCNT1_0_REG TCNT1
-#define TCNT1_1_REG TCNT1
-#define TCNT1_2_REG TCNT1
-#define TCNT1_3_REG TCNT1
-#define TCNT1_4_REG TCNT1
-#define TCNT1_5_REG TCNT1
-#define TCNT1_6_REG TCNT1
-#define TCNT1_7_REG TCNT1
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* TIFR */
-#define TOV0_REG TIFR
-#define OCF0B_REG TIFR
-#define OCF0A_REG TIFR
-#define TOV1_REG TIFR
-#define OCF1B_REG TIFR
-#define OCF1A_REG TIFR
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* EEARH */
-#define EEAR8_REG EEARH
-
-/* PLLCSR */
-#define PLOCK_REG PLLCSR
-#define PLLE_REG PLLCSR
-#define PCKE_REG PLLCSR
-#define LSM_REG PLLCSR
-
-/* USICR */
-#define USITC_REG USICR
-#define USICLK_REG USICR
-#define USICS0_REG USICR
-#define USICS1_REG USICR
-#define USIWM0_REG USICR
-#define USIWM1_REG USICR
-#define USIOIE_REG USICR
-#define USISIE_REG USICR
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* DWDR */
-#define DWDR0_REG DWDR
-#define DWDR1_REG DWDR
-#define DWDR2_REG DWDR
-#define DWDR3_REG DWDR
-#define DWDR4_REG DWDR
-#define DWDR5_REG DWDR
-#define DWDR6_REG DWDR
-#define DWDR7_REG DWDR
-
-/* ADCSRB */
-#define ACME_REG ADCSRB
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define IPR_REG ADCSRB
-#define BIN_REG ADCSRB
-
-/* OCR1B */
-#define OCR1B0_REG OCR1B
-#define OCR1B1_REG OCR1B
-#define OCR1B2_REG OCR1B
-#define OCR1B3_REG OCR1B
-#define OCR1B4_REG OCR1B
-#define OCR1B5_REG OCR1B
-#define OCR1B6_REG OCR1B
-#define OCR1B7_REG OCR1B
-
-/* OCR1C */
-#define OCR1C0_REG OCR1C
-#define OCR1C1_REG OCR1C
-#define OCR1C2_REG OCR1C
-#define OCR1C3_REG OCR1C
-#define OCR1C4_REG OCR1C
-#define OCR1C5_REG OCR1C
-#define OCR1C6_REG OCR1C
-#define OCR1C7_REG OCR1C
-
-/* DT1A */
-/* #define DTVL0_REG DT1A */ /* dup in DT1B */
-/* #define DTVL1_REG DT1A */ /* dup in DT1B */
-/* #define DTVL2_REG DT1A */ /* dup in DT1B */
-/* #define DTVL3_REG DT1A */ /* dup in DT1B */
-/* #define DTVH0_REG DT1A */ /* dup in DT1B */
-/* #define DTVH1_REG DT1A */ /* dup in DT1B */
-/* #define DTVH2_REG DT1A */ /* dup in DT1B */
-/* #define DTVH3_REG DT1A */ /* dup in DT1B */
-
-/* OCR1A */
-#define OCR1A0_REG OCR1A
-#define OCR1A1_REG OCR1A
-#define OCR1A2_REG OCR1A
-#define OCR1A3_REG OCR1A
-#define OCR1A4_REG OCR1A
-#define OCR1A5_REG OCR1A
-#define OCR1A6_REG OCR1A
-#define OCR1A7_REG OCR1A
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-
-/* USIBR */
-#define USIBR0_REG USIBR
-#define USIBR1_REG USIBR
-#define USIBR2_REG USIBR
-#define USIBR3_REG USIBR
-#define USIBR4_REG USIBR
-#define USIBR5_REG USIBR
-#define USIBR6_REG USIBR
-#define USIBR7_REG USIBR
-
-/* USIDR */
-#define USIDR0_REG USIDR
-#define USIDR1_REG USIDR
-#define USIDR2_REG USIDR
-#define USIDR3_REG USIDR
-#define USIDR4_REG USIDR
-#define USIDR5_REG USIDR
-#define USIDR6_REG USIDR
-#define USIDR7_REG USIDR
-
-/* pins mapping */
-#define MOSI_PORT PORTB
-#define MOSI_BIT 0
-#define DI_PORT PORTB
-#define DI_BIT 0
-#define SDA_PORT PORTB
-#define SDA_BIT 0
-#define AIN0_PORT PORTB
-#define AIN0_BIT 0
-#define OC0A_PORT PORTB
-#define OC0A_BIT 0
-#define OC1A_PORT PORTB
-#define OC1A_BIT 0
-#define AREF_PORT PORTB
-#define AREF_BIT 0
-#define PCINT0_PORT PORTB
-#define PCINT0_BIT 0
-
-#define MISO_PORT PORTB
-#define MISO_BIT 1
-#define DO_PORT PORTB
-#define DO_BIT 1
-#define AIN1_PORT PORTB
-#define AIN1_BIT 1
-#define OC0B_PORT PORTB
-#define OC0B_BIT 1
-#define OC1A_PORT PORTB
-#define OC1A_BIT 1
-#define PCINT1_PORT PORTB
-#define PCINT1_BIT 1
-
-#define SCK_PORT PORTB
-#define SCK_BIT 2
-#define USCK_PORT PORTB
-#define USCK_BIT 2
-#define SCL_PORT PORTB
-#define SCL_BIT 2
-#define ADC1_PORT PORTB
-#define ADC1_BIT 2
-#define T0_PORT PORTB
-#define T0_BIT 2
-#define INT0_PORT PORTB
-#define INT0_BIT 2
-#define PCINT2_PORT PORTB
-#define PCINT2_BIT 2
-
-#define ADC3_PORT PORTB
-#define ADC3_BIT 3
-#define OC1B_PORT PORTB
-#define OC1B_BIT 3
-#define XTAL1_PORT PORTB
-#define XTAL1_BIT 3
-#define PCINT4_PORT PORTB
-#define PCINT4_BIT 3
-
-#define ADC2_PORT PORTB
-#define ADC2_BIT 4
-#define OC1B_PORT PORTB
-#define OC1B_BIT 4
-#define XTAL2_PORT PORTB
-#define XTAL2_BIT 4
-#define PCINT3_PORT PORTB
-#define PCINT3_BIT 4
-
-#define RESET_PORT PORTB
-#define RESET_BIT 5
-#define ADC0_PORT PORTB
-#define ADC0_BIT 5
-#define PCINT5_PORT PORTB
-#define PCINT5_BIT 5
-#define dW_PORT PORTB
-#define dW_BIT 5
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_2 2
-#define TIMER1_PRESCALER_DIV_4 3
-#define TIMER1_PRESCALER_DIV_8 4
-#define TIMER1_PRESCALER_DIV_16 5
-#define TIMER1_PRESCALER_DIV_32 6
-#define TIMER1_PRESCALER_DIV_64 7
-#define TIMER1_PRESCALER_DIV_128 8
-#define TIMER1_PRESCALER_DIV_256 9
-#define TIMER1_PRESCALER_DIV_512 10
-#define TIMER1_PRESCALER_DIV_1024 11
-#define TIMER1_PRESCALER_DIV_2048 12
-#define TIMER1_PRESCALER_DIV_4096 13
-#define TIMER1_PRESCALER_DIV_8192 14
-#define TIMER1_PRESCALER_DIV_16384 15
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 2
-#define TIMER1_PRESCALER_REG_3 4
-#define TIMER1_PRESCALER_REG_4 8
-#define TIMER1_PRESCALER_REG_5 16
-#define TIMER1_PRESCALER_REG_6 32
-#define TIMER1_PRESCALER_REG_7 64
-#define TIMER1_PRESCALER_REG_8 128
-#define TIMER1_PRESCALER_REG_9 256
-#define TIMER1_PRESCALER_REG_10 512
-#define TIMER1_PRESCALER_REG_11 1024
-#define TIMER1_PRESCALER_REG_12 2048
-#define TIMER1_PRESCALER_REG_13 4096
-#define TIMER1_PRESCALER_REG_14 8192
-#define TIMER1_PRESCALER_REG_15 16384
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW_TOTAL_NUM 2
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1_NUM 2
-#define SIG_OUTPUT_COMPARE1A_NUM 3
-#define SIG_OUTPUT_COMPARE1B_NUM 4
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 5
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1_NUM 2
-#define PWM1A_NUM 3
-#define PWM1B_NUM 4
-#define PWM_TOTAL_NUM 5
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE0_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-#define WDP3_REG WDTCR
-#define WDIE_REG WDTCR
-#define WDIF_REG WDTCR
-
-/* GIMSK */
-#define PCIE0_REG GIMSK
-#define PCIE1_REG GIMSK
-#define INT0_REG GIMSK
-#define INT1_REG GIMSK
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define AREFD_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* TCNT0H */
-/* #define TCNT0_0_REG TCNT0H */ /* dup in TCNT0L */
-/* #define TCNT0_1_REG TCNT0H */ /* dup in TCNT0L */
-/* #define TCNT0_2_REG TCNT0H */ /* dup in TCNT0L */
-/* #define TCNT0_3_REG TCNT0H */ /* dup in TCNT0L */
-/* #define TCNT0_4_REG TCNT0H */ /* dup in TCNT0L */
-/* #define TCNT0_5_REG TCNT0H */ /* dup in TCNT0L */
-/* #define TCNT0_6_REG TCNT0H */ /* dup in TCNT0L */
-/* #define TCNT0_7_REG TCNT0H */ /* dup in TCNT0L */
-
-/* TCNT0L */
-/* #define TCNT0_0_REG TCNT0L */ /* dup in TCNT0H */
-/* #define TCNT0_1_REG TCNT0L */ /* dup in TCNT0H */
-/* #define TCNT0_2_REG TCNT0L */ /* dup in TCNT0H */
-/* #define TCNT0_3_REG TCNT0L */ /* dup in TCNT0H */
-/* #define TCNT0_4_REG TCNT0L */ /* dup in TCNT0H */
-/* #define TCNT0_5_REG TCNT0L */ /* dup in TCNT0H */
-/* #define TCNT0_6_REG TCNT0L */ /* dup in TCNT0H */
-/* #define TCNT0_7_REG TCNT0L */ /* dup in TCNT0H */
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* TCCR1D */
-#define WGM10_REG TCCR1D
-#define WGM11_REG TCCR1D
-#define FPF1_REG TCCR1D
-#define FPAC1_REG TCCR1D
-#define FPES1_REG TCCR1D
-#define FPNC1_REG TCCR1D
-#define FPEN1_REG TCCR1D
-#define FPIE1_REG TCCR1D
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define SM0_REG MCUCR
-#define SM1_REG MCUCR
-#define SE_REG MCUCR
-#define PUD_REG MCUCR
-
-/* TCCR1A */
-#define PWM1B_REG TCCR1A
-#define PWM1A_REG TCCR1A
-#define FOC1B_REG TCCR1A
-#define FOC1A_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* TCCR1C */
-#define PWM1D_REG TCCR1C
-#define FOC1D_REG TCCR1C
-#define COM1D0_REG TCCR1C
-#define COM1D1_REG TCCR1C
-#define COM1B0S_REG TCCR1C
-#define COM1B1S_REG TCCR1C
-#define COM1A0S_REG TCCR1C
-#define COM1A1S_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define CS13_REG TCCR1B
-#define DTPS10_REG TCCR1B
-#define DTPS11_REG TCCR1B
-#define PSR1_REG TCCR1B
-
-/* GIFR */
-#define PCIF_REG GIFR
-#define INTF0_REG GIFR
-#define INTF1_REG GIFR
-
-/* TIMSK */
-#define TICIE0_REG TIMSK
-#define TOIE0_REG TIMSK
-#define OCIE0B_REG TIMSK
-#define OCIE0A_REG TIMSK
-#define TOIE1_REG TIMSK
-#define OCIE1B_REG TIMSK
-#define OCIE1A_REG TIMSK
-#define OCIE1D_REG TIMSK
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ACSRB */
-#define ACM0_REG ACSRB
-#define ACM1_REG ACSRB
-#define ACM2_REG ACSRB
-#define HLEV_REG ACSRB
-#define HSEL_REG ACSRB
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define MUX5_REG ADCSRB
-#define REFS2_REG ADCSRB
-#define IPR_REG ADCSRB
-#define GSEL_REG ADCSRB
-#define BIN_REG ADCSRB
-
-/* TC1H */
-#define TC18_REG TC1H
-#define TC19_REG TC1H
-
-/* TCCR1E */
-#define OC1OE0_REG TCCR1E
-#define OC1OE1_REG TCCR1E
-#define OC1OE2_REG TCCR1E
-#define OC1OE3_REG TCCR1E
-#define OC1OE4_REG TCCR1E
-#define OC1OE5_REG TCCR1E
-
-/* OCR0A */
-/* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */
-
-/* OCR0B */
-/* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSI_REG PRR
-#define PRTIM0_REG PRR
-#define PRTIM1_REG PRR
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* USICR */
-#define USITC_REG USICR
-#define USICLK_REG USICR
-#define USICS0_REG USICR
-#define USICS1_REG USICR
-#define USIWM0_REG USICR
-#define USIWM1_REG USICR
-#define USIOIE_REG USICR
-#define USISIE_REG USICR
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define RFLB_REG SPMCSR
-#define CTPB_REG SPMCSR
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* USISR */
-#define USICNT0_REG USISR
-#define USICNT1_REG USISR
-#define USICNT2_REG USISR
-#define USICNT3_REG USISR
-#define USIDC_REG USISR
-#define USIPF_REG USISR
-#define USIOIF_REG USISR
-#define USISIF_REG USISR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* ACSRA */
-#define ACIS0_REG ACSRA
-#define ACIS1_REG ACSRA
-#define ACME_REG ACSRA
-#define ACIE_REG ACSRA
-#define ACI_REG ACSRA
-#define ACO_REG ACSRA
-#define ACBG_REG ACSRA
-#define ACD_REG ACSRA
-
-/* TCNT1 */
-#define TC1H_0_REG TCNT1
-#define TC1H_1_REG TCNT1
-#define TC1H_2_REG TCNT1
-#define TC1H_3_REG TCNT1
-#define TC1H_4_REG TCNT1
-#define TC1H_5_REG TCNT1
-#define TC1H_6_REG TCNT1
-#define TC1H_7_REG TCNT1
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define PSR0_REG TCCR0B
-#define TSM_REG TCCR0B
-
-/* TIFR */
-#define ICF0_REG TIFR
-#define TOV0_REG TIFR
-#define OCF0B_REG TIFR
-#define OCF0A_REG TIFR
-#define TOV1_REG TIFR
-#define OCF1B_REG TIFR
-#define OCF1A_REG TIFR
-#define OCF1D_REG TIFR
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define ACIC0_REG TCCR0A
-#define ICES0_REG TCCR0A
-#define ICNC0_REG TCCR0A
-#define ICEN0_REG TCCR0A
-#define TCW0_REG TCCR0A
-
-/* EEARH */
-#define EEAR8_REG EEARH
-
-/* PLLCSR */
-#define PLOCK_REG PLLCSR
-#define PLLE_REG PLLCSR
-#define PCKE_REG PLLCSR
-#define LSM_REG PLLCSR
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-#define PCINT15_REG PCMSK1
-
-/* DWDR */
-#define DWDR0_REG DWDR
-#define DWDR1_REG DWDR
-#define DWDR2_REG DWDR
-#define DWDR3_REG DWDR
-#define DWDR4_REG DWDR
-#define DWDR5_REG DWDR
-#define DWDR6_REG DWDR
-#define DWDR7_REG DWDR
-
-/* OCR1D */
-#define OCR1D0_REG OCR1D
-#define OCR1D1_REG OCR1D
-#define OCR1D2_REG OCR1D
-#define OCR1D3_REG OCR1D
-#define OCR1D4_REG OCR1D
-#define OCR1D5_REG OCR1D
-#define OCR1D6_REG OCR1D
-/* #define OCR1C7_REG OCR1D */ /* dup in OCR1C */
-
-/* OCR1B */
-#define OCR1B0_REG OCR1B
-#define OCR1B1_REG OCR1B
-#define OCR1B2_REG OCR1B
-#define OCR1B3_REG OCR1B
-#define OCR1B4_REG OCR1B
-#define OCR1B5_REG OCR1B
-#define OCR1B6_REG OCR1B
-#define OCR1B7_REG OCR1B
-
-/* OCR1C */
-#define OCR1C0_REG OCR1C
-#define OCR1C1_REG OCR1C
-#define OCR1C2_REG OCR1C
-#define OCR1C3_REG OCR1C
-#define OCR1C4_REG OCR1C
-#define OCR1C5_REG OCR1C
-#define OCR1C6_REG OCR1C
-/* #define OCR1C7_REG OCR1C */ /* dup in OCR1D */
-
-/* OCR1A */
-#define OCR1A0_REG OCR1A
-#define OCR1A1_REG OCR1A
-#define OCR1A2_REG OCR1A
-#define OCR1A3_REG OCR1A
-#define OCR1A4_REG OCR1A
-#define OCR1A5_REG OCR1A
-#define OCR1A6_REG OCR1A
-#define OCR1A7_REG OCR1A
-
-/* USIPP */
-#define USIPOS_REG USIPP
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* USIBR */
-#define USIBR0_REG USIBR
-#define USIBR1_REG USIBR
-#define USIBR2_REG USIBR
-#define USIBR3_REG USIBR
-#define USIBR4_REG USIBR
-#define USIBR5_REG USIBR
-#define USIBR6_REG USIBR
-#define USIBR7_REG USIBR
-
-/* DT1 */
-#define DT1L0_REG DT1
-#define DT1L1_REG DT1
-#define DT1L2_REG DT1
-#define DT1L3_REG DT1
-#define DT1H0_REG DT1
-#define DT1H1_REG DT1
-#define DT1H2_REG DT1
-#define DT1H3_REG DT1
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* USIDR */
-#define USIDR0_REG USIDR
-#define USIDR1_REG USIDR
-#define USIDR2_REG USIDR
-#define USIDR3_REG USIDR
-#define USIDR4_REG USIDR
-#define USIDR5_REG USIDR
-#define USIDR6_REG USIDR
-#define USIDR7_REG USIDR
-
-/* DIDR1 */
-#define ADC7D_REG DIDR1
-#define ADC8D_REG DIDR1
-#define ADC9D_REG DIDR1
-#define ADC10D_REG DIDR1
-
-/* pins mapping */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW_TOTAL_NUM 2
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-
-/* PCIFR */
-#define PCIF0_REG PCIFR
-#define PCIF1_REG PCIFR
-#define PCIF2_REG PCIFR
-#define PCIF3_REG PCIFR
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* PORTCR */
-#define PUDA_REG PORTCR
-#define PUDB_REG PORTCR
-#define PUDC_REG PORTCR
-#define PUDD_REG PORTCR
-#define BBMA_REG PORTCR
-#define BBMB_REG PORTCR
-#define BBMC_REG PORTCR
-#define BBMD_REG PORTCR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* TWDR */
-#define TWD0_REG TWDR
-#define TWD1_REG TWDR
-#define TWD2_REG TWDR
-#define TWD3_REG TWDR
-#define TWD4_REG TWDR
-#define TWD5_REG TWDR
-#define TWD6_REG TWDR
-#define TWD7_REG TWDR
-
-/* OCR0B */
-#define OCR0B_0_REG OCR0B
-#define OCR0B_1_REG OCR0B
-#define OCR0B_2_REG OCR0B
-#define OCR0B_3_REG OCR0B
-#define OCR0B_4_REG OCR0B
-#define OCR0B_5_REG OCR0B
-#define OCR0B_6_REG OCR0B
-#define OCR0B_7_REG OCR0B
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* GTCCR */
-#define PSRSYNC_REG GTCCR
-#define TSM_REG GTCCR
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ACME_REG ADCSRB
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* OCR0A */
-#define OCR0A_0_REG OCR0A
-#define OCR0A_1_REG OCR0A
-#define OCR0A_2_REG OCR0A
-#define OCR0A_3_REG OCR0A
-#define OCR0A_4_REG OCR0A
-#define OCR0A_5_REG OCR0A
-#define OCR0A_6_REG OCR0A
-#define OCR0A_7_REG OCR0A
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRSPI_REG PRR
-#define PRTIM1_REG PRR
-#define PRTIM0_REG PRR
-#define PRTWI_REG PRR
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* TWBR */
-#define TWBR0_REG TWBR
-#define TWBR1_REG TWBR
-#define TWBR2_REG TWBR
-#define TWBR3_REG TWBR
-#define TWBR4_REG TWBR
-#define TWBR5_REG TWBR
-#define TWBR6_REG TWBR
-#define TWBR7_REG TWBR
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* SPMCSR */
-#define SELFPRGEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define RFLB_REG SPMCSR
-#define CTPB_REG SPMCSR
-#define RWWSB_REG SPMCSR
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* TWHSR */
-#define TWIHS_REG TWHSR
-
-/* TWCR */
-#define TWIE_REG TWCR
-#define TWEN_REG TWCR
-#define TWWC_REG TWCR
-#define TWSTO_REG TWCR
-#define TWSTA_REG TWCR
-#define TWEA_REG TWCR
-#define TWINT_REG TWCR
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* PCICR */
-#define PCIE0_REG PCICR
-#define PCIE1_REG PCICR
-#define PCIE2_REG PCICR
-#define PCIE3_REG PCICR
-
-/* TWAR */
-#define TWGCE_REG TWAR
-#define TWA0_REG TWAR
-#define TWA1_REG TWAR
-#define TWA2_REG TWAR
-#define TWA3_REG TWAR
-#define TWA4_REG TWAR
-#define TWA5_REG TWAR
-#define TWA6_REG TWAR
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* TCCR0A */
-#define CS00_REG TCCR0A
-#define CS01_REG TCCR0A
-#define CS02_REG TCCR0A
-#define CTC0_REG TCCR0A
-
-/* TWSR */
-#define TWPS0_REG TWSR
-#define TWPS1_REG TWSR
-#define TWS3_REG TWSR
-#define TWS4_REG TWSR
-#define TWS5_REG TWSR
-#define TWS6_REG TWSR
-#define TWS7_REG TWSR
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-#define PCINT15_REG PCMSK1
-
-/* PCMSK2 */
-#define PCINT16_REG PCMSK2
-#define PCINT17_REG PCMSK2
-#define PCINT18_REG PCMSK2
-#define PCINT19_REG PCMSK2
-#define PCINT20_REG PCMSK2
-#define PCINT21_REG PCMSK2
-#define PCINT22_REG PCMSK2
-#define PCINT23_REG PCMSK2
-
-/* PCMSK3 */
-#define PCINT24_REG PCMSK3
-#define PCINT25_REG PCMSK3
-#define PCINT26_REG PCMSK3
-#define PCINT27_REG PCMSK3
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-#define AREFD_REG DIDR1
-
-/* MCUCR */
-#define PUD_REG MCUCR
-#define BODSE_REG MCUCR
-#define BODS_REG MCUCR
-
-/* TWAMR */
-#define TWAM0_REG TWAMR
-#define TWAM1_REG TWAMR
-#define TWAM2_REG TWAMR
-#define TWAM3_REG TWAMR
-#define TWAM4_REG TWAMR
-#define TWAM5_REG TWAMR
-#define TWAM6_REG TWAMR
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* pins mapping */
-#define ICP1_PORT PORTB
-#define ICP1_BIT 0
-#define CLKO_PORT PORTB
-#define CLKO_BIT 0
-#define PCINT0_PORT PORTB
-#define PCINT0_BIT 0
-
-#define OC1A_PORT PORTB
-#define OC1A_BIT 1
-#define PCINT1_PORT PORTB
-#define PCINT1_BIT 1
-
-#define SS_PORT PORTB
-#define SS_BIT 2
-#define OC1B_PORT PORTB
-#define OC1B_BIT 2
-#define PCINT2_PORT PORTB
-#define PCINT2_BIT 2
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 3
-#define OC2A_PORT PORTB
-#define OC2A_BIT 3
-#define PCINT3_PORT PORTB
-#define PCINT3_BIT 3
-
-#define MISO_PORT PORTB
-#define MISO_BIT 4
-#define PCINT4_PORT PORTB
-#define PCINT4_BIT 4
-
-#define SCK_PORT PORTB
-#define SCK_BIT 5
-#define PCINT5_PORT PORTB
-#define PCINT5_BIT 5
-
-#define XTAL1_PORT PORTB
-#define XTAL1_BIT 6
-#define TOSC1_PORT PORTB
-#define TOSC1_BIT 6
-#define PCINT6_PORT PORTB
-#define PCINT6_BIT 6
-
-#define XTAL2_PORT PORTB
-#define XTAL2_BIT 7
-#define TOSC2_PORT PORTB
-#define TOSC2_BIT 7
-#define PCINT7_PORT PORTB
-#define PCINT7_BIT 7
-
-#define ADC0_PORT PORTC
-#define ADC0_BIT 0
-#define PCINT8_PORT PORTC
-#define PCINT8_BIT 0
-
-#define ADC1_PORT PORTC
-#define ADC1_BIT 1
-#define PCINT9_PORT PORTC
-#define PCINT9_BIT 1
-
-#define ADC2_PORT PORTC
-#define ADC2_BIT 2
-#define PCINT10_PORT PORTC
-#define PCINT10_BIT 2
-
-#define ADC3_PORT PORTC
-#define ADC3_BIT 3
-#define PCINT11_PORT PORTC
-#define PCINT11_BIT 3
-
-#define ADC4_PORT PORTC
-#define ADC4_BIT 4
-#define SDA_PORT PORTC
-#define SDA_BIT 4
-#define PCINT12_PORT PORTC
-#define PCINT12_BIT 4
-
-#define ADC5_PORT PORTC
-#define ADC5_BIT 5
-#define SCL_PORT PORTC
-#define SCL_BIT 5
-#define PCINT13_PORT PORTC
-#define PCINT13_BIT 5
-
-#define RESET_PORT PORTC
-#define RESET_BIT 6
-#define PCINT14_PORT PORTC
-#define PCINT14_BIT 6
-
-#define RXD_PORT PORTD
-#define RXD_BIT 0
-#define PCINT16_PORT PORTD
-#define PCINT16_BIT 0
-
-#define TXD_PORT PORTD
-#define TXD_BIT 1
-#define PCINT17_PORT PORTD
-#define PCINT17_BIT 1
-
-#define INT0_PORT PORTD
-#define INT0_BIT 2
-#define PCINT18_PORT PORTD
-#define PCINT18_BIT 2
-
-#define PCINT19_PORT PORTD
-#define PCINT19_BIT 3
-#define OC2B_PORT PORTD
-#define OC2B_BIT 3
-#define INT1_PORT PORTD
-#define INT1_BIT 3
-
-#define XCK_PORT PORTD
-#define XCK_BIT 4
-#define T0_PORT PORTD
-#define T0_BIT 4
-#define PCINT20_PORT PORTD
-#define PCINT20_BIT 4
-
-#define T1_PORT PORTD
-#define T1_BIT 5
-#define OC0B_PORT PORTD
-#define OC0B_BIT 5
-#define PCINT21_PORT PORTD
-#define PCINT21_BIT 5
-
-#define AIN0_PORT PORTD
-#define AIN0_BIT 6
-#define OC0A_PORT PORTD
-#define OC0A_BIT 6
-#define PCINT22_PORT PORTD
-#define PCINT22_BIT 6
-
-#define AIN1_PORT PORTD
-#define AIN1_BIT 7
-#define PCINT23_PORT PORTD
-#define PCINT23_BIT 7
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-
-/* available timers */
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW_TOTAL_NUM 0
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0
-
-/* Pwm nums */
-#define PWM_TOTAL_NUM 0
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 0
-
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* pins mapping */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-
-/* available timers */
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW_TOTAL_NUM 0
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0
-
-/* Pwm nums */
-#define PWM_TOTAL_NUM 0
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 0
-
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* pins mapping */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-
-/* available timers */
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW_TOTAL_NUM 0
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0
-
-/* Pwm nums */
-#define PWM_TOTAL_NUM 0
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 0
-
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* pins mapping */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-
-/* available timers */
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW_TOTAL_NUM 0
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0
-
-/* Pwm nums */
-#define PWM_TOTAL_NUM 0
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 0
-
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* pins mapping */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-
-/* available timers */
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW_TOTAL_NUM 0
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0
-
-/* Pwm nums */
-#define PWM_TOTAL_NUM 0
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 0
-
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* pins mapping */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-
-/* available timers */
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW_TOTAL_NUM 0
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0
-
-/* Pwm nums */
-#define PWM_TOTAL_NUM 0
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 0
-
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* pins mapping */
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: pgmspace.h,v 1.1.2.4 2007-11-21 21:54:38 zer0 Exp $
- *
- */
-
-/**
- * This file is used for compatibility between host and avr : with
- * this we can emulate pgmspace on a host.
- */
-
-#ifndef _AVERSIVE_PGMSPACE_H_
-#define _AVERSIVE_PGMSPACE_H_
-
-#ifndef HOST_VERSION
-
-#include <avr/pgmspace.h>
-#define PGMS_FMT "%S"
-
-
-#else
-
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <stdarg.h>
-#include <string.h>
-
-typedef void prog_void;
-typedef char prog_char;
-typedef unsigned char prog_uchar;
-typedef int8_t prog_int8_t;
-typedef uint8_t prog_uint8_t;
-typedef int16_t prog_int16_t;
-typedef uint16_t prog_uint16_t;
-typedef int32_t prog_int32_t;
-typedef uint32_t prog_uint32_t;
-typedef int64_t prog_int64_t;
-
-
-static inline int memcmp_P(const void *s1,
- const prog_void *s2, unsigned n)
-{
- return memcmp(s1, s2, n);
-}
-
-static inline void *memcpy_P(void *s1,
- const prog_void *s2, unsigned n)
-{
- return memcpy(s1, s2, n);
-}
-
-static inline char *strcat_P(char *s1, const prog_char *s2)
-{
- return strcat(s1, s2);
-}
-
-static inline char *strcpy_P(char *s1, const prog_char *s2)
-{
- return strcpy(s1, s2);
-}
-
-static inline char *strncpy_P(char *s1, const prog_char *s2,
- unsigned n)
-{
- return strncpy(s1, s2, n);
-}
-
-static inline int strcmp_P(const char *s1, const prog_char *s2)
-{
- return strcmp(s1, s2);
-}
-
-static inline int strncmp_P(const char *s1, const prog_char *s2,
- unsigned n)
-{
- return strncmp(s1, s2, n);
-}
-
-static inline unsigned strlen_P(const prog_char *s)
-{
- return strlen(s);
-}
-
-static inline int vfprintf_P(FILE *stream,
- const prog_char *s, va_list ap)
-{
- return vfprintf(stream, s, ap);
-}
-
-static inline int vsprintf_P(char *buf, const prog_char *s,
- va_list ap)
-{
- return vsprintf(buf, s, ap);
-}
-
-#define PGM_P const char *
-#define PSTR(x) x
-#define PROGMEM
-#define printf_P(args...) printf(args)
-#define sprintf_P(buf, args...) sprintf(buf, args)
-#define snprintf_P(buf, n, args...) snprintf(buf, n, args)
-
-static inline uint32_t pgm_read_dword(const prog_void *x)
-{
- return *(uint32_t *)x;
-}
-
-static inline uint16_t pgm_read_word(const prog_void *x)
-{
- return *(uint16_t *)x;
-}
-
-static inline uint8_t pgm_read_byte(const prog_void *x)
-{
- return *(uint8_t *)x;
-}
-
-#define PGMS_FMT "%s"
-
-#endif /* HOST_VERSION */
-#endif /* _AVERSIVE_PGMSPACE_H_ */
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: pgmspace.h,v 1.1.2.4 2007-11-21 21:54:38 zer0 Exp $
- *
- */
-
-/**
- * This file is used for compatibility between host and avr : with
- * this we can emulate pgmspace on a host.
- */
-
-#ifndef _AVERSIVE_PGMSPACE_H_
-#define _AVERSIVE_PGMSPACE_H_
-
-#ifndef HOST_VERSION
-
-#include <avr/pgmspace.h>
-#define PGMS_FMT "%S"
-
-
-#else
-
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <stdarg.h>
-#include <string.h>
-
-typedef void prog_void;
-typedef char prog_char;
-typedef unsigned char prog_uchar;
-typedef int8_t prog_int8_t;
-typedef uint8_t prog_uint8_t;
-typedef int16_t prog_int16_t;
-typedef uint16_t prog_uint16_t;
-typedef int32_t prog_int32_t;
-typedef uint32_t prog_uint32_t;
-typedef int64_t prog_int64_t;
-
-
-static inline int memcmp_P(const void *s1,
- const prog_void *s2, unsigned n)
-{
- return memcmp(s1, s2, n);
-}
-
-static inline void *memcpy_P(void *s1,
- const prog_void *s2, unsigned n)
-{
- return memcpy(s1, s2, n);
-}
-
-static inline char *strcat_P(char *s1, const prog_char *s2)
-{
- return strcat(s1, s2);
-}
-
-static inline char *strcpy_P(char *s1, const prog_char *s2)
-{
- return strcpy(s1, s2);
-}
-
-static inline char *strncpy_P(char *s1, const prog_char *s2,
- unsigned n)
-{
- return strncpy(s1, s2, n);
-}
-
-static inline int strcmp_P(const char *s1, const prog_char *s2)
-{
- return strcmp(s1, s2);
-}
-
-static inline int strncmp_P(const char *s1, const prog_char *s2,
- unsigned n)
-{
- return strncmp(s1, s2, n);
-}
-
-static inline unsigned strlen_P(const prog_char *s)
-{
- return strlen(s);
-}
-
-static inline int vfprintf_P(FILE *stream,
- const prog_char *s, va_list ap)
-{
- return vfprintf(stream, s, ap);
-}
-
-static inline int vsprintf_P(char *buf, const prog_char *s,
- va_list ap)
-{
- return vsprintf(buf, s, ap);
-}
-
-#define PGM_P const char *
-#define PSTR(x) x
-#define PROGMEM
-#define printf_P(args...) printf(args)
-#define sprintf_P(buf, args...) sprintf(buf, args)
-#define snprintf_P(buf, n, args...) snprintf(buf, n, args)
-
-static inline uint32_t pgm_read_dword(const prog_void *x)
-{
- return *(uint32_t *)x;
-}
-
-static inline uint16_t pgm_read_word(const prog_void *x)
-{
- return *(uint16_t *)x;
-}
-
-static inline uint8_t pgm_read_byte(const prog_void *x)
-{
- return *(uint8_t *)x;
-}
-
-#define PGMS_FMT "%s"
-
-#endif /* HOST_VERSION */
-#endif /* _AVERSIVE_PGMSPACE_H_ */
-
-
+++ /dev/null
-/*
- * Copyright (c) 1991, 1993
- * The Regents of the University of California. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- * must display the following acknowledgement:
- * This product includes software developed by the University of
- * California, Berkeley and its contributors.
- * 4. Neither the name of the University nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @(#)queue.h 8.5 (Berkeley) 8/20/94
- * $FreeBSD: src/sys/sys/queue.h,v 1.32.2.7 2002/04/17 14:21:02 des Exp $
- */
-
-#ifndef _AVERSIVE_QUEUE_H_
-#define _AVERSIVE_QUEUE_H_
-
-#ifndef __offsetof
-#define __offsetof(type, field) ((size_t)(&(type *)0)->field))
-#endif
-
-/*
- * This file defines five types of data structures: singly-linked lists,
- * singly-linked tail queues, lists, tail queues, and circular queues.
- *
- * A singly-linked list is headed by a single forward pointer. The elements
- * are singly linked for minimum space and pointer manipulation overhead at
- * the expense of O(n) removal for arbitrary elements. New elements can be
- * added to the list after an existing element or at the head of the list.
- * Elements being removed from the head of the list should use the explicit
- * macro for this purpose for optimum efficiency. A singly-linked list may
- * only be traversed in the forward direction. Singly-linked lists are ideal
- * for applications with large datasets and few or no removals or for
- * implementing a LIFO queue.
- *
- * A singly-linked tail queue is headed by a pair of pointers, one to the
- * head of the list and the other to the tail of the list. The elements are
- * singly linked for minimum space and pointer manipulation overhead at the
- * expense of O(n) removal for arbitrary elements. New elements can be added
- * to the list after an existing element, at the head of the list, or at the
- * end of the list. Elements being removed from the head of the tail queue
- * should use the explicit macro for this purpose for optimum efficiency.
- * A singly-linked tail queue may only be traversed in the forward direction.
- * Singly-linked tail queues are ideal for applications with large datasets
- * and few or no removals or for implementing a FIFO queue.
- *
- * A list is headed by a single forward pointer (or an array of forward
- * pointers for a hash table header). The elements are doubly linked
- * so that an arbitrary element can be removed without a need to
- * traverse the list. New elements can be added to the list before
- * or after an existing element or at the head of the list. A list
- * may only be traversed in the forward direction.
- *
- * A tail queue is headed by a pair of pointers, one to the head of the
- * list and the other to the tail of the list. The elements are doubly
- * linked so that an arbitrary element can be removed without a need to
- * traverse the list. New elements can be added to the list before or
- * after an existing element, at the head of the list, or at the end of
- * the list. A tail queue may be traversed in either direction.
- *
- * A circle queue is headed by a pair of pointers, one to the head of the
- * list and the other to the tail of the list. The elements are doubly
- * linked so that an arbitrary element can be removed without a need to
- * traverse the list. New elements can be added to the list before or after
- * an existing element, at the head of the list, or at the end of the list.
- * A circle queue may be traversed in either direction, but has a more
- * complex end of list detection.
- *
- * For details on the use of these macros, see the queue(3) manual page.
- *
- *
- * SLIST LIST STAILQ TAILQ CIRCLEQ
- * _HEAD + + + + +
- * _HEAD_INITIALIZER + + + + +
- * _ENTRY + + + + +
- * _INIT + + + + +
- * _EMPTY + + + + +
- * _FIRST + + + + +
- * _NEXT + + + + +
- * _PREV - - - + +
- * _LAST - - + + +
- * _FOREACH + + + + +
- * _FOREACH_REVERSE - - - + +
- * _INSERT_HEAD + + + + +
- * _INSERT_BEFORE - + - + +
- * _INSERT_AFTER + + + + +
- * _INSERT_TAIL - - + + +
- * _REMOVE_HEAD + - + - -
- * _REMOVE + + + + +
- *
- */
-
-/*
- * Singly-linked List declarations.
- */
-#define SLIST_HEAD(name, type) \
-struct name { \
- struct type *slh_first; /* first element */ \
-}
-
-#define SLIST_HEAD_INITIALIZER(head) \
- { NULL }
-
-#define SLIST_ENTRY(type) \
-struct { \
- struct type *sle_next; /* next element */ \
-}
-
-/*
- * Singly-linked List functions.
- */
-#define SLIST_EMPTY(head) ((head)->slh_first == NULL)
-
-#define SLIST_FIRST(head) ((head)->slh_first)
-
-#define SLIST_FOREACH(var, head, field) \
- for ((var) = SLIST_FIRST((head)); \
- (var); \
- (var) = SLIST_NEXT((var), field))
-
-#define SLIST_INIT(head) do { \
- SLIST_FIRST((head)) = NULL; \
-} while (0)
-
-#define SLIST_INSERT_AFTER(slistelm, elm, field) do { \
- SLIST_NEXT((elm), field) = SLIST_NEXT((slistelm), field); \
- SLIST_NEXT((slistelm), field) = (elm); \
-} while (0)
-
-#define SLIST_INSERT_HEAD(head, elm, field) do { \
- SLIST_NEXT((elm), field) = SLIST_FIRST((head)); \
- SLIST_FIRST((head)) = (elm); \
-} while (0)
-
-#define SLIST_NEXT(elm, field) ((elm)->field.sle_next)
-
-#define SLIST_REMOVE(head, elm, type, field) do { \
- if (SLIST_FIRST((head)) == (elm)) { \
- SLIST_REMOVE_HEAD((head), field); \
- } \
- else { \
- struct type *curelm = SLIST_FIRST((head)); \
- while (SLIST_NEXT(curelm, field) != (elm)) \
- curelm = SLIST_NEXT(curelm, field); \
- SLIST_NEXT(curelm, field) = \
- SLIST_NEXT(SLIST_NEXT(curelm, field), field); \
- } \
-} while (0)
-
-#define SLIST_REMOVE_HEAD(head, field) do { \
- SLIST_FIRST((head)) = SLIST_NEXT(SLIST_FIRST((head)), field); \
-} while (0)
-
-/*
- * Singly-linked Tail queue declarations.
- */
-#define STAILQ_HEAD(name, type) \
-struct name { \
- struct type *stqh_first;/* first element */ \
- struct type **stqh_last;/* addr of last next element */ \
-}
-
-#define STAILQ_HEAD_INITIALIZER(head) \
- { NULL, &(head).stqh_first }
-
-#define STAILQ_ENTRY(type) \
-struct { \
- struct type *stqe_next; /* next element */ \
-}
-
-/*
- * Singly-linked Tail queue functions.
- */
-#define STAILQ_EMPTY(head) ((head)->stqh_first == NULL)
-
-#define STAILQ_FIRST(head) ((head)->stqh_first)
-
-#define STAILQ_FOREACH(var, head, field) \
- for((var) = STAILQ_FIRST((head)); \
- (var); \
- (var) = STAILQ_NEXT((var), field))
-
-#define STAILQ_INIT(head) do { \
- STAILQ_FIRST((head)) = NULL; \
- (head)->stqh_last = &STAILQ_FIRST((head)); \
-} while (0)
-
-#define STAILQ_INSERT_AFTER(head, tqelm, elm, field) do { \
- if ((STAILQ_NEXT((elm), field) = STAILQ_NEXT((tqelm), field)) == NULL)\
- (head)->stqh_last = &STAILQ_NEXT((elm), field); \
- STAILQ_NEXT((tqelm), field) = (elm); \
-} while (0)
-
-#define STAILQ_INSERT_HEAD(head, elm, field) do { \
- if ((STAILQ_NEXT((elm), field) = STAILQ_FIRST((head))) == NULL) \
- (head)->stqh_last = &STAILQ_NEXT((elm), field); \
- STAILQ_FIRST((head)) = (elm); \
-} while (0)
-
-#define STAILQ_INSERT_TAIL(head, elm, field) do { \
- STAILQ_NEXT((elm), field) = NULL; \
- *(head)->stqh_last = (elm); \
- (head)->stqh_last = &STAILQ_NEXT((elm), field); \
-} while (0)
-
-#define STAILQ_LAST(head, type, field) \
- (STAILQ_EMPTY(head) ? \
- NULL : \
- ((struct type *) \
- ((char *)((head)->stqh_last) - __offsetof(struct type, field))))
-
-#define STAILQ_NEXT(elm, field) ((elm)->field.stqe_next)
-
-#define STAILQ_REMOVE(head, elm, type, field) do { \
- if (STAILQ_FIRST((head)) == (elm)) { \
- STAILQ_REMOVE_HEAD(head, field); \
- } \
- else { \
- struct type *curelm = STAILQ_FIRST((head)); \
- while (STAILQ_NEXT(curelm, field) != (elm)) \
- curelm = STAILQ_NEXT(curelm, field); \
- if ((STAILQ_NEXT(curelm, field) = \
- STAILQ_NEXT(STAILQ_NEXT(curelm, field), field)) == NULL)\
- (head)->stqh_last = &STAILQ_NEXT((curelm), field);\
- } \
-} while (0)
-
-#define STAILQ_REMOVE_HEAD(head, field) do { \
- if ((STAILQ_FIRST((head)) = \
- STAILQ_NEXT(STAILQ_FIRST((head)), field)) == NULL) \
- (head)->stqh_last = &STAILQ_FIRST((head)); \
-} while (0)
-
-#define STAILQ_REMOVE_HEAD_UNTIL(head, elm, field) do { \
- if ((STAILQ_FIRST((head)) = STAILQ_NEXT((elm), field)) == NULL) \
- (head)->stqh_last = &STAILQ_FIRST((head)); \
-} while (0)
-
-/*
- * List declarations.
- */
-#define LIST_HEAD(name, type) \
-struct name { \
- struct type *lh_first; /* first element */ \
-}
-
-#define LIST_HEAD_INITIALIZER(head) \
- { NULL }
-
-#define LIST_ENTRY(type) \
-struct { \
- struct type *le_next; /* next element */ \
- struct type **le_prev; /* address of previous next element */ \
-}
-
-/*
- * List functions.
- */
-
-#define LIST_EMPTY(head) ((head)->lh_first == NULL)
-
-#define LIST_FIRST(head) ((head)->lh_first)
-
-#define LIST_FOREACH(var, head, field) \
- for ((var) = LIST_FIRST((head)); \
- (var); \
- (var) = LIST_NEXT((var), field))
-
-#define LIST_INIT(head) do { \
- LIST_FIRST((head)) = NULL; \
-} while (0)
-
-#define LIST_INSERT_AFTER(listelm, elm, field) do { \
- if ((LIST_NEXT((elm), field) = LIST_NEXT((listelm), field)) != NULL)\
- LIST_NEXT((listelm), field)->field.le_prev = \
- &LIST_NEXT((elm), field); \
- LIST_NEXT((listelm), field) = (elm); \
- (elm)->field.le_prev = &LIST_NEXT((listelm), field); \
-} while (0)
-
-#define LIST_INSERT_BEFORE(listelm, elm, field) do { \
- (elm)->field.le_prev = (listelm)->field.le_prev; \
- LIST_NEXT((elm), field) = (listelm); \
- *(listelm)->field.le_prev = (elm); \
- (listelm)->field.le_prev = &LIST_NEXT((elm), field); \
-} while (0)
-
-#define LIST_INSERT_HEAD(head, elm, field) do { \
- if ((LIST_NEXT((elm), field) = LIST_FIRST((head))) != NULL) \
- LIST_FIRST((head))->field.le_prev = &LIST_NEXT((elm), field);\
- LIST_FIRST((head)) = (elm); \
- (elm)->field.le_prev = &LIST_FIRST((head)); \
-} while (0)
-
-#define LIST_NEXT(elm, field) ((elm)->field.le_next)
-
-#define LIST_REMOVE(elm, field) do { \
- if (LIST_NEXT((elm), field) != NULL) \
- LIST_NEXT((elm), field)->field.le_prev = \
- (elm)->field.le_prev; \
- *(elm)->field.le_prev = LIST_NEXT((elm), field); \
-} while (0)
-
-/*
- * Tail queue declarations.
- */
-#define TAILQ_HEAD(name, type) \
-struct name { \
- struct type *tqh_first; /* first element */ \
- struct type **tqh_last; /* addr of last next element */ \
-}
-
-#define TAILQ_HEAD_INITIALIZER(head) \
- { NULL, &(head).tqh_first }
-
-#define TAILQ_ENTRY(type) \
-struct { \
- struct type *tqe_next; /* next element */ \
- struct type **tqe_prev; /* address of previous next element */ \
-}
-
-/*
- * Tail queue functions.
- */
-#define TAILQ_EMPTY(head) ((head)->tqh_first == NULL)
-
-#define TAILQ_FIRST(head) ((head)->tqh_first)
-
-#define TAILQ_FOREACH(var, head, field) \
- for ((var) = TAILQ_FIRST((head)); \
- (var); \
- (var) = TAILQ_NEXT((var), field))
-
-#define TAILQ_FOREACH_REVERSE(var, head, headname, field) \
- for ((var) = TAILQ_LAST((head), headname); \
- (var); \
- (var) = TAILQ_PREV((var), headname, field))
-
-#define TAILQ_INIT(head) do { \
- TAILQ_FIRST((head)) = NULL; \
- (head)->tqh_last = &TAILQ_FIRST((head)); \
-} while (0)
-
-#define TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \
- if ((TAILQ_NEXT((elm), field) = TAILQ_NEXT((listelm), field)) != NULL)\
- TAILQ_NEXT((elm), field)->field.tqe_prev = \
- &TAILQ_NEXT((elm), field); \
- else \
- (head)->tqh_last = &TAILQ_NEXT((elm), field); \
- TAILQ_NEXT((listelm), field) = (elm); \
- (elm)->field.tqe_prev = &TAILQ_NEXT((listelm), field); \
-} while (0)
-
-#define TAILQ_INSERT_BEFORE(listelm, elm, field) do { \
- (elm)->field.tqe_prev = (listelm)->field.tqe_prev; \
- TAILQ_NEXT((elm), field) = (listelm); \
- *(listelm)->field.tqe_prev = (elm); \
- (listelm)->field.tqe_prev = &TAILQ_NEXT((elm), field); \
-} while (0)
-
-#define TAILQ_INSERT_HEAD(head, elm, field) do { \
- if ((TAILQ_NEXT((elm), field) = TAILQ_FIRST((head))) != NULL) \
- TAILQ_FIRST((head))->field.tqe_prev = \
- &TAILQ_NEXT((elm), field); \
- else \
- (head)->tqh_last = &TAILQ_NEXT((elm), field); \
- TAILQ_FIRST((head)) = (elm); \
- (elm)->field.tqe_prev = &TAILQ_FIRST((head)); \
-} while (0)
-
-#define TAILQ_INSERT_TAIL(head, elm, field) do { \
- TAILQ_NEXT((elm), field) = NULL; \
- (elm)->field.tqe_prev = (head)->tqh_last; \
- *(head)->tqh_last = (elm); \
- (head)->tqh_last = &TAILQ_NEXT((elm), field); \
-} while (0)
-
-#define TAILQ_LAST(head, headname) \
- (*(((struct headname *)((head)->tqh_last))->tqh_last))
-
-#define TAILQ_NEXT(elm, field) ((elm)->field.tqe_next)
-
-#define TAILQ_PREV(elm, headname, field) \
- (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last))
-
-#define TAILQ_REMOVE(head, elm, field) do { \
- if ((TAILQ_NEXT((elm), field)) != NULL) \
- TAILQ_NEXT((elm), field)->field.tqe_prev = \
- (elm)->field.tqe_prev; \
- else \
- (head)->tqh_last = (elm)->field.tqe_prev; \
- *(elm)->field.tqe_prev = TAILQ_NEXT((elm), field); \
-} while (0)
-
-/*
- * Circular queue declarations.
- */
-#define CIRCLEQ_HEAD(name, type) \
-struct name { \
- struct type *cqh_first; /* first element */ \
- struct type *cqh_last; /* last element */ \
-}
-
-#define CIRCLEQ_HEAD_INITIALIZER(head) \
- { (void *)&(head), (void *)&(head) }
-
-#define CIRCLEQ_ENTRY(type) \
-struct { \
- struct type *cqe_next; /* next element */ \
- struct type *cqe_prev; /* previous element */ \
-}
-
-/*
- * Circular queue functions.
- */
-#define CIRCLEQ_EMPTY(head) ((head)->cqh_first == (void *)(head))
-
-#define CIRCLEQ_FIRST(head) ((head)->cqh_first)
-
-#define CIRCLEQ_FOREACH(var, head, field) \
- for ((var) = CIRCLEQ_FIRST((head)); \
- (var) != (void *)(head) || ((var) = NULL); \
- (var) = CIRCLEQ_NEXT((var), field))
-
-#define CIRCLEQ_FOREACH_REVERSE(var, head, field) \
- for ((var) = CIRCLEQ_LAST((head)); \
- (var) != (void *)(head) || ((var) = NULL); \
- (var) = CIRCLEQ_PREV((var), field))
-
-#define CIRCLEQ_INIT(head) do { \
- CIRCLEQ_FIRST((head)) = (void *)(head); \
- CIRCLEQ_LAST((head)) = (void *)(head); \
-} while (0)
-
-#define CIRCLEQ_INSERT_AFTER(head, listelm, elm, field) do { \
- CIRCLEQ_NEXT((elm), field) = CIRCLEQ_NEXT((listelm), field); \
- CIRCLEQ_PREV((elm), field) = (listelm); \
- if (CIRCLEQ_NEXT((listelm), field) == (void *)(head)) \
- CIRCLEQ_LAST((head)) = (elm); \
- else \
- CIRCLEQ_PREV(CIRCLEQ_NEXT((listelm), field), field) = (elm);\
- CIRCLEQ_NEXT((listelm), field) = (elm); \
-} while (0)
-
-#define CIRCLEQ_INSERT_BEFORE(head, listelm, elm, field) do { \
- CIRCLEQ_NEXT((elm), field) = (listelm); \
- CIRCLEQ_PREV((elm), field) = CIRCLEQ_PREV((listelm), field); \
- if (CIRCLEQ_PREV((listelm), field) == (void *)(head)) \
- CIRCLEQ_FIRST((head)) = (elm); \
- else \
- CIRCLEQ_NEXT(CIRCLEQ_PREV((listelm), field), field) = (elm);\
- CIRCLEQ_PREV((listelm), field) = (elm); \
-} while (0)
-
-#define CIRCLEQ_INSERT_HEAD(head, elm, field) do { \
- CIRCLEQ_NEXT((elm), field) = CIRCLEQ_FIRST((head)); \
- CIRCLEQ_PREV((elm), field) = (void *)(head); \
- if (CIRCLEQ_LAST((head)) == (void *)(head)) \
- CIRCLEQ_LAST((head)) = (elm); \
- else \
- CIRCLEQ_PREV(CIRCLEQ_FIRST((head)), field) = (elm); \
- CIRCLEQ_FIRST((head)) = (elm); \
-} while (0)
-
-#define CIRCLEQ_INSERT_TAIL(head, elm, field) do { \
- CIRCLEQ_NEXT((elm), field) = (void *)(head); \
- CIRCLEQ_PREV((elm), field) = CIRCLEQ_LAST((head)); \
- if (CIRCLEQ_FIRST((head)) == (void *)(head)) \
- CIRCLEQ_FIRST((head)) = (elm); \
- else \
- CIRCLEQ_NEXT(CIRCLEQ_LAST((head)), field) = (elm); \
- CIRCLEQ_LAST((head)) = (elm); \
-} while (0)
-
-#define CIRCLEQ_LAST(head) ((head)->cqh_last)
-
-#define CIRCLEQ_NEXT(elm,field) ((elm)->field.cqe_next)
-
-#define CIRCLEQ_PREV(elm,field) ((elm)->field.cqe_prev)
-
-#define CIRCLEQ_REMOVE(head, elm, field) do { \
- if (CIRCLEQ_NEXT((elm), field) == (void *)(head)) \
- CIRCLEQ_LAST((head)) = CIRCLEQ_PREV((elm), field); \
- else \
- CIRCLEQ_PREV(CIRCLEQ_NEXT((elm), field), field) = \
- CIRCLEQ_PREV((elm), field); \
- if (CIRCLEQ_PREV((elm), field) == (void *)(head)) \
- CIRCLEQ_FIRST((head)) = CIRCLEQ_NEXT((elm), field); \
- else \
- CIRCLEQ_NEXT(CIRCLEQ_PREV((elm), field), field) = \
- CIRCLEQ_NEXT((elm), field); \
-} while (0)
-
-
-#endif /* !_AVERSIVE_QUEUE_H_ */
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timers.h,v 1.1.2.4 2009-01-23 23:54:16 zer0 Exp $
- *
- */
-
-/*
- * This file contains definitions used for timer use
- *
- * In the future, most of definitions will be added in autogenerated
- * files from atmel's documentation (aversive/parts.h and
- * aversive/parts/ATxxxx.h) which are not timer specific.
- */
-
-/* XXX won't be needed : use parts.h */
-
-#ifndef _AVERSIVE_TIMERS_H_
-#define _AVERSIVE_TIMERS_H_
-
-// Timer WGM bits
-#define TIMER_8_MODE_NORMAL 0
-#define TIMER_8_MODE_PWM_PC 1 // phase correct PWM
-#define TIMER_8_MODE_CTC 2
-#define TIMER_8_MODE_PWM 3 // fast PWM
-
-#define TIMER_16_MODE_NORMAL 0
-#define TIMER_16_MODE_PWM_PC_8 1 // phase correct PWM 8 bits
-#define TIMER_16_MODE_PWM_PC_9 2 // phase correct PWM 9 bits
-#define TIMER_16_MODE_PWM_PC_10 3 // phase correct PWM 10 bits
-#define TIMER_16_MODE_CTC1 4 // clear on compare, TOP = OCRA
-#define TIMER_16_MODE_PWM_8 5 // fast PWM 8 bits
-#define TIMER_16_MODE_PWM_9 6 // fast PWM 9 bits
-#define TIMER_16_MODE_PWM_10 7 // fast PWM 10 bits
-#define TIMER_16_MODE_PWM_PFC1 8 // PWM, Phase & Freq Correct
-#define TIMER_16_MODE_PWM_PFC2 9 // PWM, Phase & Freq Correct
-#define TIMER_16_MODE_PWM_PC1 10 // PWM, Phase Correct
-#define TIMER_16_MODE_PWM_PC2 11 // PWM, Phase Correct
-#define TIMER_16_MODE_CTC2 12 // clear on compare, TOP = ICR
-#define TIMER_16_MODE_PWM_F1 14 // fast PWM
-#define TIMER_16_MODE_PWM_F2 15 // fast PWM
-
-
-// ATMEGA128 ////////////////////////////////////////
-#if defined (__AVR_ATmega128__)
-
-// OCR_BITS
-#define OCR0_DDR DDRB
-#define OCR0_BIT 4
-#define OCR1A_DDR DDRB
-#define OCR1A_BIT 5
-#define OCR1B_DDR DDRB
-#define OCR1B_BIT 6
-#define OCR1C_DDR DDRB
-#define OCR1C_BIT 7
-#define OCR2_DDR DDRB
-#define OCR2_BIT 7
-#define OCR3A_DDR DDRE
-#define OCR3A_BIT 3
-#define OCR3B_DDR DDRE
-#define OCR3B_BIT 4
-#define OCR3C_DDR DDRE
-#define OCR3C_BIT 5
-
-
-
-
-// ATMEGA1281 ////////////////////////////////////////
-#elif defined (__AVR_ATmega1281__)
-
-// OCR_BITS
-#define OCR0A_DDR DDRB
-#define OCR0A_BIT 7
-#define OCR0B_DDR DDRG
-#define OCR0B_BIT 5
-#define OCR1A_DDR DDRB
-#define OCR1A_BIT 5
-#define OCR1B_DDR DDRB
-#define OCR1B_BIT 6
-#define OCR1C_DDR DDRB
-#define OCR1C_BIT 7
-#define OCR2A_DDR DDRB
-#define OCR2A_BIT 4
-#define OCR3A_DDR DDRE
-#define OCR3A_BIT 3
-#define OCR3B_DDR DDRE
-#define OCR3B_BIT 4
-#define OCR3C_DDR DDRE
-#define OCR3C_BIT 5
-
-
-
-// ATMEGA32 ////////////////////////////////////////
-#elif defined (__AVR_ATmega32__) || defined (__AVR_ATmega323__)
-
-#ifdef __AVR_ATmega323__
-
-// renamed bits
-#define WGM20 PWM2
-#define WGM21 CTC2
-
-#define WGM10 PWM10
-#define WGM11 PWM11
-#define WGM12 3//CTC1
-#define WGM13 4 // reserve bit
-
-#define WGM00 PWM0
-#define WGM01 CTC0
-
-#endif // mega323
-
-
-// OCR_BITS
-#define OCR0_DDR DDRB
-#define OCR0_BIT 3
-#define OCR1A_DDR DDRD
-#define OCR1A_BIT 5
-#define OCR1B_DDR DDRD
-#define OCR1B_BIT 4
-#define OCR2_DDR DDRD
-#define OCR2_BIT 7
-
-
-// ATMEGA8 ////////////////////////////////////////
-#elif defined (__AVR_ATmega8__)
-
-// OCR_BITS
-#define OCR1A_DDR DDRB
-#define OCR1A_BIT 1
-#define OCR1B_DDR DDRB
-#define OCR1B_BIT 2
-#define OCR2_DDR DDRB
-#define OCR2_BIT 3
-
-
-
-// ATMEGA163 ////////////////////////////////////////
-#elif defined (__AVR_ATmega163__)
-
-// renamed bits
-#define WGM20 PWM2
-#define WGM21 CTC2
-
-#define WGM10 PWM10
-#define WGM11 PWM11
-#define WGM12 CTC1
-#define WGM13 4 // reserve bit
-
-// OCR_BITS
-#define OCR1A_DDR DDRD
-#define OCR1A_BIT 5
-#define OCR1B_DDR DDRD
-#define OCR1B_BIT 4
-#define OCR2_DDR DDRD
-#define OCR2_BIT 7
-
-
-// ATMEGAx8 ////////////////////////////////////////
-#elif defined (__AVR_ATmega48__) || defined (__AVR_ATmega88__) || defined (__AVR_ATmega168__)
-
-// OCR_BITS
-#define OCR0A_DDR DDRD
-#define OCR0A_BIT 6
-#define OCR0B_DDR DDRD
-#define OCR0B_BIT 5
-
-#define OCR1A_DDR DDRB
-#define OCR1A_BIT 1
-#define OCR1B_DDR DDRB
-#define OCR1B_BIT 2
-
-#define OCR2A_DDR DDRB
-#define OCR2A_BIT 3
-#define OCR2B_DDR DDRD
-#define OCR2B_BIT 3
-
-
-#else
-//#error No timer/prescaler definitions for your AVR type
-#endif
-
-#endif
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timers.h,v 1.1.2.4 2009-01-23 23:54:16 zer0 Exp $
- *
- */
-
-/*
- * This file contains definitions used for timer use
- *
- * In the future, most of definitions will be added in autogenerated
- * files from atmel's documentation (aversive/parts.h and
- * aversive/parts/ATxxxx.h) which are not timer specific.
- */
-
-/* XXX won't be needed : use parts.h */
-
-#ifndef _AVERSIVE_TIMERS_H_
-#define _AVERSIVE_TIMERS_H_
-
-// Timer WGM bits
-#define TIMER_8_MODE_NORMAL 0
-#define TIMER_8_MODE_PWM_PC 1 // phase correct PWM
-#define TIMER_8_MODE_CTC 2
-#define TIMER_8_MODE_PWM 3 // fast PWM
-
-#define TIMER_16_MODE_NORMAL 0
-#define TIMER_16_MODE_PWM_PC_8 1 // phase correct PWM 8 bits
-#define TIMER_16_MODE_PWM_PC_9 2 // phase correct PWM 9 bits
-#define TIMER_16_MODE_PWM_PC_10 3 // phase correct PWM 10 bits
-#define TIMER_16_MODE_CTC1 4 // clear on compare, TOP = OCRA
-#define TIMER_16_MODE_PWM_8 5 // fast PWM 8 bits
-#define TIMER_16_MODE_PWM_9 6 // fast PWM 9 bits
-#define TIMER_16_MODE_PWM_10 7 // fast PWM 10 bits
-#define TIMER_16_MODE_PWM_PFC1 8 // PWM, Phase & Freq Correct
-#define TIMER_16_MODE_PWM_PFC2 9 // PWM, Phase & Freq Correct
-#define TIMER_16_MODE_PWM_PC1 10 // PWM, Phase Correct
-#define TIMER_16_MODE_PWM_PC2 11 // PWM, Phase Correct
-#define TIMER_16_MODE_CTC2 12 // clear on compare, TOP = ICR
-#define TIMER_16_MODE_PWM_F1 14 // fast PWM
-#define TIMER_16_MODE_PWM_F2 15 // fast PWM
-
-
-// ATMEGA128 ////////////////////////////////////////
-#if defined (__AVR_ATmega128__)
-
-// OCR_BITS
-#define OCR0_DDR DDRB
-#define OCR0_BIT 4
-#define OCR1A_DDR DDRB
-#define OCR1A_BIT 5
-#define OCR1B_DDR DDRB
-#define OCR1B_BIT 6
-#define OCR1C_DDR DDRB
-#define OCR1C_BIT 7
-#define OCR2_DDR DDRB
-#define OCR2_BIT 7
-#define OCR3A_DDR DDRE
-#define OCR3A_BIT 3
-#define OCR3B_DDR DDRE
-#define OCR3B_BIT 4
-#define OCR3C_DDR DDRE
-#define OCR3C_BIT 5
-
-
-
-
-// ATMEGA1281 ////////////////////////////////////////
-#elif defined (__AVR_ATmega1281__)
-
-// OCR_BITS
-#define OCR0A_DDR DDRB
-#define OCR0A_BIT 7
-#define OCR0B_DDR DDRG
-#define OCR0B_BIT 5
-#define OCR1A_DDR DDRB
-#define OCR1A_BIT 5
-#define OCR1B_DDR DDRB
-#define OCR1B_BIT 6
-#define OCR1C_DDR DDRB
-#define OCR1C_BIT 7
-#define OCR2A_DDR DDRB
-#define OCR2A_BIT 4
-#define OCR3A_DDR DDRE
-#define OCR3A_BIT 3
-#define OCR3B_DDR DDRE
-#define OCR3B_BIT 4
-#define OCR3C_DDR DDRE
-#define OCR3C_BIT 5
-
-
-
-// ATMEGA32 ////////////////////////////////////////
-#elif defined (__AVR_ATmega32__) || defined (__AVR_ATmega323__)
-
-#ifdef __AVR_ATmega323__
-
-// renamed bits
-#define WGM20 PWM2
-#define WGM21 CTC2
-
-#define WGM10 PWM10
-#define WGM11 PWM11
-#define WGM12 3//CTC1
-#define WGM13 4 // reserve bit
-
-#define WGM00 PWM0
-#define WGM01 CTC0
-
-#endif // mega323
-
-
-// OCR_BITS
-#define OCR0_DDR DDRB
-#define OCR0_BIT 3
-#define OCR1A_DDR DDRD
-#define OCR1A_BIT 5
-#define OCR1B_DDR DDRD
-#define OCR1B_BIT 4
-#define OCR2_DDR DDRD
-#define OCR2_BIT 7
-
-
-// ATMEGA8 ////////////////////////////////////////
-#elif defined (__AVR_ATmega8__)
-
-// OCR_BITS
-#define OCR1A_DDR DDRB
-#define OCR1A_BIT 1
-#define OCR1B_DDR DDRB
-#define OCR1B_BIT 2
-#define OCR2_DDR DDRB
-#define OCR2_BIT 3
-
-
-
-// ATMEGA163 ////////////////////////////////////////
-#elif defined (__AVR_ATmega163__)
-
-// renamed bits
-#define WGM20 PWM2
-#define WGM21 CTC2
-
-#define WGM10 PWM10
-#define WGM11 PWM11
-#define WGM12 CTC1
-#define WGM13 4 // reserve bit
-
-// OCR_BITS
-#define OCR1A_DDR DDRD
-#define OCR1A_BIT 5
-#define OCR1B_DDR DDRD
-#define OCR1B_BIT 4
-#define OCR2_DDR DDRD
-#define OCR2_BIT 7
-
-
-// ATMEGAx8 ////////////////////////////////////////
-#elif defined (__AVR_ATmega48__) || defined (__AVR_ATmega88__) || defined (__AVR_ATmega168__)
-
-// OCR_BITS
-#define OCR0A_DDR DDRD
-#define OCR0A_BIT 6
-#define OCR0B_DDR DDRD
-#define OCR0B_BIT 5
-
-#define OCR1A_DDR DDRB
-#define OCR1A_BIT 1
-#define OCR1B_DDR DDRB
-#define OCR1B_BIT 2
-
-#define OCR2A_DDR DDRB
-#define OCR2A_BIT 3
-#define OCR2B_DDR DDRD
-#define OCR2B_BIT 3
-
-
-#else
-//#error No timer/prescaler definitions for your AVR type
-#endif
-
-#endif
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: types.h,v 1.1.2.1 2007-05-23 17:18:09 zer0 Exp $
- *
- */
-
-#ifndef _AVERSIVE_TYPES_H_
-#define _AVERSIVE_TYPES_H_
-
-#include <inttypes.h>
-
-#define U08_MIN 0x00
-#define U08_MAX 0xFF
-#define U16_MIN 0x0000
-#define U16_MAX 0xFFFF
-#define U32_MIN 0x00000000
-#define U32_MAX 0xFFFFFFFF
-#define U64_MIN 0x0000000000000000
-#define U64_MAX 0xFFFFFFFFFFFFFFFF
-#define S08_MIN 0x80
-#define S08_MAX 0x7F
-#define S16_MIN 0x8000
-#define S16_MAX 0x7FFF
-#define S32_MIN 0x80000000
-#define S32_MAX 0x7FFFFFFF
-#define S64_MIN 0x8000000000000000
-#define S64_MAX 0x7FFFFFFFFFFFFFFF
-
-/* you should use uintXX_t instead of uXX which is more standard */
-
-/* explicit types u = unsigned, s = signed */
-typedef uint8_t u08;
-typedef uint16_t u16;
-typedef uint32_t u32;
-typedef uint64_t u64;
-typedef int8_t s08;
-typedef int16_t s16;
-typedef int32_t s32;
-typedef int64_t s64;
-
-
-#endif /* _AVERSIVE_TYPES_H_ */
+++ /dev/null
-/* \r
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)\r
- * \r
- * This program is free software; you can redistribute it and/or modify\r
- * it under the terms of the GNU General Public License as published by\r
- * the Free Software Foundation; either version 2 of the License, or\r
- * (at your option) any later version.\r
- *\r
- * This program is distributed in the hope that it will be useful,\r
- * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
- * GNU General Public License for more details.\r
- *\r
- * You should have received a copy of the GNU General Public License\r
- * along with this program; if not, write to the Free Software\r
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
- *\r
- * Revision : $Id: wait.h,v 1.1.2.1 2007-05-23 17:18:09 zer0 Exp $\r
- *\r
- */\r
-\r
-/** \r
- * This file is an interface for wait functions, in order to put the \r
- * microcontroller in a loop state.\r
- */\r
-\r
-/**********************************************************/\r
-\r
-#ifndef _AVERSIVE_WAIT_H_\r
-#define _AVERSIVE_WAIT_H_\r
-\r
-#include <aversive.h>\r
-\r
-#ifdef HOST_VERSION\r
-\r
-#include <unistd.h>\r
-\r
-#define wait_3cyc(n) do { volatile int a = 0; a++; } while (0)\r
-#define wait_4cyc(n) do { volatile int a = 0; a++; } while (0)\r
-#define wait_ms(n) host_wait_ms(n)\r
-\r
-#else /* HOST_VERSION */\r
-\r
-#if __AVR_LIBC_VERSION__ < 10403UL\r
-#include <avr/delay.h>\r
-#else\r
-#include <util/delay.h>\r
-#endif\r
-\r
-/** wait n "3 cycles time" \r
- * n is 8 bits */\r
-#define wait_3cyc(n) _delay_loop_1(n)\r
-\r
-/** wait n "4 cycles time" \r
- * n is 16 bits */\r
-#define wait_4cyc(n) _delay_loop_2(n)\r
-\r
-/** wait n milliseconds \r
- * n is 16 bits\r
- */\r
-static inline void wait_ms(uint16_t n) \r
-{\r
- while ( n -- ) \r
- wait_4cyc(F_CPU/4000);\r
-} \r
-\r
-#endif /* else HOST_VERSION */\r
-\r
-#endif /* _AVERSIVE_WAIT_ */\r
+++ /dev/null
-/*
- * Copyright Droids Corporation (2007)
- * Olivier MATZ <zer0@droids-corp.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: cirbuf.c,v 1.1.2.2 2007-09-12 17:52:20 zer0 Exp $
- *
- */
-
-#include <string.h>
-
-#include <cirbuf.h>
-
-
-void
-cirbuf_init(struct cirbuf * cbuf, char * buf, cirbuf_uint start, cirbuf_uint maxlen)
-{
- cbuf->maxlen = maxlen;
- cbuf->len = 0;
- cbuf->start = start;
- cbuf->end = start;
- cbuf->buf = buf;
-}
-
+++ /dev/null
-/*
- * Copyright Droids Corporation (2007)
- * Olivier MATZ <zer0@droids-corp.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: cirbuf.h,v 1.1.2.5 2009-01-03 16:24:50 zer0 Exp $
- *
- *
- */
-
-/**
- * Circular buffer implementation. You should not use a circular buffer
- * size > 127.
- *
- * Funcs are not atomic, so if * necessary, each call should be
- * protected by IRQ_LOCKs.
- */
-
-
-#ifndef _CIRBUF_H_
-#define _CIRBUF_H_
-
-#include <aversive.h>
-#include <stdio.h>
-
-#ifdef CONFIG_MODULE_CIRBUF_LARGE
-typedef signed int cirbuf_int;
-typedef unsigned int cirbuf_uint;
-#else
-typedef signed char cirbuf_int;
-typedef unsigned char cirbuf_uint;
-#endif
-
-/**
- * This structure is the header of a cirbuf type.
- */
-struct cirbuf {
- cirbuf_uint maxlen; /**< total len of the fifo (number of elements) */
- volatile cirbuf_uint start; /**< indice of the first elt */
- volatile cirbuf_uint end; /**< indice of the last elt */
- volatile cirbuf_uint len; /**< current len of fifo */
- char *buf;
-};
-
-/* #define CIRBUF_DEBUG */
-
-#ifdef CIRBUF_DEBUG
-#define dprintf(fmt, ...) printf("line %3.3d - " fmt, __LINE__, ##__VA_ARGS__)
-#else
-#define dprintf(args...) do {} while(0)
-#endif
-
-
-/**
- * Init the circular buffer
- */
-void cirbuf_init(struct cirbuf *cbuf, char *buf, cirbuf_uint start, cirbuf_uint maxlen);
-
-
-/**
- * Return 1 if the circular buffer is full
- */
-#define CIRBUF_IS_FULL(cirbuf) ((cirbuf)->maxlen == (cirbuf)->len)
-
-/**
- * Return 1 if the circular buffer is empty
- */
-#define CIRBUF_IS_EMPTY(cirbuf) ((cirbuf)->len == 0)
-
-/**
- * return current size of the circular buffer (number of used elements)
- */
-#define CIRBUF_GET_LEN(cirbuf) ((cirbuf)->len)
-
-/**
- * return size of the circular buffer (used + free elements)
- */
-#define CIRBUF_GET_MAXLEN(cirbuf) ((cirbuf)->maxlen)
-
-/**
- * return the number of free elts
- */
-#define CIRBUF_GET_FREELEN(cirbuf) ((cirbuf)->maxlen - (cirbuf)->len)
-
-/**
- * Iterator for a circular buffer
- * c: struct cirbuf pointer
- * i: an integer type (cirbuf_uint is enough) internally used in the macro
- * e: char that takes the value for each iteration
- */
-#define CIRBUF_FOREACH(c, i, e) \
- for ( i=0, e=(c)->buf[(c)->start] ; \
- i<((c)->len) ; \
- i ++, e=(c)->buf[((c)->start+i)%((c)->maxlen)])
-
-
-/**
- * Add a character at head of the circular buffer. Return 0 on success, or
- * a negative value on error.
- */
-cirbuf_int cirbuf_add_head_safe(struct cirbuf *cbuf, char c);
-
-/**
- * Add a character at head of the circular buffer. You _must_ check that you
- * have enough free space in the buffer before calling this func.
- */
-void cirbuf_add_head(struct cirbuf *cbuf, char c);
-
-/**
- * Add a character at tail of the circular buffer. Return 0 on success, or
- * a negative value on error.
- */
-cirbuf_int cirbuf_add_tail_safe(struct cirbuf *cbuf, char c);
-
-/**
- * Add a character at tail of the circular buffer. You _must_ check that you
- * have enough free space in the buffer before calling this func.
- */
-void cirbuf_add_tail(struct cirbuf *cbuf, char c);
-
-/**
- * Remove a char at the head of the circular buffer. Return 0 on
- * success, or a negative value on error.
- */
-cirbuf_int cirbuf_del_head_safe(struct cirbuf *cbuf);
-
-/**
- * Remove a char at the head of the circular buffer. You _must_ check
- * that buffer is not empty before calling the function.
- */
-void cirbuf_del_head(struct cirbuf *cbuf);
-
-/**
- * Remove a char at the tail of the circular buffer. Return 0 on
- * success, or a negative value on error.
- */
-cirbuf_int cirbuf_del_tail_safe(struct cirbuf *cbuf);
-
-/**
- * Remove a char at the tail of the circular buffer. You _must_ check
- * that buffer is not empty before calling the function.
- */
-void cirbuf_del_tail(struct cirbuf *cbuf);
-
-/**
- * Return the head of the circular buffer. You _must_ check that
- * buffer is not empty before calling the function.
- */
-char cirbuf_get_head(struct cirbuf *cbuf);
-
-/**
- * Return the tail of the circular buffer. You _must_ check that
- * buffer is not empty before calling the function.
- */
-char cirbuf_get_tail(struct cirbuf *cbuf);
-
-
-
-/**
- * Add a buffer at head of the circular buffer. 'c' is a pointer to a
- * buffer, and n is the number of char to add. Return the number of
- * copied bytes on success, or a negative value on error.
- */
-cirbuf_int cirbuf_add_buf_head(struct cirbuf *cbuf, const char *c, cirbuf_uint n);
-
-/**
- * Add a buffer at tail of the circular buffer. 'c' is a pointer to a
- * buffer, and n is the number of char to add. Return the number of
- * copied bytes on success, or a negative value on error.
- */
-cirbuf_int cirbuf_add_buf_tail(struct cirbuf *cbuf, const char *c, cirbuf_uint n);
-
-/**
- * Remove chars at the head of the circular buffer. Return 0 on
- * success, or a negative value on error.
- */
-cirbuf_int cirbuf_del_buf_head(struct cirbuf *cbuf, cirbuf_uint size);
-
-/**
- * Remove chars at the tail of the circular buffer. Return 0 on
- * success, or a negative value on error.
- */
-cirbuf_int cirbuf_del_buf_tail(struct cirbuf *cbuf, cirbuf_uint size);
-
-/**
- * Copy a maximum of 'size' characters from the head of the circular
- * buffer to a flat one pointed by 'c'. Return the number of copied
- * chars.
- */
-cirbuf_int cirbuf_get_buf_head(struct cirbuf *cbuf, char *c, cirbuf_uint size);
-
-/**
- * Copy a maximum of 'size' characters from the tail of the circular
- * buffer to a flat one pointed by 'c'. Return the number of copied
- * chars.
- */
-cirbuf_int cirbuf_get_buf_tail(struct cirbuf *cbuf, char *c, cirbuf_uint size);
-
-
-/**
- * Set the start of the data to the index 0 of the internal buffer.
- */
-void cirbuf_align_left(struct cirbuf *cbuf);
-
-/**
- * Set the end of the data to the last index of the internal buffer.
- */
-void cirbuf_align_right(struct cirbuf *cbuf);
-
-#endif /* _CIRBUF_H_ */
+++ /dev/null
-/*
- * Copyright Droids Corporation (2007)
- * Olivier MATZ <zer0@droids-corp.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: cirbuf_add_buf_head.c,v 1.1.2.2 2007-09-12 17:52:20 zer0 Exp $
- *
- */
-
-#include <string.h>
-
-#include <cirbuf.h>
-
-
-/* multiple add */
-
-cirbuf_int
-cirbuf_add_buf_head(struct cirbuf * cbuf, const char * c, cirbuf_uint n)
-{
- cirbuf_uint e;
-
- if (!n || n > CIRBUF_GET_FREELEN(cbuf))
- return -EINVAL;
-
- e = CIRBUF_IS_EMPTY(cbuf) ? 1 : 0;
-
- if (n < cbuf->start + e) {
- dprintf("s[%d] -> d[%d] (%d)\n", 0, cbuf->start - n + e, n);
- memcpy(cbuf->buf + cbuf->start - n + e, c, n);
- }
- else {
- dprintf("s[%d] -> d[%d] (%d)\n", + n - (cbuf->start + e), 0, cbuf->start + e);
- dprintf("s[%d] -> d[%d] (%d)\n", cbuf->maxlen - n + (cbuf->start + e), 0, n - (cbuf->start + e));
- memcpy(cbuf->buf, c + n - (cbuf->start + e) , cbuf->start + e);
- memcpy(cbuf->buf + cbuf->maxlen - n + (cbuf->start + e), c, n - (cbuf->start + e));
- }
- cbuf->len += n;
- cbuf->start += (cbuf->maxlen - n + e);
- cbuf->start %= cbuf->maxlen;
- return n;
-}
-
+++ /dev/null
-/*
- * Copyright Droids Corporation (2007)
- * Olivier MATZ <zer0@droids-corp.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: cirbuf_add_buf_tail.c,v 1.1.2.2 2007-09-12 17:52:20 zer0 Exp $
- *
- */
-
-#include <string.h>
-
-#include <cirbuf.h>
-
-
-/* multiple add */
-
-cirbuf_int
-cirbuf_add_buf_tail(struct cirbuf * cbuf, const char * c, cirbuf_uint n)
-{
- cirbuf_uint e;
-
- if (!n || n > CIRBUF_GET_FREELEN(cbuf))
- return -EINVAL;
-
- e = CIRBUF_IS_EMPTY(cbuf) ? 1 : 0;
-
- if (n < cbuf->maxlen - cbuf->end - 1 + e) {
- dprintf("s[%d] -> d[%d] (%d)\n", 0, cbuf->end + !e, n);
- memcpy(cbuf->buf + cbuf->end + !e, c, n);
- }
- else {
- dprintf("s[%d] -> d[%d] (%d)\n", cbuf->end + !e, 0, cbuf->maxlen - cbuf->end - 1 + e);
- dprintf("s[%d] -> d[%d] (%d)\n", cbuf->maxlen - cbuf->end - 1 + e, 0, n - cbuf->maxlen + cbuf->end + 1 - e);
- memcpy(cbuf->buf + cbuf->end + !e, c, cbuf->maxlen - cbuf->end - 1 + e);
- memcpy(cbuf->buf, c + cbuf->maxlen - cbuf->end - 1 + e, n - cbuf->maxlen + cbuf->end + 1 - e);
- }
- cbuf->len += n;
- cbuf->end += n - e;
- cbuf->end %= cbuf->maxlen;
- return n;
-}
-
+++ /dev/null
-/*
- * Copyright Droids Corporation (2007)
- * Olivier MATZ <zer0@droids-corp.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: cirbuf_add_head.c,v 1.1.2.2 2007-09-12 17:52:20 zer0 Exp $
- *
- */
-
-#include <string.h>
-
-#include <cirbuf.h>
-
-
-/* add at head */
-
-static inline void
-__cirbuf_add_head(struct cirbuf * cbuf, char c)
-{
- if (!CIRBUF_IS_EMPTY(cbuf)) {
- cbuf->start += (cbuf->maxlen - 1);
- cbuf->start %= cbuf->maxlen;
- }
- cbuf->buf[cbuf->start] = c;
- cbuf->len ++;
-}
-
-cirbuf_int
-cirbuf_add_head_safe(struct cirbuf * cbuf, char c)
-{
- if (cbuf && !CIRBUF_IS_FULL(cbuf)) {
- __cirbuf_add_head(cbuf, c);
- return 0;
- }
- return -EINVAL;
-}
-
-void
-cirbuf_add_head(struct cirbuf * cbuf, char c)
-{
- __cirbuf_add_head(cbuf, c);
-}
-
+++ /dev/null
-/*
- * Copyright Droids Corporation (2007)
- * Olivier MATZ <zer0@droids-corp.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: cirbuf_add_tail.c,v 1.1.2.2 2007-09-12 17:52:20 zer0 Exp $
- *
- */
-
-#include <string.h>
-
-#include <cirbuf.h>
-
-
-/* add at tail */
-
-
-static inline void
-__cirbuf_add_tail(struct cirbuf * cbuf, char c)
-{
- if (!CIRBUF_IS_EMPTY(cbuf)) {
- cbuf->end ++;
- cbuf->end %= cbuf->maxlen;
- }
- cbuf->buf[cbuf->end] = c;
- cbuf->len ++;
-}
-
-cirbuf_int
-cirbuf_add_tail_safe(struct cirbuf * cbuf, char c)
-{
- if (cbuf && !CIRBUF_IS_FULL(cbuf)) {
- __cirbuf_add_tail(cbuf, c);
- return 0;
- }
- return -EINVAL;
-}
-
-void
-cirbuf_add_tail(struct cirbuf * cbuf, char c)
-{
- __cirbuf_add_tail(cbuf, c);
-}
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation (2007)
- * Olivier MATZ <zer0@droids-corp.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: cirbuf_align.c,v 1.1.2.2 2007-09-12 17:52:20 zer0 Exp $
- *
- */
-
-#include <string.h>
-
-#include <cirbuf.h>
-
-static inline void
-__cirbuf_shift_left(struct cirbuf * cbuf)
-{
- cirbuf_uint i;
- char tmp = cbuf->buf[cbuf->start];
-
- for (i=0 ; i<cbuf->len ; i++) {
- cbuf->buf[(cbuf->start+i)%cbuf->maxlen] =
- cbuf->buf[(cbuf->start+i+1)%cbuf->maxlen];
- }
- cbuf->buf[(cbuf->start-1+cbuf->maxlen)%cbuf->maxlen] = tmp;
- cbuf->start += (cbuf->maxlen - 1);
- cbuf->start %= cbuf->maxlen;
- cbuf->end += (cbuf->maxlen - 1);
- cbuf->end %= cbuf->maxlen;
-}
-
-static inline void
-__cirbuf_shift_right(struct cirbuf * cbuf)
-{
- cirbuf_uint i;
- char tmp = cbuf->buf[cbuf->end];
-
- for (i=0 ; i<cbuf->len ; i++) {
- cbuf->buf[(cbuf->end+cbuf->maxlen-i)%cbuf->maxlen] =
- cbuf->buf[(cbuf->end+cbuf->maxlen-i-1)%cbuf->maxlen];
- }
- cbuf->buf[(cbuf->end+1)%cbuf->maxlen] = tmp;
- cbuf->start += 1;
- cbuf->start %= cbuf->maxlen;
- cbuf->end += 1;
- cbuf->end %= cbuf->maxlen;
-}
-
-/* XXX we could do a better algorithm here... */
-void cirbuf_align_left(struct cirbuf * cbuf)
-{
- if (cbuf->start < cbuf->maxlen/2) {
- while (cbuf->start != 0) {
- __cirbuf_shift_left(cbuf);
- }
- }
- else {
- while (cbuf->start != 0) {
- __cirbuf_shift_right(cbuf);
- }
- }
-}
-
-/* XXX we could do a better algorithm here... */
-void cirbuf_align_right(struct cirbuf * cbuf)
-{
- if (cbuf->start >= cbuf->maxlen/2) {
- while (cbuf->end != cbuf->maxlen-1) {
- __cirbuf_shift_left(cbuf);
- }
- }
- else {
- while (cbuf->start != cbuf->maxlen-1) {
- __cirbuf_shift_right(cbuf);
- }
- }
-}
-
+++ /dev/null
-/*
- * Copyright Droids Corporation (2007)
- * Olivier MATZ <zer0@droids-corp.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: cirbuf_del_buf_head.c,v 1.1.2.3 2007-09-12 17:52:20 zer0 Exp $
- *
- */
-
-#include <string.h>
-
-#include <cirbuf.h>
-
-/* buffer del */
-
-cirbuf_int
-cirbuf_del_buf_head(struct cirbuf * cbuf, cirbuf_uint size)
-{
- if (!size || size > CIRBUF_GET_LEN(cbuf))
- return -EINVAL;
-
- cbuf->len -= size;
- if (CIRBUF_IS_EMPTY(cbuf)) {
- cbuf->start += size - 1;
- cbuf->start %= cbuf->maxlen;
- }
- else {
- cbuf->start += size;
- cbuf->start %= cbuf->maxlen;
- }
- return 0;
-}
+++ /dev/null
-/*
- * Copyright Droids Corporation (2007)
- * Olivier MATZ <zer0@droids-corp.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: cirbuf_del_buf_tail.c,v 1.1.2.3 2007-09-12 17:52:20 zer0 Exp $
- *
- */
-
-#include <string.h>
-
-#include <cirbuf.h>
-
-/* buffer del */
-
-cirbuf_int
-cirbuf_del_buf_tail(struct cirbuf * cbuf, cirbuf_uint size)
-{
- if (!size || size > CIRBUF_GET_LEN(cbuf))
- return -EINVAL;
-
- cbuf->len -= size;
- if (CIRBUF_IS_EMPTY(cbuf)) {
- cbuf->end += (cbuf->maxlen - size + 1);
- cbuf->end %= cbuf->maxlen;
- }
- else {
- cbuf->end += (cbuf->maxlen - size);
- cbuf->end %= cbuf->maxlen;
- }
- return 0;
-}
+++ /dev/null
-/*
- * Copyright Droids Corporation (2007)
- * Olivier MATZ <zer0@droids-corp.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: cirbuf_del_head.c,v 1.1.2.2 2007-09-12 17:52:20 zer0 Exp $
- *
- */
-
-#include <string.h>
-
-#include <cirbuf.h>
-
-/* del at head */
-
-static inline void
-__cirbuf_del_head(struct cirbuf * cbuf)
-{
- cbuf->len --;
- if (!CIRBUF_IS_EMPTY(cbuf)) {
- cbuf->start ++;
- cbuf->start %= cbuf->maxlen;
- }
-}
-
-cirbuf_int
-cirbuf_del_head_safe(struct cirbuf * cbuf)
-{
- if (cbuf && !CIRBUF_IS_EMPTY(cbuf)) {
- __cirbuf_del_head(cbuf);
- return 0;
- }
- return -EINVAL;
-}
-
-void
-cirbuf_del_head(struct cirbuf * cbuf)
-{
- __cirbuf_del_head(cbuf);
-}
-
+++ /dev/null
-/*
- * Copyright Droids Corporation (2007)
- * Olivier MATZ <zer0@droids-corp.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: cirbuf_del_tail.c,v 1.1.2.2 2007-09-12 17:52:20 zer0 Exp $
- *
- */
-
-#include <string.h>
-
-#include <cirbuf.h>
-
-
-/* del at tail */
-
-static inline void
-__cirbuf_del_tail(struct cirbuf * cbuf)
-{
- cbuf->len --;
- if (!CIRBUF_IS_EMPTY(cbuf)) {
- cbuf->end += (cbuf->maxlen - 1);
- cbuf->end %= cbuf->maxlen;
- }
-}
-
-cirbuf_int
-cirbuf_del_tail_safe(struct cirbuf * cbuf)
-{
- if (cbuf && !CIRBUF_IS_EMPTY(cbuf)) {
- __cirbuf_del_tail(cbuf);
- return 0;
- }
- return -EINVAL;
-}
-
-void
-cirbuf_del_tail(struct cirbuf * cbuf)
-{
- __cirbuf_del_tail(cbuf);
-}
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation (2007)
- * Olivier MATZ <zer0@droids-corp.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: cirbuf_get_buf_head.c,v 1.1.2.3 2007-09-12 17:52:20 zer0 Exp $
- *
- */
-
-#include <string.h>
-
-#include <cirbuf.h>
-
-/* convert to buffer */
-
-cirbuf_int
-cirbuf_get_buf_head(struct cirbuf * cbuf, char * c, cirbuf_uint size)
-{
- cirbuf_uint n = (size < CIRBUF_GET_LEN(cbuf)) ? size : CIRBUF_GET_LEN(cbuf);
-
- if (!n)
- return 0;
-
- if (cbuf->start <= cbuf->end) {
- dprintf("s[%d] -> d[%d] (%d)\n", cbuf->start, 0, n);
- memcpy(c, cbuf->buf + cbuf->start , n);
- }
- else {
- dprintf("s[%d] -> d[%d] (%d)\n", cbuf->start, 0, cbuf->maxlen - cbuf->start);
- dprintf("s[%d] -> d[%d] (%d)\n", 0, cbuf->maxlen - cbuf->start, n - cbuf->maxlen + cbuf->start);
- memcpy(c, cbuf->buf + cbuf->start , cbuf->maxlen - cbuf->start);
- memcpy(c + cbuf->maxlen - cbuf->start, cbuf->buf, n - cbuf->maxlen + cbuf->start);
- }
- return n;
-}
-
+++ /dev/null
-/*
- * Copyright Droids Corporation (2007)
- * Olivier MATZ <zer0@droids-corp.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: cirbuf_get_buf_tail.c,v 1.1.2.3 2007-09-12 17:52:20 zer0 Exp $
- *
- */
-
-#include <string.h>
-
-#include <cirbuf.h>
-
-/* convert to buffer */
-
-
-cirbuf_int
-cirbuf_get_buf_tail(struct cirbuf * cbuf, char * c, cirbuf_uint size)
-{
- cirbuf_uint n = (size < CIRBUF_GET_LEN(cbuf)) ? size : CIRBUF_GET_LEN(cbuf);
-
- if (!n)
- return 0;
-
- if (cbuf->start <= cbuf->end) {
- dprintf("s[%d] -> d[%d] (%d)\n", cbuf->end - n + 1, 0, n);
- memcpy(c, cbuf->buf + cbuf->end - n + 1, n);
- }
- else {
- dprintf("s[%d] -> d[%d] (%d)\n", 0, cbuf->maxlen - cbuf->start, cbuf->end + 1);
- dprintf("s[%d] -> d[%d] (%d)\n", cbuf->maxlen - n + cbuf->end + 1, 0, n - cbuf->end - 1);
-
- memcpy(c + cbuf->maxlen - cbuf->start, cbuf->buf, cbuf->end + 1);
- memcpy(c, cbuf->buf + cbuf->maxlen - n + cbuf->end +1, n - cbuf->end - 1);
- }
- return n;
-}
-
+++ /dev/null
-/*
- * Copyright Droids Corporation (2007)
- * Olivier MATZ <zer0@droids-corp.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: cirbuf_get_head.c,v 1.1.2.1 2007-08-19 10:33:55 zer0 Exp $
- *
- */
-
-#include <string.h>
-
-#include <cirbuf.h>
-
-/* get head or get tail */
-
-char
-cirbuf_get_head(struct cirbuf * cbuf)
-{
- return cbuf->buf[cbuf->start];
-}
-
+++ /dev/null
-/*
- * Copyright Droids Corporation (2007)
- * Olivier MATZ <zer0@droids-corp.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: cirbuf_get_tail.c,v 1.1.2.1 2007-08-19 10:33:55 zer0 Exp $
- *
- */
-
-#include <string.h>
-
-#include <cirbuf.h>
-
-/* get head or get tail */
-
-char
-cirbuf_get_tail(struct cirbuf * cbuf)
-{
- return cbuf->buf[cbuf->end];
-}
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: time.h,v 1.3.4.2 2007-05-23 17:18:11 zer0 Exp $
- *
- */
-
-/* Droids-corp, Eirbot, Microb Technology 2005 - Zer0
- * Interface of the time module
- */
-
-/**
- * This module can be used to get a human readable time. It uses the
- * scheduler module. Its goal is not to be very precise, but just
- * simple to use. provides two timers: one in s and us, and one in
- * us which doesn't overflow on seconds (better to substract two
- * times)
- */
-
-#ifndef _CLOCK_TIME_H_
-#define _CLOCK_TIME_H_
-
-#include <aversive.h>
-
-/* a 16 bit variable cannot cover one day */
-typedef int32_t seconds;
-typedef int32_t microseconds;
-
-/** the time structure */
-typedef struct
-{
- microseconds us;
- seconds s;
-} time_h;
-
-
-
-/**********************************************************/
-
-/** init time module : schedule the event with the givent priority */
-void time_init(uint8_t priority);
-
-/**********************************************************/
-
-/** get time in second since last init/reset */
-seconds time_get_s(void);
-
-/**********************************************************/
-
-/** get time in microsecond since last init/reset */
-microseconds time_get_us(void);
-
-/**********************************************************/
-
-/** get the complete time struct since last init/reset */
-time_h time_get_time(void);
-
-/**********************************************************/
-
-/** reset time counter */
-void time_reset(void);
-
-/**********************************************************/
-
-/** set time */
-void time_set(seconds s, microseconds us);
-
-/**********************************************************/
-
-/** This is an equivalent of 'wait_ms(x)', but uses time value, so it
- * is independant of CPU load. Warning, you should not use this
- * function in a irq locked context, or in a scheduled function with
- * higher priority than time module */
-void time_wait_ms(uint16_t ms);
-
-/**********************************************************/
-
-/** get a microsecond timer that overflows naturally */
-microseconds time_get_us2(void);
-
-#endif
#endif
-extern parse_pgm_ctx_t main_ctx[];
+extern const parse_ctx_t PROGMEM main_ctx[];
+
int cmdline_dev_send(char c, FILE* f)
{
+ (void)f;
#ifdef USE_USB
CDC_Device_SendByte(&VirtualSerial1_CDC_Interface, (uint8_t)c);
#else
int cmdline_dev_recv(FILE* f)
{
int16_t c;
+
+ (void)f;
#ifdef USE_USB
/* non-blocking ! */
c = CDC_Device_ReceiveByte(&VirtualSerial1_CDC_Interface);
int xbee_dev_send(char c, FILE* f)
{
+ (void)f;
#ifdef USE_USB
CDC_Device_SendByte(&VirtualSerial2_CDC_Interface, (uint8_t)c);
#else
{
int16_t c;
+ (void)f;
#ifdef USE_USB
/* non-blocking ! */
c = CDC_Device_ReceiveByte(&VirtualSerial2_CDC_Interface);
valid_buffer(const char *buf, uint8_t size)
{
int8_t ret;
+ PGM_P ctx = (PGM_P)main_ctx;
- ret = parse(main_ctx, buf);
+ (void)size;
+ ret = parse(ctx, buf);
if (ret == PARSE_AMBIGUOUS)
printf_P(PSTR("Ambiguous command\r\n"));
else if (ret == PARSE_NOMATCH)
complete_buffer(const char *buf, char *dstbuf, uint8_t dstsize,
int16_t *state)
{
- return complete(main_ctx, buf, state, dstbuf, dstsize);
+ PGM_P ctx = (PGM_P)main_ctx;
+ return complete(ctx, buf, state, dstbuf, dstsize);
}
#include "cmdline.h"
/* commands_gen.c */
-extern parse_pgm_inst_t cmd_reset;
-extern parse_pgm_inst_t cmd_bootloader;
-extern parse_pgm_inst_t cmd_log;
-extern parse_pgm_inst_t cmd_log_show;
-extern parse_pgm_inst_t cmd_log_type;
-extern parse_pgm_inst_t cmd_stack_space;
-extern parse_pgm_inst_t cmd_scheduler;
+extern const parse_inst_t PROGMEM cmd_reset;
+extern const parse_inst_t PROGMEM cmd_bootloader;
+extern const parse_inst_t PROGMEM cmd_log;
+extern const parse_inst_t PROGMEM cmd_log_show;
+extern const parse_inst_t PROGMEM cmd_log_type;
+extern const parse_inst_t PROGMEM cmd_stack_space;
+extern const parse_inst_t PROGMEM cmd_scheduler;
static int monitor_period_ms = 1000;
static int monitor_running = 0;
static void monitor_cb(struct callout_manager *cm,
struct callout *clt, void *dummy)
{
+ (void)clt;
+ (void)dummy;
+
if (monitor_current == NULL)
monitor_current = LIST_FIRST(&xbee_monitor_list);
uint8_t i, mask;
struct rc_proto_range rangepkt;
+ (void)clt;
+ (void)dummy;
+
range_cur_count--;
/* get new xmit power */
/* this structure is filled when cmd_help is parsed successfully */
struct cmd_help_result {
fixed_string_t help;
- struct xbee_atcmd_pgm *cmd;
+ struct xbee_atcmd *cmd;
};
/* function called when cmd_help is parsed successfully */
struct cmd_help_result *res = parsed_result;
struct xbee_atcmd cmdcopy;
int type;
+
+ (void)data;
+
memcpy_P(&cmdcopy, res->cmd, sizeof(cmdcopy));
type = (cmdcopy.flags & (XBEE_ATCMD_F_READ | XBEE_ATCMD_F_WRITE));
switch (type) {
printf_P(PSTR("%S\r\n"), cmdcopy.help);
}
-prog_char str_help_help[] = "help";
+const char PROGMEM str_help_help[] = "help";
-parse_pgm_token_string_t cmd_help_help =
+const parse_token_string_t PROGMEM cmd_help_help =
TOKEN_STRING_INITIALIZER(struct cmd_help_result, help, str_help_help);
-parse_pgm_token_atcmd_t cmd_help_atcmd =
+const parse_token_atcmd_t PROGMEM cmd_help_atcmd =
TOKEN_ATCMD_INITIALIZER(struct cmd_help_result, cmd, &xbee_dev,
0, 0);
-prog_char help_help[] = "Help a register using an AT command";
-parse_pgm_inst_t cmd_help = {
+const char PROGMEM help_help[] = "Help a register using an AT command";
+const parse_inst_t PROGMEM cmd_help = {
.f = cmd_help_parsed, /* function to call */
.data = NULL, /* 2nd arg of func */
.help_str = help_help,
.tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_help_help,
- (prog_void *)&cmd_help_atcmd,
+ (PGM_P)&cmd_help_help,
+ (PGM_P)&cmd_help_atcmd,
NULL,
},
};
void *data)
{
struct cmd_neigh_del_result *res = parsed_result;
+
+ (void)data;
xbee_neigh_del(xbee_dev, res->neigh);
}
-prog_char str_neigh_del_neigh[] = "neigh";
-parse_pgm_token_string_t cmd_neigh_del_cmd =
+const char PROGMEM str_neigh_del_neigh[] = "neigh";
+const parse_token_string_t PROGMEM cmd_neigh_del_cmd =
TOKEN_STRING_INITIALIZER(struct cmd_neigh_del_result, cmd,
str_neigh_del_neigh);
-prog_char str_neigh_del_del[] = "del";
-parse_pgm_token_string_t cmd_neigh_del_action =
+const char PROGMEM str_neigh_del_del[] = "del";
+const parse_token_string_t PROGMEM cmd_neigh_del_action =
TOKEN_STRING_INITIALIZER(struct cmd_neigh_del_result, action,
str_neigh_del_del);
-parse_pgm_token_neighbor_t cmd_neigh_del_neigh =
+const parse_token_neighbor_t PROGMEM cmd_neigh_del_neigh =
TOKEN_NEIGHBOR_INITIALIZER(struct cmd_neigh_del_result, neigh,
&xbee_dev);
-prog_char help_neigh_del[] = "delete a neighbor";
-parse_pgm_inst_t cmd_neigh_del = {
+const char PROGMEM help_neigh_del[] = "delete a neighbor";
+const parse_inst_t PROGMEM cmd_neigh_del = {
.f = cmd_neigh_del_parsed, /* function to call */
.data = NULL, /* 2nd arg of func */
.help_str = help_neigh_del,
.tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_neigh_del_cmd,
- (prog_void *)&cmd_neigh_del_action,
- (prog_void *)&cmd_neigh_del_neigh,
+ (PGM_P)&cmd_neigh_del_cmd,
+ (PGM_P)&cmd_neigh_del_action,
+ (PGM_P)&cmd_neigh_del_neigh,
NULL,
},
};
void *data)
{
struct cmd_neigh_add_result *res = parsed_result;
+
+ (void)data;
if (xbee_neigh_add(xbee_dev, res->name, res->addr) == NULL)
printf_P(PSTR("name or addr already exist\r\n"));
}
-prog_char str_neigh_add_neigh[] = "neigh";
-parse_pgm_token_string_t cmd_neigh_add_cmd =
+const char PROGMEM str_neigh_add_neigh[] = "neigh";
+const parse_token_string_t PROGMEM cmd_neigh_add_cmd =
TOKEN_STRING_INITIALIZER(struct cmd_neigh_add_result, cmd,
str_neigh_add_neigh);
-prog_char str_neigh_add_add[] = "add";
-parse_pgm_token_string_t cmd_neigh_add_action =
+const char PROGMEM str_neigh_add_add[] = "add";
+const parse_token_string_t PROGMEM cmd_neigh_add_action =
TOKEN_STRING_INITIALIZER(struct cmd_neigh_add_result, action,
str_neigh_add_add);
-parse_pgm_token_string_t cmd_neigh_add_name =
+const parse_token_string_t PROGMEM cmd_neigh_add_name =
TOKEN_STRING_INITIALIZER(struct cmd_neigh_add_result, name, NULL);
-parse_pgm_token_num_t cmd_neigh_add_addr =
+const parse_token_num_t PROGMEM cmd_neigh_add_addr =
TOKEN_NUM_INITIALIZER(struct cmd_neigh_add_result, addr, UINT64);
-prog_char help_neigh_add[] = "add a neighbor";
-parse_pgm_inst_t cmd_neigh_add = {
+const char PROGMEM help_neigh_add[] = "add a neighbor";
+const parse_inst_t PROGMEM cmd_neigh_add = {
.f = cmd_neigh_add_parsed, /* function to call */
.data = NULL, /* 2nd arg of func */
.help_str = help_neigh_add,
.tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_neigh_add_cmd,
- (prog_void *)&cmd_neigh_add_action,
- (prog_void *)&cmd_neigh_add_name,
- (prog_void *)&cmd_neigh_add_addr,
+ (PGM_P)&cmd_neigh_add_cmd,
+ (PGM_P)&cmd_neigh_add_action,
+ (PGM_P)&cmd_neigh_add_name,
+ (PGM_P)&cmd_neigh_add_addr,
NULL,
},
};
{
struct xbee_neigh *neigh;
+ (void)parsed_result;
+ (void)data;
LIST_FOREACH(neigh, &xbee_dev->neigh_list, next) {
printf_P(PSTR(" %s: 0x%.8"PRIx32"%.8"PRIx32"\r\n"),
neigh->name,
}
}
-prog_char str_neigh_list_neigh[] = "neigh";
-parse_pgm_token_string_t cmd_neigh_list_cmd =
+const char PROGMEM str_neigh_list_neigh[] = "neigh";
+const parse_token_string_t PROGMEM cmd_neigh_list_cmd =
TOKEN_STRING_INITIALIZER(struct cmd_neigh_list_result, cmd,
str_neigh_list_neigh);
-prog_char str_neigh_list_list[] = "list";
-parse_pgm_token_string_t cmd_neigh_list_action =
+const char PROGMEM str_neigh_list_list[] = "list";
+const parse_token_string_t PROGMEM cmd_neigh_list_action =
TOKEN_STRING_INITIALIZER(struct cmd_neigh_list_result, action,
str_neigh_list_list);
-prog_char help_neigh_list[] = "list all knwon neighbors";
-parse_pgm_inst_t cmd_neigh_list = {
+const char PROGMEM help_neigh_list[] = "list all knwon neighbors";
+const parse_inst_t PROGMEM cmd_neigh_list = {
.f = cmd_neigh_list_parsed, /* function to call */
.data = NULL, /* 2nd arg of func */
.help_str = help_neigh_list,
.tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_neigh_list_cmd,
- (prog_void *)&cmd_neigh_list_action,
+ (PGM_P)&cmd_neigh_list_cmd,
+ (PGM_P)&cmd_neigh_list_action,
NULL,
},
};
/* this structure is filled when cmd_read is parsed successfully */
struct cmd_read_result {
fixed_string_t read;
- struct xbee_atcmd_pgm *cmd;
+ struct xbee_atcmd *cmd;
};
/* function called when cmd_read is parsed successfully */
struct xbee_atcmd copy;
char cmd[3];
+ (void)data;
memcpy_P(©, res->cmd, sizeof(copy));
memcpy_P(&cmd, copy.name, 2);
cmd[2] = '\0';
xbeeapp_send_atcmd(cmd, NULL, 0, 1, NULL, NULL);
}
-prog_char str_read_read[] = "read";
+const char PROGMEM str_read_read[] = "read";
-parse_pgm_token_string_t cmd_read_read =
+const parse_token_string_t PROGMEM cmd_read_read =
TOKEN_STRING_INITIALIZER(struct cmd_read_result, read,
str_read_read);
-parse_pgm_token_atcmd_t cmd_read_atcmd =
+const parse_token_atcmd_t PROGMEM cmd_read_atcmd =
TOKEN_ATCMD_INITIALIZER(struct cmd_read_result, cmd, &xbee_dev,
XBEE_ATCMD_F_READ, XBEE_ATCMD_F_READ);
-prog_char help_read[] = "Read a register using an AT command";
-parse_pgm_inst_t cmd_read = {
+const char PROGMEM help_read[] = "Read a register using an AT command";
+const parse_inst_t PROGMEM cmd_read = {
.f = cmd_read_parsed, /* function to call */
.data = NULL, /* 2nd arg of func */
.help_str = help_read,
.tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_read_read,
- (prog_void *)&cmd_read_atcmd,
+ (PGM_P)&cmd_read_read,
+ (PGM_P)&cmd_read_atcmd,
NULL,
},
};
/* this structure is filled when cmd_write is parsed successfully */
struct cmd_write_result {
fixed_string_t write;
- struct xbee_atcmd_pgm *cmd;
+ struct xbee_atcmd *cmd;
union {
uint8_t u8;
uint16_t u16;
int len;
void *param;
+ (void)data;
memcpy_P(©, res->cmd, sizeof(copy));
if (copy.flags & XBEE_ATCMD_F_PARAM_NONE) {
xbeeapp_send_atcmd(cmd, param, len, 1, NULL, NULL);
}
-prog_char str_write_none[] = "write";
+const char PROGMEM str_write_none[] = "write";
-parse_pgm_token_string_t cmd_write_write =
+const parse_token_string_t PROGMEM cmd_write_write =
TOKEN_STRING_INITIALIZER(struct cmd_write_result, write,
str_write_none);
-parse_pgm_token_atcmd_t cmd_write_none_atcmd =
+const parse_token_atcmd_t PROGMEM cmd_write_none_atcmd =
TOKEN_ATCMD_INITIALIZER(struct cmd_write_result, cmd,
&xbee_dev,
XBEE_ATCMD_F_WRITE | XBEE_ATCMD_F_PARAM_NONE,
XBEE_ATCMD_F_WRITE | XBEE_ATCMD_F_PARAM_NONE);
-prog_char help_write_none[] = "Send an AT command (no argument)";
+const char PROGMEM help_write_none[] = "Send an AT command (no argument)";
-parse_pgm_inst_t cmd_write_none = {
+const parse_inst_t PROGMEM cmd_write_none = {
.f = cmd_write_parsed, /* function to call */
.data = NULL, /* 2nd arg of func */
.help_str = help_write_none,
.tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_write_write,
- (prog_void *)&cmd_write_none_atcmd,
+ (PGM_P)&cmd_write_write,
+ (PGM_P)&cmd_write_none_atcmd,
NULL,
},
};
-parse_pgm_token_atcmd_t cmd_write_u8_atcmd =
+const parse_token_atcmd_t PROGMEM cmd_write_u8_atcmd =
TOKEN_ATCMD_INITIALIZER(struct cmd_write_result, cmd,
&xbee_dev,
XBEE_ATCMD_F_WRITE | XBEE_ATCMD_F_PARAM_U8,
XBEE_ATCMD_F_WRITE | XBEE_ATCMD_F_PARAM_U8);
-parse_pgm_token_num_t cmd_write_u8_u8 =
+const parse_token_num_t PROGMEM cmd_write_u8_u8 =
TOKEN_NUM_INITIALIZER(struct cmd_write_result, u8, UINT8);
-prog_char help_write_u8[] = "Write a 8 bits register using an AT command";
+const char PROGMEM help_write_u8[] = "Write a 8 bits register using an AT command";
-parse_pgm_inst_t cmd_write_u8 = {
+const parse_inst_t PROGMEM cmd_write_u8 = {
.f = cmd_write_parsed, /* function to call */
.data = NULL, /* 2nd arg of func */
.help_str = help_write_u8,
.tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_write_write,
- (prog_void *)&cmd_write_u8_atcmd,
- (prog_void *)&cmd_write_u8_u8,
+ (PGM_P)&cmd_write_write,
+ (PGM_P)&cmd_write_u8_atcmd,
+ (PGM_P)&cmd_write_u8_u8,
NULL,
},
};
-parse_pgm_token_atcmd_t cmd_write_u16_atcmd =
+const parse_token_atcmd_t PROGMEM cmd_write_u16_atcmd =
TOKEN_ATCMD_INITIALIZER(struct cmd_write_result, cmd,
&xbee_dev,
XBEE_ATCMD_F_WRITE | XBEE_ATCMD_F_PARAM_U16,
XBEE_ATCMD_F_WRITE | XBEE_ATCMD_F_PARAM_U16);
-parse_pgm_token_num_t cmd_write_u16_u16 =
+const parse_token_num_t PROGMEM cmd_write_u16_u16 =
TOKEN_NUM_INITIALIZER(struct cmd_write_result, u16, UINT16);
-prog_char help_write_u16[] = "Write a 16 bits register using an AT command";
+const char PROGMEM help_write_u16[] = "Write a 16 bits register using an AT command";
-parse_pgm_inst_t cmd_write_u16 = {
+const parse_inst_t PROGMEM cmd_write_u16 = {
.f = cmd_write_parsed, /* function to call */
.data = NULL, /* 2nd arg of func */
.help_str = help_write_u16,
.tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_write_write,
- (prog_void *)&cmd_write_u16_atcmd,
- (prog_void *)&cmd_write_u16_u16,
+ (PGM_P)&cmd_write_write,
+ (PGM_P)&cmd_write_u16_atcmd,
+ (PGM_P)&cmd_write_u16_u16,
NULL,
},
};
-parse_pgm_token_atcmd_t cmd_write_u32_atcmd =
+const parse_token_atcmd_t PROGMEM cmd_write_u32_atcmd =
TOKEN_ATCMD_INITIALIZER(struct cmd_write_result, cmd,
&xbee_dev,
XBEE_ATCMD_F_WRITE | XBEE_ATCMD_F_PARAM_U32,
XBEE_ATCMD_F_WRITE | XBEE_ATCMD_F_PARAM_U32);
-parse_pgm_token_num_t cmd_write_u32_u32 =
+const parse_token_num_t PROGMEM cmd_write_u32_u32 =
TOKEN_NUM_INITIALIZER(struct cmd_write_result, u32, UINT32);
-prog_char help_write_u32[] = "Write a 32 bits register using an AT command";
+const char PROGMEM help_write_u32[] = "Write a 32 bits register using an AT command";
-parse_pgm_inst_t cmd_write_u32 = {
+const parse_inst_t PROGMEM cmd_write_u32 = {
.f = cmd_write_parsed, /* function to call */
.data = NULL, /* 2nd arg of func */
.help_str = help_write_u32,
.tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_write_write,
- (prog_void *)&cmd_write_u32_atcmd,
- (prog_void *)&cmd_write_u32_u32,
+ (PGM_P)&cmd_write_write,
+ (PGM_P)&cmd_write_u32_atcmd,
+ (PGM_P)&cmd_write_u32_u32,
NULL,
},
};
static void cmd_sendmsg_parsed(void *parsed_result, void *data)
{
struct cmd_sendmsg_result *res = parsed_result;
+
+ (void)data;
xbeeapp_send_msg(res->addr, res->data, strlen(res->data), 1);
}
-prog_char str_sendmsg[] = "sendmsg";
+const char PROGMEM str_sendmsg[] = "sendmsg";
-parse_pgm_token_string_t cmd_sendmsg_sendmsg =
+const parse_token_string_t PROGMEM cmd_sendmsg_sendmsg =
TOKEN_STRING_INITIALIZER(struct cmd_sendmsg_result, sendmsg,
str_sendmsg);
-parse_pgm_token_num_t cmd_sendmsg_addr =
+const parse_token_num_t PROGMEM cmd_sendmsg_addr =
TOKEN_NUM_INITIALIZER(struct cmd_sendmsg_result, addr, UINT64);
-parse_pgm_token_string_t cmd_sendmsg_data =
+const parse_token_string_t PROGMEM cmd_sendmsg_data =
TOKEN_STRING_INITIALIZER(struct cmd_sendmsg_result, data, NULL);
-prog_char help_sendmsg[] = "Send data to a node using its address";
+const char PROGMEM help_sendmsg[] = "Send data to a node using its address";
-parse_pgm_inst_t cmd_sendmsg = {
+const parse_inst_t PROGMEM cmd_sendmsg = {
.f = cmd_sendmsg_parsed, /* function to call */
.data = NULL, /* 2nd arg of func */
.help_str = help_sendmsg,
.tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_sendmsg_sendmsg,
- (prog_void *)&cmd_sendmsg_addr,
- (prog_void *)&cmd_sendmsg_data,
+ (PGM_P)&cmd_sendmsg_sendmsg,
+ (PGM_P)&cmd_sendmsg_addr,
+ (PGM_P)&cmd_sendmsg_data,
NULL,
},
};
static void cmd_sendmsg_name_parsed(void *parsed_result, void *data)
{
struct cmd_sendmsg_name_result *res = parsed_result;
+
+ (void)data;
xbeeapp_send_msg(res->neigh->addr, res->data, strlen(res->data), 1);
}
-parse_pgm_token_string_t cmd_sendmsg_name_sendmsg_name =
+const parse_token_string_t PROGMEM cmd_sendmsg_name_sendmsg_name =
TOKEN_STRING_INITIALIZER(struct cmd_sendmsg_name_result, sendmsg_name,
str_sendmsg);
-parse_pgm_token_neighbor_t cmd_sendmsg_name_neigh =
+const parse_token_neighbor_t PROGMEM cmd_sendmsg_name_neigh =
TOKEN_NEIGHBOR_INITIALIZER(struct cmd_sendmsg_name_result, neigh,
&xbee_dev);
-parse_pgm_token_string_t cmd_sendmsg_name_data =
+const parse_token_string_t PROGMEM cmd_sendmsg_name_data =
TOKEN_STRING_INITIALIZER(struct cmd_sendmsg_name_result, data, NULL);
-prog_char help_sendmsg_name[] = "Send data to a node using its name";
+const char PROGMEM help_sendmsg_name[] = "Send data to a node using its name";
-parse_pgm_inst_t cmd_sendmsg_name = {
+const parse_inst_t PROGMEM cmd_sendmsg_name = {
.f = cmd_sendmsg_name_parsed, /* function to call */
.data = NULL, /* 2nd arg of func */
.help_str = help_sendmsg_name,
.tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_sendmsg_name_sendmsg_name,
- (prog_void *)&cmd_sendmsg_name_neigh,
- (prog_void *)&cmd_sendmsg_name_data,
+ (PGM_P)&cmd_sendmsg_name_sendmsg_name,
+ (PGM_P)&cmd_sendmsg_name_neigh,
+ (PGM_P)&cmd_sendmsg_name_data,
NULL,
},
};
{
struct cmd_range_result *res = parsed_result;
+ (void)data;
if (!strcmp_P(res->action, PSTR("show"))) {
printf_P(PSTR("range infos:\r\n"));
printf_P(PSTR(" range period %d\r\n"), range_period_ms);
}
}
-prog_char str_range[] = "range";
-prog_char str_range_tokens[] = "show#start#end";
+const char PROGMEM str_range[] = "range";
+const char PROGMEM str_range_tokens[] = "show#start#end";
-parse_pgm_token_string_t cmd_range_range =
+const parse_token_string_t PROGMEM cmd_range_range =
TOKEN_STRING_INITIALIZER(struct cmd_range_result, range,
str_range);
-parse_pgm_token_string_t cmd_range_action =
+const parse_token_string_t PROGMEM cmd_range_action =
TOKEN_STRING_INITIALIZER(struct cmd_range_result, action,
str_range_tokens);
-prog_char help_range[] = "start/stop/show current rangeing";
+const char PROGMEM help_range[] = "start/stop/show current rangeing";
-parse_pgm_inst_t cmd_range = {
+const parse_inst_t PROGMEM cmd_range = {
.f = cmd_range_parsed, /* function to call */
.data = NULL, /* 2nd arg of func */
.help_str = help_range,
.tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_range_range,
- (prog_void *)&cmd_range_action,
+ (PGM_P)&cmd_range_range,
+ (PGM_P)&cmd_range_action,
NULL,
},
};
{
struct cmd_range_period_result *res = parsed_result;
+ (void)data;
if (res->period < 10) {
printf_P(PSTR("error, minimum period is 10 ms\r\n"));
return;
range_period_ms = res->period;
}
-prog_char str_period[] = "period";
+const char PROGMEM str_period[] = "period";
-parse_pgm_token_string_t cmd_range_period_range_period =
+const parse_token_string_t PROGMEM cmd_range_period_range_period =
TOKEN_STRING_INITIALIZER(struct cmd_range_period_result, range,
str_range);
-parse_pgm_token_string_t cmd_range_period_action =
+const parse_token_string_t PROGMEM cmd_range_period_action =
TOKEN_STRING_INITIALIZER(struct cmd_range_period_result, action,
str_period);
-parse_pgm_token_num_t cmd_range_period_period =
+const parse_token_num_t PROGMEM cmd_range_period_period =
TOKEN_NUM_INITIALIZER(struct cmd_range_period_result, period, UINT32);
-prog_char help_range_period[] = "set range test period";
+const char PROGMEM help_range_period[] = "set range test period";
-parse_pgm_inst_t cmd_range_period = {
+const parse_inst_t PROGMEM cmd_range_period = {
.f = cmd_range_period_parsed, /* function to call */
.data = NULL, /* 2nd arg of func */
.help_str = help_range_period,
.tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_range_period_range_period,
- (prog_void *)&cmd_range_period_action,
- (prog_void *)&cmd_range_period_period,
+ (PGM_P)&cmd_range_period_range_period,
+ (PGM_P)&cmd_range_period_action,
+ (PGM_P)&cmd_range_period_period,
NULL,
},
};
static void cmd_range_count_parsed(void *parsed_result, void *data)
{
struct cmd_range_count_result *res = parsed_result;
+
+ (void)data;
range_count = res->count;
}
-prog_char str_count[] = "count";
+const char PROGMEM str_count[] = "count";
-parse_pgm_token_string_t cmd_range_count_range_count =
+const parse_token_string_t PROGMEM cmd_range_count_range_count =
TOKEN_STRING_INITIALIZER(struct cmd_range_count_result, range,
str_range);
-parse_pgm_token_string_t cmd_range_count_action =
+const parse_token_string_t PROGMEM cmd_range_count_action =
TOKEN_STRING_INITIALIZER(struct cmd_range_count_result, action,
str_count);
-parse_pgm_token_num_t cmd_range_count_count =
+const parse_token_num_t PROGMEM cmd_range_count_count =
TOKEN_NUM_INITIALIZER(struct cmd_range_count_result, count, UINT32);
-prog_char help_range_count[] = "set range test count";
+const char PROGMEM help_range_count[] = "set range test count";
-parse_pgm_inst_t cmd_range_count = {
+const parse_inst_t PROGMEM cmd_range_count = {
.f = cmd_range_count_parsed, /* function to call */
.data = NULL, /* 2nd arg of func */
.help_str = help_range_count,
.tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_range_count_range_count,
- (prog_void *)&cmd_range_count_action,
- (prog_void *)&cmd_range_count_count,
+ (PGM_P)&cmd_range_count_range_count,
+ (PGM_P)&cmd_range_count_action,
+ (PGM_P)&cmd_range_count_count,
NULL,
},
};
static void cmd_range_powermask_parsed(void *parsed_result, void *data)
{
struct cmd_range_powermask_result *res = parsed_result;
+
+ (void)data;
range_powermask = res->powermask;
}
-prog_char str_powermask[] = "powermask";
+const char PROGMEM str_powermask[] = "powermask";
-parse_pgm_token_string_t cmd_range_powermask_range_powermask =
+const parse_token_string_t PROGMEM cmd_range_powermask_range_powermask =
TOKEN_STRING_INITIALIZER(struct cmd_range_powermask_result, range,
str_range);
-parse_pgm_token_string_t cmd_range_powermask_action =
+const parse_token_string_t PROGMEM cmd_range_powermask_action =
TOKEN_STRING_INITIALIZER(struct cmd_range_powermask_result, action,
str_powermask);
-parse_pgm_token_num_t cmd_range_powermask_powermask =
+const parse_token_num_t PROGMEM cmd_range_powermask_powermask =
TOKEN_NUM_INITIALIZER(struct cmd_range_powermask_result, powermask,
UINT8);
-prog_char help_range_powermask[] = "set range test powermask";
+const char PROGMEM help_range_powermask[] = "set range test powermask";
-parse_pgm_inst_t cmd_range_powermask = {
+const parse_inst_t PROGMEM cmd_range_powermask = {
.f = cmd_range_powermask_parsed, /* function to call */
.data = NULL, /* 2nd arg of func */
.help_str = help_range_powermask,
.tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_range_powermask_range_powermask,
- (prog_void *)&cmd_range_powermask_action,
- (prog_void *)&cmd_range_powermask_powermask,
+ (PGM_P)&cmd_range_powermask_range_powermask,
+ (PGM_P)&cmd_range_powermask_action,
+ (PGM_P)&cmd_range_powermask_powermask,
NULL,
},
};
static void cmd_range_dstaddr_parsed(void *parsed_result, void *data)
{
struct cmd_range_dstaddr_result *res = parsed_result;
+
+ (void)data;
range_dstaddr = res->dstaddr;
}
-prog_char str_dstaddr[] = "dstaddr";
+const char PROGMEM str_dstaddr[] = "dstaddr";
-parse_pgm_token_string_t cmd_range_dstaddr_range_dstaddr =
+const parse_token_string_t PROGMEM cmd_range_dstaddr_range_dstaddr =
TOKEN_STRING_INITIALIZER(struct cmd_range_dstaddr_result, range,
str_range);
-parse_pgm_token_string_t cmd_range_dstaddr_action =
+const parse_token_string_t PROGMEM cmd_range_dstaddr_action =
TOKEN_STRING_INITIALIZER(struct cmd_range_dstaddr_result, action,
str_dstaddr);
-parse_pgm_token_num_t cmd_range_dstaddr_dstaddr =
+const parse_token_num_t PROGMEM cmd_range_dstaddr_dstaddr =
TOKEN_NUM_INITIALIZER(struct cmd_range_dstaddr_result, dstaddr, UINT64);
-prog_char help_range_dstaddr[] = "set register rangeing dstaddr";
+const char PROGMEM help_range_dstaddr[] = "set register rangeing dstaddr";
-parse_pgm_inst_t cmd_range_dstaddr = {
+const parse_inst_t PROGMEM cmd_range_dstaddr = {
.f = cmd_range_dstaddr_parsed, /* function to call */
.data = NULL, /* 2nd arg of func */
.help_str = help_range_dstaddr,
.tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_range_dstaddr_range_dstaddr,
- (prog_void *)&cmd_range_dstaddr_action,
- (prog_void *)&cmd_range_dstaddr_dstaddr,
+ (PGM_P)&cmd_range_dstaddr_range_dstaddr,
+ (PGM_P)&cmd_range_dstaddr_action,
+ (PGM_P)&cmd_range_dstaddr_dstaddr,
NULL,
},
};
struct cmd_monitor_result *res = parsed_result;
struct monitor_reg *m;
+ (void)data;
if (!strcmp_P(res->action, PSTR("show"))) {
printf_P(PSTR("monitor period is %d ms, %d regs in list\r\n"),
monitor_period_ms, monitor_count);
}
}
-prog_char str_monitor[] = "monitor";
-prog_char str_monitor_tokens[] = "show#start#end";
+const char PROGMEM str_monitor[] = "monitor";
+const char PROGMEM str_monitor_tokens[] = "show#start#end";
-parse_pgm_token_string_t cmd_monitor_monitor =
+const parse_token_string_t PROGMEM cmd_monitor_monitor =
TOKEN_STRING_INITIALIZER(struct cmd_monitor_result, monitor,
str_monitor);
-parse_pgm_token_string_t cmd_monitor_action =
+const parse_token_string_t PROGMEM cmd_monitor_action =
TOKEN_STRING_INITIALIZER(struct cmd_monitor_result, action,
str_monitor_tokens);
-prog_char help_monitor[] = "start/stop/show current monitoring";
+const char PROGMEM help_monitor[] = "start/stop/show current monitoring";
-parse_pgm_inst_t cmd_monitor = {
+const parse_inst_t PROGMEM cmd_monitor = {
.f = cmd_monitor_parsed, /* function to call */
.data = NULL, /* 2nd arg of func */
.help_str = help_monitor,
.tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_monitor_monitor,
- (prog_void *)&cmd_monitor_action,
+ (PGM_P)&cmd_monitor_monitor,
+ (PGM_P)&cmd_monitor_action,
NULL,
},
};
struct cmd_monitor_add_result {
fixed_string_t monitor;
fixed_string_t action;
- struct xbee_atcmd_pgm *cmd;
+ struct xbee_atcmd *cmd;
};
/* function called when cmd_monitor_add is parsed successfully */
struct monitor_reg *m;
struct xbee_atcmd copy;
+ (void)data;
memcpy_P(©, res->cmd, sizeof(copy));
LIST_FOREACH(m, &xbee_monitor_list, next) {
if (!strcmp_P(m->atcmd, copy.name))
monitor_count ++;
}
-prog_char str_monitor_add[] = "add";
+const char PROGMEM str_monitor_add[] = "add";
-parse_pgm_token_string_t cmd_monitor_add_monitor_add =
+const parse_token_string_t PROGMEM cmd_monitor_add_monitor_add =
TOKEN_STRING_INITIALIZER(struct cmd_monitor_add_result, monitor,
str_monitor);
-parse_pgm_token_string_t cmd_monitor_add_action =
+const parse_token_string_t PROGMEM cmd_monitor_add_action =
TOKEN_STRING_INITIALIZER(struct cmd_monitor_add_result, action,
str_monitor_add);
-parse_pgm_token_atcmd_t cmd_monitor_add_atcmd =
+const parse_token_atcmd_t PROGMEM cmd_monitor_add_atcmd =
TOKEN_ATCMD_INITIALIZER(struct cmd_monitor_add_result, cmd, &xbee_dev,
XBEE_ATCMD_F_READ, XBEE_ATCMD_F_READ);
-prog_char help_monitor_add[] = "add a register in monitor list";
+const char PROGMEM help_monitor_add[] = "add a register in monitor list";
-parse_pgm_inst_t cmd_monitor_add = {
+const parse_inst_t PROGMEM cmd_monitor_add = {
.f = cmd_monitor_add_parsed, /* function to call */
.data = NULL, /* 2nd arg of func */
.help_str = help_monitor_add,
.tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_monitor_add_monitor_add,
- (prog_void *)&cmd_monitor_add_action,
- (prog_void *)&cmd_monitor_add_atcmd,
+ (PGM_P)&cmd_monitor_add_monitor_add,
+ (PGM_P)&cmd_monitor_add_action,
+ (PGM_P)&cmd_monitor_add_atcmd,
NULL,
},
};
{
struct cmd_monitor_period_result *res = parsed_result;
+ (void)data;
if (res->period < 100) {
printf_P(PSTR("error, minimum period is 100 ms\r\n"));
return;
monitor_period_ms = res->period;
}
-prog_char str_monitor_period[] = "period";
+const char PROGMEM str_monitor_period[] = "period";
-parse_pgm_token_string_t cmd_monitor_period_monitor_period =
+const parse_token_string_t PROGMEM cmd_monitor_period_monitor_period =
TOKEN_STRING_INITIALIZER(struct cmd_monitor_period_result, monitor,
str_monitor);
-parse_pgm_token_string_t cmd_monitor_period_action =
+const parse_token_string_t PROGMEM cmd_monitor_period_action =
TOKEN_STRING_INITIALIZER(struct cmd_monitor_period_result, action,
str_monitor_period);
-parse_pgm_token_num_t cmd_monitor_period_period =
+const parse_token_num_t PROGMEM cmd_monitor_period_period =
TOKEN_NUM_INITIALIZER(struct cmd_monitor_period_result, period, UINT32);
-prog_char help_monitor_period[] = "set register monitoring period";
+const char PROGMEM help_monitor_period[] = "set register monitoring period";
-parse_pgm_inst_t cmd_monitor_period = {
+const parse_inst_t PROGMEM cmd_monitor_period = {
.f = cmd_monitor_period_parsed, /* function to call */
.data = NULL, /* 2nd arg of func */
.help_str = help_monitor_period,
.tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_monitor_period_monitor_period,
- (prog_void *)&cmd_monitor_period_action,
- (prog_void *)&cmd_monitor_period_period,
+ (PGM_P)&cmd_monitor_period_monitor_period,
+ (PGM_P)&cmd_monitor_period_action,
+ (PGM_P)&cmd_monitor_period_period,
NULL,
},
};
{
struct cmd_monitor_del_result *res = parsed_result;
+ (void)data;
monitor_current = LIST_NEXT(res->m, next);
LIST_REMOVE(res->m, next);
free(res->m);
}
}
-prog_char str_monitor_del[] = "del";
+const char PROGMEM str_monitor_del[] = "del";
-parse_pgm_token_string_t cmd_monitor_del_monitor_del =
+const parse_token_string_t PROGMEM cmd_monitor_del_monitor_del =
TOKEN_STRING_INITIALIZER(struct cmd_monitor_del_result, monitor,
str_monitor);
-parse_pgm_token_string_t cmd_monitor_del_action =
+const parse_token_string_t PROGMEM cmd_monitor_del_action =
TOKEN_STRING_INITIALIZER(struct cmd_monitor_del_result, action,
str_monitor_del);
-parse_pgm_token_monitor_t cmd_monitor_del_atcmd =
+const parse_token_monitor_t PROGMEM cmd_monitor_del_atcmd =
TOKEN_MONITOR_INITIALIZER(struct cmd_monitor_del_result, m);
-prog_char help_monitor_del[] = "del a register in monitor list";
+const char PROGMEM help_monitor_del[] = "del a register in monitor list";
-parse_pgm_inst_t cmd_monitor_del = {
+const parse_inst_t PROGMEM cmd_monitor_del = {
.f = cmd_monitor_del_parsed, /* function to call */
.data = NULL, /* 2nd arg of func */
.help_str = help_monitor_del,
.tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_monitor_del_monitor_del,
- (prog_void *)&cmd_monitor_del_action,
- (prog_void *)&cmd_monitor_del_atcmd,
+ (PGM_P)&cmd_monitor_del_monitor_del,
+ (PGM_P)&cmd_monitor_del_action,
+ (PGM_P)&cmd_monitor_del_atcmd,
NULL,
},
};
/* function called when cmd_ping is parsed successfully */
static void cmd_ping_parsed(void *parsed_result, void *data)
{
+ (void)parsed_result;
+ (void)data;
xbeeapp_send_atcmd("VL", NULL, 0, 1, NULL, NULL);
}
-prog_char str_ping[] = "ping";
+const char PROGMEM str_ping[] = "ping";
-parse_pgm_token_string_t cmd_ping_ping =
+const parse_token_string_t PROGMEM cmd_ping_ping =
TOKEN_STRING_INITIALIZER(struct cmd_ping_result, ping,
str_ping);
-prog_char help_ping[] = "Send a ping to the xbee device";
+const char PROGMEM help_ping[] = "Send a ping to the xbee device";
-parse_pgm_inst_t cmd_ping = {
+const parse_inst_t PROGMEM cmd_ping = {
.f = cmd_ping_parsed, /* function to call */
.data = NULL, /* 2nd arg of func */
.help_str = help_ping,
.tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_ping_ping,
+ (PGM_P)&cmd_ping_ping,
NULL,
},
};
/* function called when cmd_raw is parsed successfully */
static void cmd_raw_parsed(void *parsed_result, void *data)
{
+ (void)parsed_result;
+ (void)data;
printf_P(PSTR("switched to raw mode, CTRL-D to exit\r\n"));
rdline_stop(&xbeeboard.rdl); /* don't display prompt when return */
xbee_raw = 1;
}
-prog_char str_raw[] = "raw";
+const char PROGMEM str_raw[] = "raw";
-parse_pgm_token_string_t cmd_raw_raw =
+const parse_token_string_t PROGMEM cmd_raw_raw =
TOKEN_STRING_INITIALIZER(struct cmd_raw_result, raw,
str_raw);
-prog_char help_raw[] = "Switch to raw mode";
+const char PROGMEM help_raw[] = "Switch to raw mode";
-parse_pgm_inst_t cmd_raw = {
+const parse_inst_t PROGMEM cmd_raw = {
.f = cmd_raw_parsed, /* function to call */
.data = NULL, /* 2nd arg of func */
.help_str = help_raw,
.tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_raw_raw,
+ (PGM_P)&cmd_raw_raw,
NULL,
},
};
static void cmd_dump_parsed(void *parsed_result, void *data)
{
struct cmd_dump_result *res = parsed_result;
+
+ (void)data;
if (!strcmp(res->onoff, "on"))
xbee_hexdump = 1;
else
xbee_hexdump = 0;
}
-prog_char str_dump[] = "dump";
-prog_char str_dump_onoff[] = "on#off";
+const char PROGMEM str_dump[] = "dump";
+const char PROGMEM str_dump_onoff[] = "on#off";
-parse_pgm_token_string_t cmd_dump_dump =
+const parse_token_string_t PROGMEM cmd_dump_dump =
TOKEN_STRING_INITIALIZER(struct cmd_dump_result, dump,
str_dump);
-parse_pgm_token_string_t cmd_dump_onoff =
+const parse_token_string_t PROGMEM cmd_dump_onoff =
TOKEN_STRING_INITIALIZER(struct cmd_dump_result, onoff,
str_dump_onoff);
-prog_char help_dump[] = "enable/disable hexdump of received packets";
+const char PROGMEM help_dump[] = "enable/disable hexdump of received packets";
-parse_pgm_inst_t cmd_dump = {
+const parse_inst_t PROGMEM cmd_dump = {
.f = cmd_dump_parsed, /* function to call */
.data = NULL, /* 2nd arg of func */
.help_str = help_dump,
.tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_dump_dump,
- (prog_void *)&cmd_dump_onoff,
+ (PGM_P)&cmd_dump_dump,
+ (PGM_P)&cmd_dump_onoff,
NULL,
},
};
static void cmd_debug_parsed(void *parsed_result, void *data)
{
struct cmd_debug_result *res = parsed_result;
+
+ (void)data;
if (!strcmp(res->onoff, "on"))
xbee_debug = 1;
else
xbee_debug = 0;
}
-prog_char str_debug[] = "debug";
-prog_char str_debug_onoff[] = "on#off";
+const char PROGMEM str_debug[] = "debug";
+const char PROGMEM str_debug_onoff[] = "on#off";
-parse_pgm_token_string_t cmd_debug_debug =
+const parse_token_string_t PROGMEM cmd_debug_debug =
TOKEN_STRING_INITIALIZER(struct cmd_debug_result, debug,
str_debug);
-parse_pgm_token_string_t cmd_debug_onoff =
+const parse_token_string_t PROGMEM cmd_debug_onoff =
TOKEN_STRING_INITIALIZER(struct cmd_debug_result, onoff,
str_debug_onoff);
-prog_char help_debug[] = "enable/disable additionnal debug";
+const char PROGMEM help_debug[] = "enable/disable additionnal debug";
-parse_pgm_inst_t cmd_debug = {
+const parse_inst_t PROGMEM cmd_debug = {
.f = cmd_debug_parsed, /* function to call */
.data = NULL, /* 2nd arg of func */
.help_str = help_debug,
.tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_debug_debug,
- (prog_void *)&cmd_debug_onoff,
+ (PGM_P)&cmd_debug_debug,
+ (PGM_P)&cmd_debug_onoff,
NULL,
},
};
uart_setconf(XBEE_UART, &c);
}
-prog_char str_baudrate_arg0[] = "baudrate";
-parse_pgm_token_string_t cmd_baudrate_arg0 =
+const char PROGMEM str_baudrate_arg0[] = "baudrate";
+const parse_token_string_t PROGMEM cmd_baudrate_arg0 =
TOKEN_STRING_INITIALIZER(struct cmd_baudrate_result, arg0,
str_baudrate_arg0);
-parse_pgm_token_num_t cmd_baudrate_arg1 =
+const parse_token_num_t PROGMEM cmd_baudrate_arg1 =
TOKEN_NUM_INITIALIZER(struct cmd_baudrate_result, arg1,
UINT32);
-prog_char help_baudrate[] = "Change xbee baudrate";
-parse_pgm_inst_t cmd_baudrate = {
+const char PROGMEM help_baudrate[] = "Change xbee baudrate";
+const parse_inst_t PROGMEM cmd_baudrate = {
.f = cmd_baudrate_parsed, /* function to call */
.data = NULL, /* 2nd arg of func */
.help_str = help_baudrate,
.tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_baudrate_arg0,
- (prog_void *)&cmd_baudrate_arg1,
+ (PGM_P)&cmd_baudrate_arg0,
+ (PGM_P)&cmd_baudrate_arg1,
NULL,
},
};
fixed_string_t arg0;
};
-static void cmd_test_spi_parsed(void * parsed_result,
- __attribute__((unused)) void *data)
+static void cmd_test_spi_parsed(void * parsed_result, void *data)
{
int i;
+ (void)parsed_result;
+ (void)data;
while (1) {
for (i = 0; i < 50; i++) {
}
}
-prog_char str_test_spi_arg0[] = "test_spi";
-parse_pgm_token_string_t cmd_test_spi_arg0 =
+const char PROGMEM str_test_spi_arg0[] = "test_spi";
+const parse_token_string_t PROGMEM cmd_test_spi_arg0 =
TOKEN_STRING_INITIALIZER(struct cmd_test_spi_result, arg0,
str_test_spi_arg0);
-prog_char help_test_spi[] = "Test the spi";
-parse_pgm_inst_t cmd_test_spi = {
+const char PROGMEM help_test_spi[] = "Test the spi";
+const parse_inst_t PROGMEM cmd_test_spi = {
.f = cmd_test_spi_parsed, /* function to call */
.data = NULL, /* 2nd arg of func */
.help_str = help_test_spi,
.tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_test_spi_arg0,
+ (PGM_P)&cmd_test_spi_arg0,
NULL,
},
};
/* in progmem */
-parse_pgm_ctx_t main_ctx[] = {
+const parse_ctx_t PROGMEM main_ctx[] = {
/* commands_gen.c */
- (parse_pgm_inst_t *)&cmd_reset,
- (parse_pgm_inst_t *)&cmd_bootloader,
- (parse_pgm_inst_t *)&cmd_log,
- (parse_pgm_inst_t *)&cmd_log_show,
- (parse_pgm_inst_t *)&cmd_log_type,
- (parse_pgm_inst_t *)&cmd_stack_space,
- (parse_pgm_inst_t *)&cmd_scheduler,
- (parse_pgm_inst_t *)&cmd_help,
- (parse_pgm_inst_t *)&cmd_neigh_del,
- (parse_pgm_inst_t *)&cmd_neigh_add,
- (parse_pgm_inst_t *)&cmd_neigh_list,
- (parse_pgm_inst_t *)&cmd_read,
- (parse_pgm_inst_t *)&cmd_write_none,
- (parse_pgm_inst_t *)&cmd_write_u8,
- (parse_pgm_inst_t *)&cmd_write_u16,
- (parse_pgm_inst_t *)&cmd_write_u32,
- (parse_pgm_inst_t *)&cmd_sendmsg,
- (parse_pgm_inst_t *)&cmd_sendmsg_name,
- (parse_pgm_inst_t *)&cmd_range,
- (parse_pgm_inst_t *)&cmd_range_period,
- (parse_pgm_inst_t *)&cmd_range_count,
- (parse_pgm_inst_t *)&cmd_range_powermask,
- (parse_pgm_inst_t *)&cmd_range_dstaddr,
- (parse_pgm_inst_t *)&cmd_monitor,
- (parse_pgm_inst_t *)&cmd_monitor_period,
- (parse_pgm_inst_t *)&cmd_monitor_add,
- (parse_pgm_inst_t *)&cmd_monitor_del,
- (parse_pgm_inst_t *)&cmd_ping,
- (parse_pgm_inst_t *)&cmd_raw,
- (parse_pgm_inst_t *)&cmd_dump,
- (parse_pgm_inst_t *)&cmd_debug,
+ &cmd_reset,
+ &cmd_bootloader,
+ &cmd_log,
+ &cmd_log_show,
+ &cmd_log_type,
+ &cmd_stack_space,
+ &cmd_scheduler,
+ &cmd_help,
+ &cmd_neigh_del,
+ &cmd_neigh_add,
+ &cmd_neigh_list,
+ &cmd_read,
+ &cmd_write_none,
+ &cmd_write_u8,
+ &cmd_write_u16,
+ &cmd_write_u32,
+ &cmd_sendmsg,
+ &cmd_sendmsg_name,
+ &cmd_range,
+ &cmd_range_period,
+ &cmd_range_count,
+ &cmd_range_powermask,
+ &cmd_range_dstaddr,
+ &cmd_monitor,
+ &cmd_monitor_period,
+ &cmd_monitor_add,
+ &cmd_monitor_del,
+ &cmd_ping,
+ &cmd_raw,
+ &cmd_dump,
+ &cmd_debug,
#ifndef USE_USB
- (parse_pgm_inst_t *)&cmd_baudrate,
+ &cmd_baudrate,
#endif
- (parse_pgm_inst_t *)&cmd_test_spi,
+ &cmd_test_spi,
NULL,
};
+++ /dev/null
-/*
- * Copyright (c) 2009, Olivier MATZ <zer0@droids-corp.org>
- * All rights reserved.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the University of California, Berkeley nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY
- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE REGENTS AND CONTRIBUTORS BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <stdio.h>
-#include <stdint.h>
-#include <string.h>
-#include <stdlib.h>
-#include <stdarg.h>
-#include <errno.h>
-#include <ctype.h>
-#include <sys/queue.h>
-#include <arpa/inet.h>
-#include <inttypes.h>
-
-#include <event.h>
-
-#include <cmdline_parse.h>
-#include <cmdline_parse_num.h>
-#include <cmdline_parse_string.h>
-#include <cmdline_parse_file.h>
-#include <cmdline.h>
-
-#include "xbee_neighbor.h"
-#include "xbee_atcmd.h"
-#include "xbee_stats.h"
-#include "xbee_buf.h"
-#include "xbee_proto.h"
-#include "xbee.h"
-#include "parse_atcmd.h"
-#include "parse_neighbor.h"
-#include "parse_monitor.h"
-#include "main.h"
-
-static struct monitor_reg_list monitor_list = LIST_HEAD_INITIALIZER(x/*XXX*/);
-static int monitor_period_ms = 1000;
-static int monitor_running = 0;
-static int monitor_count = 0;
-static struct event monitor_event;
-struct monitor_reg *monitor_current;
-
-static int range_period_ms = 1000;
-static int range_powermask = 0x1F;
-static uint8_t range_power = 0;
-static int range_running = 0;
-static uint64_t range_dstaddr = 0xFFFF; /* broadcast by default */
-static struct event range_event;
-static int range_count = 100;
-static int range_cur_count = 0;
-
-static const char *xbee_logfilename = "/tmp/xbee.log";
-
-static void monitor_cb(int s, short event, void *arg)
-{
- struct timeval tv;
- struct cmdline *cl = arg;
-
- if (monitor_current == NULL)
- monitor_current = LIST_FIRST(&monitor_list);
-
- xbeeapp_send_atcmd(monitor_current->atcmd, NULL, 0, 0);
- monitor_current = LIST_NEXT(monitor_current, next);
-
- evtimer_set(&monitor_event, monitor_cb, cl);
- tv.tv_sec = 0;
- tv.tv_usec = (1000 * monitor_period_ms) / monitor_count;
- evtimer_add(&monitor_event, &tv);
-}
-
-static void range_cb(int s, short event, void *arg)
-{
- struct timeval tv;
- struct cmdline *cl = arg;
- char buf[16];
- uint8_t i, mask;
-
- range_cur_count--;
-
- /* get new xmit power */
- for (i = 1; i <= 8; i++) {
- mask = 1 << ((range_power + i) & 0x7);
- if (mask & range_powermask)
- break;
- }
- range_power = ((range_power + i) & 0x7);
-
- xbeeapp_send_atcmd("PL", &range_power, sizeof(range_power), 0, NULL, NULL);
- snprintf(buf, sizeof(buf), "range%d", range_power);
- xbeeapp_send_msg(range_dstaddr, buf, strlen(buf), 0);
-
- if (range_cur_count == 0) {
- range_running = 0;
- return;
- }
-
- evtimer_set(&range_event, range_cb, cl);
- tv.tv_sec = 0;
- tv.tv_usec = 1000 * range_period_ms;
- evtimer_add(&range_event, &tv);
-}
-
-/* ************* */
-
-/* this structure is filled when cmd_stats is parsed successfully */
-struct cmd_stats_result {
- fixed_string_t stats;
- fixed_string_t action;
-};
-
-/* function called when cmd_stats is parsed successfully */
-static void cmd_stats_parsed(void *parsed_result, struct cmdline *cl, void *data)
-{
- struct cmd_stats_result *res = parsed_result;
-
- if (!strcmp(res->action, "show")) {
- xbee_dump_stats(stdout, xbee_dev);
- if (xbee_logfile != NULL)
- xbee_dump_stats(xbee_logfile, xbee_dev);
- }
- else if (!strcmp(res->action, "reset"))
- xbee_reset_stats(xbee_dev);
-}
-
-parse_pgm_token_string_t cmd_stats_stats =
- TOKEN_STRING_INITIALIZER(struct cmd_stats_result, stats, "stats");
-parse_pgm_token_string_t cmd_stats_action =
- TOKEN_STRING_INITIALIZER(struct cmd_stats_result, action, "show#reset");
-
-parse_pgm_inst_t cmd_stats = {
- .f = cmd_stats_parsed, /* function to call */
- .data = NULL, /* 2nd arg of func */
- .help_str = "Send a stats to the xbee device",
- .tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_stats_stats,
- (prog_void *)&cmd_stats_action,
- NULL,
- },
-};
-
-/* ************* */
-
-/* this structure is filled when cmd_monitor is parsed successfully */
-struct cmd_monitor_result {
- fixed_string_t monitor;
- fixed_string_t action;
-};
-
-/* function called when cmd_monitor is parsed successfully */
-static void cmd_monitor_parsed(void *parsed_result, struct cmdline *cl,
- void *data)
-{
- struct cmd_monitor_result *res = parsed_result;
- struct monitor_reg *m;
-
- if (!strcmp(res->action, "show")) {
- printf("monitor period is %d ms, %d regs in list\n",
- monitor_period_ms, monitor_count);
- LIST_FOREACH(m, &monitor_list, next)
- printf(" %s\n", m->desc);
- }
- else if (!strcmp(res->action, "start")) {
- struct timeval tv;
- if (monitor_running) {
- printf("already running\n");
- return;
- }
- if (monitor_count == 0) {
- printf("no regs to be monitored\n");
- return;
- }
- evtimer_set(&monitor_event, monitor_cb, cl);
- tv.tv_sec = 0;
- tv.tv_usec = 0;
- evtimer_add(&monitor_event, &tv);
- monitor_running = 1;
- monitor_current = LIST_FIRST(&monitor_list);
- }
- else if (!strcmp(res->action, "end")) {
- if (monitor_running == 0) {
- printf("not running\n");
- return;
- }
- monitor_running = 0;
- evtimer_del(&monitor_event);
- }
-}
-
-parse_pgm_token_string_t cmd_monitor_monitor =
- TOKEN_STRING_INITIALIZER(struct cmd_monitor_result, monitor, "monitor");
-parse_pgm_token_string_t cmd_monitor_action =
- TOKEN_STRING_INITIALIZER(struct cmd_monitor_result, action,
- "show#start#end");
-
-parse_pgm_inst_t cmd_monitor = {
- .f = cmd_monitor_parsed, /* function to call */
- .data = NULL, /* 2nd arg of func */
- .help_str = "start/stop/show current monitoring",
- .tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_monitor_monitor,
- (prog_void *)&cmd_monitor_action,
- NULL,
- },
-};
-
-/* ************* */
-
-/* this structure is filled when cmd_monitor_add is parsed successfully */
-struct cmd_monitor_add_result {
- fixed_string_t monitor;
- fixed_string_t action;
- struct xbee_atcmd *cmd;
-};
-
-/* function called when cmd_monitor_add is parsed successfully */
-static void cmd_monitor_add_parsed(void *parsed_result, struct cmdline *cl,
- void *data)
-{
- struct cmd_monitor_add_result *res = parsed_result;
- struct monitor_reg *m;
-
- LIST_FOREACH(m, &monitor_list, next) {
- if (!strcmp(m->desc, res->cmd->desc))
- break;
- }
-
- if (m != NULL) {
- printf("already exist\n");
- return;
- }
-
- m = malloc(sizeof(*m));
- if (m == NULL) {
- printf("no mem\n");
- return;
- }
-
- m->desc = res->cmd->desc;
- m->atcmd = res->cmd->name;
- LIST_INSERT_HEAD(&monitor_list, m, next);
- monitor_count ++;
-}
-
-parse_pgm_token_string_t cmd_monitor_add_monitor_add =
- TOKEN_STRING_INITIALIZER(struct cmd_monitor_add_result, monitor,
- "monitor");
-parse_pgm_token_string_t cmd_monitor_add_action =
- TOKEN_STRING_INITIALIZER(struct cmd_monitor_add_result, action,
- "add");
-parse_pgm_token_atcmd_t cmd_monitor_add_atcmd =
- TOKEN_ATCMD_INITIALIZER(struct cmd_monitor_add_result, cmd, &xbee_dev,
- XBEE_ATCMD_F_READ, XBEE_ATCMD_F_READ);
-
-
-parse_pgm_inst_t cmd_monitor_add = {
- .f = cmd_monitor_add_parsed, /* function to call */
- .data = NULL, /* 2nd arg of func */
- .help_str = "add a register in monitor list",
- .tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_monitor_add_monitor_add,
- (prog_void *)&cmd_monitor_add_action,
- (prog_void *)&cmd_monitor_add_atcmd,
- NULL,
- },
-};
-
-/* ************* */
-
-/* this structure is filled when cmd_monitor_period is parsed successfully */
-struct cmd_monitor_period_result {
- fixed_string_t monitor;
- fixed_string_t action;
- uint32_t period;
-};
-
-/* function called when cmd_monitor_period is parsed successfully */
-static void cmd_monitor_period_parsed(void *parsed_result, struct cmdline *cl,
- void *data)
-{
- struct cmd_monitor_period_result *res = parsed_result;
-
- if (res->period < 100) {
- printf("error, minimum period is 100 ms\n");
- return;
- }
-
- monitor_period_ms = res->period;
-}
-
-parse_pgm_token_string_t cmd_monitor_period_monitor_period =
- TOKEN_STRING_INITIALIZER(struct cmd_monitor_period_result, monitor,
- "monitor");
-parse_pgm_token_string_t cmd_monitor_period_action =
- TOKEN_STRING_INITIALIZER(struct cmd_monitor_period_result, action,
- "period");
-parse_pgm_token_num_t cmd_monitor_period_period =
- TOKEN_NUM_INITIALIZER(struct cmd_monitor_period_result, period, UINT32);
-
-
-parse_pgm_inst_t cmd_monitor_period = {
- .f = cmd_monitor_period_parsed, /* function to call */
- .data = NULL, /* 2nd arg of func */
- .help_str = "set register monitoring period",
- .tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_monitor_period_monitor_period,
- (prog_void *)&cmd_monitor_period_action,
- (prog_void *)&cmd_monitor_period_period,
- NULL,
- },
-};
-
-/* ************* */
-
-/* this structure is filled when cmd_monitor_del is parsed successfully */
-struct cmd_monitor_del_result {
- fixed_string_t monitor;
- fixed_string_t action;
- struct monitor_reg *m;
-};
-
-/* function called when cmd_monitor_del is parsed successfully */
-static void cmd_monitor_del_parsed(void *parsed_result, struct cmdline *cl,
- void *data)
-{
- struct cmd_monitor_del_result *res = parsed_result;
-
- monitor_current = LIST_NEXT(res->m, next);
- LIST_REMOVE(res->m, next);
- free(res->m);
- monitor_count --;
- if (monitor_count == 0) {
- printf("Disable monitoring, no more event\n");
- evtimer_del(&monitor_event);
- monitor_running = 0;
- return;
- }
-}
-
-parse_pgm_token_string_t cmd_monitor_del_monitor_del =
- TOKEN_STRING_INITIALIZER(struct cmd_monitor_del_result, monitor,
- "monitor");
-parse_pgm_token_string_t cmd_monitor_del_action =
- TOKEN_STRING_INITIALIZER(struct cmd_monitor_del_result, action,
- "del");
-parse_pgm_token_monitor_t cmd_monitor_del_atcmd =
- TOKEN_MONITOR_INITIALIZER(struct cmd_monitor_del_result, m,
- &monitor_list);
-
-
-parse_pgm_inst_t cmd_monitor_del = {
- .f = cmd_monitor_del_parsed, /* function to call */
- .data = NULL, /* 2nd arg of func */
- .help_str = "del a register in monitor list",
- .tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_monitor_del_monitor_del,
- (prog_void *)&cmd_monitor_del_action,
- (prog_void *)&cmd_monitor_del_atcmd,
- NULL,
- },
-};
-
-/* ************* */
-
-/* this structure is filled when cmd_range is parsed successfully */
-struct cmd_range_result {
- fixed_string_t range;
- fixed_string_t action;
-};
-
-/* function called when cmd_range is parsed successfully */
-static void cmd_range_parsed(void *parsed_result, struct cmdline *cl,
- void *data)
-{
- struct cmd_range_result *res = parsed_result;
-
- if (!strcmp(res->action, "show")) {
- printf("range infos:\n");
- printf(" range period %d\n", range_period_ms);
- printf(" range count %d\n", range_count);
- printf(" range powermask 0x%x\n", range_powermask);
- printf(" range dstaddr %"PRIx64"\n", range_dstaddr);
- if (range_running)
- printf(" range test is running\n");
- else
- printf(" range test is not running\n");
- }
- else if (!strcmp(res->action, "start")) {
- struct timeval tv;
- if (range_running) {
- printf("already running\n");
- return;
- }
- range_cur_count = range_count;
- evtimer_set(&range_event, range_cb, cl);
- tv.tv_sec = 0;
- tv.tv_usec = 0;
- evtimer_add(&range_event, &tv);
- range_running = 1;
- }
- else if (!strcmp(res->action, "end")) {
- if (range_running == 0) {
- printf("not running\n");
- return;
- }
- range_running = 0;
- evtimer_del(&range_event);
- }
-}
-
-parse_pgm_token_string_t cmd_range_range =
- TOKEN_STRING_INITIALIZER(struct cmd_range_result, range, "range");
-parse_pgm_token_string_t cmd_range_action =
- TOKEN_STRING_INITIALIZER(struct cmd_range_result, action,
- "show#start#end");
-
-parse_pgm_inst_t cmd_range = {
- .f = cmd_range_parsed, /* function to call */
- .data = NULL, /* 2nd arg of func */
- .help_str = "start/stop/show current rangeing",
- .tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_range_range,
- (prog_void *)&cmd_range_action,
- NULL,
- },
-};
-
-/* ************* */
-
-/* this structure is filled when cmd_range_period is parsed successfully */
-struct cmd_range_period_result {
- fixed_string_t range;
- fixed_string_t action;
- uint32_t period;
-};
-
-/* function called when cmd_range_period is parsed successfully */
-static void cmd_range_period_parsed(void *parsed_result, struct cmdline *cl,
- void *data)
-{
- struct cmd_range_period_result *res = parsed_result;
-
- if (res->period < 10) {
- printf("error, minimum period is 10 ms\n");
- return;
- }
-
- range_period_ms = res->period;
-}
-
-parse_pgm_token_string_t cmd_range_period_range_period =
- TOKEN_STRING_INITIALIZER(struct cmd_range_period_result, range,
- "range");
-parse_pgm_token_string_t cmd_range_period_action =
- TOKEN_STRING_INITIALIZER(struct cmd_range_period_result, action,
- "period");
-parse_pgm_token_num_t cmd_range_period_period =
- TOKEN_NUM_INITIALIZER(struct cmd_range_period_result, period, UINT32);
-
-
-parse_pgm_inst_t cmd_range_period = {
- .f = cmd_range_period_parsed, /* function to call */
- .data = NULL, /* 2nd arg of func */
- .help_str = "set range test period",
- .tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_range_period_range_period,
- (prog_void *)&cmd_range_period_action,
- (prog_void *)&cmd_range_period_period,
- NULL,
- },
-};
-
-/* ************* */
-
-/* this structure is filled when cmd_range_count is parsed successfully */
-struct cmd_range_count_result {
- fixed_string_t range;
- fixed_string_t action;
- uint32_t count;
-};
-
-/* function called when cmd_range_count is parsed successfully */
-static void cmd_range_count_parsed(void *parsed_result, struct cmdline *cl,
- void *data)
-{
- struct cmd_range_count_result *res = parsed_result;
- range_count = res->count;
-}
-
-parse_pgm_token_string_t cmd_range_count_range_count =
- TOKEN_STRING_INITIALIZER(struct cmd_range_count_result, range,
- "range");
-parse_pgm_token_string_t cmd_range_count_action =
- TOKEN_STRING_INITIALIZER(struct cmd_range_count_result, action,
- "count");
-parse_pgm_token_num_t cmd_range_count_count =
- TOKEN_NUM_INITIALIZER(struct cmd_range_count_result, count, UINT32);
-
-
-parse_pgm_inst_t cmd_range_count = {
- .f = cmd_range_count_parsed, /* function to call */
- .data = NULL, /* 2nd arg of func */
- .help_str = "set range test count",
- .tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_range_count_range_count,
- (prog_void *)&cmd_range_count_action,
- (prog_void *)&cmd_range_count_count,
- NULL,
- },
-};
-
-/* ************* */
-
-/* this structure is filled when cmd_range_powermask is parsed successfully */
-struct cmd_range_powermask_result {
- fixed_string_t range;
- fixed_string_t action;
- uint8_t powermask;
-};
-
-/* function called when cmd_range_powermask is parsed successfully */
-static void cmd_range_powermask_parsed(void *parsed_result, struct cmdline *cl,
- void *data)
-{
- struct cmd_range_powermask_result *res = parsed_result;
- range_powermask = res->powermask;
-}
-
-parse_pgm_token_string_t cmd_range_powermask_range_powermask =
- TOKEN_STRING_INITIALIZER(struct cmd_range_powermask_result, range,
- "range");
-parse_pgm_token_string_t cmd_range_powermask_action =
- TOKEN_STRING_INITIALIZER(struct cmd_range_powermask_result, action,
- "powermask");
-parse_pgm_token_num_t cmd_range_powermask_powermask =
- TOKEN_NUM_INITIALIZER(struct cmd_range_powermask_result, powermask,
- UINT8);
-
-
-parse_pgm_inst_t cmd_range_powermask = {
- .f = cmd_range_powermask_parsed, /* function to call */
- .data = NULL, /* 2nd arg of func */
- .help_str = "set range test powermask",
- .tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_range_powermask_range_powermask,
- (prog_void *)&cmd_range_powermask_action,
- (prog_void *)&cmd_range_powermask_powermask,
- NULL,
- },
-};
-
-/* ************* */
-
-/* this structure is filled when cmd_range_dstaddr is parsed successfully */
-struct cmd_range_dstaddr_result {
- fixed_string_t range;
- fixed_string_t action;
- uint64_t dstaddr;
-};
-
-/* function called when cmd_range_dstaddr is parsed successfully */
-static void cmd_range_dstaddr_parsed(void *parsed_result, struct cmdline *cl,
- void *data)
-{
- struct cmd_range_dstaddr_result *res = parsed_result;
-
- range_dstaddr = res->dstaddr;
-}
-
-parse_pgm_token_string_t cmd_range_dstaddr_range_dstaddr =
- TOKEN_STRING_INITIALIZER(struct cmd_range_dstaddr_result, range,
- "range");
-parse_pgm_token_string_t cmd_range_dstaddr_action =
- TOKEN_STRING_INITIALIZER(struct cmd_range_dstaddr_result, action,
- "dstaddr");
-parse_pgm_token_num_t cmd_range_dstaddr_dstaddr =
- TOKEN_NUM_INITIALIZER(struct cmd_range_dstaddr_result, dstaddr, UINT64);
-
-
-parse_pgm_inst_t cmd_range_dstaddr = {
- .f = cmd_range_dstaddr_parsed, /* function to call */
- .data = NULL, /* 2nd arg of func */
- .help_str = "set register rangeing dstaddr",
- .tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_range_dstaddr_range_dstaddr,
- (prog_void *)&cmd_range_dstaddr_action,
- (prog_void *)&cmd_range_dstaddr_dstaddr,
- NULL,
- },
-};
-
-/* ************* */
-
-/* this structure is filled when cmd_ping is parsed successfully */
-struct cmd_ping_result {
- fixed_string_t ping;
-};
-
-/* function called when cmd_ping is parsed successfully */
-static void cmd_ping_parsed(void *parsed_result, struct cmdline *cl, void *data)
-{
- xbeeapp_send_atcmd("VL", NULL, 0, 1, NULL, NULL);
-}
-
-parse_pgm_token_string_t cmd_ping_ping =
- TOKEN_STRING_INITIALIZER(struct cmd_ping_result, ping, "ping");
-
-parse_pgm_inst_t cmd_ping = {
- .f = cmd_ping_parsed, /* function to call */
- .data = NULL, /* 2nd arg of func */
- .help_str = "Send a ping to the xbee device",
- .tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_ping_ping,
- NULL,
- },
-};
-
-/* ************* */
-
-/* this structure is filled when cmd_raw is parsed successfully */
-struct cmd_raw_result {
- fixed_string_t raw;
-};
-
-/* function called when cmd_raw is parsed successfully */
-static void cmd_raw_parsed(void *parsed_result, struct cmdline *cl, void *data)
-{
- printf("switched to raw mode, CTRL-D to exit\n");
- rdline_stop(&cl->rdl); /* don't display prompt when return */
- xbee_raw = 1;
-}
-
-parse_pgm_token_string_t cmd_raw_raw =
- TOKEN_STRING_INITIALIZER(struct cmd_raw_result, raw, "raw");
-
-parse_pgm_inst_t cmd_raw = {
- .f = cmd_raw_parsed, /* function to call */
- .data = NULL, /* 2nd arg of func */
- .help_str = "Switch to raw mode",
- .tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_raw_raw,
- NULL,
- },
-};
-
-/* ************* */
-
-/* this structure is filled when cmd_dump is parsed successfully */
-struct cmd_dump_result {
- fixed_string_t dump;
- fixed_string_t onoff;
-};
-
-/* function called when cmd_dump is parsed successfully */
-static void cmd_dump_parsed(void *parsed_result, struct cmdline *cl, void *data)
-{
- struct cmd_dump_result *res = parsed_result;
- if (!strcmp(res->onoff, "on"))
- xbee_hexdump = 1;
- else
- xbee_hexdump = 0;
-}
-
-parse_pgm_token_string_t cmd_dump_dump =
- TOKEN_STRING_INITIALIZER(struct cmd_dump_result, dump, "dump");
-
-parse_pgm_token_string_t cmd_dump_onoff =
- TOKEN_STRING_INITIALIZER(struct cmd_dump_result, onoff, "on#off");
-
-parse_pgm_inst_t cmd_dump = {
- .f = cmd_dump_parsed, /* function to call */
- .data = NULL, /* 2nd arg of func */
- .help_str = "enable/disable hexdump of received packets",
- .tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_dump_dump,
- (prog_void *)&cmd_dump_onoff,
- NULL,
- },
-};
-
-/* ************* */
-
-/* this structure is filled when cmd_debug is parsed successfully */
-struct cmd_debug_result {
- fixed_string_t debug;
- fixed_string_t onoff;
-};
-
-/* function called when cmd_debug is parsed successfully */
-static void cmd_debug_parsed(void *parsed_result, struct cmdline *cl, void *data)
-{
- struct cmd_debug_result *res = parsed_result;
- if (!strcmp(res->onoff, "on"))
- xbee_debug = 1;
- else
- xbee_debug = 0;
-}
-
-parse_pgm_token_string_t cmd_debug_debug =
- TOKEN_STRING_INITIALIZER(struct cmd_debug_result, debug, "debug");
-
-parse_pgm_token_string_t cmd_debug_onoff =
- TOKEN_STRING_INITIALIZER(struct cmd_debug_result, onoff, "on#off");
-
-parse_pgm_inst_t cmd_debug = {
- .f = cmd_debug_parsed, /* function to call */
- .data = NULL, /* 2nd arg of func */
- .help_str = "enable/disable additionnal debug",
- .tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_debug_debug,
- (prog_void *)&cmd_debug_onoff,
- NULL,
- },
-};
-
-/* ************* */
-
-/* this structure is filled when cmd_help is parsed successfully */
-struct cmd_help_result {
- fixed_string_t help;
- struct xbee_atcmd *cmd;
-};
-
-/* function called when cmd_help is parsed successfully */
-static void cmd_help_parsed(void *parsed_result, struct cmdline *cl,
- void *data)
-{
- struct cmd_help_result *res = parsed_result;
- int type;
-
- type = (res->cmd->flags & (XBEE_ATCMD_F_READ | XBEE_ATCMD_F_WRITE));
- switch (type) {
- case XBEE_ATCMD_F_READ:
- printf("Read-only\n");
- break;
- case XBEE_ATCMD_F_WRITE:
- printf("Write-only\n");
- break;
- default:
- printf("Read-write\n");
- break;
- }
- if (res->cmd->flags & XBEE_ATCMD_F_PARAM_NONE)
- printf("No argument\n");
- else if (res->cmd->flags & XBEE_ATCMD_F_PARAM_U8)
- printf("Register is unsigned 8 bits\n");
- else if (res->cmd->flags & XBEE_ATCMD_F_PARAM_U16)
- printf("Register is unsigned 16 bits\n");
- else if (res->cmd->flags & XBEE_ATCMD_F_PARAM_U32)
- printf("Register is unsigned 32 bits\n");
- else if (res->cmd->flags & XBEE_ATCMD_F_PARAM_S16)
- printf("Register is signed 16 bits\n");
- else if (res->cmd->flags & XBEE_ATCMD_F_PARAM_STRING_20B)
- printf("Register is a 20 bytes string\n");
- else
- printf("Unknown argument\n");
-
- printf("%s\n", res->cmd->help);
-}
-
-parse_pgm_token_string_t cmd_help_help =
- TOKEN_STRING_INITIALIZER(struct cmd_help_result, help, "help");
-
-parse_pgm_token_atcmd_t cmd_help_atcmd =
- TOKEN_ATCMD_INITIALIZER(struct cmd_help_result, cmd, &xbee_dev,
- 0, 0);
-
-parse_pgm_inst_t cmd_help = {
- .f = cmd_help_parsed, /* function to call */
- .data = NULL, /* 2nd arg of func */
- .help_str = "Help a register using an AT command",
- .tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_help_help,
- (prog_void *)&cmd_help_atcmd,
- NULL,
- },
-};
-
-/* ************* */
-
-/* this structure is filled when cmd_read is parsed successfully */
-struct cmd_read_result {
- fixed_string_t read;
- struct xbee_atcmd *cmd;
-};
-
-/* function called when cmd_read is parsed successfully */
-static void cmd_read_parsed(void *parsed_result, struct cmdline *cl,
- void *data)
-{
- struct cmd_read_result *res = parsed_result;
- xbeeapp_send_atcmd(res->cmd->name, NULL, 0, 1, NULL, NULL);
-}
-
-parse_pgm_token_string_t cmd_read_read =
- TOKEN_STRING_INITIALIZER(struct cmd_read_result, read, "read");
-
-parse_pgm_token_atcmd_t cmd_read_atcmd =
- TOKEN_ATCMD_INITIALIZER(struct cmd_read_result, cmd, &xbee_dev,
- XBEE_ATCMD_F_READ, XBEE_ATCMD_F_READ);
-
-parse_pgm_inst_t cmd_read = {
- .f = cmd_read_parsed, /* function to call */
- .data = NULL, /* 2nd arg of func */
- .help_str = "Read a register using an AT command",
- .tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_read_read,
- (prog_void *)&cmd_read_atcmd,
- NULL,
- },
-};
-
-/* ************* */
-
-/* this structure is filled when cmd_write is parsed successfully */
-struct cmd_write_result {
- fixed_string_t write;
- struct xbee_atcmd *cmd;
- union {
- uint8_t u8;
- uint16_t u16;
- uint32_t u32;
- };
-};
-
-/* function called when cmd_write is parsed successfully */
-static void cmd_write_parsed(void *parsed_result, struct cmdline *cl,
- void *data)
-{
- struct cmd_write_result *res = parsed_result;
- int len;
- void *param;
-
- if (res->cmd->flags & XBEE_ATCMD_F_PARAM_NONE) {
- len = 0;
- param = NULL;
- }
- else if (res->cmd->flags & XBEE_ATCMD_F_PARAM_U8) {
- len = sizeof(res->u8);
- param = &res->u8;
- }
- else if (res->cmd->flags & XBEE_ATCMD_F_PARAM_U16) {
- len = sizeof(res->u16);
- res->u16 = htons(res->u16);
- param = &res->u16;
- }
- else if (res->cmd->flags & XBEE_ATCMD_F_PARAM_U32) {
- len = sizeof(res->u32);
- res->u32 = htonl(res->u32);
- param = &res->u32;
- }
- else {
- printf("Unknown argument type\n");
- return;
- }
- xbeeapp_send_atcmd(res->cmd->name, param, len, 1, NULL, NULL);
-}
-
-parse_pgm_token_string_t cmd_write_write =
- TOKEN_STRING_INITIALIZER(struct cmd_write_result, write,
- "write");
-
-parse_pgm_token_atcmd_t cmd_write_none_atcmd =
- TOKEN_ATCMD_INITIALIZER(struct cmd_write_result, cmd,
- &xbee_dev,
- XBEE_ATCMD_F_WRITE | XBEE_ATCMD_F_PARAM_NONE,
- XBEE_ATCMD_F_WRITE | XBEE_ATCMD_F_PARAM_NONE);
-
-parse_pgm_inst_t cmd_write_none = {
- .f = cmd_write_parsed, /* function to call */
- .data = NULL, /* 2nd arg of func */
- .help_str = "Send an AT command (no argument)",
- .tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_write_write,
- (prog_void *)&cmd_write_none_atcmd,
- NULL,
- },
-};
-
-parse_pgm_token_atcmd_t cmd_write_u8_atcmd =
- TOKEN_ATCMD_INITIALIZER(struct cmd_write_result, cmd,
- &xbee_dev,
- XBEE_ATCMD_F_WRITE | XBEE_ATCMD_F_PARAM_U8,
- XBEE_ATCMD_F_WRITE | XBEE_ATCMD_F_PARAM_U8);
-
-parse_pgm_token_num_t cmd_write_u8_u8 =
- TOKEN_NUM_INITIALIZER(struct cmd_write_result, u8, UINT8);
-
-parse_pgm_inst_t cmd_write_u8 = {
- .f = cmd_write_parsed, /* function to call */
- .data = NULL, /* 2nd arg of func */
- .help_str = "Write a 8 bits register using an AT command",
- .tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_write_write,
- (prog_void *)&cmd_write_u8_atcmd,
- (prog_void *)&cmd_write_u8_u8,
- NULL,
- },
-};
-
-parse_pgm_token_atcmd_t cmd_write_u16_atcmd =
- TOKEN_ATCMD_INITIALIZER(struct cmd_write_result, cmd,
- &xbee_dev,
- XBEE_ATCMD_F_WRITE | XBEE_ATCMD_F_PARAM_U16,
- XBEE_ATCMD_F_WRITE | XBEE_ATCMD_F_PARAM_U16);
-
-parse_pgm_token_num_t cmd_write_u16_u16 =
- TOKEN_NUM_INITIALIZER(struct cmd_write_result, u16, UINT16);
-
-parse_pgm_inst_t cmd_write_u16 = {
- .f = cmd_write_parsed, /* function to call */
- .data = NULL, /* 2nd arg of func */
- .help_str = "Write a 16 bits register using an AT command",
- .tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_write_write,
- (prog_void *)&cmd_write_u16_atcmd,
- (prog_void *)&cmd_write_u16_u16,
- NULL,
- },
-};
-
-parse_pgm_token_atcmd_t cmd_write_u32_atcmd =
- TOKEN_ATCMD_INITIALIZER(struct cmd_write_result, cmd,
- &xbee_dev,
- XBEE_ATCMD_F_WRITE | XBEE_ATCMD_F_PARAM_U32,
- XBEE_ATCMD_F_WRITE | XBEE_ATCMD_F_PARAM_U32);
-
-parse_pgm_token_num_t cmd_write_u32_u32 =
- TOKEN_NUM_INITIALIZER(struct cmd_write_result, u32, UINT32);
-
-parse_pgm_inst_t cmd_write_u32 = {
- .f = cmd_write_parsed, /* function to call */
- .data = NULL, /* 2nd arg of func */
- .help_str = "Write a 32 bits register using an AT command",
- .tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_write_write,
- (prog_void *)&cmd_write_u32_atcmd,
- (prog_void *)&cmd_write_u32_u32,
- NULL,
- },
-};
-
-/* ************* */
-
-/* this structure is filled when cmd_sendmsg is parsed successfully */
-struct cmd_sendmsg_result {
- fixed_string_t sendmsg;
- uint64_t addr;
- fixed_string_t data;
-};
-
-/* function called when cmd_sendmsg is parsed successfully */
-static void cmd_sendmsg_parsed(void *parsed_result, struct cmdline *cl,
- void *data)
-{
- struct cmd_sendmsg_result *res = parsed_result;
- xbeeapp_send_msg(res->addr, res->data, strlen(res->data), 1);
-}
-
-parse_pgm_token_string_t cmd_sendmsg_sendmsg =
- TOKEN_STRING_INITIALIZER(struct cmd_sendmsg_result, sendmsg, "sendmsg");
-
-parse_pgm_token_num_t cmd_sendmsg_addr =
- TOKEN_NUM_INITIALIZER(struct cmd_sendmsg_result, addr, UINT64);
-
-parse_pgm_token_string_t cmd_sendmsg_data =
- TOKEN_STRING_INITIALIZER(struct cmd_sendmsg_result, data, NULL);
-
-parse_pgm_inst_t cmd_sendmsg = {
- .f = cmd_sendmsg_parsed, /* function to call */
- .data = NULL, /* 2nd arg of func */
- .help_str = "Send data to a node using its address",
- .tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_sendmsg_sendmsg,
- (prog_void *)&cmd_sendmsg_addr,
- (prog_void *)&cmd_sendmsg_data,
- NULL,
- },
-};
-
-/* ************* */
-
-/* this structure is filled when cmd_sendmsg_name is parsed successfully */
-struct cmd_sendmsg_name_result {
- fixed_string_t sendmsg_name;
- struct xbee_neigh *neigh;
- fixed_string_t data;
-};
-
-/* function called when cmd_sendmsg_name is parsed successfully */
-static void cmd_sendmsg_name_parsed(void *parsed_result, struct cmdline *cl,
- void *data)
-{
- struct cmd_sendmsg_name_result *res = parsed_result;
- xbeeapp_send_msg(res->neigh->addr, res->data, strlen(res->data), 1);
-}
-
-parse_pgm_token_string_t cmd_sendmsg_name_sendmsg_name =
- TOKEN_STRING_INITIALIZER(struct cmd_sendmsg_name_result, sendmsg_name,
- "sendmsg");
-
-parse_pgm_token_neighbor_t cmd_sendmsg_name_neigh =
- TOKEN_NEIGHBOR_INITIALIZER(struct cmd_sendmsg_name_result, neigh,
- &xbee_dev);
-
-parse_pgm_token_string_t cmd_sendmsg_name_data =
- TOKEN_STRING_INITIALIZER(struct cmd_sendmsg_name_result, data, NULL);
-
-parse_pgm_inst_t cmd_sendmsg_name = {
- .f = cmd_sendmsg_name_parsed, /* function to call */
- .data = NULL, /* 2nd arg of func */
- .help_str = "Send data to a node using its name",
- .tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_sendmsg_name_sendmsg_name,
- (prog_void *)&cmd_sendmsg_name_neigh,
- (prog_void *)&cmd_sendmsg_name_data,
- NULL,
- },
-};
-
-/* ************* */
-
-struct cmd_neigh_del_result {
- fixed_string_t cmd;
- fixed_string_t action;
- struct xbee_neigh *neigh;
-};
-
-static void cmd_neigh_del_parsed(void *parsed_result,
- struct cmdline *cl,
- void *data)
-{
- struct cmd_neigh_del_result *res = parsed_result;
- xbee_neigh_del(xbee_dev, res->neigh);
-}
-
-parse_pgm_token_string_t cmd_neigh_del_cmd =
- TOKEN_STRING_INITIALIZER(struct cmd_neigh_del_result, cmd, "neigh");
-parse_pgm_token_string_t cmd_neigh_del_action =
- TOKEN_STRING_INITIALIZER(struct cmd_neigh_del_result, action, "del");
-parse_pgm_token_neighbor_t cmd_neigh_del_neigh =
- TOKEN_NEIGHBOR_INITIALIZER(struct cmd_neigh_del_result, neigh,
- &xbee_dev);
-
-parse_pgm_inst_t cmd_neigh_del = {
- .f = cmd_neigh_del_parsed, /* function to call */
- .data = NULL, /* 2nd arg of func */
- .help_str = "delete a neighbor",
- .tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_neigh_del_cmd,
- (prog_void *)&cmd_neigh_del_action,
- (prog_void *)&cmd_neigh_del_neigh,
- NULL,
- },
-};
-
-/* ************* */
-
-struct cmd_neigh_add_result {
- fixed_string_t cmd;
- fixed_string_t action;
- fixed_string_t name;
- uint64_t addr;
-};
-
-static void cmd_neigh_add_parsed(void *parsed_result,
- struct cmdline *cl,
- void *data)
-{
- struct cmd_neigh_add_result *res = parsed_result;
- if (xbee_neigh_add(xbee_dev, res->name, res->addr) == NULL)
- printf("name or addr already exist\n");
-}
-
-parse_pgm_token_string_t cmd_neigh_add_cmd =
- TOKEN_STRING_INITIALIZER(struct cmd_neigh_add_result, cmd, "neigh");
-parse_pgm_token_string_t cmd_neigh_add_action =
- TOKEN_STRING_INITIALIZER(struct cmd_neigh_add_result, action, "add");
-parse_pgm_token_string_t cmd_neigh_add_name =
- TOKEN_STRING_INITIALIZER(struct cmd_neigh_add_result, name, NULL);
-parse_pgm_token_num_t cmd_neigh_add_addr =
- TOKEN_NUM_INITIALIZER(struct cmd_neigh_add_result, addr, UINT64);
-
-parse_pgm_inst_t cmd_neigh_add = {
- .f = cmd_neigh_add_parsed, /* function to call */
- .data = NULL, /* 2nd arg of func */
- .help_str = "add a neighbor",
- .tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_neigh_add_cmd,
- (prog_void *)&cmd_neigh_add_action,
- (prog_void *)&cmd_neigh_add_name,
- (prog_void *)&cmd_neigh_add_addr,
- NULL,
- },
-};
-
-/* ************* */
-
-struct cmd_neigh_list_result {
- fixed_string_t cmd;
- fixed_string_t action;
-};
-
-static void cmd_neigh_list_parsed(void *parsed_result,
- struct cmdline *cl,
- void *data)
-{
- struct xbee_neigh *neigh;
-
- LIST_FOREACH(neigh, &xbee_dev->neigh_list, next) {
- printf(" %s: 0x%"PRIx64"\n", neigh->name, neigh->addr);
- }
-}
-
-parse_pgm_token_string_t cmd_neigh_list_cmd =
- TOKEN_STRING_INITIALIZER(struct cmd_neigh_list_result, cmd, "neigh");
-parse_pgm_token_string_t cmd_neigh_list_action =
- TOKEN_STRING_INITIALIZER(struct cmd_neigh_list_result, action, "list");
-
-parse_pgm_inst_t cmd_neigh_list = {
- .f = cmd_neigh_list_parsed, /* function to call */
- .data = NULL, /* 2nd arg of func */
- .help_str = "list all known neighbors",
- .tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_neigh_list_cmd,
- (prog_void *)&cmd_neigh_list_action,
- NULL,
- },
-};
-
-/*******************/
-
-struct cmd_logfile_result {
- fixed_string_t logfile;
- filename_t file;
-};
-
-static void cmd_logfile_parsed(void *parsed_result,
- struct cmdline *cl,
- void *data)
-{
- if (xbee_logfile != NULL)
- fclose(xbee_logfile);
- xbee_logfile = fopen(xbee_logfilename, "a");
- if (xbee_logfile == NULL)
- printf("cannot open file: %s\n", strerror(errno));
- fprintf(xbee_logfile, "-------------------start\n");
- printf("enabling log\n");
-}
-
-parse_pgm_token_string_t cmd_logfile_logfile =
- TOKEN_STRING_INITIALIZER(struct cmd_logfile_result, logfile, "logfile");
-
-parse_pgm_token_file_t cmd_logfile_file =
- TOKEN_FILE_INITIALIZER(struct cmd_logfile_result, file,
- PARSE_FILE_F_CREATE);
-
-parse_pgm_inst_t cmd_logfile = {
- .f = cmd_logfile_parsed, /* function to call */
- .data = NULL, /* 2nd arg of func */
- .help_str = "<logfile FILE> set log file",
- .tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_logfile_logfile,
- (prog_void *)&cmd_logfile_file,
- NULL,
- },
-};
-
-/* ************* */
-
-/* this structure is filled when cmd_log is parsed successfully */
-struct cmd_log_result {
- fixed_string_t log;
- fixed_string_t onoff;
-};
-
-/* function called when cmd_log is parsed successfully */
-static void cmd_log_parsed(void *parsed_result, struct cmdline *cl, void *data)
-{
- struct cmd_log_result *res = parsed_result;
- if (!strcmp(res->onoff, "on") && xbee_logfile == NULL) {
- xbee_logfile = fopen(xbee_logfilename, "a");
- if (xbee_logfile == NULL)
- printf("cannot open file: %s\n", strerror(errno));
- fprintf(xbee_logfile, "-------------------start\n");
- }
- else if (!strcmp(res->onoff, "off") && xbee_logfile != NULL) {
- fclose(xbee_logfile);
- xbee_logfile = NULL;
- }
-}
-
-parse_pgm_token_string_t cmd_log_log =
- TOKEN_STRING_INITIALIZER(struct cmd_log_result, log, "log");
-
-parse_pgm_token_string_t cmd_log_onoff =
- TOKEN_STRING_INITIALIZER(struct cmd_log_result, onoff, "on#off");
-
-parse_pgm_inst_t cmd_log = {
- .f = cmd_log_parsed, /* function to call */
- .data = NULL, /* 2nd arg of func */
- .help_str = "enable/disable hexlog of received packets",
- .tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_log_log,
- (prog_void *)&cmd_log_onoff,
- NULL,
- },
-};
-
-
-/*******************/
-
-struct cmd_saveconfig_result {
- fixed_string_t saveconfig;
- filename_t file;
-};
-
-static void cmd_saveconfig_parsed(void *parsed_result,
- struct cmdline *cl,
- void *data)
-{
- struct cmd_saveconfig_result *res = parsed_result;
-
- if (xbeeapp_dump_config(res->file) < 0)
- printf("cannot save config\n");
-}
-
-parse_pgm_token_string_t cmd_saveconfig_saveconfig =
- TOKEN_STRING_INITIALIZER(struct cmd_saveconfig_result, saveconfig,
- "saveconfig");
-
-parse_pgm_token_file_t cmd_saveconfig_file =
- TOKEN_FILE_INITIALIZER(struct cmd_saveconfig_result, file,
- PARSE_FILE_F_CREATE);
-
-parse_pgm_inst_t cmd_saveconfig = {
- .f = cmd_saveconfig_parsed, /* function to call */
- .data = NULL, /* 2nd arg of func */
- .help_str = "<saveconfig FILE> set log file",
- .tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_saveconfig_saveconfig,
- (prog_void *)&cmd_saveconfig_file,
- NULL,
- },
-};
-
-/*******************/
-
-struct cmd_loadconfig_result {
- fixed_string_t loadconfig;
- filename_t file;
-};
-
-static void cmd_loadconfig_parsed(void *parsed_result,
- struct cmdline *cl,
- void *data)
-{
-}
-
-parse_pgm_token_string_t cmd_loadconfig_loadconfig =
- TOKEN_STRING_INITIALIZER(struct cmd_loadconfig_result, loadconfig,
- "loadconfig");
-
-parse_pgm_token_file_t cmd_loadconfig_file =
- TOKEN_FILE_INITIALIZER(struct cmd_loadconfig_result, file,
- PARSE_FILE_F_CREATE);
-
-parse_pgm_inst_t cmd_loadconfig = {
- .f = cmd_loadconfig_parsed, /* function to call */
- .data = NULL, /* 2nd arg of func */
- .help_str = "<loadconfig FILE> set log file",
- .tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_loadconfig_loadconfig,
- (prog_void *)&cmd_loadconfig_file,
- NULL,
- },
-};
-
-/**********************************************************/
-/**********************************************************/
-/****** CONTEXT (list of instruction) */
-
-/* in progmem */
-parse_ctx_t main_ctx = {
- .name = "main",
- .insts = {
- (parse_pgm_inst_t *)&cmd_stats,
- (parse_pgm_inst_t *)&cmd_monitor,
- (parse_pgm_inst_t *)&cmd_monitor_period,
- (parse_pgm_inst_t *)&cmd_monitor_add,
- (parse_pgm_inst_t *)&cmd_monitor_del,
- (parse_pgm_inst_t *)&cmd_range,
- (parse_pgm_inst_t *)&cmd_range_period,
- (parse_pgm_inst_t *)&cmd_range_count,
- (parse_pgm_inst_t *)&cmd_range_powermask,
- (parse_pgm_inst_t *)&cmd_range_dstaddr,
- (parse_pgm_inst_t *)&cmd_ping,
- (parse_pgm_inst_t *)&cmd_raw,
- (parse_pgm_inst_t *)&cmd_dump,
- (parse_pgm_inst_t *)&cmd_debug,
- (parse_pgm_inst_t *)&cmd_help,
- (parse_pgm_inst_t *)&cmd_read,
- (parse_pgm_inst_t *)&cmd_write_none,
- (parse_pgm_inst_t *)&cmd_write_u8,
- (parse_pgm_inst_t *)&cmd_write_u16,
- (parse_pgm_inst_t *)&cmd_write_u32,
- (parse_pgm_inst_t *)&cmd_sendmsg,
- (parse_pgm_inst_t *)&cmd_sendmsg_name,
- (parse_pgm_inst_t *)&cmd_neigh_del,
- (parse_pgm_inst_t *)&cmd_neigh_add,
- (parse_pgm_inst_t *)&cmd_neigh_list,
- (parse_pgm_inst_t *)&cmd_logfile,
- (parse_pgm_inst_t *)&cmd_log,
- (parse_pgm_inst_t *)&cmd_saveconfig,
- (parse_pgm_inst_t *)&cmd_loadconfig,
- NULL,
- },
-};
/* function called when cmd_reset is parsed successfully */
static void cmd_reset_parsed(void * parsed_result, void * data)
{
+ (void)parsed_result;
+ (void)data;
#ifdef HOST_VERSION
hostsim_exit();
#endif
reset();
}
-prog_char str_reset_arg0[] = "reset";
-parse_pgm_token_string_t cmd_reset_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_reset_result, arg0, str_reset_arg0);
+const char PROGMEM str_reset_arg0[] = "reset";
+const parse_token_string_t PROGMEM cmd_reset_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_reset_result, arg0, str_reset_arg0);
-prog_char help_reset[] = "Reset the board";
-parse_pgm_inst_t cmd_reset = {
+const char PROGMEM help_reset[] = "Reset the board";
+const parse_inst_t PROGMEM cmd_reset = {
.f = cmd_reset_parsed, /* function to call */
.data = NULL, /* 2nd arg of func */
.help_str = help_reset,
.tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_reset_arg0,
+ (PGM_P)&cmd_reset_arg0,
NULL,
},
};
/* function called when cmd_bootloader is parsed successfully */
static void cmd_bootloader_parsed(void *parsed_result, void *data)
{
+ (void)parsed_result;
+ (void)data;
#ifndef HOST_VERSION
bootloader();
#else
#endif
}
-prog_char str_bootloader_arg0[] = "bootloader";
-parse_pgm_token_string_t cmd_bootloader_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_bootloader_result, arg0, str_bootloader_arg0);
+const char PROGMEM str_bootloader_arg0[] = "bootloader";
+const parse_token_string_t PROGMEM cmd_bootloader_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_bootloader_result, arg0, str_bootloader_arg0);
-prog_char help_bootloader[] = "Launch the bootloader";
-parse_pgm_inst_t cmd_bootloader = {
+const char PROGMEM help_bootloader[] = "Launch the bootloader";
+const parse_inst_t PROGMEM cmd_bootloader = {
.f = cmd_bootloader_parsed, /* function to call */
.data = NULL, /* 2nd arg of func */
.help_str = help_bootloader,
.tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_bootloader_arg0,
+ (PGM_P)&cmd_bootloader_arg0,
NULL,
},
};
/* function called when cmd_scheduler is parsed successfully */
static void cmd_scheduler_parsed(void *parsed_result, void *data)
{
+ (void)parsed_result;
+ (void)data;
scheduler_dump_events();
scheduler_stats_dump();
}
-prog_char str_scheduler_arg0[] = "scheduler";
-parse_pgm_token_string_t cmd_scheduler_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_scheduler_result, arg0, str_scheduler_arg0);
-prog_char str_scheduler_arg1[] = "show";
-parse_pgm_token_string_t cmd_scheduler_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_scheduler_result, arg1, str_scheduler_arg1);
+const char PROGMEM str_scheduler_arg0[] = "scheduler";
+const parse_token_string_t PROGMEM cmd_scheduler_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_scheduler_result, arg0, str_scheduler_arg0);
+const char PROGMEM str_scheduler_arg1[] = "show";
+const parse_token_string_t PROGMEM cmd_scheduler_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_scheduler_result, arg1, str_scheduler_arg1);
-prog_char help_scheduler[] = "Show scheduler events";
-parse_pgm_inst_t cmd_scheduler = {
+const char PROGMEM help_scheduler[] = "Show scheduler events";
+const parse_inst_t PROGMEM cmd_scheduler = {
.f = cmd_scheduler_parsed, /* function to call */
.data = NULL, /* 2nd arg of func */
.help_str = help_scheduler,
.tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_scheduler_arg0,
- (prog_void *)&cmd_scheduler_arg1,
+ (PGM_P)&cmd_scheduler_arg0,
+ (PGM_P)&cmd_scheduler_arg1,
NULL,
},
};
};
/* keep it sync with string choice */
-static const prog_char uart_log[] = "uart";
-static const prog_char i2c_log[] = "i2c";
-static const prog_char default_log[] = "default";
+static const char PROGMEM uart_log[] = "uart";
+static const char PROGMEM i2c_log[] = "i2c";
+static const char PROGMEM default_log[] = "default";
struct log_name_and_num {
- const prog_char * name;
+ const char *name;
uint8_t num;
};
return 0;
}
-const prog_char *
+const char *
log_num2name(uint8_t num)
{
uint8_t i;
static void cmd_log_do_show(void)
{
uint8_t i, empty=1;
- const prog_char * name;
+ const char *name;
printf_P(PSTR("log level is %d\r\n"), xbeeboard.log_level);
for (i=0; i<NB_LOGS; i++) {
}
/* function called when cmd_log is parsed successfully */
-static void cmd_log_parsed(void * parsed_result, void * data)
+static void cmd_log_parsed(void * parsed_result, void *data)
{
struct cmd_log_result *res = (struct cmd_log_result *) parsed_result;
+ (void)data;
if (!strcmp_P(res->arg1, PSTR("level"))) {
xbeeboard.log_level = res->arg2;
}
cmd_log_do_show();
}
-prog_char str_log_arg0[] = "log";
-parse_pgm_token_string_t cmd_log_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_log_result, arg0, str_log_arg0);
-prog_char str_log_arg1[] = "level";
-parse_pgm_token_string_t cmd_log_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_log_result, arg1, str_log_arg1);
-parse_pgm_token_num_t cmd_log_arg2 = TOKEN_NUM_INITIALIZER(struct cmd_log_result, arg2, INT8);
+const char PROGMEM str_log_arg0[] = "log";
+const parse_token_string_t PROGMEM cmd_log_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_log_result, arg0, str_log_arg0);
+const char PROGMEM str_log_arg1[] = "level";
+const parse_token_string_t PROGMEM cmd_log_arg1 = TOKEN_STRING_INITIALIZER(struct cmd_log_result, arg1, str_log_arg1);
+const parse_token_num_t PROGMEM cmd_log_arg2 = TOKEN_NUM_INITIALIZER(struct cmd_log_result, arg2, INT8);
-prog_char help_log[] = "Set log options: level (0 -> 5)";
-parse_pgm_inst_t cmd_log = {
+const char PROGMEM help_log[] = "Set log options: level (0 -> 5)";
+const parse_inst_t PROGMEM cmd_log = {
.f = cmd_log_parsed, /* function to call */
.data = NULL, /* 2nd arg of func */
.help_str = help_log,
.tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_log_arg0,
- (prog_void *)&cmd_log_arg1,
- (prog_void *)&cmd_log_arg2,
+ (PGM_P)&cmd_log_arg0,
+ (PGM_P)&cmd_log_arg1,
+ (PGM_P)&cmd_log_arg2,
NULL,
},
};
-prog_char str_log_arg1_show[] = "show";
-parse_pgm_token_string_t cmd_log_arg1_show = TOKEN_STRING_INITIALIZER(struct cmd_log_result, arg1, str_log_arg1_show);
+const char PROGMEM str_log_arg1_show[] = "show";
+const parse_token_string_t PROGMEM cmd_log_arg1_show = TOKEN_STRING_INITIALIZER(struct cmd_log_result, arg1, str_log_arg1_show);
-prog_char help_log_show[] = "Show configured logs";
-parse_pgm_inst_t cmd_log_show = {
+const char PROGMEM help_log_show[] = "Show configured logs";
+const parse_inst_t PROGMEM cmd_log_show = {
.f = cmd_log_parsed, /* function to call */
.data = NULL, /* 2nd arg of func */
.help_str = help_log_show,
.tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_log_arg0,
- (prog_void *)&cmd_log_arg1_show,
+ (PGM_P)&cmd_log_arg0,
+ (PGM_P)&cmd_log_arg1_show,
NULL,
},
};
};
/* function called when cmd_log is parsed successfully */
-static void cmd_log_type_parsed(void * parsed_result, void * data)
+static void cmd_log_type_parsed(void * parsed_result, void *data)
{
struct cmd_log_type_result *res = (struct cmd_log_type_result *) parsed_result;
uint8_t lognum;
uint8_t i;
-
+
+ (void)data;
+
lognum = log_name2num(res->arg2);
if (lognum == 0) {
printf_P(PSTR("Cannot find log num\r\n"));
cmd_log_do_show();
}
-prog_char str_log_arg1_type[] = "type";
-parse_pgm_token_string_t cmd_log_arg1_type = TOKEN_STRING_INITIALIZER(struct cmd_log_type_result, arg1, str_log_arg1_type);
+const char PROGMEM str_log_arg1_type[] = "type";
+const parse_token_string_t PROGMEM cmd_log_arg1_type = TOKEN_STRING_INITIALIZER(struct cmd_log_type_result, arg1, str_log_arg1_type);
/* keep it sync with log_name_and_num above */
-prog_char str_log_arg2_type[] = "uart#rs#servo#traj#i2c#oa#strat#i2cproto#ext#sensor#bd#cs";
-parse_pgm_token_string_t cmd_log_arg2_type = TOKEN_STRING_INITIALIZER(struct cmd_log_type_result, arg2, str_log_arg2_type);
-prog_char str_log_arg3[] = "on#off";
-parse_pgm_token_string_t cmd_log_arg3 = TOKEN_STRING_INITIALIZER(struct cmd_log_type_result, arg3, str_log_arg3);
+const char PROGMEM str_log_arg2_type[] = "uart#rs#servo#traj#i2c#oa#strat#i2cproto#ext#sensor#bd#cs";
+const parse_token_string_t PROGMEM cmd_log_arg2_type = TOKEN_STRING_INITIALIZER(struct cmd_log_type_result, arg2, str_log_arg2_type);
+const char PROGMEM str_log_arg3[] = "on#off";
+const parse_token_string_t PROGMEM cmd_log_arg3 = TOKEN_STRING_INITIALIZER(struct cmd_log_type_result, arg3, str_log_arg3);
-prog_char help_log_type[] = "Set log type";
-parse_pgm_inst_t cmd_log_type = {
+const char PROGMEM help_log_type[] = "Set log type";
+const parse_inst_t PROGMEM cmd_log_type = {
.f = cmd_log_type_parsed, /* function to call */
.data = NULL, /* 2nd arg of func */
.help_str = help_log_type,
.tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_log_arg0,
- (prog_void *)&cmd_log_arg1_type,
- (prog_void *)&cmd_log_arg2_type,
- (prog_void *)&cmd_log_arg3,
+ (PGM_P)&cmd_log_arg0,
+ (PGM_P)&cmd_log_arg1_type,
+ (PGM_P)&cmd_log_arg2_type,
+ (PGM_P)&cmd_log_arg3,
NULL,
},
};
/* function called when cmd_stack_space is parsed successfully */
static void cmd_stack_space_parsed(void *parsed_result, void *data)
{
+ (void)parsed_result;
+ (void)data;
#ifdef HOST_VERSION
printf("not implemented\n");
#else
#endif
}
-prog_char str_stack_space_arg0[] = "stack_space";
-parse_pgm_token_string_t cmd_stack_space_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_stack_space_result, arg0, str_stack_space_arg0);
+const char PROGMEM str_stack_space_arg0[] = "stack_space";
+const parse_token_string_t PROGMEM cmd_stack_space_arg0 = TOKEN_STRING_INITIALIZER(struct cmd_stack_space_result, arg0, str_stack_space_arg0);
-prog_char help_stack_space[] = "Display remaining stack space";
-parse_pgm_inst_t cmd_stack_space = {
+const char PROGMEM help_stack_space[] = "Display remaining stack space";
+const parse_inst_t PROGMEM cmd_stack_space = {
.f = cmd_stack_space_parsed, /* function to call */
.data = NULL, /* 2nd arg of func */
.help_str = help_stack_space,
.tokens = { /* token list, NULL terminated */
- (prog_void *)&cmd_stack_space_arg0,
+ (PGM_P)&cmd_stack_space_arg0,
NULL,
},
};
+++ /dev/null
-/* empty */
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: diagnostic.h,v 1.6.4.2 2008-05-09 08:23:52 zer0 Exp $
- *
- */
-
-#include <diagnostic_config.h>
-
-
-
-/** shows the interrupt cycles on an oscilloscope or a multimeter you
- * can then measure the interrupt busy time of your device. this
- * function is an infinite loop which has to be the main program, and
- * will be interrupted. a port bit is needed as diagnostic interface
- * with scope or multimeter. if you use a scope : freezing of the
- * oscillation shows interrupt if you use a multimeter : voltage is
- * proportionnal to idle time
- * 0V >> 0% idle (always busy)
- * Vcc/2 >> 100% idle (not interupted)
- * be careful, you perhaps need a low pass filter for your voltmeter */
-extern void show_int_loop(void);
-
-/** This functuion allows to monitor the maximal stack space that was
- * used since the last reset (peak value) you can then monitor the
- * available space in your ram returns the minimal value of the free
- * space left */
-extern uint16_t min_stack_space_available(void);
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: error.c,v 1.10.4.3 2007-12-31 16:25:00 zer0 Exp $
- *
- */
-
-
-#include <string.h>
-
-#ifndef HOST_VERSION
-#include <avr/io.h>
-#endif
-
-#include <aversive.h>
-#include <aversive/error.h>
-
-struct error_fct g_error_fct;
-
-/** All fcts pointers to NULL */
-void error_init(void)
-{
- uint8_t flags;
- IRQ_LOCK(flags);
- memset(&g_error_fct, 0, sizeof(g_error_fct));
- IRQ_UNLOCK(flags);
-}
-
-
-struct error error_generate(uint8_t num, uint8_t severity, PGM_P t,
- PGM_P f, uint16_t l) {
- struct error e;
-
- e.err_num = num;
- e.severity = severity;
-#ifdef ERROR_DUMP_TEXTLOG
- e.text = t;
-#else
- e.text = PSTR("");
-#endif
-#ifdef ERROR_DUMP_FILE_LINE
- e.file = f;
- e.line = l;
-#else
- e.file = PSTR("");
- e.line = 0;
-#endif
- return e;
-}
-
-
-/** Register log function for EMERG level */
-void error_register_emerg(void (*f)(struct error *, ...))
-{
- uint8_t flags;
- IRQ_LOCK(flags);
- g_error_fct.emerg = f;
- IRQ_UNLOCK(flags);
-}
-
-/** Register log function for ERROR level */
-void error_register_error(void (*f)(struct error *, ...))
-{
- uint8_t flags;
- IRQ_LOCK(flags);
- g_error_fct.error = f;
- IRQ_UNLOCK(flags);
-}
-
-/** Register log function for WARNING level */
-void error_register_warning(void (*f)(struct error *, ...))
-{
- uint8_t flags;
- IRQ_LOCK(flags);
- g_error_fct.warning = f;
- IRQ_UNLOCK(flags);
-}
-
-/** Register log function for NOTICE level */
-void error_register_notice(void (*f)(struct error *, ...))
-{
- uint8_t flags;
- IRQ_LOCK(flags);
- g_error_fct.notice = f;
- IRQ_UNLOCK(flags);
-}
-
-/** Register log function for DEBUG level */
-void error_register_debug(void (*f)(struct error *, ...))
-{
- uint8_t flags;
- IRQ_LOCK(flags);
- g_error_fct.debug = f;
- IRQ_UNLOCK(flags);
-}
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: error.h,v 1.11.4.3 2007-12-31 16:25:00 zer0 Exp $
- *
- */
-
-#ifndef _ERROR_H_
-#define _ERROR_H_
-
-#ifndef _AVERSIVE_ERROR_H_
-#error "Don't include <error.h>, include <aversive/error.h> instead"
-#endif
-
-#include <aversive/pgmspace.h>
-#include <aversive.h>
-#include <general_errors.h>
-
-#include "error_config.h"
-
-#define ERROR_SEVERITY_EMERG 0
-#define ERROR_SEVERITY_ERROR 1
-#define ERROR_SEVERITY_WARNING 2
-#define ERROR_SEVERITY_NOTICE 3
-#define ERROR_SEVERITY_DEBUG 4
-
-/** The error structure, which is given as a parameter in log funcs */
-struct error {
- uint8_t err_num;
- uint8_t severity;
- PGM_P text;
- PGM_P file;
- uint16_t line;
-};
-
-
-struct error_fct {
- void (*emerg)(struct error *, ...);
- void (*error)(struct error *, ...);
- void (*warning)(struct error *, ...);
- void (*notice)(struct error *, ...);
- void (*debug)(struct error *, ...);
-} ;
-
-extern struct error_fct g_error_fct;
-
-
-struct error error_generate(uint8_t num, uint8_t severity, PGM_P t, PGM_P f, uint16_t l);
-
-/** Register log function for EMERG level */
-void error_register_emerg(void (*f)(struct error *, ...));
-
-/** Register log function for ERROR level */
-void error_register_error(void (*f)(struct error *, ...));
-
-/** Register log function for WARNING level */
-void error_register_warning(void (*f)(struct error *, ...));
-
-/** Register log function for NOTICE level */
-void error_register_notice(void (*f)(struct error *, ...));
-
-/** Register log function for DEBUG level */
-void error_register_debug(void (*f)(struct error *, ...));
-
-
-
-
-/** Call this macro to log EMERG events */
-#define EMERG(num, text, ...) do { \
- if(g_error_fct.emerg) { \
- struct error e = error_generate(num, ERROR_SEVERITY_EMERG, \
- PSTR(text), \
- PSTR(__FILE__),\
- __LINE__); \
- g_error_fct.emerg(&e, ##__VA_ARGS__); \
- } \
-} while(0)
-
-/** Call this macro to log ERROR events */
-#define ERROR(num, text, ...) do { \
- if(g_error_fct.error) { \
- struct error e = error_generate(num, ERROR_SEVERITY_ERROR, \
- PSTR(text), \
- PSTR(__FILE__),\
- __LINE__); \
- g_error_fct.error(&e, ##__VA_ARGS__); \
- } \
-} while(0)
-
-/** Call this macro to log WARNING events */
-#define WARNING(num, text, ...) do { \
- if(g_error_fct.warning) { \
- struct error e = error_generate(num, ERROR_SEVERITY_WARNING, \
- PSTR(text), \
- PSTR(__FILE__),\
- __LINE__); \
- g_error_fct.warning(&e, ##__VA_ARGS__); \
- } \
-} while(0)
-
-/** Call this macro to log NOTICE events */
-#define NOTICE(num, text, ...) do { \
- if(g_error_fct.notice) { \
- struct error e = error_generate(num, ERROR_SEVERITY_NOTICE, \
- PSTR(text), \
- PSTR(__FILE__),\
- __LINE__); \
- g_error_fct.notice(&e, ##__VA_ARGS__); \
- } \
-} while(0)
-
-/** Call this macro to log DEBUG events */
-#define DEBUG(num, text, ...) do { \
- if(g_error_fct.debug) { \
- struct error e = error_generate(num, ERROR_SEVERITY_DEBUG, \
- PSTR(text), \
- PSTR(__FILE__),\
- __LINE__); \
- g_error_fct.debug(&e, ##__VA_ARGS__); \
- } \
-} while(0)
-
-
-
-
-#endif /* _ERROR_H_ */
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: general_errors.h,v 1.5.4.3 2009-01-23 23:54:15 zer0 Exp $
- *
- */
-
-
-/**
- * these are general errors.
- */
-
-/* Not module specific */
-
-/* Operation not permitted */
-#define EPERM_COMMENT "Operation not permitted"
-
-/* No such file or directory */
-#define ENOENT_COMMENT "No such file or directory"
-
-/* I/O error */
-#define EIO_COMMENT "I/O error"
-
-/* No such device or address */
-#define ENXIO_COMMENT "No such device or address"
-
-/* Argument list too long */
-#define E2BIG_COMMENT "Argument list too long"
-
-/* Try again */
-#define EAGAIN_COMMENT "Try again"
-
-/* Out of memory */
-#define ENOMEM_COMMENT "Out of memory"
-
-/* Bad address */
-#define EFAULT_COMMENT "Bad address"
-
-/* Device or resource busy */
-#define EBUSY_COMMENT "Device or resource busy"
-
-/* Invalid argument */
-#define EINVAL_COMMENT "Invalid argument"
-
-/* Unkwow error */
-#define EUNKNOW_COMMENT "Unkwow error"
-
-
-/* Module specific, from 129 to 192 */
-
-#define E_UART 129
-#define E_ROBOT_SYSTEM 130
-#define E_MULTISERVO 131
-#define E_TRAJECTORY 132
-#define E_I2C 133
-#define E_BLOCKING_DETECTION_MANAGER 134
-#define E_OA 135
-#define E_SPI 136
-#define E_CC2420 137
-#define E_TIME_EXT 138
-
-/* ... etc TBD */
-
-/* User specific, from > 192 */
-
-/* defined in user app */
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: int_show.c,v 1.6.10.3 2008-05-09 08:23:52 zer0 Exp $
- *
- */
-
-#include <avr/io.h>
-#include <aversive.h>
-#include <diagnostic.h>
-
-
-#ifdef INTERRUPT_SHOW_PORT
-
-/** this loop is to be used as main program if you have interrupts
- * running and want to see how much time is consumed by the
- * interrupts. you must then observe the test pin with an
- * oscilloscope, or eventually a multimeter. as long as there are no
- * interrupts, the test port will toggle at 50% rate. when an
- * interrupt occurs, the port stops to toggle, and remain low. the
- * space before the next impulsion is the int time (always one toggle
- * between ints!) if you look whith a multimeter, the processor free
- * time is proportinnal to the observed voltage. 0V corresponds to
- * an always busy processor, while if you read Vcc/2 the processor is
- * almost always free. */
-void show_int_loop(void)
-{
- sbi(DDR(INTERRUPT_SHOW_PORT), INTERRUPT_SHOW_BIT);
-
- while(1) {
- cbi(INTERRUPT_SHOW_PORT, INTERRUPT_SHOW_BIT); // port to 0
-
- sei();
- nop(); // ints can only arrive there (on low level of probe pin)
- cli();
-
- sbi(INTERRUPT_SHOW_PORT, INTERRUPT_SHOW_BIT); // port to 1
-
- nop(); // is there to equalize the duty cycle
- }
-}
-#endif
static int parse_xmit_status(struct xbee_ctx *ctx,
struct xbee_xmit_status_hdr *frame, unsigned len)
{
+ (void)len;
+
if (ctx == NULL) {
printf_P(PSTR("no context\r\n"));
return -1;
unsigned len)
{
char atcmd_str[3];
- struct xbee_atcmd_pgm *cmd_pgm;
+ const struct xbee_atcmd *cmd_pgm;
struct xbee_atcmd cmd;
union {
uint8_t u8;
int xbee_recv_data(struct xbee_recv_hdr *recvframe, unsigned len)
{
- int datalen = len - sizeof(*recvframe);
+ unsigned int datalen;
struct rc_proto_hdr *rch = (struct rc_proto_hdr *) &recvframe->data;
+ if (len < sizeof(*recvframe))
+ return -1;
+
+ datalen = len - sizeof(*recvframe);
if (datalen < sizeof(struct rc_proto_hdr))
return -1;
{
struct xbee_ctx *ctx = arg;
+ (void)cm;
+ (void)clt;
+
printf_P(PSTR("Timeout\r\n"));
/* restart command line */
TIMSK1 = 0;
TIMSK2 = 0;
TIMSK3 = 0;
- TIMSK4 = 0;
- TIMSK5 = 0;
EIMSK = 0;
UCSR0B = 0;
UCSR1B = 0;
- UCSR2B = 0;
- UCSR3B = 0;
SPCR = 0;
TWCR = 0;
ACSR = 0;
ADCSRA = 0;
- EIND = 1;
- __asm__ __volatile__ ("ldi r31,0xf8\n");
- __asm__ __volatile__ ("ldi r30,0x00\n");
- __asm__ __volatile__ ("eijmp\n");
+ /* XXX */
+ /* __asm__ __volatile__ ("ldi r31,0xf8\n"); */
+ /* __asm__ __volatile__ ("ldi r30,0x00\n"); */
+ /* __asm__ __volatile__ ("eijmp\n"); */
#endif
}
{
static uint8_t a = 0;
+ (void)cm;
+ (void)clt;
+ (void)dummy;
+
#ifdef USE_USB
if (a & 1)
LEDs_SetAllLEDs(0);
static void increment_ms(void *dummy)
{
+ (void)dummy;
global_ms++;
}
+++ /dev/null
-\r
-# Hey Emacs, this is a -*- makefile -*-\r
-#----------------------------------------------------------------------------\r
-# WinAVR Makefile Template written by Eric B. Weddington, Jörg Wunsch, et al.\r
-# >> Modified for use with the LUFA project. <<\r
-#\r
-# Released to the Public Domain\r
-#\r
-# Additional material for this makefile was written by:\r
-# Peter Fleury\r
-# Tim Henigan\r
-# Colin O'Flynn\r
-# Reiner Patommel\r
-# Markus Pfaff\r
-# Sander Pool\r
-# Frederik Rouleau\r
-# Carlos Lamas\r
-# Dean Camera\r
-# Opendous Inc.\r
-# Denver Gingerich\r
-#\r
-#----------------------------------------------------------------------------\r
-# On command line:\r
-#\r
-# make all = Make software.\r
-#\r
-# make clean = Clean out built project files.\r
-#\r
-# make coff = Convert ELF to AVR COFF.\r
-#\r
-# make extcoff = Convert ELF to AVR Extended COFF.\r
-#\r
-# make program = Download the hex file to the device, using avrdude.\r
-# Please customize the avrdude settings below first!\r
-#\r
-# make dfu = Download the hex file to the device, using dfu-programmer (must\r
-# have dfu-programmer installed).\r
-#\r
-# make flip = Download the hex file to the device, using Atmel FLIP (must\r
-# have Atmel FLIP installed).\r
-#\r
-# make dfu-ee = Download the eeprom file to the device, using dfu-programmer\r
-# (must have dfu-programmer installed).\r
-#\r
-# make flip-ee = Download the eeprom file to the device, using Atmel FLIP\r
-# (must have Atmel FLIP installed).\r
-#\r
-# make doxygen = Generate DoxyGen documentation for the project (must have\r
-# DoxyGen installed)\r
-#\r
-# make debug = Start either simulavr or avarice as specified for debugging,\r
-# with avr-gdb or avr-insight as the front end for debugging.\r
-#\r
-# make filename.s = Just compile filename.c into the assembler code only.\r
-#\r
-# make filename.i = Create a preprocessed source file for use in submitting\r
-# bug reports to the GCC project.\r
-#\r
-# To rebuild project do "make clean" then "make all".\r
-#----------------------------------------------------------------------------\r
-\r
-\r
-# MCU name\r
-ifneq ($(USE_USB),)\r
-MCU = at90usb1287\r
-else\r
-MCU = atmega2560\r
-endif\r
-\r
-# Target architecture (see library "Board Types" documentation).\r
-ARCH = AVR8\r
-\r
-\r
-# Target board (see library "Board Types" documentation, NONE for projects not requiring\r
-# LUFA board drivers). If USER is selected, put custom board drivers in a directory called\r
-# "Board" inside the application directory.\r
-BOARD = USBKEY\r
-\r
-\r
-# Processor frequency.\r
-# This will define a symbol, F_CPU, in all source code files equal to the\r
-# processor frequency in Hz. You can then use this symbol in your source code to\r
-# calculate timings. Do NOT tack on a 'UL' at the end, this will be done\r
-# automatically to create a 32-bit value in your source code.\r
-#\r
-# This will be an integer division of F_USB below, as it is sourced by\r
-# F_USB after it has run through any CPU prescalers. Note that this value\r
-# does not *change* the processor frequency - it should merely be updated to\r
-# reflect the processor speed set externally so that the code can use accurate\r
-# software delays.\r
-F_CPU = 8000000\r
-\r
-\r
-# Input clock frequency.\r
-# This will define a symbol, F_USB, in all source code files equal to the\r
-# input clock frequency (before any prescaling is performed) in Hz. This value may\r
-# differ from F_CPU if prescaling is used on the latter, and is required as the\r
-# raw input clock is fed directly to the PLL sections of the AVR for high speed\r
-# clock generation for the USB and other AVR subsections. Do NOT tack on a 'UL'\r
-# at the end, this will be done automatically to create a 32-bit value in your\r
-# source code.\r
-#\r
-# If no clock division is performed on the input clock inside the AVR (via the\r
-# CPU clock adjust registers or the clock division fuses), this will be equal to F_CPU.\r
-F_USB = $(F_CPU)\r
-\r
-\r
-# Output format. (can be srec, ihex, binary)\r
-FORMAT = ihex\r
-\r
-\r
-# Target file name (without extension).\r
-TARGET = DualVirtualSerial\r
-\r
-\r
-# Object files directory\r
-# To put object files in current directory, use a dot (.), do NOT make\r
-# this an empty or blank macro!\r
-OBJDIR = .\r
-\r
-\r
-# Path to the LUFA library\r
-LUFA_PATH = ../../../..\r
-\r
-\r
-# LUFA library compile-time options and predefined tokens\r
-LUFA_OPTS = -D USB_DEVICE_ONLY\r
-LUFA_OPTS += -D FIXED_CONTROL_ENDPOINT_SIZE=8\r
-LUFA_OPTS += -D FIXED_NUM_CONFIGURATIONS=1\r
-LUFA_OPTS += -D USE_FLASH_DESCRIPTORS\r
-LUFA_OPTS += -D USE_STATIC_OPTIONS="(USB_DEVICE_OPT_FULLSPEED | USB_OPT_REG_ENABLED | USB_OPT_AUTO_PLL)"\r
-\r
-\r
-# Create the LUFA source path variables by including the LUFA root makefile\r
-include $(LUFA_PATH)/LUFA/makefile\r
-\r
-ifneq ($(USE_USB),)\r
-SRC = \\r
- $(TARGET).c \\r
- Descriptors.c \\r
- $(LUFA_SRC_USB) \\r
- $(LUFA_SRC_USBCLASS) \\r
- DualVirtualSerial.c\r
-endif\r
-\r
-# List C source files here. (C dependencies are automatically generated.)\r
-SRC += \\r
- spi_servo.c \\r
- cirbuf_add_buf_head.c \\r
- cirbuf_add_buf_tail.c \\r
- cirbuf_add_head.c \\r
- cirbuf_add_tail.c \\r
- cirbuf_align.c \\r
- cirbuf.c \\r
- cirbuf_del_buf_head.c \\r
- cirbuf_del_buf_tail.c \\r
- cirbuf_del_head.c \\r
- cirbuf_del_tail.c \\r
- cirbuf_get_buf_head.c \\r
- cirbuf_get_buf_tail.c \\r
- cirbuf_get_head.c \\r
- cirbuf_get_tail.c \\r
- commands.c \\r
- commands_gen.c \\r
- main.c \\r
- rc_proto.c \\r
- parse.c \\r
- parse_num.c \\r
- parse_string.c \\r
- rdline.c \\r
- scheduler_add.c \\r
- scheduler.c \\r
- scheduler_del.c \\r
- scheduler_dump.c \\r
- scheduler_interrupt.c \\r
- scheduler_stats.c \\r
- uart.c \\r
- uart_dev_io.c \\r
- uart_events.c \\r
- uart_getconf.c \\r
- uart_recv.c \\r
- uart_recv_nowait.c \\r
- uart_send.c \\r
- uart_send_nowait.c \\r
- uart_setconf.c \\r
- xbee_atcmd.c \\r
- xbee.c \\r
- xbee_neighbor.c \\r
- xbee_proto.c \\r
- xbee_stats.c \\r
- vt100.c \\r
- error.c \\r
- int_show.c \\r
- stackdump.c \\r
- stack_space.c \\r
- timer0_getset.c \\r
- timer0_prescaler.c \\r
- timer0_register_OC_at_tics.c \\r
- timer0_register_OC_in_us.c \\r
- timer0_register_OV.c \\r
- timer0_startstop.c \\r
- timer1_getset.c \\r
- timer1_prescaler.c \\r
- timer1_register_OC_at_tics.c \\r
- timer1_register_OC_in_us.c \\r
- timer1_register_OV.c \\r
- timer1_startstop.c \\r
- timer2_getset.c \\r
- timer2_prescaler.c \\r
- timer2_register_OC_at_tics.c \\r
- timer2_register_OC_in_us.c \\r
- timer2_register_OV.c \\r
- timer2_startstop.c \\r
- timer3_getset.c \\r
- timer3_prescaler.c \\r
- timer3_register_OC_at_tics.c \\r
- timer3_register_OC_in_us.c \\r
- timer3_register_OV.c \\r
- timer3_startstop.c \\r
- timer4_getset.c \\r
- timer4_prescaler.c \\r
- timer4_register_OC_at_tics.c \\r
- timer4_register_OC_in_us.c \\r
- timer4_register_OV.c \\r
- timer4_startstop.c \\r
- timer5_getset.c \\r
- timer5_prescaler.c \\r
- timer5_register_OC_at_tics.c \\r
- timer5_register_OC_in_us.c \\r
- timer5_register_OV.c \\r
- timer5_startstop.c \\r
- timer_conf_check.c \\r
- timer_init.c \\r
- timer_intr.c \\r
- callout.c \\r
- parse_neighbor.c \\r
- parse_atcmd.c \\r
- parse_monitor.c \\r
- time.c \\r
- cmdline.c\r
-\r
-# List C++ source files here. (C dependencies are automatically generated.)\r
-CPPSRC =\r
-\r
-\r
-# List Assembler source files here.\r
-# Make them always end in a capital .S. Files ending in a lowercase .s\r
-# will not be considered source files but generated files (assembler\r
-# output from the compiler), and will be deleted upon "make clean"!\r
-# Even though the DOS/Win* filesystem matches both .s and .S the same,\r
-# it will preserve the spelling of the filenames, and gcc itself does\r
-# care about how the name is spelled on its command-line.\r
-ASRC =\r
-\r
-\r
-# Optimization level, can be [0, 1, 2, 3, s].\r
-# 0 = turn off optimization. s = optimize for size.\r
-# (Note: 3 is not always the best optimization level. See avr-libc FAQ.)\r
-OPT = s\r
-\r
-\r
-# Debugging format.\r
-# Native formats for AVR-GCC's -g are dwarf-2 [default] or stabs.\r
-# AVR Studio 4.10 requires dwarf-2.\r
-# AVR [Extended] COFF format requires stabs, plus an avr-objcopy run.\r
-DEBUG = dwarf-2\r
-\r
-\r
-# List any extra directories to look for include files here.\r
-# Each directory must be seperated by a space.\r
-# Use forward slashes for directory separators.\r
-# For a directory that has spaces, enclose it in quotes.\r
-EXTRAINCDIRS = $(LUFA_PATH)/\r
-\r
-\r
-# Compiler flag to set the C Standard level.\r
-# c89 = "ANSI" C\r
-# gnu89 = c89 plus GCC extensions\r
-# c99 = ISO C99 standard (not yet fully implemented)\r
-# gnu99 = c99 plus GCC extensions\r
-CSTANDARD = -std=c99\r
-\r
-\r
-# Place -D or -U options here for C sources\r
-CDEFS = -DF_CPU=$(F_CPU)UL\r
-CDEFS += -DF_USB=$(F_USB)UL\r
-CDEFS += -DBOARD=BOARD_$(BOARD) -DARCH=ARCH_$(ARCH)\r
-CDEFS += $(LUFA_OPTS)\r
-\r
-\r
-# Place -D or -U options here for ASM sources\r
-ADEFS = -DF_CPU=$(F_CPU)\r
-ADEFS += -DF_USB=$(F_USB)UL\r
-ADEFS += -DBOARD=BOARD_$(BOARD) -DARCH=ARCH_$(ARCH)\r
-ADEFS += $(LUFA_OPTS)\r
-\r
-# Place -D or -U options here for C++ sources\r
-CPPDEFS = -DF_CPU=$(F_CPU)UL\r
-CPPDEFS += -DF_USB=$(F_USB)UL\r
-CPPDEFS += -DBOARD=BOARD_$(BOARD) -DARCH=ARCH_$(ARCH)\r
-CPPDEFS += $(LUFA_OPTS)\r
-#CPPDEFS += -D__STDC_LIMIT_MACROS\r
-#CPPDEFS += -D__STDC_CONSTANT_MACROS\r
-\r
-\r
-\r
-#---------------- Compiler Options C ----------------\r
-# -g*: generate debugging information\r
-# -O*: optimization level\r
-# -f...: tuning, see GCC manual and avr-libc documentation\r
-# -Wall...: warning level\r
-# -Wa,...: tell GCC to pass this to the assembler.\r
-# -adhlns...: create assembler listing\r
-CFLAGS = -g$(DEBUG)\r
-CFLAGS += $(CDEFS)\r
-CFLAGS += -O$(OPT)\r
-CFLAGS += -funsigned-char\r
-CFLAGS += -funsigned-bitfields\r
-CFLAGS += -ffunction-sections\r
-CFLAGS += -fno-inline-small-functions\r
-CFLAGS += -fpack-struct\r
-CFLAGS += -fshort-enums\r
-CFLAGS += -fno-strict-aliasing\r
-CFLAGS += -Wall -Werror\r
-CFLAGS += -Wstrict-prototypes\r
-CFLAGS += -ffreestanding\r
-#CFLAGS += -mshort-calls\r
-#CFLAGS += -fno-unit-at-a-time\r
-#CFLAGS += -Wundef\r
-#CFLAGS += -Wunreachable-code\r
-#CFLAGS += -Wsign-compare\r
-CFLAGS += -Wa,-adhlns=$(<:%.c=$(OBJDIR)/%.lst)\r
-CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS))\r
-CFLAGS += $(CSTANDARD)\r
-CFLAGS += -std=gnu99\r
-ifneq ($(USE_USB),)\r
-CFLAGS += -DUSE_USB\r
-endif\r
-\r
-\r
-#---------------- Compiler Options C++ ----------------\r
-# -g*: generate debugging information\r
-# -O*: optimization level\r
-# -f...: tuning, see GCC manual and avr-libc documentation\r
-# -Wall...: warning level\r
-# -Wa,...: tell GCC to pass this to the assembler.\r
-# -adhlns...: create assembler listing\r
-CPPFLAGS = -g$(DEBUG)\r
-CPPFLAGS += $(CPPDEFS)\r
-CPPFLAGS += -O$(OPT)\r
-CPPFLAGS += -funsigned-char\r
-CPPFLAGS += -funsigned-bitfields\r
-CPPFLAGS += -fpack-struct\r
-CPPFLAGS += -fshort-enums\r
-CPPFLAGS += -fno-exceptions\r
-CPPFLAGS += -Wall\r
-CPPFLAGS += -Wundef\r
-#CPPFLAGS += -mshort-calls\r
-#CPPFLAGS += -fno-unit-at-a-time\r
-#CPPFLAGS += -Wstrict-prototypes\r
-#CPPFLAGS += -Wunreachable-code\r
-#CPPFLAGS += -Wsign-compare\r
-CPPFLAGS += -Wa,-adhlns=$(<:%.cpp=$(OBJDIR)/%.lst)\r
-CPPFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS))\r
-#CPPFLAGS += $(CSTANDARD)\r
-\r
-\r
-#---------------- Assembler Options ----------------\r
-# -Wa,...: tell GCC to pass this to the assembler.\r
-# -adhlns: create listing\r
-# -gstabs: have the assembler create line number information; note that\r
-# for use in COFF files, additional information about filenames\r
-# and function names needs to be present in the assembler source\r
-# files -- see avr-libc docs [FIXME: not yet described there]\r
-# -listing-cont-lines: Sets the maximum number of continuation lines of hex\r
-# dump that will be displayed for a given single line of source input.\r
-ASFLAGS = $(ADEFS) -Wa,-adhlns=$(<:%.S=$(OBJDIR)/%.lst),-gstabs,--listing-cont-lines=100\r
-\r
-\r
-#---------------- Library Options ----------------\r
-# Minimalistic printf version\r
-PRINTF_LIB_MIN = -Wl,-u,vfprintf -lprintf_min\r
-\r
-# Floating point printf version (requires MATH_LIB = -lm below)\r
-PRINTF_LIB_FLOAT = -Wl,-u,vfprintf -lprintf_flt\r
-\r
-# If this is left blank, then it will use the Standard printf version.\r
-PRINTF_LIB =\r
-#PRINTF_LIB = $(PRINTF_LIB_MIN)\r
-#PRINTF_LIB = $(PRINTF_LIB_FLOAT)\r
-\r
-\r
-# Minimalistic scanf version\r
-SCANF_LIB_MIN = -Wl,-u,vfscanf -lscanf_min\r
-\r
-# Floating point + %[ scanf version (requires MATH_LIB = -lm below)\r
-SCANF_LIB_FLOAT = -Wl,-u,vfscanf -lscanf_flt\r
-\r
-# If this is left blank, then it will use the Standard scanf version.\r
-SCANF_LIB =\r
-#SCANF_LIB = $(SCANF_LIB_MIN)\r
-#SCANF_LIB = $(SCANF_LIB_FLOAT)\r
-\r
-\r
-MATH_LIB = -lm\r
-\r
-\r
-# List any extra directories to look for libraries here.\r
-# Each directory must be seperated by a space.\r
-# Use forward slashes for directory separators.\r
-# For a directory that has spaces, enclose it in quotes.\r
-EXTRALIBDIRS =\r
-\r
-\r
-\r
-#---------------- External Memory Options ----------------\r
-\r
-# 64 KB of external RAM, starting after internal RAM (ATmega128!),\r
-# used for variables (.data/.bss) and heap (malloc()).\r
-#EXTMEMOPTS = -Wl,-Tdata=0x801100,--defsym=__heap_end=0x80ffff\r
-\r
-# 64 KB of external RAM, starting after internal RAM (ATmega128!),\r
-# only used for heap (malloc()).\r
-#EXTMEMOPTS = -Wl,--section-start,.data=0x801100,--defsym=__heap_end=0x80ffff\r
-\r
-EXTMEMOPTS =\r
-\r
-\r
-\r
-#---------------- Linker Options ----------------\r
-# -Wl,...: tell GCC to pass this to linker.\r
-# -Map: create map file\r
-# --cref: add cross reference to map file\r
-LDFLAGS = -Wl,-Map=$(TARGET).map,--cref\r
-LDFLAGS += -Wl,--relax\r
-LDFLAGS += -Wl,--gc-sections\r
-LDFLAGS += $(EXTMEMOPTS)\r
-LDFLAGS += $(patsubst %,-L%,$(EXTRALIBDIRS))\r
-LDFLAGS += $(PRINTF_LIB) $(SCANF_LIB) $(MATH_LIB)\r
-ifeq ($(USE_USB),)\r
-LDFLAGS = -T avr6.x\r
-endif\r
-\r
-\r
-#---------------- Programming Options (avrdude) ----------------\r
-\r
-# Programming hardware\r
-# Type: avrdude -c ?\r
-# to get a full listing.\r
-#\r
-AVRDUDE_PROGRAMMER = jtagmkII\r
-\r
-# com1 = serial port. Use lpt1 to connect to parallel port.\r
-AVRDUDE_PORT = usb\r
-\r
-AVRDUDE_WRITE_FLASH = -U flash:w:$(TARGET).hex\r
-#AVRDUDE_WRITE_EEPROM = -U eeprom:w:$(TARGET).eep\r
-\r
-\r
-# Uncomment the following if you want avrdude's erase cycle counter.\r
-# Note that this counter needs to be initialized first using -Yn,\r
-# see avrdude manual.\r
-#AVRDUDE_ERASE_COUNTER = -y\r
-\r
-# Uncomment the following if you do /not/ wish a verification to be\r
-# performed after programming the device.\r
-#AVRDUDE_NO_VERIFY = -V\r
-\r
-# Increase verbosity level. Please use this when submitting bug\r
-# reports about avrdude. See <http://savannah.nongnu.org/projects/avrdude>\r
-# to submit bug reports.\r
-#AVRDUDE_VERBOSE = -v -v\r
-\r
-AVRDUDE_FLAGS = -p $(MCU) -P $(AVRDUDE_PORT) -c $(AVRDUDE_PROGRAMMER)\r
-AVRDUDE_FLAGS += $(AVRDUDE_NO_VERIFY)\r
-AVRDUDE_FLAGS += $(AVRDUDE_VERBOSE)\r
-AVRDUDE_FLAGS += $(AVRDUDE_ERASE_COUNTER)\r
-\r
-\r
-\r
-#---------------- Debugging Options ----------------\r
-\r
-# For simulavr only - target MCU frequency.\r
-DEBUG_MFREQ = $(F_CPU)\r
-\r
-# Set the DEBUG_UI to either gdb or insight.\r
-# DEBUG_UI = gdb\r
-DEBUG_UI = insight\r
-\r
-# Set the debugging back-end to either avarice, simulavr.\r
-DEBUG_BACKEND = avarice\r
-#DEBUG_BACKEND = simulavr\r
-\r
-# GDB Init Filename.\r
-GDBINIT_FILE = __avr_gdbinit\r
-\r
-# When using avarice settings for the JTAG\r
-JTAG_DEV = /dev/com1\r
-\r
-# Debugging port used to communicate between GDB / avarice / simulavr.\r
-DEBUG_PORT = 4242\r
-\r
-# Debugging host used to communicate between GDB / avarice / simulavr, normally\r
-# just set to localhost unless doing some sort of crazy debugging when\r
-# avarice is running on a different computer.\r
-DEBUG_HOST = localhost\r
-\r
-\r
-\r
-#============================================================================\r
-\r
-\r
-# Define programs and commands.\r
-SHELL = sh\r
-CC = avr-gcc\r
-OBJCOPY = avr-objcopy\r
-OBJDUMP = avr-objdump\r
-SIZE = avr-size\r
-AR = avr-ar rcs\r
-NM = avr-nm\r
-AVRDUDE = avrdude\r
-REMOVE = rm -f\r
-REMOVEDIR = rm -rf\r
-COPY = cp\r
-WINSHELL = cmd\r
-\r
-\r
-# Define Messages\r
-# English\r
-MSG_ERRORS_NONE = Errors: none\r
-MSG_BEGIN = -------- begin --------\r
-MSG_END = -------- end --------\r
-MSG_SIZE_BEFORE = Size before:\r
-MSG_SIZE_AFTER = Size after:\r
-MSG_COFF = Converting to AVR COFF:\r
-MSG_EXTENDED_COFF = Converting to AVR Extended COFF:\r
-MSG_FLASH = Creating load file for Flash:\r
-MSG_EEPROM = Creating load file for EEPROM:\r
-MSG_EXTENDED_LISTING = Creating Extended Listing:\r
-MSG_SYMBOL_TABLE = Creating Symbol Table:\r
-MSG_LINKING = Linking:\r
-MSG_COMPILING = Compiling C:\r
-MSG_COMPILING_CPP = Compiling C++:\r
-MSG_ASSEMBLING = Assembling:\r
-MSG_CLEANING = Cleaning project:\r
-MSG_CREATING_LIBRARY = Creating library:\r
-\r
-\r
-\r
-\r
-# Define all object files.\r
-OBJ = $(SRC:%.c=$(OBJDIR)/%.o) $(CPPSRC:%.cpp=$(OBJDIR)/%.o) $(ASRC:%.S=$(OBJDIR)/%.o)\r
-\r
-# Define all listing files.\r
-LST = $(SRC:%.c=$(OBJDIR)/%.lst) $(CPPSRC:%.cpp=$(OBJDIR)/%.lst) $(ASRC:%.S=$(OBJDIR)/%.lst)\r
-\r
-\r
-# Compiler flags to generate dependency files.\r
-GENDEPFLAGS = -MMD -MP -MF .dep/$(@F).d\r
-\r
-\r
-# Combine all necessary flags and optional flags.\r
-# Add target processor to flags.\r
-ALL_CFLAGS = -mmcu=$(MCU) -I. $(CFLAGS) $(GENDEPFLAGS)\r
-ALL_CPPFLAGS = -mmcu=$(MCU) -I. -x c++ $(CPPFLAGS) $(GENDEPFLAGS)\r
-ALL_ASFLAGS = -mmcu=$(MCU) -I. -x assembler-with-cpp $(ASFLAGS)\r
-\r
-\r
-\r
-\r
-\r
-# Default target.\r
-all: begin gccversion sizebefore build sizeafter end\r
-\r
-# Change the build target to build a HEX file or a library.\r
-build: elf hex eep lss sym\r
-#build: lib\r
-\r
-\r
-elf: $(TARGET).elf\r
-hex: $(TARGET).hex\r
-eep: $(TARGET).eep\r
-lss: $(TARGET).lss\r
-sym: $(TARGET).sym\r
-LIBNAME=lib$(TARGET).a\r
-lib: $(LIBNAME)\r
-\r
-\r
-\r
-# Eye candy.\r
-# AVR Studio 3.x does not check make's exit code but relies on\r
-# the following magic strings to be generated by the compile job.\r
-begin:\r
- @echo\r
- @echo $(MSG_BEGIN)\r
-\r
-end:\r
- @echo $(MSG_END)\r
- @echo\r
-\r
-\r
-# Display size of file.\r
-HEXSIZE = $(SIZE) --target=$(FORMAT) $(TARGET).hex\r
-ELFSIZE = $(SIZE) $(MCU_FLAG) $(FORMAT_FLAG) $(TARGET).elf\r
-MCU_FLAG = $(shell $(SIZE) --help | grep -- --mcu > /dev/null && echo --mcu=$(MCU) )\r
-FORMAT_FLAG = $(shell $(SIZE) --help | grep -- --format=.*avr > /dev/null && echo --format=avr )\r
-\r
-\r
-sizebefore:\r
- @if test -f $(TARGET).elf; then echo; echo $(MSG_SIZE_BEFORE); $(ELFSIZE); \\r
- 2>/dev/null; echo; fi\r
-\r
-sizeafter:\r
- @if test -f $(TARGET).elf; then echo; echo $(MSG_SIZE_AFTER); $(ELFSIZE); \\r
- 2>/dev/null; echo; fi\r
-\r
-\r
-\r
-# Display compiler version information.\r
-gccversion :\r
- @$(CC) --version\r
-\r
-\r
-# Program the device.\r
-program: $(TARGET).hex $(TARGET).eep\r
- $(AVRDUDE) $(AVRDUDE_FLAGS) $(AVRDUDE_WRITE_FLASH) $(AVRDUDE_WRITE_EEPROM)\r
-\r
-flip: $(TARGET).hex\r
- batchisp -hardware usb -device $(MCU) -operation erase f\r
- batchisp -hardware usb -device $(MCU) -operation loadbuffer $(TARGET).hex program\r
- batchisp -hardware usb -device $(MCU) -operation start reset 0\r
-\r
-dfu: $(TARGET).hex\r
- dfu-programmer $(MCU) erase\r
- dfu-programmer $(MCU) flash $(TARGET).hex\r
- dfu-programmer $(MCU) reset\r
-\r
-flip-ee: $(TARGET).hex $(TARGET).eep\r
- $(COPY) $(TARGET).eep $(TARGET)eep.hex\r
- batchisp -hardware usb -device $(MCU) -operation memory EEPROM erase\r
- batchisp -hardware usb -device $(MCU) -operation memory EEPROM loadbuffer $(TARGET)eep.hex program\r
- batchisp -hardware usb -device $(MCU) -operation start reset 0\r
- $(REMOVE) $(TARGET)eep.hex\r
-\r
-dfu-ee: $(TARGET).hex $(TARGET).eep\r
- dfu-programmer $(MCU) eeprom-flash $(TARGET).eep\r
- dfu-programmer $(MCU) reset\r
-\r
-\r
-# Generate avr-gdb config/init file which does the following:\r
-# define the reset signal, load the target file, connect to target, and set\r
-# a breakpoint at main().\r
-gdb-config:\r
- @$(REMOVE) $(GDBINIT_FILE)\r
- @echo define reset >> $(GDBINIT_FILE)\r
- @echo SIGNAL SIGHUP >> $(GDBINIT_FILE)\r
- @echo end >> $(GDBINIT_FILE)\r
- @echo file $(TARGET).elf >> $(GDBINIT_FILE)\r
- @echo target remote $(DEBUG_HOST):$(DEBUG_PORT) >> $(GDBINIT_FILE)\r
-ifeq ($(DEBUG_BACKEND),simulavr)\r
- @echo load >> $(GDBINIT_FILE)\r
-endif\r
- @echo break main >> $(GDBINIT_FILE)\r
-\r
-debug: gdb-config $(TARGET).elf\r
-ifeq ($(DEBUG_BACKEND), avarice)\r
- @echo Starting AVaRICE - Press enter when "waiting to connect" message displays.\r
- @$(WINSHELL) /c start avarice --jtag $(JTAG_DEV) --erase --program --file \\r
- $(TARGET).elf $(DEBUG_HOST):$(DEBUG_PORT)\r
- @$(WINSHELL) /c pause\r
-\r
-else\r
- @$(WINSHELL) /c start simulavr --gdbserver --device $(MCU) --clock-freq \\r
- $(DEBUG_MFREQ) --port $(DEBUG_PORT)\r
-endif\r
- @$(WINSHELL) /c start avr-$(DEBUG_UI) --command=$(GDBINIT_FILE)\r
-\r
-\r
-\r
-\r
-# Convert ELF to COFF for use in debugging / simulating in AVR Studio or VMLAB.\r
-COFFCONVERT = $(OBJCOPY) --debugging\r
-COFFCONVERT += --change-section-address .data-0x800000\r
-COFFCONVERT += --change-section-address .bss-0x800000\r
-COFFCONVERT += --change-section-address .noinit-0x800000\r
-COFFCONVERT += --change-section-address .eeprom-0x810000\r
-\r
-\r
-\r
-coff: $(TARGET).elf\r
- @echo\r
- @echo $(MSG_COFF) $(TARGET).cof\r
- $(COFFCONVERT) -O coff-avr $< $(TARGET).cof\r
-\r
-\r
-extcoff: $(TARGET).elf\r
- @echo\r
- @echo $(MSG_EXTENDED_COFF) $(TARGET).cof\r
- $(COFFCONVERT) -O coff-ext-avr $< $(TARGET).cof\r
-\r
-\r
-\r
-# Create final output files (.hex, .eep) from ELF output file.\r
-%.hex: %.elf\r
- @echo\r
- @echo $(MSG_FLASH) $@\r
- $(OBJCOPY) -O binary -R .eeprom -R .fuse -R .lock $< $(TARGET).bin\r
- $(OBJCOPY) -O $(FORMAT) -R .eeprom -R .fuse -R .lock $< $@\r
-\r
-%.eep: %.elf\r
- @echo\r
- @echo $(MSG_EEPROM) $@\r
- -$(OBJCOPY) -j .eeprom --set-section-flags=.eeprom="alloc,load" \\r
- --change-section-lma .eeprom=0 --no-change-warnings -O $(FORMAT) $< $@ || exit 0\r
-\r
-# Create extended listing file from ELF output file.\r
-%.lss: %.elf\r
- @echo\r
- @echo $(MSG_EXTENDED_LISTING) $@\r
- $(OBJDUMP) -h -S -z $< > $@\r
-\r
-# Create a symbol table from ELF output file.\r
-%.sym: %.elf\r
- @echo\r
- @echo $(MSG_SYMBOL_TABLE) $@\r
- $(NM) -n $< > $@\r
-\r
-\r
-\r
-# Create library from object files.\r
-.SECONDARY : $(TARGET).a\r
-.PRECIOUS : $(OBJ)\r
-%.a: $(OBJ)\r
- @echo\r
- @echo $(MSG_CREATING_LIBRARY) $@\r
- $(AR) $@ $(OBJ)\r
-\r
-\r
-# Link: create ELF output file from object files.\r
-.SECONDARY : $(TARGET).elf\r
-.PRECIOUS : $(OBJ)\r
-%.elf: $(OBJ)\r
- @echo\r
- @echo $(MSG_LINKING) $@\r
- $(CC) $(ALL_CFLAGS) $^ --output $@ $(LDFLAGS)\r
-\r
-\r
-# Compile: create object files from C source files.\r
-$(OBJDIR)/%.o : %.c\r
- @echo\r
- @echo $(MSG_COMPILING) $<\r
- $(CC) -c $(ALL_CFLAGS) $< -o $@\r
-\r
-\r
-# Compile: create object files from C++ source files.\r
-$(OBJDIR)/%.o : %.cpp\r
- @echo\r
- @echo $(MSG_COMPILING_CPP) $<\r
- $(CC) -c $(ALL_CPPFLAGS) $< -o $@\r
-\r
-\r
-# Compile: create assembler files from C source files.\r
-%.s : %.c\r
- $(CC) -S $(ALL_CFLAGS) $< -o $@\r
-\r
-\r
-# Compile: create assembler files from C++ source files.\r
-%.s : %.cpp\r
- $(CC) -S $(ALL_CPPFLAGS) $< -o $@\r
-\r
-\r
-# Assemble: create object files from assembler source files.\r
-$(OBJDIR)/%.o : %.S\r
- @echo\r
- @echo $(MSG_ASSEMBLING) $<\r
- $(CC) -c $(ALL_ASFLAGS) $< -o $@\r
-\r
-\r
-# Create preprocessed source for use in sending a bug report.\r
-%.i : %.c\r
- $(CC) -E -mmcu=$(MCU) -I. $(CFLAGS) $< -o $@\r
-\r
-\r
-# Target: clean project.\r
-clean: begin clean_list end\r
-\r
-clean_list :\r
- @echo\r
- @echo $(MSG_CLEANING)\r
- $(REMOVE) $(TARGET).hex\r
- $(REMOVE) $(TARGET).eep\r
- $(REMOVE) $(TARGET).cof\r
- $(REMOVE) $(TARGET).elf\r
- $(REMOVE) $(TARGET).map\r
- $(REMOVE) $(TARGET).sym\r
- $(REMOVE) $(TARGET).lss\r
- $(REMOVE) $(SRC:%.c=$(OBJDIR)/%.o) $(CPPSRC:%.cpp=$(OBJDIR)/%.o) $(ASRC:%.S=$(OBJDIR)/%.o)\r
- $(REMOVE) $(SRC:%.c=$(OBJDIR)/%.lst) $(CPPSRC:%.cpp=$(OBJDIR)/%.lst) $(ASRC:%.S=$(OBJDIR)/%.lst)\r
- $(REMOVE) $(SRC:.c=.s)\r
- $(REMOVE) $(SRC:.c=.d)\r
- $(REMOVE) $(SRC:.c=.i)\r
- $(REMOVEDIR) .dep\r
-\r
-doxygen:\r
- @echo Generating Project Documentation \($(TARGET)\)...\r
- @doxygen Doxygen.conf\r
- @echo Documentation Generation Complete.\r
-\r
-clean_doxygen:\r
- rm -rf Documentation\r
-\r
-checksource:\r
- @for f in $(SRC) $(CPPSRC) $(ASRC); do \\r
- if [ -f $$f ]; then \\r
- echo "Found Source File: $$f" ; \\r
- else \\r
- echo "Source File Not Found: $$f" ; \\r
- fi; done \r
-\r
-\r
-# Create object files directory\r
-$(shell mkdir $(OBJDIR) 2>/dev/null)\r
-\r
-\r
-# Include the dependency files.\r
--include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*)\r
-\r
-\r
-# Listing of phony targets.\r
-.PHONY : all begin finish end sizebefore sizeafter gccversion \\r
-build elf hex eep lss sym coff extcoff doxygen clean \\r
-clean_list clean_doxygen program dfu flip flip-ee dfu-ee \\r
-debug gdb-config checksource\r
-\r
+++ /dev/null
-/*
- * Copyright Droids Corporation (2007)
- * Olivier MATZ <zer0@droids-corp.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: parse.c,v 1.1.2.11 2009-04-07 20:00:46 zer0 Exp $
- *
- *
- */
-
-#include <stdio.h>
-#include <string.h>
-#include <inttypes.h>
-#include <ctype.h>
-
-#include <aversive/pgmspace.h>
-
-#include "parse.h"
-
-#ifdef HOST_VERSION
-#define pgm_read_pgmptr(x) ((void *)(*(x)))
-#else
-#define pgm_read_pgmptr(x) (void *)pgm_read_word(x)
-#endif
-
-//#define CMDLINE_DEBUG
-//#define debug_printf printf
-#define debug_printf(args...) do {} while(0)
-
-
-static int
-isendofline(char c)
-{
- if (c == '\n' ||
- c == '\r' )
- return 1;
- return 0;
-}
-
-static int
-iscomment(char c)
-{
- if (c == '#')
- return 1;
- return 0;
-}
-
-int
-isendoftoken(char c)
-{
- if (!c || iscomment(c) || isblank(c) || isendofline(c))
- return 1;
- return 0;
-}
-
-static uint8_t
-nb_common_chars(const char * s1, const char * s2)
-{
- uint8_t i=0;
-
- while (*s1==*s2 && *s1 && *s2) {
- s1++;
- s2++;
- i++;
- }
- return i;
-}
-
-/**
- * try to match the buffer with an instruction (only the first
- * nb_match_token tokens if != 0). Return 0 if we match all the
- * tokens, else the number of matched tokens, else -1.
- */
-static int8_t
-match_inst(parse_pgm_inst_t *inst, const char * buf, uint8_t nb_match_token,
- void * result_buf)
-{
- uint8_t token_num=0;
- parse_pgm_token_hdr_t * token_p;
- uint8_t i=0;
- int8_t n = 0;
- struct token_hdr token_hdr;
-
- token_p = (parse_pgm_token_hdr_t *)pgm_read_pgmptr(&inst->tokens[token_num]);
- if (token_p)
- memcpy_P(&token_hdr, token_p, sizeof(token_hdr));
-
- /* check if we match all tokens of inst */
- while (token_p && (!nb_match_token || i<nb_match_token)) {
- debug_printf("TK\n");
- /* skip spaces */
- while (isblank(*buf)) {
- buf++;
- }
-
- /* end of buf */
- if ( isendofline(*buf) || iscomment(*buf) )
- break;
-
- n = token_hdr.ops->parse(token_p, buf, (result_buf ? result_buf+token_hdr.offset : NULL));
- if ( n < 0 )
- break;
- debug_printf("TK parsed (len=%d)\n", n);
- i++;
- buf += n;
-
- token_num ++;
- token_p = (parse_pgm_token_hdr_t *)pgm_read_pgmptr(&inst->tokens[token_num]);
- if (token_p)
- memcpy_P(&token_hdr, token_p, sizeof(token_hdr));
- }
-
- /* does not match */
- if (i==0)
- return -1;
-
- /* in case we want to match a specific num of token */
- if (nb_match_token) {
- if (i == nb_match_token) {
- return 0;
- }
- return i;
- }
-
- /* we don't match all the tokens */
- if (token_p) {
- return i;
- }
-
- /* are there are some tokens more */
- while (isblank(*buf)) {
- buf++;
- }
-
- /* end of buf */
- if ( isendofline(*buf) || iscomment(*buf) )
- return 0;
-
- /* garbage after inst */
- return i;
-}
-
-
-int8_t
-parse(parse_pgm_ctx_t ctx[], const char * buf)
-{
- uint8_t inst_num=0;
- parse_pgm_inst_t * inst;
- const char * curbuf;
- char result_buf[256]; /* XXX align, size zé in broblém */
- void (*f)(void *, void *) = NULL;
- void * data = NULL;
- int comment = 0;
- int linelen = 0;
- int parse_it = 0;
- int8_t err = PARSE_NOMATCH;
- int8_t tok;
-#ifdef CMDLINE_DEBUG
- char debug_buf[64];
-#endif
-
- /*
- * - look if the buffer contains at least one line
- * - look if line contains only spaces or comments
- * - count line length
- */
- curbuf = buf;
- while (! isendofline(*curbuf)) {
- if ( *curbuf == '\0' ) {
- debug_printf("Incomplete buf (len=%d)\n", linelen);
- return 0;
- }
- if ( iscomment(*curbuf) ) {
- comment = 1;
- }
- if ( ! isblank(*curbuf) && ! comment) {
- parse_it = 1;
- }
- curbuf++;
- linelen++;
- }
-
- /* skip all endofline chars */
- while (isendofline(buf[linelen])) {
- linelen++;
- }
-
- /* empty line */
- if ( parse_it == 0 ) {
- debug_printf("Empty line (len=%d)\n", linelen);
- return linelen;
- }
-
-#ifdef CMDLINE_DEBUG
- snprintf(debug_buf, (linelen>64 ? 64 : linelen), "%s", buf);
- debug_printf("Parse line : len=%d, <%s>\n", linelen, debug_buf);
-#endif
-
- /* parse it !! */
- inst = (parse_pgm_inst_t *)pgm_read_pgmptr(ctx+inst_num);
- while (inst) {
- debug_printf("INST\n");
-
- /* fully parsed */
- tok = match_inst(inst, buf, 0, result_buf);
-
- if (tok > 0) /* we matched at least one token */
- err = PARSE_BAD_ARGS;
-
- else if (!tok) {
- debug_printf("INST fully parsed\n");
- /* skip spaces */
- while (isblank(*curbuf)) {
- curbuf++;
- }
-
- /* if end of buf -> there is no garbage after inst */
- if (isendofline(*curbuf) || iscomment(*curbuf)) {
- if (!f) {
- memcpy_P(&f, &inst->f, sizeof(f));
- memcpy_P(&data, &inst->data, sizeof(data));
- }
- else {
- /* more than 1 inst matches */
- err = PARSE_AMBIGUOUS;
- f=NULL;
- debug_printf("Ambiguous cmd\n");
- break;
- }
- }
- }
-
- inst_num ++;
- inst = (parse_pgm_inst_t *)pgm_read_pgmptr(ctx+inst_num);
- }
-
- /* call func */
- if (f) {
- f(result_buf, data);
- }
-
- /* no match */
- else {
- debug_printf("No match err=%d\n", err);
- return err;
- }
-
- return linelen;
-}
-
-int8_t
-complete(parse_pgm_ctx_t ctx[], const char *buf, int16_t *state,
- char *dst, uint8_t size)
-{
- const char * incomplete_token = buf;
- uint8_t inst_num = 0;
- parse_pgm_inst_t *inst;
- parse_pgm_token_hdr_t *token_p;
- struct token_hdr token_hdr;
- char tmpbuf[64], completion_buf[64];
- uint8_t incomplete_token_len;
- int8_t completion_len = -1;
- int8_t nb_token = 0;
- uint8_t i, n;
- int8_t l;
- uint8_t nb_completable;
- uint8_t nb_non_completable;
- int16_t local_state=0;
- prog_char *help_str;
-
- debug_printf("%s called\n", __FUNCTION__);
- /* count the number of complete token to parse */
- for (i=0 ; buf[i] ; i++) {
- if (!isblank(buf[i]) && isblank(buf[i+1]))
- nb_token++;
- if (isblank(buf[i]) && !isblank(buf[i+1]))
- incomplete_token = buf+i+1;
- }
- incomplete_token_len = strlen(incomplete_token);
-
- /* first call -> do a first pass */
- if (*state <= 0) {
- debug_printf("try complete <%s>\n", buf);
- debug_printf("there is %d complete tokens, <%s> is incomplete\n", nb_token, incomplete_token);
-
- nb_completable = 0;
- nb_non_completable = 0;
-
- inst = (parse_pgm_inst_t *)pgm_read_pgmptr(ctx+inst_num);
- while (inst) {
- /* parse the first tokens of the inst */
- if (nb_token && match_inst(inst, buf, nb_token, NULL))
- goto next;
-
- debug_printf("instruction match \n");
- token_p = (parse_pgm_token_hdr_t *) pgm_read_pgmptr(&inst->tokens[nb_token]);
- if (token_p)
- memcpy_P(&token_hdr, token_p, sizeof(token_hdr));
-
- /* non completable */
- if (!token_p ||
- !token_hdr.ops->complete_get_nb ||
- !token_hdr.ops->complete_get_elt ||
- (n = token_hdr.ops->complete_get_nb(token_p)) == 0) {
- nb_non_completable++;
- goto next;
- }
-
- debug_printf("%d choices for this token\n", n);
- for (i=0 ; i<n ; i++) {
- if (token_hdr.ops->complete_get_elt(token_p, i, tmpbuf, sizeof(tmpbuf)) < 0)
- continue;
- strcat_P(tmpbuf, PSTR(" ")); /* we have at least room for one char */
- debug_printf(" choice <%s>\n", tmpbuf);
- /* does the completion match the beginning of the word ? */
- if (!strncmp(incomplete_token, tmpbuf, incomplete_token_len)) {
- if (completion_len == -1) {
- strcpy(completion_buf, tmpbuf+incomplete_token_len);
- completion_len = strlen(tmpbuf+incomplete_token_len);
-
- }
- else {
- completion_len = nb_common_chars(completion_buf,
- tmpbuf+incomplete_token_len);
- completion_buf[completion_len] = 0;
- }
- nb_completable++;
- }
- }
- next:
- inst_num ++;
- inst = (parse_pgm_inst_t *)pgm_read_pgmptr(ctx+inst_num);
- }
-
- debug_printf("total choices %d for this completion\n", nb_completable);
-
- /* no possible completion */
- if (nb_completable == 0 && nb_non_completable == 0)
- return 0;
-
- /* if multichoice is not required */
- if (*state == 0 && incomplete_token_len > 0) {
- /* one or several choices starting with the
- same chars */
- if (completion_len > 0) {
- if (completion_len + 1 > size)
- return 0;
-
- strcpy(dst, completion_buf);
- return 2;
- }
- }
- }
-
- /* init state correctly */
- if (*state == -1)
- *state = 0;
-
- debug_printf("Multiple choice STATE=%d\n", *state);
-
- inst_num = 0;
- inst = (parse_pgm_inst_t *)pgm_read_pgmptr(ctx+inst_num);
- while (inst) {
- /* we need to redo it */
- inst = (parse_pgm_inst_t *)pgm_read_pgmptr(ctx+inst_num);
-
- if (nb_token && match_inst(inst, buf, nb_token, NULL))
- goto next2;
-
- token_p = (parse_pgm_token_hdr_t *)pgm_read_pgmptr(&inst->tokens[nb_token]);
- if (token_p)
- memcpy_P(&token_hdr, token_p, sizeof(token_hdr));
-
- /* one choice for this token */
- if (!token_p ||
- !token_hdr.ops->complete_get_nb ||
- !token_hdr.ops->complete_get_elt ||
- (n = token_hdr.ops->complete_get_nb(token_p)) == 0) {
- if (local_state < *state) {
- local_state++;
- goto next2;
- }
- (*state)++;
- if (token_p && token_hdr.ops->get_help) {
- token_hdr.ops->get_help(token_p, tmpbuf, sizeof(tmpbuf));
- help_str = (prog_char *) pgm_read_pgmptr(&inst->help_str);
- if (help_str)
- snprintf_P(dst, size, PSTR("[%s]: "PGMS_FMT""), tmpbuf, help_str);
- else
- snprintf_P(dst, size, PSTR("[%s]: No help"), tmpbuf);
- }
- else {
- snprintf_P(dst, size, PSTR("[RETURN]"));
- }
- return 1;
- }
-
- /* several choices */
- for (i=0 ; i<n ; i++) {
- if (token_hdr.ops->complete_get_elt(token_p, i, tmpbuf, sizeof(tmpbuf)) < 0)
- continue;
- strcat_P(tmpbuf, PSTR(" ")); /* we have at least room for one char */
- debug_printf(" choice <%s>\n", tmpbuf);
- /* does the completion match the beginning of the word ? */
- if (!strncmp(incomplete_token, tmpbuf, incomplete_token_len)) {
- if (local_state < *state) {
- local_state++;
- continue;
- }
- (*state)++;
- l=snprintf(dst, size, "%s", tmpbuf);
- if (l>=0 && token_hdr.ops->get_help) {
- token_hdr.ops->get_help(token_p, tmpbuf, sizeof(tmpbuf));
- help_str = (prog_char *) pgm_read_pgmptr(&inst->help_str);
- if (help_str)
- snprintf_P(dst+l, size-l, PSTR("[%s]: "PGMS_FMT), tmpbuf, help_str);
- else
- snprintf_P(dst+l, size-l, PSTR("[%s]: No help"), tmpbuf);
- }
-
- return 1;
- }
- }
- next2:
- inst_num ++;
- inst = (parse_pgm_inst_t *)pgm_read_pgmptr(ctx+inst_num);
- }
- return 0;
-}
-
+++ /dev/null
-/*
- * Copyright Droids Corporation (2007)
- * Olivier MATZ <zer0@droids-corp.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: parse.h,v 1.1.2.9 2009-01-03 16:25:13 zer0 Exp $
- *
- *
- */
-
-#ifndef _PARSE_H_
-#define _PARSE_H_
-
-#include <aversive/pgmspace.h>
-#include <aversive/types.h>
-
-#ifndef offsetof
-#define offsetof(type, field) ((size_t) &( ((type *)0)->field) )
-#endif
-
-#define PARSE_SUCCESS 0
-#define PARSE_AMBIGUOUS -1
-#define PARSE_NOMATCH -2
-#define PARSE_BAD_ARGS -3
-
-/**
- * Stores a pointer to the ops struct, and the offset: the place to
- * write the parsed result in the destination structure.
- */
-struct token_hdr {
- struct token_ops *ops;
- uint8_t offset;
-};
-typedef struct token_hdr parse_token_hdr_t;
-
-struct token_hdr_pgm {
- struct token_ops *ops;
- uint8_t offset;
-} PROGMEM;
-typedef struct token_hdr_pgm parse_pgm_token_hdr_t;
-
-/**
- * A token is defined by this structure.
- *
- * parse() takes the token as first argument, then the source buffer
- * starting at the token we want to parse. The 3rd arg is a pointer
- * where we store the parsed data (as binary). It returns the number of
- * parsed chars on success and a negative value on error.
- *
- * complete_get_nb() returns the number of possible values for this
- * token if completion is possible. If it is NULL or if it returns 0,
- * no completion is possible.
- *
- * complete_get_elt() copy in dstbuf (the size is specified in the
- * parameter) the i-th possible completion for this token. returns 0
- * on success or and a negative value on error.
- *
- * get_help() fills the dstbuf with the help for the token. It returns
- * -1 on error and 0 on success.
- */
-struct token_ops {
- /** parse(token ptr, buf, res pts) */
- int8_t (*parse)(parse_pgm_token_hdr_t *, const char *, void *);
- /** return the num of possible choices for this token */
- int8_t (*complete_get_nb)(parse_pgm_token_hdr_t *);
- /** return the elt x for this token (token, idx, dstbuf, size) */
- int8_t (*complete_get_elt)(parse_pgm_token_hdr_t *, int8_t, char *, uint8_t);
- /** get help for this token (token, dstbuf, size) */
- int8_t (*get_help)(parse_pgm_token_hdr_t *, char *, uint8_t);
-};
-
-/**
- * Store a instruction, which is a pointer to a callback function and
- * its parameter that is called when the instruction is parsed, a help
- * string, and a list of token composing this instruction.
- */
-struct inst {
- /* f(parsed_struct, data) */
- void (*f)(void *, void *);
- void * data;
- char * help_str;
- prog_void * tokens[];
-};
-typedef struct inst parse_inst_t;
-struct inst_pgm {
- /* f(parsed_struct, data) */
- void (*f)(void *, void *);
- void * data;
- char * help_str;
- prog_void * tokens[];
-} PROGMEM;
-typedef struct inst_pgm parse_pgm_inst_t;
-
-/**
- * A context is identified by its name, and contains a list of
- * instruction
- *
- */
-typedef parse_pgm_inst_t * parse_ctx_t;
-typedef PROGMEM parse_ctx_t parse_pgm_ctx_t;
-
-/**
- * Try to parse a buffer according to the specified context. The
- * argument buf must ends with "\n\0". The function returns
- * PARSE_AMBIGUOUS, PARSE_NOMATCH or PARSE_BAD_ARGS on error. Else it
- * calls the associated function (defined in the context) and returns
- * 0 (PARSE_SUCCESS).
- */
-int8_t parse(parse_pgm_ctx_t ctx[], const char * buf);
-
-/**
- * complete() must be called with *state==0.
- * It returns < 0 on error.
- *
- * Else it returns:
- * 2 on completion (one possible choice). In this case, the chars
- * are appended in dst buffer.
- * 1 if there is several possible choices. In this case, you must
- * call the function again, keeping the value of state intact.
- * 0 when the iteration is finished. The dst is not valid for this
- * last call.
- *
- * The returned dst buf ends with \0.
- *
- */
-int8_t complete(parse_pgm_ctx_t ctx[], const char *buf, int16_t *state,
- char *dst, uint8_t size);
-
-
-/* true if(!c || iscomment(c) || isblank(c) || isendofline(c)) */
-int isendoftoken(char c);
-
-#endif /* _PARSE_H_ */
#include "parse_atcmd.h"
static int8_t
-parse_atcmd(parse_pgm_token_hdr_t *tk, const char *buf, void *res)
+parse_atcmd(PGM_P tk, const char *buf, void *res)
{
struct xbee_atcmd copy;
struct token_atcmd_data ad;
- struct xbee_atcmd_pgm *cmd;
+ const struct xbee_atcmd *cmd;
char bufcopy[32];
uint8_t token_len = 0;
return -1;
/* store the address of object in structure */
if (res)
- *(struct xbee_atcmd_pgm **)res = cmd;
+ *(const struct xbee_atcmd **)res = cmd;
return token_len;
}
-static int8_t complete_get_nb_atcmd(parse_pgm_token_hdr_t *tk)
+static int8_t complete_get_nb_atcmd(PGM_P tk)
{
struct token_atcmd_data ad;
- struct xbee_atcmd_pgm *cmd;
+ const struct xbee_atcmd *cmd;
struct xbee_atcmd copy;
int8_t cnt = 0;
return cnt;
}
-static int8_t complete_get_elt_atcmd(parse_pgm_token_hdr_t *tk, int8_t idx,
+static int8_t complete_get_elt_atcmd(PGM_P tk, int8_t idx,
char *dstbuf, uint8_t size)
{
struct token_atcmd_data ad;
- struct xbee_atcmd_pgm *cmd;
+ const struct xbee_atcmd *cmd;
struct xbee_atcmd copy;
int8_t cnt = 0;
}
static int8_t
-help_atcmd(parse_pgm_token_hdr_t *tk, char *dstbuf,
- uint8_t size)
+help_atcmd(PGM_P tk, char *dstbuf, uint8_t size)
{
+ (void)tk;
snprintf(dstbuf, size, "ATCMD");
return 0;
}
struct monitor_reg_list xbee_monitor_list = LIST_HEAD_INITIALIZER();
static int8_t
-parse_monitor(parse_pgm_token_hdr_t *tk, const char *buf, void *res)
+parse_monitor(PGM_P tk, const char *buf, void *res)
{
struct monitor_reg *m;
uint8_t token_len = 0;
char bufcopy[32];
+ (void)tk;
while (!isendoftoken(buf[token_len]) &&
token_len < (sizeof(bufcopy)-1)) {
bufcopy[token_len] = buf[token_len];
}
static int8_t
-complete_get_nb_monitor(parse_pgm_token_hdr_t *tk)
+complete_get_nb_monitor(PGM_P tk)
{
struct monitor_reg *m;
int8_t i = 0;
+ (void)tk;
LIST_FOREACH(m, &xbee_monitor_list, next) {
i++;
}
}
static int8_t
-complete_get_elt_monitor(parse_pgm_token_hdr_t *tk, int8_t idx,
+complete_get_elt_monitor(PGM_P tk, int8_t idx,
char *dstbuf, uint8_t size)
{
struct monitor_reg *m;
int8_t i = 0, len;
+ (void)tk;
LIST_FOREACH(m, &xbee_monitor_list, next) {
if (i == idx)
break;
static int8_t
-help_monitor(parse_pgm_token_hdr_t *tk, char *dstbuf,
+help_monitor(PGM_P tk, char *dstbuf,
uint8_t size)
{
+ (void)tk;
snprintf_P(dstbuf, size, PSTR("Monitor-register"));
return 0;
}
struct monitor_reg {
LIST_ENTRY(monitor_reg) next;
- const prog_char *desc;
+ const char *desc;
char atcmd[3];
};
LIST_HEAD(monitor_reg_list, monitor_reg);
extern struct monitor_reg_list xbee_monitor_list;
-/* data is a pointer to a list */
struct token_monitor_data {
};
};
typedef struct token_monitor parse_token_monitor_t;
-struct token_monitor_pgm {
- struct token_hdr hdr;
- struct token_monitor_data monitor_data;
-} PROGMEM;
-typedef struct token_monitor_pgm parse_pgm_token_monitor_t;
-
extern struct token_ops token_monitor_ops;
#define TOKEN_MONITOR_INITIALIZER(structure, field){ \
#include "parse_neighbor.h"
static int8_t
-parse_neighbor(parse_pgm_token_hdr_t *tk, const char *buf, void *res)
+parse_neighbor(PGM_P tk, const char *buf, void *res)
{
struct token_neighbor_data tkd;
struct xbee_dev *dev;
}
static int8_t
-complete_get_nb_neighbor(parse_pgm_token_hdr_t *tk)
+complete_get_nb_neighbor(PGM_P tk)
{
struct token_neighbor_data tkd;
struct xbee_dev *dev;
}
static int8_t
-complete_get_elt_neighbor(parse_pgm_token_hdr_t *tk, int8_t idx,
+complete_get_elt_neighbor(PGM_P tk, int8_t idx,
char *dstbuf, uint8_t size)
{
struct token_neighbor_data tkd;
static int8_t
-help_neighbor(parse_pgm_token_hdr_t *tk, char *dstbuf,
- uint8_t size)
+help_neighbor(PGM_P tk, char *dstbuf, uint8_t size)
{
+ (void)tk;
snprintf_P(dstbuf, size, PSTR("Neighbor"));
return 0;
}
+++ /dev/null
-#include <stdio.h>
-#include <inttypes.h>
-#include <ctype.h>
-#include <string.h>
-
-#include "parse.h"
-#include "parse_num.h"
-
-//#define debug_printf(args...) printf(args)
-#define debug_printf(args...) do {} while(0)
-
-/* XXX to remove ?? */
-#define U08_MIN 0x00
-#define U08_MAX 0xFF
-#define U16_MIN 0x0000
-#define U16_MAX 0xFFFF
-#define U32_MIN 0x00000000
-#define U32_MAX 0xFFFFFFFF
-#define U64_MIN 0x0000000000000000
-#define U64_MAX 0xFFFFFFFFFFFFFFFF
-#define S08_MIN 0x80
-#define S08_MAX 0x7F
-#define S16_MIN 0x8000
-#define S16_MAX 0x7FFF
-#define S32_MIN 0x80000000
-#define S32_MAX 0x7FFFFFFF
-#define S64_MIN 0x8000000000000000
-#define S64_MAX 0x7FFFFFFFFFFFFFFF
-
-
-struct token_ops token_num_ops = {
- .parse = parse_num,
- .complete_get_nb = NULL,
- .complete_get_elt = NULL,
- .get_help = get_help_num,
-};
-
-
-enum num_parse_state_t {
- START,
- DEC_NEG,
- BIN,
- HEX,
- FLOAT_POS,
- FLOAT_NEG,
- ERROR,
-
- FIRST_OK, /* not used */
- ZERO_OK,
- HEX_OK,
- OCTAL_OK,
- BIN_OK,
- DEC_NEG_OK,
- DEC_POS_OK,
- FLOAT_POS_OK,
- FLOAT_NEG_OK,
-};
-
-/* Keep it sync with enum in .h */
-static const prog_char help1[] = "UINT8";
-static const prog_char help2[] = "UINT16";
-static const prog_char help3[] = "UINT32";
-static const prog_char help4[] = "UINT64";
-static const prog_char help5[] = "INT8";
-static const prog_char help6[] = "INT16";
-static const prog_char help7[] = "INT32";
-static const prog_char help8[] = "INT64";
-#ifndef CONFIG_MODULE_PARSE_NO_FLOAT
-static const prog_char help9[] = "FLOAT";
-#endif
-static const prog_char * num_help[] = {
- help1, help2, help3, help4,
- help5, help6, help7, help8,
-#ifndef CONFIG_MODULE_PARSE_NO_FLOAT
- help9,
-#endif
-};
-
-static inline int8_t
-add_to_res(uint8_t c, uint64_t * res, uint8_t base)
-{
- /* overflow */
- if ( (U64_MAX - c) / base < *res ) {
- return -1;
- }
-
- *res = *res * base + c ;
- return 0;
-}
-
-
-/* parse an int or a float */
-int8_t
-parse_num(parse_pgm_token_hdr_t * tk, const char * srcbuf, void * res)
-{
- struct token_num_data nd;
- enum num_parse_state_t st = START;
- const char * buf = srcbuf;
- char c = *buf;
- uint64_t res1=0, res2=0, res3=1;
-
- memcpy_P(&nd, &((struct token_num *)tk)->num_data, sizeof(nd));
-
- while ( st != ERROR && c && ! isendoftoken(c) ) {
- debug_printf("%c %x -> ", c, c);
- switch (st) {
- case START:
- if (c == '-') {
- st = DEC_NEG;
- }
- else if (c == '0') {
- st = ZERO_OK;
- }
-#ifndef CONFIG_MODULE_PARSE_NO_FLOAT
- else if (c == '.') {
- st = FLOAT_POS;
- res1 = 0;
- }
-#endif
- else if (c >= '1' && c <= '9') {
- if (add_to_res(c - '0', &res1, 10) < 0)
- st = ERROR;
- else
- st = DEC_POS_OK;
- }
- else {
- st = ERROR;
- }
- break;
-
- case ZERO_OK:
- if (c == 'x') {
- st = HEX;
- }
- else if (c == 'b') {
- st = BIN;
- }
-#ifndef CONFIG_MODULE_PARSE_NO_FLOAT
- else if (c == '.') {
- st = FLOAT_POS;
- res1 = 0;
- }
-#endif
- else if (c >= '0' && c <= '7') {
- if (add_to_res(c - '0', &res1, 10) < 0)
- st = ERROR;
- else
- st = OCTAL_OK;
- }
- else {
- st = ERROR;
- }
- break;
-
- case DEC_NEG:
- if (c >= '0' && c <= '9') {
- if (add_to_res(c - '0', &res1, 10) < 0)
- st = ERROR;
- else
- st = DEC_NEG_OK;
- }
-#ifndef CONFIG_MODULE_PARSE_NO_FLOAT
- else if (c == '.') {
- res1 = 0;
- st = FLOAT_NEG;
- }
-#endif
- else {
- st = ERROR;
- }
- break;
-
- case DEC_NEG_OK:
- if (c >= '0' && c <= '9') {
- if (add_to_res(c - '0', &res1, 10) < 0)
- st = ERROR;
- }
-#ifndef CONFIG_MODULE_PARSE_NO_FLOAT
- else if (c == '.') {
- st = FLOAT_NEG;
- }
-#endif
- else {
- st = ERROR;
- }
- break;
-
- case DEC_POS_OK:
- if (c >= '0' && c <= '9') {
- if (add_to_res(c - '0', &res1, 10) < 0)
- st = ERROR;
- }
-#ifndef CONFIG_MODULE_PARSE_NO_FLOAT
- else if (c == '.') {
- st = FLOAT_POS;
- }
-#endif
- else {
- st = ERROR;
- }
- break;
-
- case HEX:
- st = HEX_OK;
- /* no break */
- case HEX_OK:
- if (c >= '0' && c <= '9') {
- if (add_to_res(c - '0', &res1, 16) < 0)
- st = ERROR;
- }
- else if (c >= 'a' && c <= 'f') {
- if (add_to_res(c - 'a' + 10, &res1, 16) < 0)
- st = ERROR;
- }
- else if (c >= 'A' && c <= 'F') {
- if (add_to_res(c - 'A' + 10, &res1, 16) < 0)
- st = ERROR;
- }
- else {
- st = ERROR;
- }
- break;
-
-
- case OCTAL_OK:
- if (c >= '0' && c <= '7') {
- if (add_to_res(c - '0', &res1, 8) < 0)
- st = ERROR;
- }
- else {
- st = ERROR;
- }
- break;
-
- case BIN:
- st = BIN_OK;
- /* no break */
- case BIN_OK:
- if (c >= '0' && c <= '1') {
- if (add_to_res(c - '0', &res1, 2) < 0)
- st = ERROR;
- }
- else {
- st = ERROR;
- }
- break;
-
-#ifndef CONFIG_MODULE_PARSE_NO_FLOAT
- case FLOAT_POS:
- if (c >= '0' && c <= '9') {
- if (add_to_res(c - '0', &res2, 10) < 0)
- st = ERROR;
- else
- st = FLOAT_POS_OK;
- res3 = 10;
- }
- else {
- st = ERROR;
- }
- break;
-
- case FLOAT_NEG:
- if (c >= '0' && c <= '9') {
- if (add_to_res(c - '0', &res2, 10) < 0)
- st = ERROR;
- else
- st = FLOAT_NEG_OK;
- res3 = 10;
- }
- else {
- st = ERROR;
- }
- break;
-
- case FLOAT_POS_OK:
- if (c >= '0' && c <= '9') {
- if (add_to_res(c - '0', &res2, 10) < 0)
- st = ERROR;
- if (add_to_res(0, &res3, 10) < 0)
- st = ERROR;
- }
- else {
- st = ERROR;
- }
- break;
-
- case FLOAT_NEG_OK:
- if (c >= '0' && c <= '9') {
- if (add_to_res(c - '0', &res2, 10) < 0)
- st = ERROR;
- if (add_to_res(0, &res3, 10) < 0)
- st = ERROR;
- }
- else {
- st = ERROR;
- }
- break;
-#endif
-
- default:
- debug_printf("not impl ");
-
- }
-
- debug_printf("(%d) (%d) (%d)\n",
- (int)res1, (int)res2, (int)res3);
-
- buf ++;
- c = *buf;
-
- /* token too long */
- if (buf-srcbuf > 127)
- return -1;
- }
-
- switch (st) {
- case ZERO_OK:
- case DEC_POS_OK:
- case HEX_OK:
- case OCTAL_OK:
- case BIN_OK:
- if ( nd.type == INT8 && res1 <= S08_MAX ) {
- if (res)
- *(int8_t *)res = (int8_t) res1;
- return (buf-srcbuf);
- }
- else if ( nd.type == INT16 && res1 <= S16_MAX ) {
- if (res)
- *(int16_t *)res = (int16_t) res1;
- return (buf-srcbuf);
- }
- else if ( nd.type == INT32 && res1 <= S32_MAX ) {
- if (res)
- *(int32_t *)res = (int32_t) res1;
- return (buf-srcbuf);
- }
- else if ( nd.type == INT64 && res1 <= S64_MAX ) {
- if (res)
- *(int64_t *)res = (int64_t) res1;
- return (buf-srcbuf);
- }
- else if ( nd.type == UINT8 && res1 <= U08_MAX ) {
- if (res)
- *(uint8_t *)res = (uint8_t) res1;
- return (buf-srcbuf);
- }
- else if (nd.type == UINT16 && res1 <= U16_MAX ) {
- if (res)
- *(uint16_t *)res = (uint16_t) res1;
- return (buf-srcbuf);
- }
- else if ( nd.type == UINT32 ) {
- if (res)
- *(uint32_t *)res = (uint32_t) res1;
- return (buf-srcbuf);
- }
- else if ( nd.type == UINT64 ) {
- if (res)
- *(uint64_t *)res = (uint64_t) res1;
- return (buf-srcbuf);
- }
-#ifndef CONFIG_MODULE_PARSE_NO_FLOAT
- else if ( nd.type == FLOAT ) {
- if (res)
- *(float *)res = (float)res1;
- return (buf-srcbuf);
- }
-#endif
- else {
- return -1;
- }
- break;
-
- case DEC_NEG_OK:
- if ( nd.type == INT8 && res1 <= S08_MAX + 1 ) {
- if (res)
- *(int8_t *)res = - (int8_t) res1;
- return (buf-srcbuf);
- }
- else if ( nd.type == INT16 && res1 <= (uint16_t)S16_MAX + 1 ) {
- if (res)
- *(int16_t *)res = - (int16_t) res1;
- return (buf-srcbuf);
- }
- else if ( nd.type == INT32 && res1 <= (uint32_t)S32_MAX + 1 ) {
- if (res)
- *(int32_t *)res = - (int32_t) res1;
- return (buf-srcbuf);
- }
- else if ( nd.type == INT64 && res1 <= (uint64_t)S64_MAX + 1 ) {
- if (res)
- *(int64_t *)res = - (int64_t) res1;
- return (buf-srcbuf);
- }
-#ifndef CONFIG_MODULE_PARSE_NO_FLOAT
- else if ( nd.type == FLOAT ) {
- if (res)
- *(float *)res = - (float)res1;
- return (buf-srcbuf);
- }
-#endif
- else {
- return -1;
- }
- break;
-
-#ifndef CONFIG_MODULE_PARSE_NO_FLOAT
- case FLOAT_POS:
- case FLOAT_POS_OK:
- if ( nd.type == FLOAT ) {
- if (res)
- *(float *)res = (float)res1 + ((float)res2 / (float)res3);
- return (buf-srcbuf);
-
- }
- else {
- return -1;
- }
- break;
-
- case FLOAT_NEG:
- case FLOAT_NEG_OK:
- if ( nd.type == FLOAT ) {
- if (res)
- *(float *)res = - ((float)res1 + ((float)res2 / (float)res3));
- return (buf-srcbuf);
-
- }
- else {
- return -1;
- }
- break;
-#endif
- default:
- debug_printf("error\n");
- return -1;
- }
- return -1;
-}
-
-
-/* parse an int or a float */
-int8_t
-get_help_num(parse_pgm_token_hdr_t * tk, char * dstbuf, uint8_t size)
-{
- struct token_num_data nd;
-
- memcpy_P(&nd, &((struct token_num *)tk)->num_data, sizeof(nd));
-
- /* should not happen.... don't so this test */
-/* if (nd.type >= (sizeof(num_help)/sizeof(const char *))) */
-/* return -1; */
-
- strncpy_P(dstbuf, num_help[nd.type], size);
- dstbuf[size-1] = '\0';
- return 0;
-}
+++ /dev/null
-#ifndef _PARSE_NUM_H_
-#define _PARSE_NUM_H_
-
-#include "parse.h"
-
-enum numtype {
- UINT8 = 0,
- UINT16,
- UINT32,
- UINT64,
- INT8,
- INT16,
- INT32,
- INT64,
-#ifndef CONFIG_MODULE_PARSE_NO_FLOAT
- FLOAT,
-#endif
-};
-
-struct token_num_data {
- enum numtype type;
-};
-
-struct token_num {
- struct token_hdr hdr;
- struct token_num_data num_data;
-};
-typedef struct token_num parse_token_num_t;
-struct token_num_pgm {
- struct token_hdr hdr;
- struct token_num_data num_data;
-} PROGMEM;
-typedef struct token_num_pgm parse_pgm_token_num_t;
-
-extern struct token_ops token_num_ops;
-
-int8_t parse_num(parse_pgm_token_hdr_t * tk,
- const char * srcbuf, void * res);
-int8_t get_help_num(parse_pgm_token_hdr_t * tk,
- char * dstbuf, uint8_t size);
-
-#define TOKEN_NUM_INITIALIZER(structure, field, numtype) \
-{ \
- .hdr = { \
- .ops = &token_num_ops, \
- .offset = offsetof(structure, field), \
- }, \
- .num_data = { \
- .type = numtype, \
- }, \
-}
-
-#endif /* _PARSE_NUM_H_ */
+++ /dev/null
-#include <stdio.h>
-#include <inttypes.h>
-#include <ctype.h>
-#include <string.h>
-
-#include "parse.h"
-#include "parse_string.h"
-
-struct token_ops token_string_ops = {
- .parse = parse_string,
- .complete_get_nb = complete_get_nb_string,
- .complete_get_elt = complete_get_elt_string,
- .get_help = get_help_string,
-};
-
-#define MULTISTRING_HELP PSTR("Mul-choice STRING")
-#define ANYSTRING_HELP PSTR("Any STRING")
-#define FIXEDSTRING_HELP PSTR("Fixed STRING")
-
-static uint8_t
-get_token_len(const prog_char * s)
-{
- prog_char c;
- uint8_t i=0;
-
- c = pgm_read_byte(s+i);
- while (c!='#' && c!='\0') {
- i++;
- c = pgm_read_byte(s+i);
- }
- return i;
-}
-
-static const prog_char *
-get_next_token(const prog_char * s)
-{
- uint8_t i;
- i = get_token_len(s);
- if (pgm_read_byte(s+i) == '#')
- return s+i+1;
- return NULL;
-}
-
-int8_t
-parse_string(parse_pgm_token_hdr_t * tk, const char * buf, void * res)
-{
- struct token_string_data sd;
- uint8_t token_len;
- const prog_char * str;
-
- if (! *buf)
- return -1;
-
- memcpy_P(&sd, &((struct token_string *)tk)->string_data, sizeof(sd));
-
- /* fixed string */
- if (sd.str) {
- str = sd.str;
- do {
- token_len = get_token_len(str);
-
- /* if token is too big... */
- if (token_len >= STR_TOKEN_SIZE - 1) {
- continue;
- }
-
- if ( strncmp_P(buf, str, token_len) ) {
- continue;
- }
-
- if ( !isendoftoken(*(buf+token_len)) ) {
- continue;
- }
-
- break;
- } while ( (str = get_next_token(str)) != NULL );
-
- if (!str)
- return -1;
- }
- /* unspecified string */
- else {
- token_len=0;
- while(!isendoftoken(buf[token_len]) &&
- token_len < (STR_TOKEN_SIZE-1))
- token_len++;
-
- /* return if token too long */
- if (token_len >= STR_TOKEN_SIZE - 1) {
- return -1;
- }
- }
-
- if (res) {
- /* we are sure that token_len is < STR_TOKEN_SIZE-1 */
- strncpy(res, buf, token_len);
- *((char *)res + token_len) = 0;
- }
-
- return token_len;
-}
-
-int8_t complete_get_nb_string(parse_pgm_token_hdr_t * tk)
-{
- struct token_string_data sd;
- int8_t ret=1;
-
- memcpy_P(&sd, &((struct token_string *)tk)->string_data, sizeof(sd));
-
- if (!sd.str)
- return 0;
-
- while( (sd.str = get_next_token(sd.str)) != NULL ) {
- ret++;
- }
- return ret;
-}
-
-int8_t complete_get_elt_string(parse_pgm_token_hdr_t * tk, int8_t idx,
- char * dstbuf, uint8_t size)
-{
- struct token_string_data sd;
- const prog_char * s;
- uint8_t len;
-
- memcpy_P(&sd, &((struct token_string *)tk)->string_data, sizeof(sd));
- s = sd.str;
-
- while (idx-- && s)
- s = get_next_token(s);
-
- if (!s)
- return -1;
-
- len = get_token_len(s);
- if (len > size - 1)
- return -1;
-
- memcpy_P(dstbuf, s, len);
- dstbuf[len] = '\0';
-
- return 0;
-}
-
-
-int8_t get_help_string(parse_pgm_token_hdr_t * tk, char * dstbuf, uint8_t size)
-{
- struct token_string_data sd;
- const prog_char * s;
-
- memcpy_P(&sd, &((struct token_string *)tk)->string_data, sizeof(sd));
- s = sd.str;
-
- if (s) {
- if (get_next_token(s)) {
- strncpy_P(dstbuf, MULTISTRING_HELP, size);
- }
- else {
- strncpy_P(dstbuf, FIXEDSTRING_HELP, size);
- }
- }
- else {
- strncpy_P(dstbuf, ANYSTRING_HELP, size);
- }
-
- dstbuf[size-1] = '\0';
-
- return 0;
-}
+++ /dev/null
-#ifndef _PARSE_STRING_H_
-#define _PARSE_STRING_H_
-
-#include "parse.h"
-
-/* size of a parsed string */
-#define STR_TOKEN_SIZE 32
-
-typedef char fixed_string_t[STR_TOKEN_SIZE];
-
-struct token_string_data {
- const prog_char * str;
-};
-
-struct token_string {
- struct token_hdr hdr;
- struct token_string_data string_data;
-};
-typedef struct token_string parse_token_string_t;
-struct token_string_pgm {
- struct token_hdr hdr;
- struct token_string_data string_data;
-} PROGMEM;
-typedef struct token_string_pgm parse_pgm_token_string_t;
-
-extern struct token_ops token_string_ops;
-
-int8_t parse_string(parse_pgm_token_hdr_t * tk, const char * srcbuf, void * res);
-int8_t complete_get_nb_string(parse_pgm_token_hdr_t * tk);
-int8_t complete_get_elt_string(parse_pgm_token_hdr_t * tk, int8_t idx,
- char * dstbuf, uint8_t size);
-int8_t get_help_string(parse_pgm_token_hdr_t * tk, char * dstbuf, uint8_t size);
-
-#define TOKEN_STRING_INITIALIZER(structure, field, string) \
-{ \
- .hdr = { \
- .ops = &token_string_ops, \
- .offset = offsetof(structure, field), \
- }, \
- .string_data = { \
- .str = string, \
- }, \
-}
-
-#endif /* _PARSE_STRING_H_ */
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- *
- *
- */
-
-#ifndef PID_CONFIG_H
-#define PID_CONFIG_H
-
-/** the derivate term can be filtered to remove the noise. This value
- * is the maxium sample count to keep in memory to do this
- * filtering. For an instance of pid, this count is defined o*/
-#define PID_DERIVATE_FILTER_MAX_SIZE 6
-
-#endif
struct xbee_atresp_hdr *atresp = (struct xbee_atresp_hdr *)frame;
int level = (intptr_t)arg;
uint8_t db;
- db = atresp->data[0];
+ /* XXX check if this test is correct */
+ if (len < sizeof(struct xbee_atresp_hdr) + sizeof(uint8_t))
+ return -1;
+
+ db = atresp->data[0];
power_levels[level].power_db = db;
power_levels[level].ttl = 2;
return 0;
+++ /dev/null
-/*
- * Copyright Droids Corporation (2007)
- * Olivier MATZ <zer0@droids-corp.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: rdline.c,v 1.1.2.9 2009-02-27 21:41:31 zer0 Exp $
- *
- *
- */
-
-#include <stdlib.h>
-#include <stdio.h>
-#include <string.h>
-#include <stdarg.h>
-#include <ctype.h>
-
-#include <aversive/pgmspace.h>
-
-#include <cirbuf.h>
-#include "rdline.h"
-
-static void rdline_puts_P(struct rdline * rdl, const prog_char * buf);
-static void rdline_miniprintf_P(struct rdline * rdl,
- const prog_char * buf, uint8_t val);
-
-#ifdef CONFIG_MODULE_RDLINE_HISTORY
-static void rdline_remove_old_history_item(struct rdline * rdl);
-static void rdline_remove_first_history_item(struct rdline * rdl);
-static uint8_t rdline_get_history_size(struct rdline * rdl);
-#endif /* CONFIG_MODULE_RDLINE_HISTORY */
-
-
-void rdline_init(struct rdline *rdl,
- rdline_write_char_t *write_char,
- rdline_validate_t *validate,
- rdline_complete_t *complete)
-{
- memset(rdl, 0, sizeof(*rdl));
- rdl->validate = validate;
- rdl->complete = complete;
- rdl->write_char = write_char;
- rdl->status = RDLINE_STOPPED;
-#ifdef CONFIG_MODULE_RDLINE_HISTORY
- cirbuf_init(&rdl->history, rdl->history_buf, 0, RDLINE_HISTORY_BUF_SIZE);
-#endif /* CONFIG_MODULE_RDLINE_HISTORY */
-}
-
-void
-rdline_newline(struct rdline * rdl, const char * prompt)
-{
- uint8_t i;
-
- vt100_init(&rdl->vt100);
- cirbuf_init(&rdl->left, rdl->left_buf, 0, RDLINE_BUF_SIZE);
- cirbuf_init(&rdl->right, rdl->right_buf, 0, RDLINE_BUF_SIZE);
-
- if (prompt != rdl->prompt)
- memcpy(rdl->prompt, prompt, sizeof(rdl->prompt)-1);
- rdl->prompt_size = strlen(prompt);
-
- for (i=0 ; i<rdl->prompt_size ; i++)
- rdl->write_char(rdl->prompt[i]);
- rdl->status = RDLINE_RUNNING;
-
-#ifdef CONFIG_MODULE_RDLINE_HISTORY
- rdl->history_cur_line = -1;
-#endif /* CONFIG_MODULE_RDLINE_HISTORY */
-}
-
-void
-rdline_stop(struct rdline * rdl)
-{
- rdl->status = RDLINE_STOPPED;
-}
-
-void
-rdline_restart(struct rdline * rdl)
-{
- rdl->status = RDLINE_RUNNING;
-}
-
-const char *
-rdline_get_buffer(struct rdline * rdl)
-{
- uint8_t len_l, len_r;
- cirbuf_align_left(&rdl->left);
- cirbuf_align_left(&rdl->right);
-
- len_l = CIRBUF_GET_LEN(&rdl->left);
- len_r = CIRBUF_GET_LEN(&rdl->right);
- memcpy(rdl->left_buf+len_l, rdl->right_buf, len_r);
-
- rdl->left_buf[len_l + len_r] = '\n';
- rdl->left_buf[len_l + len_r + 1] = '\0';
- return rdl->left_buf;
-}
-
-static void
-display_right_buffer(struct rdline * rdl)
-{
- uint8_t i;
- char tmp;
-
- rdline_puts_P(rdl, PSTR(vt100_clear_right));
- if (!CIRBUF_IS_EMPTY(&rdl->right)) {
- CIRBUF_FOREACH(&rdl->right, i, tmp) {
- rdl->write_char(tmp);
- }
- rdline_miniprintf_P(rdl, PSTR(vt100_multi_left),
- CIRBUF_GET_LEN(&rdl->right));
- }
-}
-
-void rdline_redisplay(struct rdline * rdl)
-{
- uint8_t i;
- char tmp;
-
- rdline_puts_P(rdl, PSTR(vt100_home));
- for (i=0 ; i<rdl->prompt_size ; i++)
- rdl->write_char(rdl->prompt[i]);
- CIRBUF_FOREACH(&rdl->left, i, tmp) {
- rdl->write_char(tmp);
- }
- display_right_buffer(rdl);
-}
-
-int8_t
-rdline_char_in(struct rdline * rdl, char c)
-{
- uint8_t i;
- int8_t cmd;
- char tmp;
-#ifdef CONFIG_MODULE_RDLINE_HISTORY
- char * buf;
-#endif
-
- if (rdl->status != RDLINE_RUNNING)
- return -1;
-
- cmd = vt100_parser(&rdl->vt100, c);
- if (cmd == -2)
- return 0;
-
- if (cmd >= 0) {
- switch (cmd) {
- case KEY_CTRL_B:
- case KEY_LEFT_ARR:
- if (CIRBUF_IS_EMPTY(&rdl->left))
- break;
- tmp = cirbuf_get_tail(&rdl->left);
- cirbuf_del_tail(&rdl->left);
- cirbuf_add_head(&rdl->right, tmp);
- rdline_puts_P(rdl, PSTR(vt100_left_arr));
- break;
-
- case KEY_CTRL_F:
- case KEY_RIGHT_ARR:
- if (CIRBUF_IS_EMPTY(&rdl->right))
- break;
- tmp = cirbuf_get_head(&rdl->right);
- cirbuf_del_head(&rdl->right);
- cirbuf_add_tail(&rdl->left, tmp);
- rdline_puts_P(rdl, PSTR(vt100_right_arr));
- break;
-
- case KEY_WLEFT:
- while (! CIRBUF_IS_EMPTY(&rdl->left) &&
- (tmp = cirbuf_get_tail(&rdl->left)) &&
- isblank(tmp)) {
- rdline_puts_P(rdl, PSTR(vt100_left_arr));
- cirbuf_del_tail(&rdl->left);
- cirbuf_add_head(&rdl->right, tmp);
- }
- while (! CIRBUF_IS_EMPTY(&rdl->left) &&
- (tmp = cirbuf_get_tail(&rdl->left)) &&
- !isblank(tmp)) {
- rdline_puts_P(rdl, PSTR(vt100_left_arr));
- cirbuf_del_tail(&rdl->left);
- cirbuf_add_head(&rdl->right, tmp);
- }
- break;
-
- case KEY_WRIGHT:
- while (! CIRBUF_IS_EMPTY(&rdl->right) &&
- (tmp = cirbuf_get_head(&rdl->right)) &&
- isblank(tmp)) {
- rdline_puts_P(rdl, PSTR(vt100_right_arr));
- cirbuf_del_head(&rdl->right);
- cirbuf_add_tail(&rdl->left, tmp);
- }
- while (! CIRBUF_IS_EMPTY(&rdl->right) &&
- (tmp = cirbuf_get_head(&rdl->right)) &&
- !isblank(tmp)) {
- rdline_puts_P(rdl, PSTR(vt100_right_arr));
- cirbuf_del_head(&rdl->right);
- cirbuf_add_tail(&rdl->left, tmp);
- }
- break;
-
- case KEY_BKSPACE:
- if(!cirbuf_del_tail_safe(&rdl->left)) {
- rdline_puts_P(rdl, PSTR(vt100_bs));
- display_right_buffer(rdl);
- }
- break;
-
- case KEY_META_BKSPACE:
- while (! CIRBUF_IS_EMPTY(&rdl->left) && isblank(cirbuf_get_tail(&rdl->left))) {
- rdline_puts_P(rdl, PSTR(vt100_bs));
- cirbuf_del_tail(&rdl->left);
- }
- while (! CIRBUF_IS_EMPTY(&rdl->left) && !isblank(cirbuf_get_tail(&rdl->left))) {
- rdline_puts_P(rdl, PSTR(vt100_bs));
- cirbuf_del_tail(&rdl->left);
- }
- display_right_buffer(rdl);
- break;
-
- case KEY_SUPPR:
- case KEY_CTRL_D:
- if(!cirbuf_del_head_safe(&rdl->right)) {
- display_right_buffer(rdl);
- }
- if (cmd == KEY_CTRL_D &&
- CIRBUF_IS_EMPTY(&rdl->left) &&
- CIRBUF_IS_EMPTY(&rdl->right)) {
- return -2;
- }
- break;
-
- case KEY_CTRL_A:
- if (CIRBUF_IS_EMPTY(&rdl->left))
- break;
- rdline_miniprintf_P(rdl, PSTR(vt100_multi_left),
- CIRBUF_GET_LEN(&rdl->left));
- while (! CIRBUF_IS_EMPTY(&rdl->left)) {
- tmp = cirbuf_get_tail(&rdl->left);
- cirbuf_del_tail(&rdl->left);
- cirbuf_add_head(&rdl->right, tmp);
- }
- break;
-
- case KEY_CTRL_E:
- if (CIRBUF_IS_EMPTY(&rdl->right))
- break;
- rdline_miniprintf_P(rdl, PSTR(vt100_multi_right),
- CIRBUF_GET_LEN(&rdl->right));
- while (! CIRBUF_IS_EMPTY(&rdl->right)) {
- tmp = cirbuf_get_head(&rdl->right);
- cirbuf_del_head(&rdl->right);
- cirbuf_add_tail(&rdl->left, tmp);
- }
- break;
-
-#ifdef CONFIG_MODULE_RDLINE_KILL_BUF
- case KEY_CTRL_K:
- cirbuf_get_buf_head(&rdl->right, rdl->kill_buf, RDLINE_BUF_SIZE);
- rdl->kill_size = CIRBUF_GET_LEN(&rdl->right);
- cirbuf_del_buf_head(&rdl->right, rdl->kill_size);
- rdline_puts_P(rdl, PSTR(vt100_clear_right));
- break;
-
- case KEY_CTRL_Y:
- i=0;
- while(CIRBUF_GET_LEN(&rdl->right) + CIRBUF_GET_LEN(&rdl->left) <
- RDLINE_BUF_SIZE &&
- i < rdl->kill_size) {
- cirbuf_add_tail(&rdl->left, rdl->kill_buf[i]);
- rdl->write_char(rdl->kill_buf[i]);
- i++;
- }
- display_right_buffer(rdl);
- break;
-#endif /* CONFIG_MODULE_RDLINE_KILL_BUF */
-
- case KEY_CTRL_C:
- rdline_puts_P(rdl, PSTR("\r\n"));
- rdline_newline(rdl, rdl->prompt);
- break;
-
- case KEY_CTRL_L:
- rdline_redisplay(rdl);
- break;
-
- case KEY_TAB:
- case KEY_HELP:
- cirbuf_align_left(&rdl->left);
- rdl->left_buf[CIRBUF_GET_LEN(&rdl->left)] = '\0';
- if (rdl->complete) {
- char tmp_buf[127]; /* XXX */
- int16_t complete_state;
- int8_t ret;
- int tmp_size;
-
- if (cmd == KEY_TAB)
- complete_state = 0;
- else
- complete_state = -1;
-
- ret = rdl->complete(rdl->left_buf, tmp_buf, sizeof(tmp_buf),
- &complete_state);
- /* no completion or error */
- if (ret <= 0) {
- return 2;
- }
-
- tmp_size = strlen(tmp_buf);
- /* add chars */
- if (ret == 2) {
- i=0;
- while(CIRBUF_GET_LEN(&rdl->right) + CIRBUF_GET_LEN(&rdl->left) <
- RDLINE_BUF_SIZE &&
- i < tmp_size) {
- cirbuf_add_tail(&rdl->left, tmp_buf[i]);
- rdl->write_char(tmp_buf[i]);
- i++;
- }
- display_right_buffer(rdl);
- return 2; /* ?? */
- }
-
- /* choice */
- rdline_puts_P(rdl, PSTR("\r\n"));
- while (ret) {
- rdl->write_char(' ');
- for (i=0 ; tmp_buf[i] ; i++)
- rdl->write_char(tmp_buf[i]);
- rdline_puts_P(rdl, PSTR("\r\n"));
- ret = rdl->complete(rdl->left_buf, tmp_buf,
- sizeof(tmp_buf), &complete_state);
- }
-
- rdline_redisplay(rdl);
- }
- return 2;
-
- case KEY_RETURN:
- case KEY_RETURN2:
- rdline_get_buffer(rdl);
- rdline_puts_P(rdl, PSTR("\r\n"));
-#ifdef CONFIG_MODULE_RDLINE_HISTORY
- if (rdl->history_cur_line != -1)
- rdline_remove_first_history_item(rdl);
-#endif
-
- if (rdl->validate)
- rdl->validate(rdl->left_buf, CIRBUF_GET_LEN(&rdl->left)+2);
- return 1;
-
-#ifdef CONFIG_MODULE_RDLINE_HISTORY
- case KEY_UP_ARR:
- if (rdl->history_cur_line == 0) {
- rdline_remove_first_history_item(rdl);
- }
- if (rdl->history_cur_line <= 0) {
- rdline_add_history(rdl, rdline_get_buffer(rdl));
- rdl->history_cur_line = 0;
- }
-
- buf = rdline_get_history_item(rdl, rdl->history_cur_line + 1);
- if (!buf)
- break;
-
- rdl->history_cur_line ++;
- vt100_init(&rdl->vt100);
- cirbuf_init(&rdl->left, rdl->left_buf, 0, RDLINE_BUF_SIZE);
- cirbuf_init(&rdl->right, rdl->right_buf, 0, RDLINE_BUF_SIZE);
- cirbuf_add_buf_tail(&rdl->left, buf, strlen(buf));
- rdline_redisplay(rdl);
- break;
-
- case KEY_DOWN_ARR:
- if (rdl->history_cur_line - 1 < 0)
- break;
-
- rdl->history_cur_line --;
- buf = rdline_get_history_item(rdl, rdl->history_cur_line);
- if (!buf)
- break;
- vt100_init(&rdl->vt100);
- cirbuf_init(&rdl->left, rdl->left_buf, 0, RDLINE_BUF_SIZE);
- cirbuf_init(&rdl->right, rdl->right_buf, 0, RDLINE_BUF_SIZE);
- cirbuf_add_buf_tail(&rdl->left, buf, strlen(buf));
- rdline_redisplay(rdl);
-
- break;
-#endif /* CONFIG_MODULE_RDLINE_HISTORY */
-
-
- default:
- break;
- }
-
- return 0;
- }
-
- if (! isprint(c))
- return 0;
-
- /* standard chars */
- if (CIRBUF_GET_LEN(&rdl->left) + CIRBUF_GET_LEN(&rdl->right) >= RDLINE_BUF_SIZE)
- return 0;
-
- if (cirbuf_add_tail_safe(&rdl->left, c))
- return 0;
-
- rdl->write_char(c);
- display_right_buffer(rdl);
-
- return 0;
-}
-
-
-/* HISTORY */
-
-#ifdef CONFIG_MODULE_RDLINE_HISTORY
-static void
-rdline_remove_old_history_item(struct rdline * rdl)
-{
- char tmp;
-
- while (! CIRBUF_IS_EMPTY(&rdl->history) ) {
- tmp = cirbuf_get_head(&rdl->history);
- cirbuf_del_head(&rdl->history);
- if (!tmp)
- break;
- }
-}
-
-static void
-rdline_remove_first_history_item(struct rdline * rdl)
-{
- char tmp;
-
- if ( CIRBUF_IS_EMPTY(&rdl->history) ) {
- return;
- }
- else {
- cirbuf_del_tail(&rdl->history);
- }
-
- while (! CIRBUF_IS_EMPTY(&rdl->history) ) {
- tmp = cirbuf_get_tail(&rdl->history);
- if (!tmp)
- break;
- cirbuf_del_tail(&rdl->history);
- }
-}
-
-static uint8_t
-rdline_get_history_size(struct rdline * rdl)
-{
- uint8_t i, tmp, ret=0;
-
- CIRBUF_FOREACH(&rdl->history, i, tmp) {
- if (tmp == 0)
- ret ++;
- }
-
- return ret;
-}
-
-char *
-rdline_get_history_item(struct rdline * rdl, uint8_t idx)
-{
- uint8_t len, i, tmp;
-
- len = rdline_get_history_size(rdl);
- if ( idx >= len ) {
- return NULL;
- }
-
- cirbuf_align_left(&rdl->history);
-
- CIRBUF_FOREACH(&rdl->history, i, tmp) {
- if ( idx == len - 1) {
- return rdl->history_buf + i;
- }
- if (tmp == 0)
- len --;
- }
-
- return NULL;
-}
-
-int8_t
-rdline_add_history(struct rdline * rdl, const char * buf)
-{
- cirbuf_uint len, i;
-
- len = strlen(buf);
- for (i=0; i<len ; i++) {
- if (buf[i] == '\n') {
- len = i;
- break;
- }
- }
-
- if ( len >= RDLINE_HISTORY_BUF_SIZE )
- return -1;
-
- while ( len >= CIRBUF_GET_FREELEN(&rdl->history) ) {
- rdline_remove_old_history_item(rdl);
- }
-
- cirbuf_add_buf_tail(&rdl->history, buf, len);
- cirbuf_add_tail(&rdl->history, 0);
-
- return 0;
-}
-
-void
-rdline_clear_history(struct rdline * rdl)
-{
- cirbuf_init(&rdl->history, rdl->history_buf, 0, RDLINE_HISTORY_BUF_SIZE);
-}
-
-#else /* CONFIG_MODULE_RDLINE_HISTORY */
-
-int8_t rdline_add_history(struct rdline * rdl, const char * buf) {return -1;}
-void rdline_clear_history(struct rdline * rdl) {}
-char * rdline_get_history_item(struct rdline * rdl, uint8_t i) {return NULL;}
-
-
-#endif /* CONFIG_MODULE_RDLINE_HISTORY */
-
-
-/* STATIC USEFUL FUNCS */
-
-static void
-rdline_puts_P(struct rdline * rdl, const prog_char * buf)
-{
- char c;
- while ( (c=pgm_read_byte(buf++)) != '\0' ) {
- rdl->write_char(c);
- }
-}
-
-/* a very very basic printf with one arg and one format 'u' */
-static void
-rdline_miniprintf_P(struct rdline * rdl, const prog_char * buf, uint8_t val)
-{
- char c, started=0, div=100;
-
- while ( (c=pgm_read_byte(buf++)) ) {
- if (c=='%') {
- c = pgm_read_byte(buf++);
-
- if (c=='u') { /* val is never more than 255 */
- while (div) {
- c = val / div;
- if (c || started) {
- rdl->write_char(c+'0');
- started = 1;
- }
- val %= div;
- div /= 10;
- }
- }
- else {
- rdl->write_char('%');
- rdl->write_char(c);
- }
- }
- else {
- rdl->write_char(c);
- }
- }
-}
-
+++ /dev/null
-/*
- * Copyright Droids Corporation (2007)
- * Olivier MATZ <zer0@droids-corp.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: rdline.h,v 1.1.2.6 2009-02-27 21:41:31 zer0 Exp $
- *
- *
- */
-
-#ifndef _RDLINE_H_
-#define _RDLINE_H_
-
-/**
- * This library is a small equivalent to the GNU readline library, but
- * it is designed for small systems, like Atmel AVR microcontrollers
- * (8 bits). Indeed, we don't use any malloc that is sometimes not
- * implemented on such systems.
- */
-
-#include <cirbuf.h>
-#include <vt100.h>
-
-#define vt100_bell "\007"
-#define vt100_bs "\010"
-#define vt100_bs_clear "\010 \010"
-#define vt100_tab "\011"
-#define vt100_crnl "\012\015"
-#define vt100_clear_right "\033[0K"
-#define vt100_clear_left "\033[1K"
-#define vt100_clear_down "\033[0J"
-#define vt100_clear_up "\033[1J"
-#define vt100_clear_line "\033[2K"
-#define vt100_clear_screen "\033[2J"
-#define vt100_up_arr "\033\133\101"
-#define vt100_down_arr "\033\133\102"
-#define vt100_right_arr "\033\133\103"
-#define vt100_left_arr "\033\133\104"
-#define vt100_multi_right "\033\133%uC"
-#define vt100_multi_left "\033\133%uD"
-#define vt100_suppr "\033\133\063\176"
-#define vt100_home "\033M\033E"
-#define vt100_word_left "\033\142"
-#define vt100_word_right "\033\146"
-
-/* configuration */
-#define RDLINE_BUF_SIZE 64
-#define RDLINE_PROMPT_SIZE 16
-#define RDLINE_VT100_BUF_SIZE 8
-#define RDLINE_HISTORY_BUF_SIZE 128
-#define RDLINE_HISTORY_MAX_LINE 64
-
-enum rdline_status {
- RDLINE_STOPPED,
- RDLINE_RUNNING,
-};
-
-struct rdline;
-
-typedef void (rdline_write_char_t)(char);
-typedef void (rdline_validate_t)(const char *buf, uint8_t size);
-typedef int8_t (rdline_complete_t)(const char *buf, char *dstbuf,
- uint8_t dstsize, int16_t *state);
-
-struct rdline {
- enum rdline_status status;
- /* rdline bufs */
- struct cirbuf left;
- struct cirbuf right;
- char left_buf[RDLINE_BUF_SIZE+2]; /* reserve 2 chars for the \n\0 */
- char right_buf[RDLINE_BUF_SIZE];
-
- char prompt[RDLINE_PROMPT_SIZE];
- uint8_t prompt_size;
-
-#ifdef CONFIG_MODULE_RDLINE_KILL_BUF
- char kill_buf[RDLINE_BUF_SIZE];
- uint8_t kill_size;
-#endif
-
-#ifdef CONFIG_MODULE_RDLINE_HISTORY
- /* history */
- struct cirbuf history;
- char history_buf[RDLINE_HISTORY_BUF_SIZE];
- int8_t history_cur_line;
-#endif
-
- /* callbacks and func pointers */
- rdline_write_char_t *write_char;
- rdline_validate_t *validate;
- rdline_complete_t *complete;
-
- /* vt100 parser */
- struct vt100 vt100;
-};
-
-/**
- * Init fields for a struct rdline. Call this only once at the beginning
- * of your program.
- * \param rdl A pointer to an uninitialized struct rdline
- * \param write_char The function used by the function to write a character
- * \param validate A pointer to the function to execute when the
- * user validates the buffer.
- * \param complete A pointer to the function to execute when the
- * user completes the buffer.
- */
-void rdline_init(struct rdline *rdl,
- rdline_write_char_t *write_char,
- rdline_validate_t *validate,
- rdline_complete_t *complete);
-
-
-/**
- * Init the current buffer, and display a prompt.
- * \param rdl A pointer to a struct rdline
- * \param prompt A string containing the prompt
- */
-void rdline_newline(struct rdline *rdl, const char *prompt);
-
-/**
- * Call it and all received chars will be ignored.
- * \param rdl A pointer to a struct rdline
- */
-void rdline_stop(struct rdline *rdl);
-
-/**
- * Restart after a call to rdline_stop()
- * \param rdl A pointer to a struct rdline
- */
-void rdline_restart(struct rdline *rdl);
-
-/**
- * Redisplay the current buffer
- * \param rdl A pointer to a struct rdline
- */
-void rdline_redisplay(struct rdline *rdl);
-
-
-/**
- * append a char to the readline buffer.
- * Return 1 when the line has been validated.
- * Return 2 when the user asked to complete the buffer.
- * Return -1 if it is not running.
- * Return -2 if EOF (ctrl-d on an empty line).
- * Else return 0.
- * XXX error case when the buffer is full ?
- *
- * \param rdl A pointer to a struct rdline
- * \param c The character to append
- */
-int8_t rdline_char_in(struct rdline * rdl, char c);
-
-/**
- * Return the current buffer, terminated by '\0'.
- * \param rdl A pointer to a struct rdline
- */
-const char *rdline_get_buffer(struct rdline *rdl);
-
-
-/**
- * Add the buffer to history.
- * return < 0 on error.
- * \param rdl A pointer to a struct rdline
- * \param buf A buffer that is terminated by '\0'
- */
-int8_t rdline_add_history(struct rdline *rdl, const char *buf);
-
-/**
- * Clear current history
- * \param rdl A pointer to a struct rdline
- */
-void rdline_clear_history(struct rdline *rdl);
-
-/**
- * Get the i-th history item
- */
-char *rdline_get_history_item(struct rdline *rdl, uint8_t i);
-
-#endif /* _RDLINE_H_ */
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: scheduler.c,v 1.9.4.6 2009-11-08 17:33:14 zer0 Exp $
- *
- */
-
-#include <string.h>
-#include <stdio.h>
-#include <inttypes.h>
-
-#include <aversive/parts.h>
-#include <aversive/pgmspace.h>
-#include <aversive.h>
-
-#include <scheduler.h>
-#include <scheduler_private.h>
-#include <scheduler_stats.h>
-#include <scheduler_config.h>
-
-
-/* this file is compiled for AVR version only */
-
-/** declared in scheduler_host.c in case of host version */
-struct event_t g_tab_event[SCHEDULER_NB_MAX_EVENT];
-
-#ifdef CONFIG_MODULE_SCHEDULER_STATS
-struct scheduler_stats sched_stats;
-#endif
-
-void scheduler_init(void)
-{
- memset(g_tab_event, 0, sizeof(g_tab_event));
-
-#ifdef CONFIG_MODULE_SCHEDULER_USE_TIMERS
- SCHEDULER_TIMER_REGISTER();
-#endif
-
-#ifdef CONFIG_MODULE_SCHEDULER_TIMER0
- /* activation of corresponding interrupt */
- TOIE0_REG |= (1<<TOIE0); /* TIMSK */
-
- TCNT0 = 0;
- CS00_REG = SCHEDULER_CK; /* TCCR0 */
-#endif
-}
-
-
-#ifdef CONFIG_MODULE_SCHEDULER_TIMER0
-SIGNAL(SIG_OVERFLOW0)
-{
- scheduler_interrupt();
-}
-#endif /* CONFIG_MODULE_SCHEDULER_USE_TIMERS */
+++ /dev/null
-/*
- * Copyright Droids Corporation (2007)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: scheduler.h,v 1.8.4.11 2009-05-18 12:30:36 zer0 Exp $
- *
- */
-
-/* Olivier MATZ <zer0@droids-corp.org>
- * Interface of the SCHEDULER Module
- */
-
-/** \file scheduler.h
- *
- * This module provides a function scheduler. You can call
- * scheduler_add_event for adding a function to the scheduler, and
- * specifying what interval between each call. During the execution of
- * the function, interrupts are masked !! So use this module with
- * caution (small functions) for avoiding problems.
- *
- * Functions with a high priority value will be call before others
- * (default is 128).
- *
- * This module uses Timer 0
- */
-
-
-#ifndef _SCHEDULER_H_
-#define _SCHEDULER_H_
-
-#include <aversive.h>
-
-#ifdef CONFIG_MODULE_SCHEDULER_USE_TIMERS
-#include <timer.h>
-#endif /* CONFIG_MODULE_SCHEDULER_USE_TIMERS */
-
-#include <scheduler_config.h>
-
-#ifdef CONFIG_MODULE_SCHEDULER_USE_TIMERS
-#if SCHEDULER_TIMER_NUM == 0
-#define SCHEDULER_TIMER_REGISTER() timer0_register_OV_intr(scheduler_interrupt)
-#define SCHEDULER_CLOCK_PRESCALER timer0_get_prescaler_div()
-#ifdef TCNT0H
-#define SCHEDULER_TIMER_BITS 16
-#else
-#define SCHEDULER_TIMER_BITS 8
-#endif
-
-#elif SCHEDULER_TIMER_NUM == 1
-#define SCHEDULER_TIMER_REGISTER() timer1_register_OV_intr(scheduler_interrupt)
-#define SCHEDULER_CLOCK_PRESCALER timer1_get_prescaler_div()
-#ifdef TCNT1H
-#define SCHEDULER_TIMER_BITS 16
-#else
-#define SCHEDULER_TIMER_BITS 8
-#endif
-
-#elif SCHEDULER_TIMER_NUM == 2
-#define SCHEDULER_TIMER_REGISTER() timer2_register_OV_intr(scheduler_interrupt)
-#define SCHEDULER_CLOCK_PRESCALER timer2_get_prescaler_div()
-#ifdef TCNT2H
-#define SCHEDULER_TIMER_BITS 16
-#else
-#define SCHEDULER_TIMER_BITS 8
-#endif
-
-#elif SCHEDULER_TIMER_NUM == 3
-#define SCHEDULER_TIMER_REGISTER() timer3_register_OV_intr(scheduler_interrupt)
-#define SCHEDULER_CLOCK_PRESCALER timer3_get_prescaler_div()
-#ifdef TCNT3H
-#define SCHEDULER_TIMER_BITS 16
-#else
-#define SCHEDULER_TIMER_BITS 8
-#endif
-
-#else
-#error "Bad SCHEDULER_TIMER_NUM value in config file"
-#endif
-
-#endif /* CONFIG_MODULE_SCHEDULER_USE_TIMERS */
-
-#ifdef CONFIG_MODULE_SCHEDULER_TIMER0
-#define SCHEDULER_TIMER_BITS 8
-#endif /* CONFIG_MODULE_SCHEDULER_TIMER0 */
-
-#ifndef CONFIG_MODULE_SCHEDULER_MANUAL
-
-/** TIME_UNIT is the number of microseconds between each interruption
- * if the prescaler equals 1 */
-#if SCHEDULER_TIMER_BITS == 8
-#define TIMER_UNIT_FLOAT ( 256000000.0 / (double)(CONFIG_QUARTZ) )
-#else
-#define TIMER_UNIT_FLOAT ( 65536000000.0 / (double)(CONFIG_QUARTZ) )
-#endif
-
-/** SCHEDULER_UNIT is the number of microseconds between each
- * scheduler interruption. We can use it like this :
- * scheduler_add_periodical_event(f, 1000L/SCHEDULER_UNIT);
- * The function f will be called every ms.
- */
-#define SCHEDULER_UNIT_FLOAT ( TIMER_UNIT_FLOAT * (double)SCHEDULER_CLOCK_PRESCALER )
-#define SCHEDULER_UNIT ( (unsigned long) SCHEDULER_UNIT_FLOAT )
-
-#endif /* ! CONFIG_MODULE_SCHEDULER_MANUAL */
-
-
-
-#define SCHEDULER_PERIODICAL 0
-#define SCHEDULER_SINGLE 1
-
-#define SCHEDULER_DEFAULT_PRIORITY 128
-
-
-/** Initialisation of the module */
-void scheduler_init(void);
-
-/** dump all loaded events */
-void scheduler_dump_events(void);
-
-/**
- * Add an event to the event table.
- * Return the id of the event on succes and -1 on error
- * You can use static inline funcs below for simpler use.
- */
-int8_t scheduler_add_event(uint8_t unicity, void (*f)(void *), void * data, uint16_t period, uint8_t priority);
-
-
-/**
- * Add a single event to the event table, specifying the priority
- */
-static inline int8_t scheduler_add_single_event_priority(void (*f)(void *), void * data, uint16_t period, uint8_t priority)
-{
- return scheduler_add_event(SCHEDULER_SINGLE, f, data, period, priority);
-}
-
-/**
- * Add a periodical event to the event table, specifying the priority
- */
-static inline int8_t scheduler_add_periodical_event_priority(void (*f)(void *), void * data, uint16_t period, uint8_t priority)
-{
- return scheduler_add_event(SCHEDULER_PERIODICAL, f, data, period, priority);
-}
-
-/**
- * Add a single event to the event table, with the default priority
- */
-static inline int8_t scheduler_add_single_event(void (*f)(void *), void * data, uint16_t period)
-{
- return scheduler_add_event(SCHEDULER_SINGLE, f, data, period, SCHEDULER_DEFAULT_PRIORITY);
-}
-
-/**
- * Add a periodical event to the event table, with the default priority
- */
-static inline int8_t scheduler_add_periodical_event(void (*f)(void *), void * data, uint16_t period)
-{
- return scheduler_add_event(SCHEDULER_PERIODICAL, f, data, period, SCHEDULER_DEFAULT_PRIORITY);
-}
-
-/**
- * Dels an event from the table by its ID. If there is no event,
- * nothing is done.
- */
-int8_t scheduler_del_event(int8_t num);
-
-/** Function called by the interruption. It is public in case of host
- * version, because you have to call it by hand. In AVR version, you
- * don't have to do anything with this function, it is called
- * automatilcally by the timer interruption, except if
- * CONFIG_MODULE_SCHEDULER_MANUAL is defined. In this case you have
- * to call it manually too. */
-void scheduler_interrupt(void);
-
-/**
- * Temporarily disable scheduler events. You may loose precision in
- * events schedule. It returns the current priority of the scheduler.
- */
-uint8_t scheduler_disable_save(void);
-
-/**
- * Re-enable scheduler after a call to scheduler_disable_save().
- */
-void scheduler_enable_restore(uint8_t old_prio);
-
-#endif
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: scheduler_add.c,v 1.1.2.4 2009-11-08 17:33:14 zer0 Exp $
- *
- */
-
-#include <aversive.h>
-#include <scheduler_config.h>
-#include <scheduler_private.h>
-#include <scheduler_stats.h>
-
-/** get a free event, mark it as allocated and return its index, or -1
- * if not found. */
-static inline int8_t
-scheduler_alloc_event(void)
-{
- uint8_t i;
- uint8_t flags;
-
- for (i=0 ; i<SCHEDULER_NB_MAX_EVENT ; i++) {
- IRQ_LOCK(flags);
- if( g_tab_event[i].state == SCHEDULER_EVENT_FREE ) {
- g_tab_event[i].state = SCHEDULER_EVENT_ALLOCATED;
- IRQ_UNLOCK(flags);
- return i;
- }
- IRQ_UNLOCK(flags);
- }
- SCHED_INC_STAT(alloc_fails);
- return -1;
-}
-
-
-/** Alloc an event, and fill its field, then mark it as active.
- * return its index in the table, or -1 if no evt is available */
-int8_t
-scheduler_add_event(uint8_t unicity, void (*f)(void *),
- void *data, uint16_t period,
- uint8_t priority) {
- int8_t i;
- uint8_t flags;
-
- if (period == 0)
- return -1;
-
- i = scheduler_alloc_event();
- if ( i == -1 )
- return -1;
-
- SCHED_INC_STAT(add_event);
-
- if (!unicity)
- g_tab_event[i].period = period ;
- else
- g_tab_event[i].period = 0 ;
- g_tab_event[i].current_time = period ;
- g_tab_event[i].priority = priority ;
- g_tab_event[i].f = f;
- g_tab_event[i].data = data;
-
- IRQ_LOCK(flags);
- g_tab_event[i].state = SCHEDULER_EVENT_ACTIVE;
- IRQ_UNLOCK(flags);
-
- return i;
-}
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: scheduler_del.c,v 1.1.2.3 2009-11-08 17:33:14 zer0 Exp $
- *
- */
-
-#include <aversive.h>
-#include <scheduler_config.h>
-#include <scheduler_private.h>
-#include <scheduler_stats.h>
-
-void scheduler_del_event(int8_t i)
-{
- uint8_t flags;
-
- /* if scheduled, it will be deleted after execution.
- * if active, free it.
- * else do nothing. */
- IRQ_LOCK(flags);
- if (g_tab_event[i].state == SCHEDULER_EVENT_SCHEDULED) {
- g_tab_event[i].state = SCHEDULER_EVENT_DELETING;
- }
- else if (g_tab_event[i].state == SCHEDULER_EVENT_ACTIVE) {
- g_tab_event[i].state = SCHEDULER_EVENT_FREE;
- }
- IRQ_UNLOCK(flags);
- SCHED_INC_STAT(del_event);
-}
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: scheduler_dump.c,v 1.1.2.3 2009-05-18 12:30:36 zer0 Exp $
- *
- */
-
-#include <stdio.h>
-
-#include <aversive.h>
-#include <aversive/pgmspace.h>
-
-#include <scheduler_config.h>
-#include <scheduler_private.h>
-
-/** Dump the event structure table */
-void scheduler_dump_events(void)
-{
- int i;
-
- printf_P(PSTR("== Dump events ==\r\n"));
- for (i=0 ; i<SCHEDULER_NB_MAX_EVENT ; i++) {
- printf_P(PSTR(" [%d]@%p : "), i, &g_tab_event[i]);
- printf_P(PSTR(" state=%d"), g_tab_event[i].state);
- if (g_tab_event[i].state >= SCHEDULER_EVENT_ACTIVE ) {
- printf_P(PSTR(", f=%p, "), g_tab_event[i].f);
- printf_P(PSTR("data=%p, "), g_tab_event[i].data);
- printf_P(PSTR("period=%d, "), g_tab_event[i].period);
- printf_P(PSTR("current_time=%d, "), g_tab_event[i].current_time);
- printf_P(PSTR("priority=%d, "), g_tab_event[i].priority);
- printf_P(PSTR("list_next=%p\r\n"), SLIST_NEXT(&g_tab_event[i], next));
- }
- else {
- printf_P(PSTR("\r\n"));
- }
- }
-}
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: scheduler_host.c,v 1.5.10.2 2007-03-05 14:41:07 zer0 Exp $
- *
- */
-
-#include <aversive.h>
-#include <stdio.h>
-#include <string.h>
-
-#include <scheduler_config.h>
-#include <scheduler_private.h>
-#include <scheduler_stats.h>
-
-/* this file is compiled for host version only */
-
-/** declared in scheduler.c in case of AVR version */
-struct event_t g_tab_event[SCHEDULER_NB_MAX_EVENT];
-
-#ifdef CONFIG_MODULE_SCHEDULER_STATS
-struct scheduler_stats sched_stats;
-#endif
-
-/** init all global data */
-void scheduler_init(void)
-{
- memset(g_tab_event, 0, sizeof(g_tab_event));
- printf("Scheduler init (host). Warning, you have to call\n"
- "scheduler_interrupt() by yourself on host version\n");
- DUMP_EVENTS();
-}
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: scheduler_interrupt.c,v 1.1.2.9 2009-11-08 17:33:14 zer0 Exp $
- *
- */
-
-#include <stdlib.h>
-
-#include <aversive.h>
-#include <scheduler_config.h>
-#include <scheduler_private.h>
-#include <scheduler_stats.h>
-
-/** priority of the running event */
-static volatile uint8_t priority_running=0;
-
-/** number of imbricated scheduler interruptions */
-static volatile uint8_t nb_stacking=0;
-
-uint8_t scheduler_disable_save(void)
-{
- uint8_t ret;
- ret = priority_running;
- priority_running = 255;
- return ret;
-}
-
-void scheduler_enable_restore(uint8_t old_prio)
-{
- priority_running = old_prio;
-}
-
-/**
- * this function is called from a timer interruption. If an event has
- * to be scheduled, it will execute the fonction (IRQ are allowed
- * during the execution of the function). This interruption can be
- * interrupted by itself too, in this case only events with a higher
- * priority can be scheduled.
- *
- * We assume that this function is called from a SIGNAL(), with
- * global interrupt flag disabled --> that's why we can use cli() and
- * sei() instead of IRQ_LOCK(flags).
- */
-void
-scheduler_interrupt(void)
-{
- uint8_t i;
- uint8_t priority_tmp;
- SLIST_HEAD(event_list_t, event_t) event_list;
- struct event_t *e, *next_e, *prev_e=NULL;
-
- /* maximize the number of imbrications */
- if (nb_stacking >= SCHEDULER_NB_STACKING_MAX) {
- SCHED_INC_STAT(max_stacking);
- return;
- }
-
- nb_stacking ++;
- sei();
-
- SLIST_INIT(&event_list);
-
- /* browse events table to determine which events should be
- * scheduled */
- for (i=0 ; i<SCHEDULER_NB_MAX_EVENT ; i++) {
- cli();
-
- /* the event is already present in a schedule list,
- * only update its current time until it reaches 1 */
- if (g_tab_event[i].state == SCHEDULER_EVENT_SCHEDULED) {
- if (g_tab_event[i].current_time > 1) {
- g_tab_event[i].current_time --;
- sei();
- continue;
- }
- else {
- SCHED_INC_STAT2(task_delayed, i);
- sei();
- continue;
- }
- }
-
- /* nothing to do with other unactive events */
- if (g_tab_event[i].state != SCHEDULER_EVENT_ACTIVE) {
- sei();
- continue;
- }
-
- /* decrement current time (we know it is >0 if it is
- * in SCHEDULER_EVENT_ACTIVE state */
- g_tab_event[i].current_time --;
-
- /* don't need to schedule now */
- if ( g_tab_event[i].current_time != 0 ) {
- sei();
- continue;
- }
-
- /* time to schedule, but priority is too low,
- * delay it */
- if (g_tab_event[i].priority <= priority_running) {
- g_tab_event[i].current_time = 1;
- SCHED_INC_STAT2(task_delayed, i);
- sei();
- continue;
- }
-
- /* reload event (it is 0 if it is non-periodical) */
- g_tab_event[i].current_time = g_tab_event[i].period;
-
- /* schedule it */
- g_tab_event[i].state = SCHEDULER_EVENT_SCHEDULED;
- SCHED_INC_STAT2(task_scheduled, i);
- sei();
-
- /* insert it in the list (list is ordered).
- this should be quite fast since the list is
- expected to be small. */
-
- e = SLIST_FIRST(&event_list);
- /* easy case : list is empty */
- if (e == NULL) {
- SLIST_INSERT_HEAD(&event_list, &g_tab_event[i], next);
- continue;
- }
-
- /* insert at head if it's the event with highest prio */
- if (g_tab_event[i].priority >= e->priority) {
- SLIST_INSERT_HEAD(&event_list, &g_tab_event[i], next);
- continue;
- }
-
- /* harder : find the good place in list */
- SLIST_FOREACH(e, &event_list, next) {
- next_e = SLIST_NEXT(e, next);
- if (next_e == NULL ||
- g_tab_event[i].priority >= next_e->priority) {
- SLIST_INSERT_AFTER(e, &g_tab_event[i], next);
- break;
- }
- }
- }
-
- /* only called if SCHEDULER_DEBUG is defined */
- DUMP_EVENTS();
-
- cli();
- priority_tmp = priority_running;
-
- SLIST_FOREACH(e, &event_list, next) {
- /* remove previous elt from list */
- if (prev_e)
- SLIST_NEXT(prev_e, next) = NULL;
-
- /* set running priority */
- priority_running = e->priority;
- sei();
-
- /* the following fields (f and data) can't be modified
- * while an event is in state SCHEDULED */
- e->f(e->data);
-
- cli();
- /* free it if it is single (non-periodical) */
- if (!e->period) {
- e->state = SCHEDULER_EVENT_FREE;
- }
-
- /* free event if someone asked for deletion during
- * schedule */
- if (e->state == SCHEDULER_EVENT_DELETING) {
- e->state = SCHEDULER_EVENT_FREE;
- }
-
- /* end of schedule, mark it as active */
- if (e->state == SCHEDULER_EVENT_SCHEDULED) {
- e->state = SCHEDULER_EVENT_ACTIVE;
- }
-
- prev_e = e;
- }
- /* remove previous elt from list */
- if (prev_e)
- SLIST_NEXT(prev_e, next) = NULL;
-
- priority_running = priority_tmp;
- nb_stacking--;
-}
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: scheduler_private.h,v 1.1.2.8 2009-05-18 12:30:36 zer0 Exp $
- *
- */
-
-#ifndef _SCHEDULER_PRIVATE_H_
-#define _SCHEDULER_PRIVATE_H_
-
-/* sanity checks */
-#if _SCHEDULER_CONFIG_VERSION_ != 4
-#warning "You are using an old version of scheduler_config.h file"
-#warning "_SCHEDULER_CONFIG_VERSION_ is != 4"
-#warning "Look in modules/base/scheduler/config directory to import changes"
-#warning "You should define SCHEDULER_NB_STACKING_MAX and SCHEDULER_CK"
-#endif
-
-#include <stdint.h>
-
-#include <aversive/queue.h>
-
-/** state of events */
-enum event_state_t {
- SCHEDULER_EVENT_FREE, /**< event is free */
- SCHEDULER_EVENT_ALLOCATED, /**< a place is reserved in the tab */
- SCHEDULER_EVENT_ACTIVE, /**< fields are filled correctly, event can be scheduled */
- SCHEDULER_EVENT_SCHEDULED, /**< event is inserted in a list to be running soon, or is running */
- SCHEDULER_EVENT_DELETING, /**< event is scheduled but we asked to delete it */
-};
-
-/** The event structure */
-struct event_t
-{
- void (*f)(void *); /**< a pointer to the scheduled function */
- void * data; /**< a pointer to the data parameters */
- uint16_t period; /**< interval between each call */
- uint16_t current_time; /**< time remaining before next call */
- uint8_t priority; /**< if many events occur at the
- same time, the first to be executed
- will be the one with the highest
- value of priority */
- enum event_state_t state; /**< (scheduled, active, allocated, free, deleting) */
-
- SLIST_ENTRY(event_t) next;
-};
-
-extern struct event_t g_tab_event[SCHEDULER_NB_MAX_EVENT];
-
-
-/* define dump_events() if we are in debug mode */
-#ifdef SCHEDULER_DEBUG
-#define DUMP_EVENTS() scheduler_dump_events()
-
-#else /* SCHEDULER_DEBUG */
-#define DUMP_EVENTS() do {} while(0)
-
-#endif /* SCHEDULER_DEBUG */
-
-#endif /* _SCHEDULER_PRIVATE_H_ */
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: scheduler.c,v 1.9.4.6 2009-11-08 17:33:14 zer0 Exp $
- *
- */
-
-#include <string.h>
-#include <stdio.h>
-#include <inttypes.h>
-
-#include <aversive/parts.h>
-#include <aversive/pgmspace.h>
-#include <aversive.h>
-
-#include <scheduler.h>
-#include <scheduler_stats.h>
-
-void scheduler_stats_dump(void)
-{
-#ifdef CONFIG_MODULE_SCHEDULER_STATS
- uint8_t i;
-
- printf_P(PSTR("alloc_fails: %"PRIu32"\r\n"), sched_stats.alloc_fails);
- printf_P(PSTR("add_event: %"PRIu32"\r\n"), sched_stats.add_event);
- printf_P(PSTR("del_event: %"PRIu32"\r\n"), sched_stats.del_event);
- printf_P(PSTR("max_stacking: %"PRIu32"\r\n"), sched_stats.max_stacking);
- for (i=0; i<SCHEDULER_NB_MAX_EVENT; i++) {
- printf_P(PSTR("[%d] task_delayed: %"PRIu32", "
- "task_scheduled: %"PRIu32"\r\n"),
- i, sched_stats.task_delayed[i],sched_stats.task_scheduled[i]);
- }
-#endif /* CONFIG_MODULE_SCHEDULER_STATS */
-}
+++ /dev/null
-/*
- * Copyright Droids Corporation (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: scheduler_stats.h,v 1.1.2.1 2009-11-08 17:33:14 zer0 Exp $
- *
- * Olivier MATZ <zer0@droids-corp.org>
- */
-
-#ifndef _SCHEDULER_STATS_H_
-#define _SCHEDULER_STATS_H_
-
-#ifdef CONFIG_MODULE_SCHEDULER_STATS
-struct scheduler_stats {
- uint32_t alloc_fails;
- uint32_t add_event;
- uint32_t del_event;
- uint32_t max_stacking;
- uint32_t task_delayed[SCHEDULER_NB_MAX_EVENT];
- uint32_t task_scheduled[SCHEDULER_NB_MAX_EVENT];
-};
-
-extern struct scheduler_stats sched_stats;
-
-#define SCHED_INC_STAT(x) do { \
- uint8_t flags; \
- IRQ_LOCK(flags); \
- sched_stats.x++; \
- IRQ_UNLOCK(flags); \
- } while(0)
-
-#define SCHED_INC_STAT2(x, i) do { \
- uint8_t flags; \
- IRQ_LOCK(flags); \
- sched_stats.x[i]++; \
- IRQ_UNLOCK(flags); \
- } while(0)
-
-
-#else /* CONFIG_MODULE_SCHEDULER_STATS */
-
-#define SCHED_INC_STAT(x) do { } while(0)
-#define SCHED_INC_STAT2(x, i) do { } while(0)
-
-#endif /* CONFIG_MODULE_SCHEDULER_STATS */
-
-void scheduler_stats_dump(void);
-
-#endif /* _SCHEDULER_STATS_H_ */
};
} byte1;
+#define SS_HIGH() PORTB |= (1 << 4)
+#define SS_LOW() PORTB &= (~(1 << 4))
+
void spi_servo_init(void)
{
- /* real SS ! */
- DDRK = 0x2;
/* SCK, SS & MOSI */
- DDRB = 0x7;
+ DDRB = 0xb0;
/* remove power reduction on spi */
PRR0 &= ~(1 << PRSPI);
/* Enable SPI, Master, set clock rate fck/64 */
SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR1);
- PORTK |= (1<<1);
+ SS_HIGH();
spi_servo_set(BYPASS_DISABLE, 0);
}
byte1.one = 1;
byte1.val_lsb = val;
- PORTK &= ~(1<<1);
+ SS_LOW();
SPDR = byte0.u8;
/* Wait for transmission complete */
while(!(SPSR & (1<<SPIF)));
- PORTK |= (1<<1);
+ SS_HIGH();
_delay_loop_1(5);
- PORTK &= ~(1<<1);
+ SS_LOW();
SPDR = byte1.u8;
/* Wait for transmission complete */
while(!(SPSR & (1<<SPIF)));
- PORTK |= (1<<1);
+ SS_HIGH();
}
void spi_servo_bypass(uint8_t enable)
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: stack_space.c,v 1.7.4.3 2008-05-09 08:23:52 zer0 Exp $
- *
- */
-
-#include <avr/io.h>
-#include <aversive.h>
-
-
-#include <diagnostic.h>
-
-
-/** This diagnostical software fills the RAM with a mark, and counts
- * how many of these marks are unmodified, in order to avaluate the
- * min stack space available after code execution. You can then know
- * how much your stack your program needed in a peak, without looking
- * espacially when this peak arises. you see the minmal stack space
- * left since the reset of the microcontroller. */
-
-// call this function at the beginning of program
-void fill_mem_with_mark(void) __attribute__ ((naked)) \
-__attribute__ ((section (".init1")));
-
-
-/** this functions fills the ram with a predefined pattern after a
- * reset and BEFORE any other operation */
-void fill_mem_with_mark(void)
-{
-/* register int i asm("r16"); */
-/* register int end asm("r18"); */
-
-
-/* // where is the beginning of the RAM memory ? */
-/* #ifdef DIAG_FILL_ENTIRE_RAM // fill entire RAM */
-/* asm( "ldi r16,lo8(__data_start)" ); */
-/* asm( "ldi r17,hi8(__data_start)" ); */
-/* #else // fill only stack and heap spaces */
-/* asm( "ldi r16,lo8(__heap_start)" ); */
-/* asm( "ldi r17,hi8(__heap_start)" ); */
-/* #endif */
-
-/* // end of RAM */
-/* asm( "ldi r18,lo8(__stack)" ); */
-/* asm( "ldi r19,hi8(__stack)" ); */
-
-/* // fill ram with the spacified pattern */
-/* for(; i< end ; i++) */
-/* * ( (volatile unsigned char* )(i) ) = MARK; */
-
-}
-
-
-uint16_t min_stack_space_available(void)
-{
- /* register int i asm("r16"); */
- /* register int end asm("r18"); */
- /* uint16_t count , max; */
-
- /* // where is the beginning of the stack space ? */
- /* asm( "ldi r16,lo8(__heap_start)" ); */
- /* asm( "ldi r17,hi8(__heap_start)" ); */
- /* // end of RAM */
- /* asm( "ldi r18,lo8(__stack)" ); */
- /* asm( "ldi r19,hi8(__stack)" ); */
-
- /* /\* the algorithm finds the size of the biggest zone filled */
- /* * with the mark, which is normally the stack space left *\/ */
- /* count = 0; */
- /* max = 0; */
- /* for(; i<end; i++) { */
- /* // = mark? */
- /* if (MARK == * ( (volatile unsigned char* )(i) )) { */
- /* // count */
- /* count ++; */
- /* if (count > max) */
- /* max = count; */
- /* } */
- /* else */
- /* count = 0; // reset counter */
- /* } */
-
- /* return max; */
- return 0;
-}
+++ /dev/null
-/*
- * Copyright Droids Corporation (2010)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: trajectory_manager.c,v 1.4.4.17 2009-05-18 12:28:36 zer0 Exp $
- *
- */
-
-#include <stdint.h>
-#include <stdio.h>
-
-void stackdump(void)
-{
- uint8_t dummy = 0x55;
- uint16_t i;
-
- for (i=0; i<256; i++) {
- printf("%.2x%s", *(&dummy + i),
- ((i % 16) == 15) ? "\n" : " ");
- }
-}
+++ /dev/null
-/*
- * Copyright Droids Corporation (2010)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: trajectory_manager.c,v 1.4.4.17 2009-05-18 12:28:36 zer0 Exp $
- *
- */
-
-void stackdump(void);
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: time.c,v 1.4.4.5 2009-04-24 19:26:37 zer0 Exp $
- *
- */
-
-/* Droids-corp, Eirbot, Microb Technology 2005 - Zer0
- * Implementation of the time module
- */
-
-/** \file time.c
- * \brief Implementation of the TIME module.
- *
- *
- * This module can be used to get a human readable time. It uses the
- * scheduler module. Its goal is not to be very precise, but just
- * simple to use.
- */
-
-
-/**********************************************************/
-
-#include <stdlib.h>
-#include <scheduler.h>
-
-#include <clock_time.h>
-#include <time_config.h>
-
-/**********************************************************/
-
-#define NB_SCHEDULER_UNIT ( ((float)(TIME_PRECISION)) / SCHEDULER_UNIT_FLOAT )
-#define NB_SCHEDULER_UNIT_NOT_NULL (NB_SCHEDULER_UNIT == 0 ? 1.0 : NB_SCHEDULER_UNIT)
-
-static volatile time_h t;
-
-static volatile microseconds us2; // this one overflows naturally
-
-
-void time_increment(void * dummy);
-
-/**********************************************************/
-
-void time_init(uint8_t priority)
-{
- time_reset();
- scheduler_add_periodical_event_priority(time_increment,NULL,
- (int)NB_SCHEDULER_UNIT_NOT_NULL, priority);
-}
-
-/**********************************************************/
-
-seconds time_get_s(void)
-{
- uint16_t tmp;
- uint8_t flags;
- IRQ_LOCK(flags);
- tmp = t.s;
- IRQ_UNLOCK(flags);
- return tmp;
-}
-
-/**********************************************************/
-
-microseconds time_get_us(void)
-{
- microseconds tmp;
- uint8_t flags;
- IRQ_LOCK(flags);
- tmp = t.us;
- IRQ_UNLOCK(flags);
- return tmp;
-}
-
-/**********************************************************/
-
-microseconds time_get_us2(void)
-{
- microseconds tmp;
- uint8_t flags;
- IRQ_LOCK(flags);
- tmp = us2;
- IRQ_UNLOCK(flags);
- return tmp;
-}
-
-/**********************************************************/
-
-time_h time_get_time(void)
-{
- time_h tmp;
- uint8_t flags;
- IRQ_LOCK(flags);
- tmp = t;
- IRQ_UNLOCK(flags);
- return tmp;
-}
-
-/**********************************************************/
-
-void time_reset(void)
-{
- uint8_t flags;
- IRQ_LOCK(flags);
- t.us = 0;
- t.s = 0;
- IRQ_UNLOCK(flags);
-}
-
-/**********************************************************/
-
-void time_set(seconds s, microseconds us)
-{
- uint8_t flags;
- IRQ_LOCK(flags);
- t.us = us;
- t.s = s;
- IRQ_UNLOCK(flags);
-}
-
-/**********************************************************/
-
-void time_wait_ms(uint16_t ms)
-{
- microseconds old = time_get_us2();
- while (time_get_us2() - old < ms*1000L);
-}
-
-/**********************************************************/
-/* private */
-/**********************************************************/
-
-void time_increment(__attribute__((unused)) void * dummy)
-{
- uint8_t flags;
- /* XXX we should lock only when writing */
- IRQ_LOCK(flags); // for reading correct time inside an interrupt
-
- us2 += ((int)NB_SCHEDULER_UNIT_NOT_NULL * SCHEDULER_UNIT);
- t.us += ((int)NB_SCHEDULER_UNIT_NOT_NULL * SCHEDULER_UNIT);
- while (t.us > 1000000) {
- t.s ++;
- t.us -= 1000000;
- }
-
- IRQ_UNLOCK(flags);
-}
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer.h,v 1.1.2.4 2007-05-23 17:18:14 zer0 Exp $
- *
- */
-
-/**
- * Olivier MATZ - Droids-corp 2006
- *
- * \brief Interface of the timer module
- *
- * The objective of this module is to provide a simple and portable
- * interface to the hardware timers of AVR devices.
- */
-
-#ifndef _TIMER_H_
-#define _TIMER_H_
-
-#include <aversive/parts.h>
-
-#include <aversive.h>
-#include <timer_declarations.h>
-#include <timer_definitions.h>
-#include <timer_prescaler.h>
-
-#include <timer_config.h>
-
-
-/** Init of all timers with static configutaion (see timer_config.h) */
-void timer_init(void);
-
-/* declare all timer functions (see timer_declarations.h) */
-
-#if defined TIMER0_ENABLED && defined TIMER0_AVAILABLE
-DECLARE_TIMER_FUNCS(0)
-#endif
-
-#if defined TIMER1_ENABLED && defined TIMER1_AVAILABLE
-DECLARE_TIMER_FUNCS(1)
-#endif
-
-#if defined TIMER2_ENABLED && defined TIMER2_AVAILABLE
-DECLARE_TIMER_FUNCS(2)
-#endif
-
-#if defined TIMER3_ENABLED && defined TIMER3_AVAILABLE
-DECLARE_TIMER_FUNCS(3)
-#endif
-
-/* define static inline functions (see timer_definitions.h) */
-
-#if defined TIMER0_ENABLED && defined TIMER0_AVAILABLE
-DEFINE_TIMER_US_CONVERSIONS(0)
-#endif
-
-#if defined TIMER1_ENABLED && defined TIMER1_AVAILABLE
-DEFINE_TIMER_US_CONVERSIONS(1)
-#endif
-
-#if defined TIMER2_ENABLED && defined TIMER2_AVAILABLE
-DEFINE_TIMER_US_CONVERSIONS(2)
-#endif
-
-#if defined TIMER3_ENABLED && defined TIMER3_AVAILABLE
-DEFINE_TIMER_US_CONVERSIONS(3)
-#endif
-
-#endif
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer0_getset.c,v 1.1.2.2 2007-05-23 17:18:14 zer0 Exp $
- *
- */
-
-#include <stdint.h>
-
-#include <aversive.h>
-#include <aversive/parts.h>
-#include <aversive/timers.h>
-
-#include <timer.h>
-#include <timer_definitions.h>
-#include <timer_config.h>
-
-#if defined TIMER0_ENABLED && defined TIMER0_AVAILABLE
-DEFINE_TIMER_GET_SET(0)
-#endif
-
+++ /dev/null
-/*
- * Copyright Droids-corporation, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer0_prescaler.c,v 1.1.2.3 2009-01-30 20:18:36 zer0 Exp $
- *
- */
-
-#include <stdint.h>
-
-#include <aversive.h>
-#include <aversive/parts.h>
-#include <aversive/timers.h>
-
-#include <timer.h>
-#include <timer_definitions.h>
-#include <timer_prescaler.h>
-
-#include <timer_config.h>
-
-
-#ifdef CONFIG_MODULE_TIMER_DYNAMIC
-
-#if defined TIMER0_ENABLED && defined TIMER0_AVAILABLE
-DEFINE_DYNAMIC_PRESCALER_FUNCS(0)
-#endif
-
-#else
-
-#if defined TIMER0_ENABLED && defined TIMER0_AVAILABLE
-DEFINE_STATIC_PRESCALER_FUNCS(0)
-#endif
-
-#endif
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer0_register_OC_at_tics.c,v 1.1.2.3 2009-01-30 20:18:36 zer0 Exp $
- *
- */
-
-#include <stdint.h>
-#include <string.h>
-
-#include <aversive.h>
-#include <aversive/parts.h>
-#include <aversive/timers.h>
-
-#include <timer.h>
-#include <timer_definitions.h>
-#include <timer_intr.h>
-#include <timer_config.h>
-
-
-#if defined TIMER0_ENABLED && defined SIG_OUTPUT_COMPARE0
-DEFINE_REGISTER_OC_INTR_AT_TICS(0)
-#endif
-
-#if defined TIMER0A_ENABLED && defined SIG_OUTPUT_COMPARE0A
-DEFINE_REGISTER_OC_INTR_AT_TICS(0A)
-#endif
-
-#if defined TIMER0B_ENABLED && defined SIG_OUTPUT_COMPARE0B
-DEFINE_REGISTER_OC_INTR_AT_TICS(0B)
-#endif
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer0_register_OC_in_us.c,v 1.1.2.3 2009-01-30 20:18:36 zer0 Exp $
- *
- */
-
-#include <stdint.h>
-#include <string.h>
-
-#include <aversive.h>
-#include <aversive/parts.h>
-#include <aversive/timers.h>
-
-#include <timer.h>
-#include <timer_definitions.h>
-#include <timer_intr.h>
-#include <timer_config.h>
-
-
-#if defined TIMER0_ENABLED && defined SIG_OUTPUT_COMPARE0
-DEFINE_REGISTER_OC_INTR_IN_US(0,0)
-#endif
-
-#if defined TIMER0A_ENABLED && defined SIG_OUTPUT_COMPARE0A
-DEFINE_REGISTER_OC_INTR_IN_US(0,0A)
-#endif
-
-#if defined TIMER0B_ENABLED && defined SIG_OUTPUT_COMPARE0B
-DEFINE_REGISTER_OC_INTR_IN_US(0,0B)
-#endif
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer0_register_OV.c,v 1.1.2.2 2007-05-23 17:18:14 zer0 Exp $
- *
- */
-
-#include <stdint.h>
-#include <string.h>
-
-#include <aversive.h>
-#include <aversive/parts.h>
-#include <aversive/timers.h>
-
-#include <timer.h>
-#include <timer_definitions.h>
-#include <timer_intr.h>
-#include <timer_config.h>
-
-#if defined TIMER0_ENABLED && defined SIG_OVERFLOW0
-DEFINE_REGISTER_OV_INTR(0)
-#endif
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer0_startstop.c,v 1.1.2.2 2007-05-23 17:18:14 zer0 Exp $
- *
- */
-
-#include <stdint.h>
-
-#include <aversive.h>
-#include <aversive/parts.h>
-#include <aversive/timers.h>
-
-#include <timer.h>
-#include <timer_definitions.h>
-#include <timer_prescaler.h>
-#include <timer_config.h>
-
-#if defined TIMER0_ENABLED && defined TIMER0_AVAILABLE
-DEFINE_TIMER_START_STOP(0)
-#endif
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer1_getset.c,v 1.1.2.2 2007-05-23 17:18:14 zer0 Exp $
- *
- */
-
-#include <stdint.h>
-
-#include <aversive.h>
-#include <aversive/parts.h>
-#include <aversive/timers.h>
-
-#include <timer.h>
-#include <timer_definitions.h>
-#include <timer_config.h>
-
-#if defined TIMER1_ENABLED && defined TIMER1_AVAILABLE
-DEFINE_TIMER_GET_SET(1)
-#endif
-
+++ /dev/null
-/*
- * Copyright DroidsDEFINE_STATIC_CONVERSIONS_FUNCSion, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer1_prescaler.c,v 1.1.2.2 2007-05-23 17:18:14 zer0 Exp $
- *
- */
-
-#include <stdint.h>
-
-#include <aversive.h>
-#include <aversive/parts.h>
-#include <aversive/timers.h>
-
-#include <timer.h>
-#include <timer_definitions.h>
-#include <timer_prescaler.h>
-
-#include <timer_config.h>
-
-
-#ifdef CONFIG_MODULE_TIMER_DYNAMIC
-
-#if defined TIMER1_ENABLED && defined TIMER1_AVAILABLE
-DEFINE_DYNAMIC_PRESCALER_FUNCS(1)
-#endif
-
-#else
-
-#if defined TIMER1_ENABLED && defined TIMER1_AVAILABLE
-DEFINE_STATIC_PRESCALER_FUNCS(1)
-#endif
-
-#endif
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer1_register_OC_at_tics.c,v 1.1.2.2 2007-05-23 17:18:15 zer0 Exp $
- *
- */
-
-#include <stdint.h>
-#include <string.h>
-
-#include <aversive.h>
-#include <aversive/parts.h>
-#include <aversive/timers.h>
-
-#include <timer.h>
-#include <timer_definitions.h>
-#include <timer_intr.h>
-#include <timer_config.h>
-
-
-#if defined TIMER1A_ENABLED && defined SIG_OUTPUT_COMPARE1A
-DEFINE_REGISTER_OC_INTR_AT_TICS(1A)
-#endif
-
-#if defined TIMER1B_ENABLED && defined SIG_OUTPUT_COMPARE1B
-DEFINE_REGISTER_OC_INTR_AT_TICS(1B)
-#endif
-
-#if defined TIMER1C_ENABLED && defined SIG_OUTPUT_COMPARE1C
-DEFINE_REGISTER_OC_INTR_AT_TICS(1C)
-#endif
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer1_register_OC_in_us.c,v 1.1.2.2 2007-05-23 17:18:15 zer0 Exp $
- *
- */
-
-#include <stdint.h>
-#include <string.h>
-
-#include <aversive.h>
-#include <aversive/parts.h>
-#include <aversive/timers.h>
-
-#include <timer.h>
-#include <timer_definitions.h>
-#include <timer_intr.h>
-#include <timer_config.h>
-
-
-#if defined TIMER1A_ENABLED && defined SIG_OUTPUT_COMPARE1A
-DEFINE_REGISTER_OC_INTR_IN_US(1,1A)
-#endif
-
-#if defined TIMER1B_ENABLED && defined SIG_OUTPUT_COMPARE1B
-DEFINE_REGISTER_OC_INTR_IN_US(1,1B)
-#endif
-
-#if defined TIMER1C_ENABLED && defined SIG_OUTPUT_COMPARE1C
-DEFINE_REGISTER_OC_INTR_IN_US(1,1C)
-#endif
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer1_register_OV.c,v 1.1.2.2 2007-05-23 17:18:15 zer0 Exp $
- *
- */
-
-#include <stdint.h>
-#include <string.h>
-
-#include <aversive.h>
-#include <aversive/parts.h>
-#include <aversive/timers.h>
-
-#include <timer.h>
-#include <timer_definitions.h>
-#include <timer_intr.h>
-#include <timer_config.h>
-
-
-#if defined TIMER1_ENABLED && defined SIG_OVERFLOW1
-DEFINE_REGISTER_OV_INTR(1)
-#endif
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer1_startstop.c,v 1.1.2.2 2007-05-23 17:18:15 zer0 Exp $
- *
- */
-
-#include <stdint.h>
-
-#include <aversive.h>
-#include <aversive/parts.h>
-#include <aversive/timers.h>
-#include <timer.h>
-#include <timer_definitions.h>
-#include <timer_prescaler.h>
-#include <timer_config.h>
-
-#if defined TIMER1_ENABLED && defined TIMER1_AVAILABLE
-DEFINE_TIMER_START_STOP(1)
-#endif
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer2_getset.c,v 1.1.2.2 2007-05-23 17:18:15 zer0 Exp $
- *
- */
-
-#include <stdint.h>
-
-#include <aversive.h>
-#include <aversive/parts.h>
-#include <aversive/timers.h>
-#include <timer.h>
-#include <timer_definitions.h>
-#include <timer_config.h>
-
-#if defined TIMER2_ENABLED && defined TIMER2_AVAILABLE
-DEFINE_TIMER_GET_SET(2)
-#endif
-
+++ /dev/null
-/*
- * Copyright DroidsDEFINE_STATIC_CONVERSIONS_FUNCSion, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer2_prescaler.c,v 1.1.2.2 2007-05-23 17:18:15 zer0 Exp $
- *
- */
-
-#include <stdint.h>
-
-#include <aversive.h>
-#include <aversive/parts.h>
-#include <aversive/timers.h>
-
-#include <timer.h>
-#include <timer_definitions.h>
-#include <timer_prescaler.h>
-
-#include <timer_config.h>
-
-
-#ifdef CONFIG_MODULE_TIMER_DYNAMIC
-
-#if defined TIMER2_ENABLED && defined TIMER2_AVAILABLE
-DEFINE_DYNAMIC_PRESCALER_FUNCS(2)
-#endif
-
-#else
-
-#if defined TIMER2_ENABLED && defined TIMER2_AVAILABLE
-DEFINE_STATIC_PRESCALER_FUNCS(2)
-#endif
-
-#endif
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer2_register_OC_at_tics.c,v 1.1.2.2 2007-05-23 17:18:15 zer0 Exp $
- *
- */
-
-#include <stdint.h>
-#include <string.h>
-
-#include <aversive.h>
-#include <aversive/parts.h>
-#include <aversive/timers.h>
-
-#include <timer.h>
-#include <timer_definitions.h>
-#include <timer_intr.h>
-#include <timer_config.h>
-
-
-#if defined TIMER2_ENABLED && defined SIG_OUTPUT_COMPARE2
-DEFINE_REGISTER_OC_INTR_AT_TICS(2)
-#endif
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer2_register_OC_in_us.c,v 1.1.2.2 2007-05-23 17:18:15 zer0 Exp $
- *
- */
-
-#include <stdint.h>
-#include <string.h>
-
-#include <aversive.h>
-#include <aversive/parts.h>
-#include <aversive/timers.h>
-
-#include <timer.h>
-#include <timer_definitions.h>
-#include <timer_intr.h>
-#include <timer_config.h>
-
-
-#if defined TIMER2_ENABLED && defined SIG_OUTPUT_COMPARE2
-DEFINE_REGISTER_OC_INTR_IN_US(2,2)
-#endif
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer2_register_OV.c,v 1.1.2.2 2007-05-23 17:18:15 zer0 Exp $
- *
- */
-
-#include <stdint.h>
-#include <string.h>
-
-#include <aversive.h>
-#include <aversive/parts.h>
-#include <aversive/timers.h>
-
-#include <timer.h>
-#include <timer_definitions.h>
-#include <timer_intr.h>
-#include <timer_config.h>
-
-
-#if defined TIMER2_ENABLED && defined SIG_OVERFLOW2
-DEFINE_REGISTER_OV_INTR(2)
-#endif
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer2_startstop.c,v 1.1.2.2 2007-05-23 17:18:15 zer0 Exp $
- *
- */
-
-#include <stdint.h>
-
-#include <aversive.h>
-#include <aversive/parts.h>
-#include <aversive/timers.h>
-#include <timer.h>
-#include <timer_definitions.h>
-#include <timer_prescaler.h>
-#include <timer_config.h>
-
-#if defined TIMER2_ENABLED && defined TIMER2_AVAILABLE
-DEFINE_TIMER_START_STOP(2)
-#endif
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer3_getset.c,v 1.1.2.2 2007-05-23 17:18:15 zer0 Exp $
- *
- */
-
-#include <stdint.h>
-
-#include <aversive.h>
-#include <aversive/parts.h>
-#include <aversive/timers.h>
-#include <timer.h>
-#include <timer_definitions.h>
-#include <timer_config.h>
-
-#if defined TIMER3_ENABLED && defined TIMER3_AVAILABLE
-DEFINE_TIMER_GET_SET(3)
-#endif
-
+++ /dev/null
-/*
- * Copyright DroidsDEFINE_STATIC_CONVERSIONS_FUNCSion, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer3_prescaler.c,v 1.1.2.2 2007-05-23 17:18:15 zer0 Exp $
- *
- */
-
-#include <stdint.h>
-
-#include <aversive.h>
-#include <aversive/parts.h>
-#include <aversive/timers.h>
-
-#include <timer.h>
-#include <timer_definitions.h>
-#include <timer_prescaler.h>
-
-#include <timer_config.h>
-
-
-#ifdef CONFIG_MODULE_TIMER_DYNAMIC
-
-#if defined TIMER3_ENABLED && defined TIMER3_AVAILABLE
-DEFINE_DYNAMIC_PRESCALER_FUNCS(3)
-#endif
-
-#else
-
-#if defined TIMER3_ENABLED && defined TIMER3_AVAILABLE
-DEFINE_STATIC_PRESCALER_FUNCS(3)
-#endif
-
-#endif
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer3_register_OC_at_tics.c,v 1.1.2.2 2007-05-23 17:18:15 zer0 Exp $
- *
- */
-
-#include <stdint.h>
-#include <string.h>
-
-#include <aversive.h>
-#include <aversive/parts.h>
-#include <aversive/timers.h>
-
-#include <timer.h>
-#include <timer_definitions.h>
-#include <timer_intr.h>
-#include <timer_config.h>
-
-
-#if defined TIMER3A_ENABLED && defined SIG_OUTPUT_COMPARE3A
-DEFINE_REGISTER_OC_INTR_AT_TICS(3A)
-#endif
-
-#if defined TIMER3B_ENABLED && defined SIG_OUTPUT_COMPARE3B
-DEFINE_REGISTER_OC_INTR_AT_TICS(3B)
-#endif
-
-#if defined TIMER3C_ENABLED && defined SIG_OUTPUT_COMPARE3C
-DEFINE_REGISTER_OC_INTR_AT_TICS(3C)
-#endif
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer3_register_OC_in_us.c,v 1.1.2.2 2007-05-23 17:18:15 zer0 Exp $
- *
- */
-
-#include <stdint.h>
-#include <string.h>
-
-#include <aversive.h>
-#include <aversive/parts.h>
-#include <aversive/timers.h>
-
-#include <timer.h>
-#include <timer_definitions.h>
-#include <timer_intr.h>
-#include <timer_config.h>
-
-
-#if defined TIMER3A_ENABLED && defined SIG_OUTPUT_COMPARE3A
-DEFINE_REGISTER_OC_INTR_IN_US(3,3A)
-#endif
-
-#if defined TIMER3B_ENABLED && defined SIG_OUTPUT_COMPARE3B
-DEFINE_REGISTER_OC_INTR_IN_US(3,3B)
-#endif
-
-#if defined TIMER3C_ENABLED && defined SIG_OUTPUT_COMPARE3C
-DEFINE_REGISTER_OC_INTR_IN_US(3,3C)
-#endif
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer3_register_OV.c,v 1.1.2.2 2007-05-23 17:18:15 zer0 Exp $
- *
- */
-
-#include <stdint.h>
-#include <string.h>
-
-#include <aversive.h>
-#include <aversive/parts.h>
-#include <aversive/timers.h>
-
-#include <timer.h>
-#include <timer_definitions.h>
-#include <timer_intr.h>
-#include <timer_config.h>
-
-
-#if defined TIMER3_ENABLED && defined SIG_OVERFLOW3
-DEFINE_REGISTER_OV_INTR(3)
-#endif
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer3_startstop.c,v 1.1.2.2 2007-05-23 17:18:15 zer0 Exp $
- *
- */
-
-#include <stdint.h>
-
-#include <aversive.h>
-#include <aversive/parts.h>
-#include <aversive/timers.h>
-#include <timer.h>
-#include <timer_definitions.h>
-#include <timer_prescaler.h>
-#include <timer_config.h>
-
-#if defined TIMER3_ENABLED && defined TIMER3_AVAILABLE
-DEFINE_TIMER_START_STOP(3)
-#endif
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer4_getset.c,v 1.1.2.1 2009-01-30 20:18:36 zer0 Exp $
- *
- */
-
-#include <stdint.h>
-
-#include <aversive.h>
-#include <aversive/parts.h>
-#include <aversive/timers.h>
-#include <timer.h>
-#include <timer_definitions.h>
-#include <timer_config.h>
-
-#if defined TIMER4_ENABLED && defined TIMER4_AVAILABLE
-DEFINE_TIMER_GET_SET(4)
-#endif
-
+++ /dev/null
-/*
- * Copyright DroidsDEFINE_STATIC_CONVERSIONS_FUNCSion, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer4_prescaler.c,v 1.1.2.1 2009-01-30 20:18:36 zer0 Exp $
- *
- */
-
-#include <stdint.h>
-
-#include <aversive.h>
-#include <aversive/parts.h>
-#include <aversive/timers.h>
-
-#include <timer.h>
-#include <timer_definitions.h>
-#include <timer_prescaler.h>
-
-#include <timer_config.h>
-
-
-#ifdef CONFIG_MODULE_TIMER_DYNAMIC
-
-#if defined TIMER4_ENABLED && defined TIMER4_AVAILABLE
-DEFINE_DYNAMIC_PRESCALER_FUNCS(4)
-#endif
-
-#else
-
-#if defined TIMER4_ENABLED && defined TIMER4_AVAILABLE
-DEFINE_STATIC_PRESCALER_FUNCS(4)
-#endif
-
-#endif
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer4_register_OC_at_tics.c,v 1.1.2.1 2009-01-30 20:18:36 zer0 Exp $
- *
- */
-
-#include <stdint.h>
-#include <string.h>
-
-#include <aversive.h>
-#include <aversive/parts.h>
-#include <aversive/timers.h>
-
-#include <timer.h>
-#include <timer_definitions.h>
-#include <timer_intr.h>
-#include <timer_config.h>
-
-
-#if defined TIMER4A_ENABLED && defined SIG_OUTPUT_COMPARE4A
-DEFINE_REGISTER_OC_INTR_AT_TICS(4A)
-#endif
-
-#if defined TIMER4B_ENABLED && defined SIG_OUTPUT_COMPARE4B
-DEFINE_REGISTER_OC_INTR_AT_TICS(4B)
-#endif
-
-#if defined TIMER4C_ENABLED && defined SIG_OUTPUT_COMPARE4C
-DEFINE_REGISTER_OC_INTR_AT_TICS(4C)
-#endif
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer4_register_OC_in_us.c,v 1.1.2.1 2009-01-30 20:18:36 zer0 Exp $
- *
- */
-
-#include <stdint.h>
-#include <string.h>
-
-#include <aversive.h>
-#include <aversive/parts.h>
-#include <aversive/timers.h>
-
-#include <timer.h>
-#include <timer_definitions.h>
-#include <timer_intr.h>
-#include <timer_config.h>
-
-
-#if defined TIMER4A_ENABLED && defined SIG_OUTPUT_COMPARE4A
-DEFINE_REGISTER_OC_INTR_IN_US(4,4A)
-#endif
-
-#if defined TIMER4B_ENABLED && defined SIG_OUTPUT_COMPARE4B
-DEFINE_REGISTER_OC_INTR_IN_US(4,4B)
-#endif
-
-#if defined TIMER4C_ENABLED && defined SIG_OUTPUT_COMPARE4C
-DEFINE_REGISTER_OC_INTR_IN_US(4,4C)
-#endif
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer4_register_OV.c,v 1.1.2.1 2009-01-30 20:18:36 zer0 Exp $
- *
- */
-
-#include <stdint.h>
-#include <string.h>
-
-#include <aversive.h>
-#include <aversive/parts.h>
-#include <aversive/timers.h>
-
-#include <timer.h>
-#include <timer_definitions.h>
-#include <timer_intr.h>
-#include <timer_config.h>
-
-
-#if defined TIMER4_ENABLED && defined SIG_OVERFLOW4
-DEFINE_REGISTER_OV_INTR(4)
-#endif
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer4_startstop.c,v 1.1.2.1 2009-01-30 20:18:36 zer0 Exp $
- *
- */
-
-#include <stdint.h>
-
-#include <aversive.h>
-#include <aversive/parts.h>
-#include <aversive/timers.h>
-#include <timer.h>
-#include <timer_definitions.h>
-#include <timer_prescaler.h>
-#include <timer_config.h>
-
-#if defined TIMER4_ENABLED && defined TIMER4_AVAILABLE
-DEFINE_TIMER_START_STOP(4)
-#endif
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer5_getset.c,v 1.1.2.1 2009-01-30 20:18:36 zer0 Exp $
- *
- */
-
-#include <stdint.h>
-
-#include <aversive.h>
-#include <aversive/parts.h>
-#include <aversive/timers.h>
-#include <timer.h>
-#include <timer_definitions.h>
-#include <timer_config.h>
-
-#if defined TIMER5_ENABLED && defined TIMER5_AVAILABLE
-DEFINE_TIMER_GET_SET(5)
-#endif
-
+++ /dev/null
-/*
- * Copyright DroidsDEFINE_STATIC_CONVERSIONS_FUNCSion, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer5_prescaler.c,v 1.1.2.1 2009-01-30 20:18:36 zer0 Exp $
- *
- */
-
-#include <stdint.h>
-
-#include <aversive.h>
-#include <aversive/parts.h>
-#include <aversive/timers.h>
-
-#include <timer.h>
-#include <timer_definitions.h>
-#include <timer_prescaler.h>
-
-#include <timer_config.h>
-
-
-#ifdef CONFIG_MODULE_TIMER_DYNAMIC
-
-#if defined TIMER5_ENABLED && defined TIMER5_AVAILABLE
-DEFINE_DYNAMIC_PRESCALER_FUNCS(5)
-#endif
-
-#else
-
-#if defined TIMER5_ENABLED && defined TIMER5_AVAILABLE
-DEFINE_STATIC_PRESCALER_FUNCS(5)
-#endif
-
-#endif
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer5_register_OC_at_tics.c,v 1.1.2.1 2009-01-30 20:18:36 zer0 Exp $
- *
- */
-
-#include <stdint.h>
-#include <string.h>
-
-#include <aversive.h>
-#include <aversive/parts.h>
-#include <aversive/timers.h>
-
-#include <timer.h>
-#include <timer_definitions.h>
-#include <timer_intr.h>
-#include <timer_config.h>
-
-
-#if defined TIMER5A_ENABLED && defined SIG_OUTPUT_COMPARE5A
-DEFINE_REGISTER_OC_INTR_AT_TICS(5A)
-#endif
-
-#if defined TIMER5B_ENABLED && defined SIG_OUTPUT_COMPARE5B
-DEFINE_REGISTER_OC_INTR_AT_TICS(5B)
-#endif
-
-#if defined TIMER5C_ENABLED && defined SIG_OUTPUT_COMPARE5C
-DEFINE_REGISTER_OC_INTR_AT_TICS(5C)
-#endif
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer5_register_OC_in_us.c,v 1.1.2.1 2009-01-30 20:18:36 zer0 Exp $
- *
- */
-
-#include <stdint.h>
-#include <string.h>
-
-#include <aversive.h>
-#include <aversive/parts.h>
-#include <aversive/timers.h>
-
-#include <timer.h>
-#include <timer_definitions.h>
-#include <timer_intr.h>
-#include <timer_config.h>
-
-
-#if defined TIMER5A_ENABLED && defined SIG_OUTPUT_COMPARE5A
-DEFINE_REGISTER_OC_INTR_IN_US(5,5A)
-#endif
-
-#if defined TIMER5B_ENABLED && defined SIG_OUTPUT_COMPARE5B
-DEFINE_REGISTER_OC_INTR_IN_US(5,5B)
-#endif
-
-#if defined TIMER5C_ENABLED && defined SIG_OUTPUT_COMPARE5C
-DEFINE_REGISTER_OC_INTR_IN_US(5,5C)
-#endif
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer5_register_OV.c,v 1.1.2.1 2009-01-30 20:18:36 zer0 Exp $
- *
- */
-
-#include <stdint.h>
-#include <string.h>
-
-#include <aversive.h>
-#include <aversive/parts.h>
-#include <aversive/timers.h>
-
-#include <timer.h>
-#include <timer_definitions.h>
-#include <timer_intr.h>
-#include <timer_config.h>
-
-
-#if defined TIMER5_ENABLED && defined SIG_OVERFLOW5
-DEFINE_REGISTER_OV_INTR(5)
-#endif
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer5_startstop.c,v 1.1.2.1 2009-01-30 20:18:36 zer0 Exp $
- *
- */
-
-#include <stdint.h>
-
-#include <aversive.h>
-#include <aversive/parts.h>
-#include <aversive/timers.h>
-#include <timer.h>
-#include <timer_definitions.h>
-#include <timer_prescaler.h>
-#include <timer_config.h>
-
-#if defined TIMER5_ENABLED && defined TIMER5_AVAILABLE
-DEFINE_TIMER_START_STOP(5)
-#endif
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer_conf_check.c,v 1.1.2.4 2009-01-30 20:18:36 zer0 Exp $
- *
- */
-
-#include <aversive.h>
-#include <aversive/parts.h>
-#include <aversive/timers.h>
-
-#include <timer.h>
-#include <timer_definitions.h>
-#include <timer_prescaler.h>
-
-#include <timer_config.h>
-
-
-#if defined TIMER0_ENABLED && ! defined TIMER0_AVAILABLE
-#error This arch has no TIMER0
-#endif
-
-#if defined TIMER1_ENABLED && ! defined TIMER1_AVAILABLE
-#error This arch has no TIMER1
-#endif
-
-#if defined TIMER2_ENABLED && ! defined TIMER2_AVAILABLE
-#error This arch has no TIMER2
-#endif
-
-#if defined TIMER3_ENABLED && ! defined TIMER3_AVAILABLE
-#error This arch has no TIMER3
-#endif
-
-#if defined TIMER4_ENABLED && ! defined TIMER4_AVAILABLE
-#error This arch has no TIMER4
-#endif
-
-#if defined TIMER5_ENABLED && ! defined TIMER5_AVAILABLE
-#error This arch has no TIMER5
-#endif
-
-
-#if defined TIMER0_ENABLED
-
-#if defined TIMER0_PRESCALER_REG_0 && TIMER0_PRESCALER_REG_0 == TIMER0_PRESCALER_DIV
-#define TIMER0_CONF_OK
-#endif
-
-#if defined TIMER0_PRESCALER_REG_1 && TIMER0_PRESCALER_REG_1 == TIMER0_PRESCALER_DIV
-#define TIMER0_CONF_OK
-#endif
-
-#if defined TIMER0_PRESCALER_REG_2 && TIMER0_PRESCALER_REG_2 == TIMER0_PRESCALER_DIV
-#define TIMER0_CONF_OK
-#endif
-
-#if defined TIMER0_PRESCALER_REG_3 && TIMER0_PRESCALER_REG_3 == TIMER0_PRESCALER_DIV
-#define TIMER0_CONF_OK
-#endif
-
-#if defined TIMER0_PRESCALER_REG_4 && TIMER0_PRESCALER_REG_4 == TIMER0_PRESCALER_DIV
-#define TIMER0_CONF_OK
-#endif
-
-#if defined TIMER0_PRESCALER_REG_5 && TIMER0_PRESCALER_REG_5 == TIMER0_PRESCALER_DIV
-#define TIMER0_CONF_OK
-#endif
-
-#if defined TIMER0_PRESCALER_REG_6 && TIMER0_PRESCALER_REG_6 == TIMER0_PRESCALER_DIV
-#define TIMER0_CONF_OK
-#endif
-
-#if defined TIMER0_PRESCALER_REG_7 && TIMER0_PRESCALER_REG_7 == TIMER0_PRESCALER_DIV
-#define TIMER0_CONF_OK
-#endif
-
-#if defined TIMER0_PRESCALER_REG_8 && TIMER0_PRESCALER_REG_8 == TIMER0_PRESCALER_DIV
-#define TIMER0_CONF_OK
-#endif
-
-#if defined TIMER0_PRESCALER_REG_9 && TIMER0_PRESCALER_REG_9 == TIMER0_PRESCALER_DIV
-#define TIMER0_CONF_OK
-#endif
-
-#if defined TIMER0_PRESCALER_REG_10 && TIMER0_PRESCALER_REG_10 == TIMER0_PRESCALER_DIV
-#define TIMER0_CONF_OK
-#endif
-
-#if defined TIMER0_PRESCALER_REG_11 && TIMER0_PRESCALER_REG_11 == TIMER0_PRESCALER_DIV
-#define TIMER0_CONF_OK
-#endif
-
-#if defined TIMER0_PRESCALER_REG_12 && TIMER0_PRESCALER_REG_12 == TIMER0_PRESCALER_DIV
-#define TIMER0_CONF_OK
-#endif
-
-#if defined TIMER0_PRESCALER_REG_13 && TIMER0_PRESCALER_REG_13 == TIMER0_PRESCALER_DIV
-#define TIMER0_CONF_OK
-#endif
-
-#if defined TIMER0_PRESCALER_REG_14 && TIMER0_PRESCALER_REG_14 == TIMER0_PRESCALER_DIV
-#define TIMER0_CONF_OK
-#endif
-
-#if defined TIMER0_PRESCALER_REG_15 && TIMER0_PRESCALER_REG_15 == TIMER0_PRESCALER_DIV
-#define TIMER0_CONF_OK
-#endif
-
-#ifndef TIMER0_CONF_OK
-#error TIMER0 has a bad prescaler value
-#endif
-
-#endif
-
-
-
-#if defined TIMER1_ENABLED
-
-#if defined TIMER1_PRESCALER_REG_0 && TIMER1_PRESCALER_REG_0 == TIMER1_PRESCALER_DIV
-#define TIMER1_CONF_OK
-#endif
-
-#if defined TIMER1_PRESCALER_REG_1 && TIMER1_PRESCALER_REG_1 == TIMER1_PRESCALER_DIV
-#define TIMER1_CONF_OK
-#endif
-
-#if defined TIMER1_PRESCALER_REG_2 && TIMER1_PRESCALER_REG_2 == TIMER1_PRESCALER_DIV
-#define TIMER1_CONF_OK
-#endif
-
-#if defined TIMER1_PRESCALER_REG_3 && TIMER1_PRESCALER_REG_3 == TIMER1_PRESCALER_DIV
-#define TIMER1_CONF_OK
-#endif
-
-#if defined TIMER1_PRESCALER_REG_4 && TIMER1_PRESCALER_REG_4 == TIMER1_PRESCALER_DIV
-#define TIMER1_CONF_OK
-#endif
-
-#if defined TIMER1_PRESCALER_REG_5 && TIMER1_PRESCALER_REG_5 == TIMER1_PRESCALER_DIV
-#define TIMER1_CONF_OK
-#endif
-
-#if defined TIMER1_PRESCALER_REG_6 && TIMER1_PRESCALER_REG_6 == TIMER1_PRESCALER_DIV
-#define TIMER1_CONF_OK
-#endif
-
-#if defined TIMER1_PRESCALER_REG_7 && TIMER1_PRESCALER_REG_7 == TIMER1_PRESCALER_DIV
-#define TIMER1_CONF_OK
-#endif
-
-#if defined TIMER1_PRESCALER_REG_8 && TIMER1_PRESCALER_REG_8 == TIMER1_PRESCALER_DIV
-#define TIMER1_CONF_OK
-#endif
-
-#if defined TIMER1_PRESCALER_REG_9 && TIMER1_PRESCALER_REG_9 == TIMER1_PRESCALER_DIV
-#define TIMER1_CONF_OK
-#endif
-
-#if defined TIMER1_PRESCALER_REG_10 && TIMER1_PRESCALER_REG_10 == TIMER1_PRESCALER_DIV
-#define TIMER1_CONF_OK
-#endif
-
-#if defined TIMER1_PRESCALER_REG_11 && TIMER1_PRESCALER_REG_11 == TIMER1_PRESCALER_DIV
-#define TIMER1_CONF_OK
-#endif
-
-#if defined TIMER1_PRESCALER_REG_12 && TIMER1_PRESCALER_REG_12 == TIMER1_PRESCALER_DIV
-#define TIMER1_CONF_OK
-#endif
-
-#if defined TIMER1_PRESCALER_REG_13 && TIMER1_PRESCALER_REG_13 == TIMER1_PRESCALER_DIV
-#define TIMER1_CONF_OK
-#endif
-
-#if defined TIMER1_PRESCALER_REG_14 && TIMER1_PRESCALER_REG_14 == TIMER1_PRESCALER_DIV
-#define TIMER1_CONF_OK
-#endif
-
-#if defined TIMER1_PRESCALER_REG_15 && TIMER1_PRESCALER_REG_15 == TIMER1_PRESCALER_DIV
-#define TIMER1_CONF_OK
-#endif
-
-#ifndef TIMER1_CONF_OK
-#error TIMER1 has a bad prescaler value
-#endif
-
-#endif
-
-
-#if defined TIMER2_ENABLED
-
-#if defined TIMER2_PRESCALER_REG_0 && TIMER2_PRESCALER_REG_0 == TIMER2_PRESCALER_DIV
-#define TIMER2_CONF_OK
-#endif
-
-#if defined TIMER2_PRESCALER_REG_1 && TIMER2_PRESCALER_REG_1 == TIMER2_PRESCALER_DIV
-#define TIMER2_CONF_OK
-#endif
-
-#if defined TIMER2_PRESCALER_REG_2 && TIMER2_PRESCALER_REG_2 == TIMER2_PRESCALER_DIV
-#define TIMER2_CONF_OK
-#endif
-
-#if defined TIMER2_PRESCALER_REG_3 && TIMER2_PRESCALER_REG_3 == TIMER2_PRESCALER_DIV
-#define TIMER2_CONF_OK
-#endif
-
-#if defined TIMER2_PRESCALER_REG_4 && TIMER2_PRESCALER_REG_4 == TIMER2_PRESCALER_DIV
-#define TIMER2_CONF_OK
-#endif
-
-#if defined TIMER2_PRESCALER_REG_5 && TIMER2_PRESCALER_REG_5 == TIMER2_PRESCALER_DIV
-#define TIMER2_CONF_OK
-#endif
-
-#if defined TIMER2_PRESCALER_REG_6 && TIMER2_PRESCALER_REG_6 == TIMER2_PRESCALER_DIV
-#define TIMER2_CONF_OK
-#endif
-
-#if defined TIMER2_PRESCALER_REG_7 && TIMER2_PRESCALER_REG_7 == TIMER2_PRESCALER_DIV
-#define TIMER2_CONF_OK
-#endif
-
-#if defined TIMER2_PRESCALER_REG_8 && TIMER2_PRESCALER_REG_8 == TIMER2_PRESCALER_DIV
-#define TIMER2_CONF_OK
-#endif
-
-#if defined TIMER2_PRESCALER_REG_9 && TIMER2_PRESCALER_REG_9 == TIMER2_PRESCALER_DIV
-#define TIMER2_CONF_OK
-#endif
-
-#if defined TIMER2_PRESCALER_REG_10 && TIMER2_PRESCALER_REG_10 == TIMER2_PRESCALER_DIV
-#define TIMER2_CONF_OK
-#endif
-
-#if defined TIMER2_PRESCALER_REG_11 && TIMER2_PRESCALER_REG_11 == TIMER2_PRESCALER_DIV
-#define TIMER2_CONF_OK
-#endif
-
-#if defined TIMER2_PRESCALER_REG_12 && TIMER2_PRESCALER_REG_12 == TIMER2_PRESCALER_DIV
-#define TIMER2_CONF_OK
-#endif
-
-#if defined TIMER2_PRESCALER_REG_13 && TIMER2_PRESCALER_REG_13 == TIMER2_PRESCALER_DIV
-#define TIMER2_CONF_OK
-#endif
-
-#if defined TIMER2_PRESCALER_REG_14 && TIMER2_PRESCALER_REG_14 == TIMER2_PRESCALER_DIV
-#define TIMER2_CONF_OK
-#endif
-
-#if defined TIMER2_PRESCALER_REG_15 && TIMER2_PRESCALER_REG_15 == TIMER2_PRESCALER_DIV
-#define TIMER2_CONF_OK
-#endif
-
-#ifndef TIMER2_CONF_OK
-#error TIMER2 has a bad prescaler value
-#endif
-
-#endif
-
-
-#if defined TIMER3_ENABLED
-
-#if defined TIMER3_PRESCALER_REG_0 && TIMER3_PRESCALER_REG_0 == TIMER3_PRESCALER_DIV
-#define TIMER3_CONF_OK
-#endif
-
-#if defined TIMER3_PRESCALER_REG_1 && TIMER3_PRESCALER_REG_1 == TIMER3_PRESCALER_DIV
-#define TIMER3_CONF_OK
-#endif
-
-#if defined TIMER3_PRESCALER_REG_2 && TIMER3_PRESCALER_REG_2 == TIMER3_PRESCALER_DIV
-#define TIMER3_CONF_OK
-#endif
-
-#if defined TIMER3_PRESCALER_REG_3 && TIMER3_PRESCALER_REG_3 == TIMER3_PRESCALER_DIV
-#define TIMER3_CONF_OK
-#endif
-
-#if defined TIMER3_PRESCALER_REG_4 && TIMER3_PRESCALER_REG_4 == TIMER3_PRESCALER_DIV
-#define TIMER3_CONF_OK
-#endif
-
-#if defined TIMER3_PRESCALER_REG_5 && TIMER3_PRESCALER_REG_5 == TIMER3_PRESCALER_DIV
-#define TIMER3_CONF_OK
-#endif
-
-#if defined TIMER3_PRESCALER_REG_6 && TIMER3_PRESCALER_REG_6 == TIMER3_PRESCALER_DIV
-#define TIMER3_CONF_OK
-#endif
-
-#if defined TIMER3_PRESCALER_REG_7 && TIMER3_PRESCALER_REG_7 == TIMER3_PRESCALER_DIV
-#define TIMER3_CONF_OK
-#endif
-
-#if defined TIMER3_PRESCALER_REG_8 && TIMER3_PRESCALER_REG_8 == TIMER3_PRESCALER_DIV
-#define TIMER3_CONF_OK
-#endif
-
-#if defined TIMER3_PRESCALER_REG_9 && TIMER3_PRESCALER_REG_9 == TIMER3_PRESCALER_DIV
-#define TIMER3_CONF_OK
-#endif
-
-#if defined TIMER3_PRESCALER_REG_10 && TIMER3_PRESCALER_REG_10 == TIMER3_PRESCALER_DIV
-#define TIMER3_CONF_OK
-#endif
-
-#if defined TIMER3_PRESCALER_REG_11 && TIMER3_PRESCALER_REG_11 == TIMER3_PRESCALER_DIV
-#define TIMER3_CONF_OK
-#endif
-
-#if defined TIMER3_PRESCALER_REG_12 && TIMER3_PRESCALER_REG_12 == TIMER3_PRESCALER_DIV
-#define TIMER3_CONF_OK
-#endif
-
-#if defined TIMER3_PRESCALER_REG_13 && TIMER3_PRESCALER_REG_13 == TIMER3_PRESCALER_DIV
-#define TIMER3_CONF_OK
-#endif
-
-#if defined TIMER3_PRESCALER_REG_14 && TIMER3_PRESCALER_REG_14 == TIMER3_PRESCALER_DIV
-#define TIMER3_CONF_OK
-#endif
-
-#if defined TIMER3_PRESCALER_REG_15 && TIMER3_PRESCALER_REG_15 == TIMER3_PRESCALER_DIV
-#define TIMER3_CONF_OK
-#endif
-
-#ifndef TIMER3_CONF_OK
-#error TIMER3 has a bad prescaler value
-#endif
-
-#endif
-
-#if defined TIMER4_ENABLED
-
-#if defined TIMER4_PRESCALER_REG_0 && TIMER4_PRESCALER_REG_0 == TIMER4_PRESCALER_DIV
-#define TIMER4_CONF_OK
-#endif
-
-#if defined TIMER4_PRESCALER_REG_1 && TIMER4_PRESCALER_REG_1 == TIMER4_PRESCALER_DIV
-#define TIMER4_CONF_OK
-#endif
-
-#if defined TIMER4_PRESCALER_REG_2 && TIMER4_PRESCALER_REG_2 == TIMER4_PRESCALER_DIV
-#define TIMER4_CONF_OK
-#endif
-
-#if defined TIMER4_PRESCALER_REG_3 && TIMER4_PRESCALER_REG_3 == TIMER4_PRESCALER_DIV
-#define TIMER4_CONF_OK
-#endif
-
-#if defined TIMER4_PRESCALER_REG_4 && TIMER4_PRESCALER_REG_4 == TIMER4_PRESCALER_DIV
-#define TIMER4_CONF_OK
-#endif
-
-#if defined TIMER4_PRESCALER_REG_5 && TIMER4_PRESCALER_REG_5 == TIMER4_PRESCALER_DIV
-#define TIMER4_CONF_OK
-#endif
-
-#if defined TIMER4_PRESCALER_REG_6 && TIMER4_PRESCALER_REG_6 == TIMER4_PRESCALER_DIV
-#define TIMER4_CONF_OK
-#endif
-
-#if defined TIMER4_PRESCALER_REG_7 && TIMER4_PRESCALER_REG_7 == TIMER4_PRESCALER_DIV
-#define TIMER4_CONF_OK
-#endif
-
-#if defined TIMER4_PRESCALER_REG_8 && TIMER4_PRESCALER_REG_8 == TIMER4_PRESCALER_DIV
-#define TIMER4_CONF_OK
-#endif
-
-#if defined TIMER4_PRESCALER_REG_9 && TIMER4_PRESCALER_REG_9 == TIMER4_PRESCALER_DIV
-#define TIMER4_CONF_OK
-#endif
-
-#if defined TIMER4_PRESCALER_REG_10 && TIMER4_PRESCALER_REG_10 == TIMER4_PRESCALER_DIV
-#define TIMER4_CONF_OK
-#endif
-
-#if defined TIMER4_PRESCALER_REG_11 && TIMER4_PRESCALER_REG_11 == TIMER4_PRESCALER_DIV
-#define TIMER4_CONF_OK
-#endif
-
-#if defined TIMER4_PRESCALER_REG_12 && TIMER4_PRESCALER_REG_12 == TIMER4_PRESCALER_DIV
-#define TIMER4_CONF_OK
-#endif
-
-#if defined TIMER4_PRESCALER_REG_13 && TIMER4_PRESCALER_REG_13 == TIMER4_PRESCALER_DIV
-#define TIMER4_CONF_OK
-#endif
-
-#if defined TIMER4_PRESCALER_REG_14 && TIMER4_PRESCALER_REG_14 == TIMER4_PRESCALER_DIV
-#define TIMER4_CONF_OK
-#endif
-
-#if defined TIMER4_PRESCALER_REG_15 && TIMER4_PRESCALER_REG_15 == TIMER4_PRESCALER_DIV
-#define TIMER4_CONF_OK
-#endif
-
-#ifndef TIMER4_CONF_OK
-#error TIMER4 has a bad prescaler value
-#endif
-
-#endif
-
-#if defined TIMER5_ENABLED
-
-#if defined TIMER5_PRESCALER_REG_0 && TIMER5_PRESCALER_REG_0 == TIMER5_PRESCALER_DIV
-#define TIMER5_CONF_OK
-#endif
-
-#if defined TIMER5_PRESCALER_REG_1 && TIMER5_PRESCALER_REG_1 == TIMER5_PRESCALER_DIV
-#define TIMER5_CONF_OK
-#endif
-
-#if defined TIMER5_PRESCALER_REG_2 && TIMER5_PRESCALER_REG_2 == TIMER5_PRESCALER_DIV
-#define TIMER5_CONF_OK
-#endif
-
-#if defined TIMER5_PRESCALER_REG_3 && TIMER5_PRESCALER_REG_3 == TIMER5_PRESCALER_DIV
-#define TIMER5_CONF_OK
-#endif
-
-#if defined TIMER5_PRESCALER_REG_4 && TIMER5_PRESCALER_REG_4 == TIMER5_PRESCALER_DIV
-#define TIMER5_CONF_OK
-#endif
-
-#if defined TIMER5_PRESCALER_REG_5 && TIMER5_PRESCALER_REG_5 == TIMER5_PRESCALER_DIV
-#define TIMER5_CONF_OK
-#endif
-
-#if defined TIMER5_PRESCALER_REG_6 && TIMER5_PRESCALER_REG_6 == TIMER5_PRESCALER_DIV
-#define TIMER5_CONF_OK
-#endif
-
-#if defined TIMER5_PRESCALER_REG_7 && TIMER5_PRESCALER_REG_7 == TIMER5_PRESCALER_DIV
-#define TIMER5_CONF_OK
-#endif
-
-#if defined TIMER5_PRESCALER_REG_8 && TIMER5_PRESCALER_REG_8 == TIMER5_PRESCALER_DIV
-#define TIMER5_CONF_OK
-#endif
-
-#if defined TIMER5_PRESCALER_REG_9 && TIMER5_PRESCALER_REG_9 == TIMER5_PRESCALER_DIV
-#define TIMER5_CONF_OK
-#endif
-
-#if defined TIMER5_PRESCALER_REG_10 && TIMER5_PRESCALER_REG_10 == TIMER5_PRESCALER_DIV
-#define TIMER5_CONF_OK
-#endif
-
-#if defined TIMER5_PRESCALER_REG_11 && TIMER5_PRESCALER_REG_11 == TIMER5_PRESCALER_DIV
-#define TIMER5_CONF_OK
-#endif
-
-#if defined TIMER5_PRESCALER_REG_12 && TIMER5_PRESCALER_REG_12 == TIMER5_PRESCALER_DIV
-#define TIMER5_CONF_OK
-#endif
-
-#if defined TIMER5_PRESCALER_REG_13 && TIMER5_PRESCALER_REG_13 == TIMER5_PRESCALER_DIV
-#define TIMER5_CONF_OK
-#endif
-
-#if defined TIMER5_PRESCALER_REG_14 && TIMER5_PRESCALER_REG_14 == TIMER5_PRESCALER_DIV
-#define TIMER5_CONF_OK
-#endif
-
-#if defined TIMER5_PRESCALER_REG_15 && TIMER5_PRESCALER_REG_15 == TIMER5_PRESCALER_DIV
-#define TIMER5_CONF_OK
-#endif
-
-#ifndef TIMER5_CONF_OK
-#error TIMER5 has a bad prescaler value
-#endif
-
-#endif
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer_declarations.h,v 1.1.2.2 2006-12-04 23:48:22 zer0 Exp $
- *
- */
-
-#ifndef _TIMER_DECLARATIONS_H
-#define _TIMER_DECLARATIONS_H_
-
-#define DECLARE_TIMER_FUNCS(x) \
- \
-/** start the timer at initial prescaler */ \
-void timer##x##_start(void); \
- \
-/** stop the timer */ \
-void timer##x##_stop(void); \
- \
-/** Set the timer value */ \
-void timer##x##_set(uint16_t t); \
- \
-/** return the value of the timer */ \
-uint16_t timer##x##_get(void); \
- \
- \
-/** Enable overflow interruption, and register a function to be called */ \
-/* every interrupt. If func is NULL, unregisters interrupt. */ \
-void timer##x##_register_OV_intr(void (*func)(void)); \
- \
-/** Enable output compare interruption, and register a function to be */ \
-/* called every output compare interrupt. Note that interruption */ \
-/* will occur when the timer will reach the same value than t. If */ \
-/* func is NULL, unregisters interrupt (other arg is useless). */ \
-void timer##x##A_register_OC_intr_at_tics(void (*func)(void), uint16_t t); \
-void timer##x##B_register_OC_intr_at_tics(void (*func)(void), uint16_t t); \
-void timer##x##C_register_OC_intr_at_tics(void (*func)(void), uint16_t t); \
- \
-/** Enable output compare interruption, and register a function to be */ \
-/* called every output compare interrupt. Note that interruption */ \
-/* will occur when the timer will reach CURRENT_TIMER + t_us */ \
-/* (parameter is in microseconds). If func is NULL, unregisters */ \
-/* interrupt (other arg is useless). return 0 on success */ \
-/* WARNING : this function can be slower due to float conversion */ \
-/* If you are in static timer mode (no dynamic modifications of */ \
-/* the prescaler), and if your value is a constant, you should use */ \
-/* a code like this to allow beeing optmized by the preprocessor: */ \
-/* timerxy_register_OC_intr_in_tics(timerx_us_to_tics(1000)); */ \
-/* Indeed this code is optimized. In any case, it is better to */ \
-/* them in 2 separated funcs, because you can save the result of */ \
-/* timerx_us_to_tics() in a variable. */ \
-int8_t timer##x##A_register_OC_intr_in_us(void (*func)(void), uint16_t t); \
-int8_t timer##x##B_register_OC_intr_in_us(void (*func)(void), uint16_t t); \
-int8_t timer##x##C_register_OC_intr_in_us(void (*func)(void), uint16_t t); \
- \
-/** Return current prescaler divisor. If CONFIG_MODULE_TIMER_DYNAMIC */ \
-/* is not defined, it only returns TIMERX_PRESCALER specified in */ \
-/* configuration. If you use a dynamic configuration, it reads the */ \
-/* current prescaler register value and converts it to divisor */ \
-/* value. */ \
-uint16_t timer##x##_get_prescaler_div(void); \
- \
-/** Configure the prescaler register depending on divisor param. */ \
-/* only defined if CONFIG_MODULE_TIMER_DYNAMIC is 'y' */ \
-void timer##x##_set_prescaler_div(uint16_t); \
- \
-/** Use timerX_get_prescaler_div() and CONFIG_QUARTZ to do the */ \
-/* conversion from microseconds to tics (timer unit) */ \
-/* Be carreful, this function is inline static, so if you use it */ \
-/* quite often, you should include it in a standard function and call */ \
-/* this function instead */ \
-static inline float timer##x##_us_to_tics(float us); \
- \
-/** Use timerX_get_prescaler_div() and CONFIG_QUARTZ to do the */ \
-/* conversion from tics to microseconds */ \
-/* Be carreful, this function is inline static, so if you use it */ \
-/* quite often, you should include it in a standard function and call */ \
-/* this function instead */ \
-static inline float timer##x##_tics_to_us(float t);
-
-#endif
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer_definitions.h,v 1.1.2.5 2009-04-07 20:00:46 zer0 Exp $
- *
- */
-
-#ifndef _TIMER_DEFINITIONS_H_
-#define _TIMER_DEFINITIONS_H_
-
-/* needed by nearly all .c */
-#include <aversive/parts.h>
-
-#define DEFINE_TIMER_START_STOP(x) \
- \
-/** start the timer */ \
-void timer##x##_start(void) \
-{ \
- TCNT##x = 0; \
- CS##x##0_REG = __timer##x##_div_to_reg(TIMER##x##_PRESCALER_DIV) << CS##x##0 ; \
-} \
- \
-/** stop the timer */ \
-void timer##x##_stop(void) \
-{ \
- CS##x##0_REG = 0; \
- TCNT##x = 0; \
-}
-
-
-
-#define DEFINE_TIMER_GET_SET(x) \
- \
-uint16_t timer##x##_get(void) \
-{ \
- return TCNT##x ; \
-} \
- \
-void timer##x##_set(uint16_t t) \
-{ \
- TCNT##x = t; \
-}
-
-
-#define DEFINE_OV_INTR(x) \
-SIGNAL(x) \
-{ \
- if(timer_OV_callback_table[x##_NUM]) \
- timer_OV_callback_table[x##_NUM](); \
-}
-
-
-#define DEFINE_OC_INTR(x) \
-SIGNAL(x) \
-{ \
- if(timer_OC_callback_table[x##_NUM]) \
- timer_OC_callback_table[x##_NUM](); \
-}
-
-
-#define DEFINE_REGISTER_OV_INTR(x) \
- \
-void timer##x##_register_OV_intr(void (*func)(void)) \
-{ \
- uint8_t flags; \
- \
- IRQ_LOCK(flags); \
- timer_OV_callback_table[SIG_OVERFLOW##x##_NUM] = func; \
- if (func) { \
- TOIE##x##_REG |= (1<<TOIE##x); \
- } \
- else { \
- TOIE##x##_REG &= (uint8_t)(~(1<<TOIE##x)); \
- } \
- IRQ_UNLOCK(flags); \
-}
-
-
-#define DEFINE_REGISTER_OC_INTR_AT_TICS(x) \
- \
-void timer##x##_register_OC_intr_at_tics(void (*func)(void), uint16_t t) \
-{ \
- uint8_t flags; \
- \
- IRQ_LOCK(flags); \
- timer_OC_callback_table[SIG_OUTPUT_COMPARE##x##_NUM] = func; \
- if (func) { \
- OCIE##x##_REG |= (1<<OCIE##x); \
- OCR##x = t; \
- } \
- else { \
- OCIE##x##_REG &= (uint8_t)(~(1<<OCIE##x)); \
- } \
- IRQ_UNLOCK(flags); \
-}
-
-
-#define DEFINE_REGISTER_OC_INTR_IN_US(x,y) \
- \
-int8_t timer##y##_register_OC_intr_in_us(void (*func)(void), uint16_t t) \
-{ \
- uint8_t flags; \
- float tics; \
- \
- IRQ_LOCK(flags); \
- if (! func) { \
- timer_OC_callback_table[SIG_OUTPUT_COMPARE##y##_NUM] = func; \
- OCIE##y##_REG &= (uint8_t)(~(1<<OCIE##y)); \
- IRQ_UNLOCK(flags); \
- return 0; \
- } \
- \
- tics = timer##x##_us_to_tics(t); \
- if ( tics > 0xFFFF ) { /* XXX use MAX_TIMER */ \
- IRQ_UNLOCK(flags); \
- return -1; \
- } \
- \
- OCR##y = TCNT##x + tics; \
- timer_OC_callback_table[SIG_OUTPUT_COMPARE##y##_NUM] = func; \
- OCIE##y##_REG |= (1<<OCIE##y); \
- IRQ_UNLOCK(flags); \
- return 0; \
-}
-
-
-#define DEFINE_DYNAMIC_PRESCALER_FUNCS(x) \
- \
-int16_t timer##x##_div_to_reg(uint16_t div) \
-{ \
- return __timer##x##_div_to_reg(div); \
-} \
- \
-int16_t timer##x##_reg_to_div(uint8_t reg) \
-{ \
- return __timer##x##_reg_to_div(reg); \
-} \
- \
-uint16_t timer##x##_get_prescaler_div(void) \
-{ \
- return __timer##x##_reg_to_div(CS##x##0_REG >> CS##x##0); \
-} \
- \
-void timer##x##_set_prescaler_div(uint16_t div) \
-{ \
- CS##x##0_REG = __timer##x##_div_to_reg(div) << CS##x##0 ; \
-}
-
-
-#define DEFINE_STATIC_PRESCALER_FUNCS(x) \
- \
-int16_t timer##x##_div_to_reg(__attribute__((unused)) uint16_t div) \
-{ \
- return __timer##x##_div_to_reg(TIMER##x##_PRESCALER_DIV); \
-} \
- \
-uint16_t timer##x##_get_prescaler_div(void) \
-{ \
- return TIMER##x##_PRESCALER_DIV; \
-}
-
-#define DEFINE_TIMER_US_CONVERSIONS(x) \
- \
-static inline float timer##x##_us_to_tics(float us) \
-{ \
- return ((float)CONFIG_QUARTZ / \
- ((float)MHz * timer##x##_get_prescaler_div()) ) * us; \
-} \
- \
-static inline float timer##x##_tics_to_us(float t) \
-{ \
- return t / ((float)CONFIG_QUARTZ / \
- ((float)MHz * timer##x##_get_prescaler_div()) ); \
-}
-
-#endif
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, (2010)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer_init.c,v 1.1.2.4 2009-01-30 20:18:36 zer0 Exp $
- *
- */
-
-void timer_init(void)
-{
-}
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer_init.c,v 1.1.2.4 2009-01-30 20:18:36 zer0 Exp $
- *
- */
-
-#include <aversive.h>
-#include <aversive/parts.h>
-#include <aversive/timers.h>
-#include <timer.h>
-#include <timer_intr.h>
-#include <timer_prescaler.h>
-
-#include <timer_config.h>
-
-/** Init of all timers with static configutaion (see timer_config.h) */
-void timer_init(void)
-{
- uint8_t flags;
-
- IRQ_LOCK(flags);
- timer_intr_init();
-
-#if defined TIMER0_ENABLED && defined TIMER0_AVAILABLE
- CS00_REG = __timer0_div_to_reg(TIMER0_PRESCALER_DIV) << CS00 ;
- TCNT0 = 0;
-#endif
-#if defined TIMER1_ENABLED && defined TIMER1_AVAILABLE
- CS10_REG = __timer1_div_to_reg(TIMER1_PRESCALER_DIV) << CS10 ;
- TCNT1 = 0;
-#endif
-#if defined TIMER2_ENABLED && defined TIMER2_AVAILABLE
- CS20_REG = __timer2_div_to_reg(TIMER2_PRESCALER_DIV) << CS20 ;
- TCNT2 = 0;
-#endif
-#if defined TIMER3_ENABLED && defined TIMER3_AVAILABLE
- CS30_REG = __timer3_div_to_reg(TIMER3_PRESCALER_DIV) << CS30 ;
- TCNT3 = 0;
-#endif
-#if defined TIMER4_ENABLED && defined TIMER4_AVAILABLE
- CS40_REG = __timer4_div_to_reg(TIMER4_PRESCALER_DIV) << CS40 ;
- TCNT4 = 0;
-#endif
-#if defined TIMER5_ENABLED && defined TIMER5_AVAILABLE
- CS50_REG = __timer5_div_to_reg(TIMER5_PRESCALER_DIV) << CS50 ;
- TCNT5 = 0;
-#endif
- IRQ_UNLOCK(flags);
-}
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer_intr.c,v 1.1.2.4 2009-01-30 20:18:36 zer0 Exp $
- *
- */
-
-#include <stdint.h>
-#include <string.h>
-
-#include <aversive.h>
-#include <aversive/parts.h>
-#include <aversive/timers.h>
-
-#include <timer.h>
-#include <timer_definitions.h>
-#include <timer_intr.h>
-
-#include <timer_config.h>
-
-volatile timer_callback_t timer_OV_callback_table[SIG_OVERFLOW_TOTAL_NUM];
-volatile timer_callback_t timer_OC_callback_table[SIG_OUTPUT_COMPARE_TOTAL_NUM];
-
-/*************************/
-
-#if defined TIMER0_ENABLED && defined SIG_OVERFLOW0
-DEFINE_OV_INTR(SIG_OVERFLOW0)
-#endif
-
-#if defined TIMER0_ENABLED && defined SIG_OUTPUT_COMPARE0
-DEFINE_OC_INTR(SIG_OUTPUT_COMPARE0)
-#endif
-
-#if defined TIMER0_ENABLED && defined SIG_OUTPUT_COMPARE0A
-DEFINE_OC_INTR(SIG_OUTPUT_COMPARE0A)
-#endif
-
-#if defined TIMER0_ENABLED && defined SIG_OUTPUT_COMPARE0B
-DEFINE_OC_INTR(SIG_OUTPUT_COMPARE0B)
-#endif
-
-/*************************/
-
-#if defined TIMER1_ENABLED && defined SIG_OVERFLOW1
-DEFINE_OV_INTR(SIG_OVERFLOW1)
-#endif
-
-#if defined TIMER1A_ENABLED && defined SIG_OUTPUT_COMPARE1A
-DEFINE_OC_INTR(SIG_OUTPUT_COMPARE1A)
-#endif
-
-#if defined TIMER1B_ENABLED && defined SIG_OUTPUT_COMPARE1B
-DEFINE_OC_INTR(SIG_OUTPUT_COMPARE1B)
-#endif
-
-#if defined TIMER1C_ENABLED && defined SIG_OUTPUT_COMPARE1C
-DEFINE_OC_INTR(SIG_OUTPUT_COMPARE1C)
-#endif
-
-/*************************/
-
-#if defined TIMER2_ENABLED && defined SIG_OVERFLOW2
-DEFINE_OV_INTR(SIG_OVERFLOW2)
-#endif
-
-#if defined TIMER2_ENABLED && defined SIG_OUTPUT_COMPARE2
-DEFINE_OC_INTR(SIG_OUTPUT_COMPARE2)
-#endif
-
-#if defined TIMER2_ENABLED && defined SIG_OUTPUT_COMPARE2A
-DEFINE_OC_INTR(SIG_OUTPUT_COMPARE2A)
-#endif
-
-#if defined TIMER2_ENABLED && defined SIG_OUTPUT_COMPARE2B
-DEFINE_OC_INTR(SIG_OUTPUT_COMPARE2B)
-#endif
-
-/*************************/
-
-#if defined TIMER3_ENABLED && defined SIG_OVERFLOW3
-DEFINE_OV_INTR(SIG_OVERFLOW3)
-#endif
-
-#if defined TIMER3A_ENABLED && defined SIG_OUTPUT_COMPARE3A
-DEFINE_OC_INTR(SIG_OUTPUT_COMPARE3A)
-#endif
-
-#if defined TIMER3B_ENABLED && defined SIG_OUTPUT_COMPARE3B
-DEFINE_OC_INTR(SIG_OUTPUT_COMPARE3B)
-#endif
-
-#if defined TIMER3C_ENABLED && defined SIG_OUTPUT_COMPARE3C
-DEFINE_OC_INTR(SIG_OUTPUT_COMPARE3C)
-#endif
-
-/*************************/
-
-#if defined TIMER4_ENABLED && defined SIG_OVERFLOW4
-DEFINE_OV_INTR(SIG_OVERFLOW4)
-#endif
-
-#if defined TIMER4A_ENABLED && defined SIG_OUTPUT_COMPARE4A
-DEFINE_OC_INTR(SIG_OUTPUT_COMPARE4A)
-#endif
-
-#if defined TIMER4B_ENABLED && defined SIG_OUTPUT_COMPARE4B
-DEFINE_OC_INTR(SIG_OUTPUT_COMPARE4B)
-#endif
-
-#if defined TIMER4C_ENABLED && defined SIG_OUTPUT_COMPARE4C
-DEFINE_OC_INTR(SIG_OUTPUT_COMPARE4C)
-#endif
-
-/*************************/
-
-#if defined TIMER5_ENABLED && defined SIG_OVERFLOW5
-DEFINE_OV_INTR(SIG_OVERFLOW5)
-#endif
-
-#if defined TIMER5A_ENABLED && defined SIG_OUTPUT_COMPARE5A
-DEFINE_OC_INTR(SIG_OUTPUT_COMPARE5A)
-#endif
-
-#if defined TIMER5B_ENABLED && defined SIG_OUTPUT_COMPARE5B
-DEFINE_OC_INTR(SIG_OUTPUT_COMPARE5B)
-#endif
-
-#if defined TIMER5C_ENABLED && defined SIG_OUTPUT_COMPARE5C
-DEFINE_OC_INTR(SIG_OUTPUT_COMPARE5C)
-#endif
-
-/*************************/
-
-void timer_intr_init(void)
-{
- memset((void*)timer_OV_callback_table, 0, sizeof(timer_OV_callback_table));
- memset((void*)timer_OC_callback_table, 0, sizeof(timer_OC_callback_table));
-}
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer_intr.h,v 1.1.2.3 2007-05-23 17:18:15 zer0 Exp $
- *
- */
-
-#include <aversive/parts.h>
-
-typedef void (*timer_callback_t)(void);
-
-extern volatile timer_callback_t timer_OV_callback_table[SIG_OVERFLOW_TOTAL_NUM];
-extern volatile timer_callback_t timer_OC_callback_table[SIG_OUTPUT_COMPARE_TOTAL_NUM];
-
-/* initialisation of callback table */
-void timer_intr_init(void);
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2006)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: timer_prescaler.h,v 1.1.2.4 2009-01-30 20:18:36 zer0 Exp $
- *
- */
-
-#ifndef _TIMER_PRESCALER_H_
-#define _TIMER_PRESCALER_H_
-
-/* return <0 on error, else return reg value */
-/* This static inline function is very optimized if div is
- * a constant */
-static inline int16_t __timer0_div_to_reg(uint16_t div)
-{
- switch(div) {
-#if defined TIMER0_PRESCALER_REG_0 && TIMER0_PRESCALER_REG_0 >= 0
- case TIMER0_PRESCALER_REG_0:
- return 0;
-#endif
-
-#if defined TIMER0_PRESCALER_REG_1 && TIMER0_PRESCALER_REG_1 >= 0
- case TIMER0_PRESCALER_REG_1:
- return 1;
-#endif
-
-#if defined TIMER0_PRESCALER_REG_2 && TIMER0_PRESCALER_REG_2 >= 0
- case TIMER0_PRESCALER_REG_2:
- return 2;
-#endif
-
-#if defined TIMER0_PRESCALER_REG_3 && TIMER0_PRESCALER_REG_3 >= 0
- case TIMER0_PRESCALER_REG_3:
- return 3;
-#endif
-
-#if defined TIMER0_PRESCALER_REG_4 && TIMER0_PRESCALER_REG_4 >= 0
- case TIMER0_PRESCALER_REG_4:
- return 4;
-#endif
-
-#if defined TIMER0_PRESCALER_REG_5 && TIMER0_PRESCALER_REG_5 >= 0
- case TIMER0_PRESCALER_REG_5:
- return 5;
-#endif
-
-#if defined TIMER0_PRESCALER_REG_6 && TIMER0_PRESCALER_REG_6 >= 0
- case TIMER0_PRESCALER_REG_6:
- return 6;
-#endif
-
-#if defined TIMER0_PRESCALER_REG_7 && TIMER0_PRESCALER_REG_7 >= 0
- case TIMER0_PRESCALER_REG_7:
- return 7;
-#endif
-
-#if defined TIMER0_PRESCALER_REG_8 && TIMER0_PRESCALER_REG_8 >= 0
- case TIMER0_PRESCALER_REG_8:
- return 8;
-#endif
-
-#if defined TIMER0_PRESCALER_REG_9 && TIMER0_PRESCALER_REG_9 >= 0
- case TIMER0_PRESCALER_REG_9:
- return 9;
-#endif
-
-#if defined TIMER0_PRESCALER_REG_10 && TIMER0_PRESCALER_REG_10 >= 0
- case TIMER0_PRESCALER_REG_10:
- return 10;
-#endif
-
-#if defined TIMER0_PRESCALER_REG_11 && TIMER0_PRESCALER_REG_11 >= 0
- case TIMER0_PRESCALER_REG_11:
- return 11;
-#endif
-
-#if defined TIMER0_PRESCALER_REG_12 && TIMER0_PRESCALER_REG_12 >= 0
- case TIMER0_PRESCALER_REG_12:
- return 12;
-#endif
-
-#if defined TIMER0_PRESCALER_REG_13 && TIMER0_PRESCALER_REG_13 >= 0
- case TIMER0_PRESCALER_REG_13:
- return 13;
-#endif
-
-#if defined TIMER0_PRESCALER_REG_14 && TIMER0_PRESCALER_REG_14 >= 0
- case TIMER0_PRESCALER_REG_14:
- return 14;
-#endif
-
-#if defined TIMER0_PRESCALER_REG_15 && TIMER0_PRESCALER_REG_15 >= 0
- case TIMER0_PRESCALER_REG_15:
- return 15;
-#endif
- default:
- return -1;
- }
-}
-
-/* return <0 on error, else return div value */
-/* This static inline function is very optimized if reg is
- * a constant */
-static inline int16_t __timer0_reg_to_div(uint8_t reg)
-{
- switch(reg) {
-#if defined TIMER0_PRESCALER_DIV_0
- case TIMER0_PRESCALER_DIV_0:
- return 0;
-#endif
-
-#if defined TIMER0_PRESCALER_DIV_1
- case TIMER0_PRESCALER_DIV_1:
- return 1;
-#endif
-
-#if defined TIMER0_PRESCALER_DIV_2
- case TIMER0_PRESCALER_DIV_2:
- return 2;
-#endif
-
-#if defined TIMER0_PRESCALER_DIV_4
- case TIMER0_PRESCALER_DIV_4:
- return 4;
-#endif
-
-#if defined TIMER0_PRESCALER_DIV_8
- case TIMER0_PRESCALER_DIV_8:
- return 8;
-#endif
-
-#if defined TIMER0_PRESCALER_DIV_16
- case TIMER0_PRESCALER_DIV_16:
- return 16;
-#endif
-
-#if defined TIMER0_PRESCALER_DIV_32
- case TIMER0_PRESCALER_DIV_32:
- return 32;
-#endif
-
-#if defined TIMER0_PRESCALER_DIV_64
- case TIMER0_PRESCALER_DIV_64:
- return 64;
-#endif
-
-#if defined TIMER0_PRESCALER_DIV_128
- case TIMER0_PRESCALER_DIV_128:
- return 128;
-#endif
-
-#if defined TIMER0_PRESCALER_DIV_256
- case TIMER0_PRESCALER_DIV_256:
- return 256;
-#endif
-
-#if defined TIMER0_PRESCALER_DIV_512
- case TIMER0_PRESCALER_DIV_512:
- return 512;
-#endif
-
-#if defined TIMER0_PRESCALER_DIV_1024
- case TIMER0_PRESCALER_DIV_1024:
- return 1024;
-#endif
-
-#if defined TIMER0_PRESCALER_DIV_2048
- case TIMER0_PRESCALER_DIV_2048:
- return 2048;
-#endif
-
-#if defined TIMER0_PRESCALER_DIV_4096
- case TIMER0_PRESCALER_DIV_4096:
- return 4096;
-#endif
-
-#if defined TIMER0_PRESCALER_DIV_8192
- case TIMER0_PRESCALER_DIV_8192:
- return 8192;
-#endif
-
-#if defined TIMER0_PRESCALER_DIV_16384
- case TIMER0_PRESCALER_DIV_16384:
- return 16384;
-#endif
-
- default:
- return -1;
- }
-}
-
-
-/* return <0 on error, else return reg value */
-/* This static inline function is very optimized if div is
- * a constant */
-static inline int16_t __timer1_div_to_reg(uint16_t div)
-{
- switch(div) {
-#if defined TIMER1_PRESCALER_REG_0 && TIMER1_PRESCALER_REG_0 >= 0
- case TIMER1_PRESCALER_REG_0:
- return 0;
-#endif
-
-#if defined TIMER1_PRESCALER_REG_1 && TIMER1_PRESCALER_REG_1 >= 0
- case TIMER1_PRESCALER_REG_1:
- return 1;
-#endif
-
-#if defined TIMER1_PRESCALER_REG_2 && TIMER1_PRESCALER_REG_2 >= 0
- case TIMER1_PRESCALER_REG_2:
- return 2;
-#endif
-
-#if defined TIMER1_PRESCALER_REG_3 && TIMER1_PRESCALER_REG_3 >= 0
- case TIMER1_PRESCALER_REG_3:
- return 3;
-#endif
-
-#if defined TIMER1_PRESCALER_REG_4 && TIMER1_PRESCALER_REG_4 >= 0
- case TIMER1_PRESCALER_REG_4:
- return 4;
-#endif
-
-#if defined TIMER1_PRESCALER_REG_5 && TIMER1_PRESCALER_REG_5 >= 0
- case TIMER1_PRESCALER_REG_5:
- return 5;
-#endif
-
-#if defined TIMER1_PRESCALER_REG_6 && TIMER1_PRESCALER_REG_6 >= 0
- case TIMER1_PRESCALER_REG_6:
- return 6;
-#endif
-
-#if defined TIMER1_PRESCALER_REG_7 && TIMER1_PRESCALER_REG_7 >= 0
- case TIMER1_PRESCALER_REG_7:
- return 7;
-#endif
-
-#if defined TIMER1_PRESCALER_REG_8 && TIMER1_PRESCALER_REG_8 >= 0
- case TIMER1_PRESCALER_REG_8:
- return 8;
-#endif
-
-#if defined TIMER1_PRESCALER_REG_9 && TIMER1_PRESCALER_REG_9 >= 0
- case TIMER1_PRESCALER_REG_9:
- return 9;
-#endif
-
-#if defined TIMER1_PRESCALER_REG_10 && TIMER1_PRESCALER_REG_10 >= 0
- case TIMER1_PRESCALER_REG_10:
- return 10;
-#endif
-
-#if defined TIMER1_PRESCALER_REG_11 && TIMER1_PRESCALER_REG_11 >= 0
- case TIMER1_PRESCALER_REG_11:
- return 11;
-#endif
-
-#if defined TIMER1_PRESCALER_REG_12 && TIMER1_PRESCALER_REG_12 >= 0
- case TIMER1_PRESCALER_REG_12:
- return 12;
-#endif
-
-#if defined TIMER1_PRESCALER_REG_13 && TIMER1_PRESCALER_REG_13 >= 0
- case TIMER1_PRESCALER_REG_13:
- return 13;
-#endif
-
-#if defined TIMER1_PRESCALER_REG_14 && TIMER1_PRESCALER_REG_14 >= 0
- case TIMER1_PRESCALER_REG_14:
- return 14;
-#endif
-
-#if defined TIMER1_PRESCALER_REG_15 && TIMER1_PRESCALER_REG_15 >= 0
- case TIMER1_PRESCALER_REG_15:
- return 15;
-#endif
- default:
- return -1;
- }
-}
-
-/* return <0 on error, else return div value */
-/* This static inline function is very optimized if reg is
- * a constant */
-static inline int16_t __timer1_reg_to_div(uint8_t reg)
-{
- switch(reg) {
-#if defined TIMER1_PRESCALER_DIV_0
- case TIMER1_PRESCALER_DIV_0:
- return 0;
-#endif
-
-#if defined TIMER1_PRESCALER_DIV_1
- case TIMER1_PRESCALER_DIV_1:
- return 1;
-#endif
-
-#if defined TIMER1_PRESCALER_DIV_2
- case TIMER1_PRESCALER_DIV_2:
- return 2;
-#endif
-
-#if defined TIMER1_PRESCALER_DIV_4
- case TIMER1_PRESCALER_DIV_4:
- return 4;
-#endif
-
-#if defined TIMER1_PRESCALER_DIV_8
- case TIMER1_PRESCALER_DIV_8:
- return 8;
-#endif
-
-#if defined TIMER1_PRESCALER_DIV_16
- case TIMER1_PRESCALER_DIV_16:
- return 16;
-#endif
-
-#if defined TIMER1_PRESCALER_DIV_32
- case TIMER1_PRESCALER_DIV_32:
- return 32;
-#endif
-
-#if defined TIMER1_PRESCALER_DIV_64
- case TIMER1_PRESCALER_DIV_64:
- return 64;
-#endif
-
-#if defined TIMER1_PRESCALER_DIV_128
- case TIMER1_PRESCALER_DIV_128:
- return 128;
-#endif
-
-#if defined TIMER1_PRESCALER_DIV_256
- case TIMER1_PRESCALER_DIV_256:
- return 256;
-#endif
-
-#if defined TIMER1_PRESCALER_DIV_512
- case TIMER1_PRESCALER_DIV_512:
- return 512;
-#endif
-
-#if defined TIMER1_PRESCALER_DIV_1024
- case TIMER1_PRESCALER_DIV_1024:
- return 1024;
-#endif
-
-#if defined TIMER1_PRESCALER_DIV_2048
- case TIMER1_PRESCALER_DIV_2048:
- return 2048;
-#endif
-
-#if defined TIMER1_PRESCALER_DIV_4096
- case TIMER1_PRESCALER_DIV_4096:
- return 4096;
-#endif
-
-#if defined TIMER1_PRESCALER_DIV_8192
- case TIMER1_PRESCALER_DIV_8192:
- return 8192;
-#endif
-
-#if defined TIMER1_PRESCALER_DIV_16384
- case TIMER1_PRESCALER_DIV_16384:
- return 16384;
-#endif
-
- default:
- return -1;
- }
-}
-
-
-
-/* return <0 on error, else return reg value */
-/* This static inline function is very optimized if div is
- * a constant */
-static inline int16_t __timer2_div_to_reg(uint16_t div)
-{
- switch(div) {
-#if defined TIMER2_PRESCALER_REG_0 && TIMER2_PRESCALER_REG_0 >= 0
- case TIMER2_PRESCALER_REG_0:
- return 0;
-#endif
-
-#if defined TIMER2_PRESCALER_REG_1 && TIMER2_PRESCALER_REG_1 >= 0
- case TIMER2_PRESCALER_REG_1:
- return 1;
-#endif
-
-#if defined TIMER2_PRESCALER_REG_2 && TIMER2_PRESCALER_REG_2 >= 0
- case TIMER2_PRESCALER_REG_2:
- return 2;
-#endif
-
-#if defined TIMER2_PRESCALER_REG_3 && TIMER2_PRESCALER_REG_3 >= 0
- case TIMER2_PRESCALER_REG_3:
- return 3;
-#endif
-
-#if defined TIMER2_PRESCALER_REG_4 && TIMER2_PRESCALER_REG_4 >= 0
- case TIMER2_PRESCALER_REG_4:
- return 4;
-#endif
-
-#if defined TIMER2_PRESCALER_REG_5 && TIMER2_PRESCALER_REG_5 >= 0
- case TIMER2_PRESCALER_REG_5:
- return 5;
-#endif
-
-#if defined TIMER2_PRESCALER_REG_6 && TIMER2_PRESCALER_REG_6 >= 0
- case TIMER2_PRESCALER_REG_6:
- return 6;
-#endif
-
-#if defined TIMER2_PRESCALER_REG_7 && TIMER2_PRESCALER_REG_7 >= 0
- case TIMER2_PRESCALER_REG_7:
- return 7;
-#endif
-
-#if defined TIMER2_PRESCALER_REG_8 && TIMER2_PRESCALER_REG_8 >= 0
- case TIMER2_PRESCALER_REG_8:
- return 8;
-#endif
-
-#if defined TIMER2_PRESCALER_REG_9 && TIMER2_PRESCALER_REG_9 >= 0
- case TIMER2_PRESCALER_REG_9:
- return 9;
-#endif
-
-#if defined TIMER2_PRESCALER_REG_10 && TIMER2_PRESCALER_REG_10 >= 0
- case TIMER2_PRESCALER_REG_10:
- return 10;
-#endif
-
-#if defined TIMER2_PRESCALER_REG_11 && TIMER2_PRESCALER_REG_11 >= 0
- case TIMER2_PRESCALER_REG_11:
- return 11;
-#endif
-
-#if defined TIMER2_PRESCALER_REG_12 && TIMER2_PRESCALER_REG_12 >= 0
- case TIMER2_PRESCALER_REG_12:
- return 12;
-#endif
-
-#if defined TIMER2_PRESCALER_REG_13 && TIMER2_PRESCALER_REG_13 >= 0
- case TIMER2_PRESCALER_REG_13:
- return 13;
-#endif
-
-#if defined TIMER2_PRESCALER_REG_14 && TIMER2_PRESCALER_REG_14 >= 0
- case TIMER2_PRESCALER_REG_14:
- return 14;
-#endif
-
-#if defined TIMER2_PRESCALER_REG_15 && TIMER2_PRESCALER_REG_15 >= 0
- case TIMER2_PRESCALER_REG_15:
- return 15;
-#endif
- default:
- return -1;
- }
-}
-
-/* return <0 on error, else return div value */
-/* This static inline function is very optimized if reg is
- * a constant */
-static inline int16_t __timer2_reg_to_div(uint8_t reg)
-{
- switch(reg) {
-#if defined TIMER2_PRESCALER_DIV_0
- case TIMER2_PRESCALER_DIV_0:
- return 0;
-#endif
-
-#if defined TIMER2_PRESCALER_DIV_1
- case TIMER2_PRESCALER_DIV_1:
- return 1;
-#endif
-
-#if defined TIMER2_PRESCALER_DIV_2
- case TIMER2_PRESCALER_DIV_2:
- return 2;
-#endif
-
-#if defined TIMER2_PRESCALER_DIV_4
- case TIMER2_PRESCALER_DIV_4:
- return 4;
-#endif
-
-#if defined TIMER2_PRESCALER_DIV_8
- case TIMER2_PRESCALER_DIV_8:
- return 8;
-#endif
-
-#if defined TIMER2_PRESCALER_DIV_16
- case TIMER2_PRESCALER_DIV_16:
- return 16;
-#endif
-
-#if defined TIMER2_PRESCALER_DIV_32
- case TIMER2_PRESCALER_DIV_32:
- return 32;
-#endif
-
-#if defined TIMER2_PRESCALER_DIV_64
- case TIMER2_PRESCALER_DIV_64:
- return 64;
-#endif
-
-#if defined TIMER2_PRESCALER_DIV_128
- case TIMER2_PRESCALER_DIV_128:
- return 128;
-#endif
-
-#if defined TIMER2_PRESCALER_DIV_256
- case TIMER2_PRESCALER_DIV_256:
- return 256;
-#endif
-
-#if defined TIMER2_PRESCALER_DIV_512
- case TIMER2_PRESCALER_DIV_512:
- return 512;
-#endif
-
-#if defined TIMER2_PRESCALER_DIV_1024
- case TIMER2_PRESCALER_DIV_1024:
- return 1024;
-#endif
-
-#if defined TIMER2_PRESCALER_DIV_2048
- case TIMER2_PRESCALER_DIV_2048:
- return 2048;
-#endif
-
-#if defined TIMER2_PRESCALER_DIV_4096
- case TIMER2_PRESCALER_DIV_4096:
- return 4096;
-#endif
-
-#if defined TIMER2_PRESCALER_DIV_8192
- case TIMER2_PRESCALER_DIV_8192:
- return 8192;
-#endif
-
-#if defined TIMER2_PRESCALER_DIV_16384
- case TIMER2_PRESCALER_DIV_16384:
- return 16384;
-#endif
-
- default:
- return -1;
- }
-}
-
-
-
-/* return <0 on error, else return reg value */
-/* This static inline function is very optimized if div is
- * a constant */
-static inline int16_t __timer3_div_to_reg(uint16_t div)
-{
- switch(div) {
-#if defined TIMER3_PRESCALER_REG_0 && TIMER3_PRESCALER_REG_0 >= 0
- case TIMER3_PRESCALER_REG_0:
- return 0;
-#endif
-
-#if defined TIMER3_PRESCALER_REG_1 && TIMER3_PRESCALER_REG_1 >= 0
- case TIMER3_PRESCALER_REG_1:
- return 1;
-#endif
-
-#if defined TIMER3_PRESCALER_REG_2 && TIMER3_PRESCALER_REG_2 >= 0
- case TIMER3_PRESCALER_REG_2:
- return 2;
-#endif
-
-#if defined TIMER3_PRESCALER_REG_3 && TIMER3_PRESCALER_REG_3 >= 0
- case TIMER3_PRESCALER_REG_3:
- return 3;
-#endif
-
-#if defined TIMER3_PRESCALER_REG_4 && TIMER3_PRESCALER_REG_4 >= 0
- case TIMER3_PRESCALER_REG_4:
- return 4;
-#endif
-
-#if defined TIMER3_PRESCALER_REG_5 && TIMER3_PRESCALER_REG_5 >= 0
- case TIMER3_PRESCALER_REG_5:
- return 5;
-#endif
-
-#if defined TIMER3_PRESCALER_REG_6 && TIMER3_PRESCALER_REG_6 >= 0
- case TIMER3_PRESCALER_REG_6:
- return 6;
-#endif
-
-#if defined TIMER3_PRESCALER_REG_7 && TIMER3_PRESCALER_REG_7 >= 0
- case TIMER3_PRESCALER_REG_7:
- return 7;
-#endif
-
-#if defined TIMER3_PRESCALER_REG_8 && TIMER3_PRESCALER_REG_8 >= 0
- case TIMER3_PRESCALER_REG_8:
- return 8;
-#endif
-
-#if defined TIMER3_PRESCALER_REG_9 && TIMER3_PRESCALER_REG_9 >= 0
- case TIMER3_PRESCALER_REG_9:
- return 9;
-#endif
-
-#if defined TIMER3_PRESCALER_REG_10 && TIMER3_PRESCALER_REG_10 >= 0
- case TIMER3_PRESCALER_REG_10:
- return 10;
-#endif
-
-#if defined TIMER3_PRESCALER_REG_11 && TIMER3_PRESCALER_REG_11 >= 0
- case TIMER3_PRESCALER_REG_11:
- return 11;
-#endif
-
-#if defined TIMER3_PRESCALER_REG_12 && TIMER3_PRESCALER_REG_12 >= 0
- case TIMER3_PRESCALER_REG_12:
- return 12;
-#endif
-
-#if defined TIMER3_PRESCALER_REG_13 && TIMER3_PRESCALER_REG_13 >= 0
- case TIMER3_PRESCALER_REG_13:
- return 13;
-#endif
-#if defined TIMER3_PRESCALER_REG_14 && TIMER3_PRESCALER_REG_14 >= 0
- case TIMER3_PRESCALER_REG_14:
- return 14;
-#endif
-
-#if defined TIMER3_PRESCALER_REG_15 && TIMER3_PRESCALER_REG_15 >= 0
- case TIMER3_PRESCALER_REG_15:
- return 15;
-#endif
- default:
- return -1;
- }
-}
-
-/* return <0 on error, else return div value */
-/* This static inline function is very optimized if reg is
- * a constant */
-static inline int16_t __timer3_reg_to_div(uint8_t reg)
-{
- switch(reg) {
-#if defined TIMER3_PRESCALER_DIV_0
- case TIMER3_PRESCALER_DIV_0:
- return 0;
-#endif
-
-#if defined TIMER3_PRESCALER_DIV_1
- case TIMER3_PRESCALER_DIV_1:
- return 1;
-#endif
-
-#if defined TIMER3_PRESCALER_DIV_2
- case TIMER3_PRESCALER_DIV_2:
- return 2;
-#endif
-
-#if defined TIMER3_PRESCALER_DIV_4
- case TIMER3_PRESCALER_DIV_4:
- return 4;
-#endif
-
-#if defined TIMER3_PRESCALER_DIV_8
- case TIMER3_PRESCALER_DIV_8:
- return 8;
-#endif
-
-#if defined TIMER3_PRESCALER_DIV_16
- case TIMER3_PRESCALER_DIV_16:
- return 16;
-#endif
-
-#if defined TIMER3_PRESCALER_DIV_32
- case TIMER3_PRESCALER_DIV_32:
- return 32;
-#endif
-
-#if defined TIMER3_PRESCALER_DIV_64
- case TIMER3_PRESCALER_DIV_64:
- return 64;
-#endif
-
-#if defined TIMER3_PRESCALER_DIV_128
- case TIMER3_PRESCALER_DIV_128:
- return 128;
-#endif
-
-#if defined TIMER3_PRESCALER_DIV_256
- case TIMER3_PRESCALER_DIV_256:
- return 256;
-#endif
-
-#if defined TIMER3_PRESCALER_DIV_512
- case TIMER3_PRESCALER_DIV_512:
- return 512;
-#endif
-
-#if defined TIMER3_PRESCALER_DIV_1024
- case TIMER3_PRESCALER_DIV_1024:
- return 1024;
-#endif
-
-#if defined TIMER3_PRESCALER_DIV_2048
- case TIMER3_PRESCALER_DIV_2048:
- return 2048;
-#endif
-
-#if defined TIMER3_PRESCALER_DIV_4096
- case TIMER3_PRESCALER_DIV_4096:
- return 4096;
-#endif
-
-#if defined TIMER3_PRESCALER_DIV_8192
- case TIMER3_PRESCALER_DIV_8192:
- return 8192;
-#endif
-
-#if defined TIMER3_PRESCALER_DIV_16384
- case TIMER3_PRESCALER_DIV_16384:
- return 16384;
-#endif
-
- default:
- return -1;
- }
-}
-
-/* return <0 on error, else return reg value */
-/* This static inline function is very optimized if div is
- * a constant */
-static inline int16_t __timer4_div_to_reg(uint16_t div)
-{
- switch(div) {
-#if defined TIMER4_PRESCALER_REG_0 && TIMER4_PRESCALER_REG_0 >= 0
- case TIMER4_PRESCALER_REG_0:
- return 0;
-#endif
-
-#if defined TIMER4_PRESCALER_REG_1 && TIMER4_PRESCALER_REG_1 >= 0
- case TIMER4_PRESCALER_REG_1:
- return 1;
-#endif
-
-#if defined TIMER4_PRESCALER_REG_2 && TIMER4_PRESCALER_REG_2 >= 0
- case TIMER4_PRESCALER_REG_2:
- return 2;
-#endif
-
-#if defined TIMER4_PRESCALER_REG_3 && TIMER4_PRESCALER_REG_3 >= 0
- case TIMER4_PRESCALER_REG_3:
- return 3;
-#endif
-
-#if defined TIMER4_PRESCALER_REG_4 && TIMER4_PRESCALER_REG_4 >= 0
- case TIMER4_PRESCALER_REG_4:
- return 4;
-#endif
-
-#if defined TIMER4_PRESCALER_REG_5 && TIMER4_PRESCALER_REG_5 >= 0
- case TIMER4_PRESCALER_REG_5:
- return 5;
-#endif
-
-#if defined TIMER4_PRESCALER_REG_6 && TIMER4_PRESCALER_REG_6 >= 0
- case TIMER4_PRESCALER_REG_6:
- return 6;
-#endif
-
-#if defined TIMER4_PRESCALER_REG_7 && TIMER4_PRESCALER_REG_7 >= 0
- case TIMER4_PRESCALER_REG_7:
- return 7;
-#endif
-
-#if defined TIMER4_PRESCALER_REG_8 && TIMER4_PRESCALER_REG_8 >= 0
- case TIMER4_PRESCALER_REG_8:
- return 8;
-#endif
-
-#if defined TIMER4_PRESCALER_REG_9 && TIMER4_PRESCALER_REG_9 >= 0
- case TIMER4_PRESCALER_REG_9:
- return 9;
-#endif
-
-#if defined TIMER4_PRESCALER_REG_10 && TIMER4_PRESCALER_REG_10 >= 0
- case TIMER4_PRESCALER_REG_10:
- return 10;
-#endif
-
-#if defined TIMER4_PRESCALER_REG_11 && TIMER4_PRESCALER_REG_11 >= 0
- case TIMER4_PRESCALER_REG_11:
- return 11;
-#endif
-
-#if defined TIMER4_PRESCALER_REG_12 && TIMER4_PRESCALER_REG_12 >= 0
- case TIMER4_PRESCALER_REG_12:
- return 12;
-#endif
-
-#if defined TIMER4_PRESCALER_REG_13 && TIMER4_PRESCALER_REG_13 >= 0
- case TIMER4_PRESCALER_REG_13:
- return 13;
-#endif
-#if defined TIMER4_PRESCALER_REG_14 && TIMER4_PRESCALER_REG_14 >= 0
- case TIMER4_PRESCALER_REG_14:
- return 14;
-#endif
-
-#if defined TIMER4_PRESCALER_REG_15 && TIMER4_PRESCALER_REG_15 >= 0
- case TIMER4_PRESCALER_REG_15:
- return 15;
-#endif
- default:
- return -1;
- }
-}
-
-/* return <0 on error, else return div value */
-/* This static inline function is very optimized if reg is
- * a constant */
-static inline int16_t __timer4_reg_to_div(uint8_t reg)
-{
- switch(reg) {
-#if defined TIMER4_PRESCALER_DIV_0
- case TIMER4_PRESCALER_DIV_0:
- return 0;
-#endif
-
-#if defined TIMER4_PRESCALER_DIV_1
- case TIMER4_PRESCALER_DIV_1:
- return 1;
-#endif
-
-#if defined TIMER4_PRESCALER_DIV_2
- case TIMER4_PRESCALER_DIV_2:
- return 2;
-#endif
-
-#if defined TIMER4_PRESCALER_DIV_4
- case TIMER4_PRESCALER_DIV_4:
- return 4;
-#endif
-
-#if defined TIMER4_PRESCALER_DIV_8
- case TIMER4_PRESCALER_DIV_8:
- return 8;
-#endif
-
-#if defined TIMER4_PRESCALER_DIV_16
- case TIMER4_PRESCALER_DIV_16:
- return 16;
-#endif
-
-#if defined TIMER4_PRESCALER_DIV_32
- case TIMER4_PRESCALER_DIV_32:
- return 32;
-#endif
-
-#if defined TIMER4_PRESCALER_DIV_64
- case TIMER4_PRESCALER_DIV_64:
- return 64;
-#endif
-
-#if defined TIMER4_PRESCALER_DIV_128
- case TIMER4_PRESCALER_DIV_128:
- return 128;
-#endif
-
-#if defined TIMER4_PRESCALER_DIV_256
- case TIMER4_PRESCALER_DIV_256:
- return 256;
-#endif
-
-#if defined TIMER4_PRESCALER_DIV_512
- case TIMER4_PRESCALER_DIV_512:
- return 512;
-#endif
-
-#if defined TIMER4_PRESCALER_DIV_1024
- case TIMER4_PRESCALER_DIV_1024:
- return 1024;
-#endif
-
-#if defined TIMER4_PRESCALER_DIV_2048
- case TIMER4_PRESCALER_DIV_2048:
- return 2048;
-#endif
-
-#if defined TIMER4_PRESCALER_DIV_4096
- case TIMER4_PRESCALER_DIV_4096:
- return 4096;
-#endif
-
-#if defined TIMER4_PRESCALER_DIV_8192
- case TIMER4_PRESCALER_DIV_8192:
- return 8192;
-#endif
-
-#if defined TIMER4_PRESCALER_DIV_16384
- case TIMER4_PRESCALER_DIV_16384:
- return 16384;
-#endif
-
- default:
- return -1;
- }
-}
-
-/* return <0 on error, else return reg value */
-/* This static inline function is very optimized if div is
- * a constant */
-static inline int16_t __timer5_div_to_reg(uint16_t div)
-{
- switch(div) {
-#if defined TIMER5_PRESCALER_REG_0 && TIMER5_PRESCALER_REG_0 >= 0
- case TIMER5_PRESCALER_REG_0:
- return 0;
-#endif
-
-#if defined TIMER5_PRESCALER_REG_1 && TIMER5_PRESCALER_REG_1 >= 0
- case TIMER5_PRESCALER_REG_1:
- return 1;
-#endif
-
-#if defined TIMER5_PRESCALER_REG_2 && TIMER5_PRESCALER_REG_2 >= 0
- case TIMER5_PRESCALER_REG_2:
- return 2;
-#endif
-
-#if defined TIMER5_PRESCALER_REG_3 && TIMER5_PRESCALER_REG_3 >= 0
- case TIMER5_PRESCALER_REG_3:
- return 3;
-#endif
-
-#if defined TIMER5_PRESCALER_REG_4 && TIMER5_PRESCALER_REG_4 >= 0
- case TIMER5_PRESCALER_REG_4:
- return 4;
-#endif
-
-#if defined TIMER5_PRESCALER_REG_5 && TIMER5_PRESCALER_REG_5 >= 0
- case TIMER5_PRESCALER_REG_5:
- return 5;
-#endif
-
-#if defined TIMER5_PRESCALER_REG_6 && TIMER5_PRESCALER_REG_6 >= 0
- case TIMER5_PRESCALER_REG_6:
- return 6;
-#endif
-
-#if defined TIMER5_PRESCALER_REG_7 && TIMER5_PRESCALER_REG_7 >= 0
- case TIMER5_PRESCALER_REG_7:
- return 7;
-#endif
-
-#if defined TIMER5_PRESCALER_REG_8 && TIMER5_PRESCALER_REG_8 >= 0
- case TIMER5_PRESCALER_REG_8:
- return 8;
-#endif
-
-#if defined TIMER5_PRESCALER_REG_9 && TIMER5_PRESCALER_REG_9 >= 0
- case TIMER5_PRESCALER_REG_9:
- return 9;
-#endif
-
-#if defined TIMER5_PRESCALER_REG_10 && TIMER5_PRESCALER_REG_10 >= 0
- case TIMER5_PRESCALER_REG_10:
- return 10;
-#endif
-
-#if defined TIMER5_PRESCALER_REG_11 && TIMER5_PRESCALER_REG_11 >= 0
- case TIMER5_PRESCALER_REG_11:
- return 11;
-#endif
-
-#if defined TIMER5_PRESCALER_REG_12 && TIMER5_PRESCALER_REG_12 >= 0
- case TIMER5_PRESCALER_REG_12:
- return 12;
-#endif
-
-#if defined TIMER5_PRESCALER_REG_13 && TIMER5_PRESCALER_REG_13 >= 0
- case TIMER5_PRESCALER_REG_13:
- return 13;
-#endif
-#if defined TIMER5_PRESCALER_REG_14 && TIMER5_PRESCALER_REG_14 >= 0
- case TIMER5_PRESCALER_REG_14:
- return 14;
-#endif
-
-#if defined TIMER5_PRESCALER_REG_15 && TIMER5_PRESCALER_REG_15 >= 0
- case TIMER5_PRESCALER_REG_15:
- return 15;
-#endif
- default:
- return -1;
- }
-}
-
-/* return <0 on error, else return div value */
-/* This static inline function is very optimized if reg is
- * a constant */
-static inline int16_t __timer5_reg_to_div(uint8_t reg)
-{
- switch(reg) {
-#if defined TIMER5_PRESCALER_DIV_0
- case TIMER5_PRESCALER_DIV_0:
- return 0;
-#endif
-
-#if defined TIMER5_PRESCALER_DIV_1
- case TIMER5_PRESCALER_DIV_1:
- return 1;
-#endif
-
-#if defined TIMER5_PRESCALER_DIV_2
- case TIMER5_PRESCALER_DIV_2:
- return 2;
-#endif
-
-#if defined TIMER5_PRESCALER_DIV_4
- case TIMER5_PRESCALER_DIV_4:
- return 4;
-#endif
-
-#if defined TIMER5_PRESCALER_DIV_8
- case TIMER5_PRESCALER_DIV_8:
- return 8;
-#endif
-
-#if defined TIMER5_PRESCALER_DIV_16
- case TIMER5_PRESCALER_DIV_16:
- return 16;
-#endif
-
-#if defined TIMER5_PRESCALER_DIV_32
- case TIMER5_PRESCALER_DIV_32:
- return 32;
-#endif
-
-#if defined TIMER5_PRESCALER_DIV_64
- case TIMER5_PRESCALER_DIV_64:
- return 64;
-#endif
-
-#if defined TIMER5_PRESCALER_DIV_128
- case TIMER5_PRESCALER_DIV_128:
- return 128;
-#endif
-
-#if defined TIMER5_PRESCALER_DIV_256
- case TIMER5_PRESCALER_DIV_256:
- return 256;
-#endif
-
-#if defined TIMER5_PRESCALER_DIV_512
- case TIMER5_PRESCALER_DIV_512:
- return 512;
-#endif
-
-#if defined TIMER5_PRESCALER_DIV_1024
- case TIMER5_PRESCALER_DIV_1024:
- return 1024;
-#endif
-
-#if defined TIMER5_PRESCALER_DIV_2048
- case TIMER5_PRESCALER_DIV_2048:
- return 2048;
-#endif
-
-#if defined TIMER5_PRESCALER_DIV_4096
- case TIMER5_PRESCALER_DIV_4096:
- return 4096;
-#endif
-
-#if defined TIMER5_PRESCALER_DIV_8192
- case TIMER5_PRESCALER_DIV_8192:
- return 8192;
-#endif
-
-#if defined TIMER5_PRESCALER_DIV_16384
- case TIMER5_PRESCALER_DIV_16384:
- return 16384;
-#endif
-
- default:
- return -1;
- }
-}
-
-#endif
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: uart.c,v 1.33.4.7 2009-01-23 23:08:42 zer0 Exp $
- *
- */
-
-/* Olivier MATZ, Droids-corp 2004 - 2009 */
-
-#include <aversive.h>
-#include <aversive/list.h>
-
-#include <uart.h>
-#include <uart_defs.h>
-#include <uart_private.h>
-
-struct cirbuf g_tx_fifo[UART_HW_NUM];
-struct cirbuf g_rx_fifo[UART_HW_NUM];
-
-/* global vars are initialized to 0 (NULL) */
-event *rx_event[UART_HW_NUM];
-event *tx_event[UART_HW_NUM];
-
-const struct regs uart_regs[UART_HW_NUM] = {
-#ifdef UDR0
- {
- .udr = &UDR0,
- .ucsra = &UCSR0A,
- .ucsrb = &UCSR0B,
- .ucsrc = &UCSR0C,
- .ubrrl = &UBRR0L,
- .ubrrh = &UBRR0H,
- },
-#endif
-#ifdef UDR1
- {
- .udr = &UDR1,
- .ucsra = &UCSR1A,
- .ucsrb = &UCSR1B,
- .ucsrc = &UCSR1C,
- .ubrrl = &UBRR1L,
- .ubrrh = &UBRR1H,
- },
-#endif
-#ifdef UDR2
- {
- .udr = &UDR2,
- .ucsra = &UCSR2A,
- .ucsrb = &UCSR2B,
- .ucsrc = &UCSR2C,
- .ubrrl = &UBRR2L,
- .ubrrh = &UBRR2H,
- },
-#endif
-#ifdef UDR3
- {
- .udr = &UDR3,
- .ucsra = &UCSR3A,
- .ucsrb = &UCSR3B,
- .ucsrc = &UCSR3C,
- .ubrrl = &UBRR3L,
- .ubrrh = &UBRR3H,
- },
-#endif
-};
-
-/**
- * This is the interruption function which occurs when the entire
- * frame in the transmit shift register has been shifted out and
- * there is no new data in the transmit buffer.
- */
-#ifdef UART0_COMPILE
-#ifndef SIG_UART0_DATA
-#define SIG_UART0_DATA USART0_UDRE_vect
-#endif
-#ifndef SIG_UART0_DATA
-#define SIG_UART0_DATA SIG_USART0_DATA
-#endif
-SIGNAL(SIG_UART0_DATA)
-{
- uart_send_next_char(0);
-}
-#endif
-#ifdef UART1_COMPILE
-#ifndef SIG_UART1_DATA
-#define SIG_UART1_DATA USART1_UDRE_vect
-#endif
-#ifndef SIG_UART1_DATA
-#define SIG_UART1_DATA SIG_USART1_DATA
-#endif
-SIGNAL(SIG_UART1_DATA)
-{
- uart_send_next_char(1);
-}
-#endif
-#ifdef UART2_COMPILE
-#ifndef SIG_UART2_DATA
-#define SIG_UART2_DATA USART2_UDRE_vect
-#endif
-#ifndef SIG_UART2_DATA
-#define SIG_UART2_DATA SIG_USART2_DATA
-#endif
-SIGNAL(SIG_UART2_DATA)
-{
- uart_send_next_char(2);
-}
-#endif
-#ifdef UART3_COMPILE
-#ifndef SIG_UART3_DATA
-#define SIG_UART3_DATA USART3_UDRE_vect
-#endif
-#ifndef SIG_UART3_DATA
-#define SIG_UART3_DATA SIG_USART3_DATA
-#endif
-SIGNAL(SIG_UART3_DATA)
-{
- uart_send_next_char(3);
-}
-#endif
-
-static void uart_recv_next_char(uint8_t num);
-
-/**
- * This is the interruption function which occurs when there is
- * a new unread data in the reception buffer.
- */
-#ifdef UART0_COMPILE
-#ifndef SIG_UART0_RECV
-#define SIG_UART0_RECV USART0_RX_vect
-#endif
-#ifndef SIG_UART0_RECV
-#define SIG_UART0_RECV SIG_USART0_RECV
-#endif
-SIGNAL(SIG_UART0_RECV)
-{
- uart_recv_next_char(0);
-}
-#endif
-#ifdef UART1_COMPILE
-#ifndef SIG_UART1_RECV
-#define SIG_UART1_RECV USART1_RX_vect
-#endif
-#ifndef SIG_UART1_RECV
-#define SIG_UART1_RECV SIG_USART1_RECV
-#endif
-SIGNAL(SIG_UART1_RECV)
-{
- uart_recv_next_char(1);
-}
-#endif
-#ifdef UART2_COMPILE
-#ifndef SIG_UART2_RECV
-#define SIG_UART2_RECV USART2_RX_vect
-#endif
-#ifndef SIG_UART2_RECV
-#define SIG_UART2_RECV SIG_USART2_RECV
-#endif
-SIGNAL(SIG_UART2_RECV)
-{
- uart_recv_next_char(2);
-}
-#endif
-#ifdef UART3_COMPILE
-#ifndef SIG_UART3_RECV
-#define SIG_UART3_RECV USART3_RX_vect
-#endif
-#ifndef SIG_UART3_RECV
-#define SIG_UART3_RECV SIG_USART3_RECV
-#endif
-SIGNAL(SIG_UART3_RECV)
-{
- uart_recv_next_char(3);
-}
-#endif
-
-
-/**
- * transmit next character of fifo if any, and call the event function.
- * This function is executed with intr locked.
- */
-void uart_send_next_char(uint8_t num)
-{
-#ifdef CONFIG_MODULE_UART_9BITS
- if (uart_getconf_nbits(num) == 9) {
- int elt = 0;
-
- /* for 9 bits, it uses 2 places in the fifo */
- if (CIRBUF_GET_LEN(&g_tx_fifo[num]) < 2) {
- cbi(*uart_regs[num].ucsrb, UDRIE);
- return;
- }
-
- cirbuf_get_buf_tail(&g_tx_fifo[num], (char *)&elt, 2);
- cirbuf_del_buf_tail(&g_tx_fifo[num], 2);
-
- uart_set_udr_9bits(num, elt);
- sbi(*uart_regs[num].ucsrb, UDRIE);
- }
- else /* 5, 6, 7 or 8 bits */
-#endif /* CONFIG_MODULE_UART_9BITS */
- {
- char elt = 0;
-
- if (CIRBUF_IS_EMPTY(&g_tx_fifo[num])) {
- cbi(*uart_regs[num].ucsrb, UDRIE);
- return;
- }
-
- elt = cirbuf_get_tail(&g_tx_fifo[num]);
- cirbuf_del_tail(&g_tx_fifo[num]);
- uart_set_udr(num, elt);
- sbi(*uart_regs[num].ucsrb, UDRIE);
- }
-}
-
-/**
- * UART RX Interrupt
- */
-static void uart_recv_next_char(uint8_t num)
-{
-#ifdef CONFIG_MODULE_UART_9BITS
- if (uart_getconf_nbits() == 9) {
- int elt = 0;
-
- elt = uart_get_udr_9bits(num);
- if (CIRBUF_GET_FREELEN(&g_rx_fifo[num]) >= 2) {
- cirbuf_add_buf_head(&g_rx_fifo[num], (char *)&elt, 2);
- }
-
- if (rx_event[num])
- ((event_9bits *)rx_event[num])(elt);
- }
- else
-#endif /* CONFIG_MODULE_UART_9BITS */
- {
- char elt = 0;
-
- elt = uart_get_udr(num);
- if (!CIRBUF_IS_FULL(&g_rx_fifo[num])) {
- cirbuf_add_head(&g_rx_fifo[num], elt);
- }
-
- if (rx_event[num])
- rx_event[num](elt);
- }
-}
-
-/* init all uarts */
-void uart_init(void)
-{
-#if (defined UDR0) && (defined UART0_COMPILE)
- uart_setconf(0, NULL);
-#endif
-
-#if (defined UDR1) && (defined UART1_COMPILE)
- uart_setconf(1, NULL);
-#endif
-
-#if (defined UDR2) && (defined UART2_COMPILE)
- uart_setconf(2, NULL);
-#endif
-
-#if (defined UDR3) && (defined UART3_COMPILE)
- uart_setconf(3, NULL);
-#endif
-}
+++ /dev/null
-/* \r
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)\r
- * \r
- * This program is free software; you can redistribute it and/or modify\r
- * it under the terms of the GNU General Public License as published by\r
- * the Free Software Foundation; either version 2 of the License, or\r
- * (at your option) any later version.\r
- *\r
- * This program is distributed in the hope that it will be useful,\r
- * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
- * GNU General Public License for more details.\r
- *\r
- * You should have received a copy of the GNU General Public License\r
- * along with this program; if not, write to the Free Software\r
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
- *\r
- * Revision : $Id: uart.h,v 1.22.4.4 2008-12-27 16:29:07 zer0 Exp $\r
- *\r
- */\r
-\r
-/* Olivier MATZ, 2004 - 2006\r
- * Interface of the uart module\r
- */\r
-\r
-/** \file uart.h\r
- * \brief Interface of the UART module.\r
- *\r
- * This module provides :\r
- * - Tx and Rx with fifo\r
- * - Speed selection\r
- * - Parity selection (if the uC support it)\r
- * - 5 to 8 data bits (if the uC support it).\r
- * - 1 or 2 stop bits (if the uC support it).\r
- * - up to 4 UARTs (if the uC support it).\r
- * \r
- * Number of bits in frame, parity, stop bits are the same for tx and\r
- * rx. TX fifo is useless if interrupts are disabled because the uart\r
- * wait that all bytes are transmitted before returning.\r
- *\r
- * It doesn't support some USART capabilities :\r
- * - Synchronous mode\r
- * - Multiprocessor communication\r
- */\r
-\r
-#ifndef _UART_H_\r
-#define _UART_H_\r
-\r
-#include <stdio.h>\r
-#include <aversive.h>\r
-#include <uart_config.h>\r
-#include <uart_defs.h>\r
-\r
-#include <cirbuf.h>\r
-\r
-/** this structure stores the configuration of the uart */\r
-struct uart_config {\r
- uint8_t enabled : 1, /**< enable or disable the uart */\r
- intr_enabled : 1, /**< use interruptions or not */\r
- use_double_speed : 1, /**< less acurate, but can reach faster baudrate */\r
- parity : 2, /**< none, odd or even */\r
- stop_bits : 1, /**< 1 or 2 bits at the end of the frame */\r
- reserved : 1; /**< nothing for now */\r
- uint8_t nbits; /**< number of bits in frame, 5,6,7,8 or 9 */\r
- uint32_t baudrate; /**< speed of uart */\r
-};\r
-\r
-/** The emission fifo of uart */\r
-extern struct cirbuf g_tx_fifo[UART_HW_NUM];\r
-\r
-/** The reception fifo of uart */\r
-extern struct cirbuf g_rx_fifo[UART_HW_NUM];\r
-\r
-/** \r
- * Initialisation function. This function puts the registers of the\r
- * microcontroler in a correct state in order to use the uart. It\r
- * uses the configuration file <uart_config.h> ; this function is\r
- * equivalent to call uartX_setconf(NULL) for each uart.\r
- */\r
-void uart_init(void);\r
-\r
-/** \r
- * Configure the uart 'num' with the given configuration. Returns 0 on\r
- * success.\r
- */\r
-int8_t uart_setconf(uint8_t num, struct uart_config *u);\r
-\r
-/** Get the current configuration of the uart 'num' */\r
-void uart_getconf(uint8_t num, struct uart_config *u);\r
-\r
-/** \r
- * uart_recv returns the next character, taken from the fifo (if\r
- * any). If there is nothing to read, the function waits until\r
- * something come on the uart.\r
- */\r
-int uart_recv(uint8_t num);\r
-\r
-/** \r
- * uart_recv returns the next character, taken from the fifo (if\r
- * any). If there is nothing to read, the function returns -1.\r
- */\r
-int uart_recv_nowait(uint8_t num);\r
-\r
-/**\r
- * same than uart_recv with 9 bits.\r
- */\r
-int uart_9bits_recv(uint8_t num);\r
-\r
-/** \r
- * same than uart_recv_nowait() with 9 bits.\r
- */\r
-int uart_9bits_recv_nowait(uint8_t num);\r
-\r
-/**\r
- * uart_send_nowait is used to send data to the uart 'num'. The data\r
- * is first stored in the FIFO before beeing sent. If the FIFO is\r
- * full, data is dropped and the function returns -1, else it returns\r
- * the character c.\r
- */\r
-int uart_send_nowait(uint8_t num, char c);\r
-\r
-/**\r
- * uart_send is used to send data to the uart 'num'. The data is first\r
- * stored in the FIFO before beeing sent. If the FIFO is full, the\r
- * function wait until the uart is ready. The function returns c.\r
- */\r
-int uart_send(uint8_t num, char c);\r
-\r
-/**\r
- * uart_send_9bits is the same that uart_send but arg is 16 bits so\r
- * data can be 9 bits wide.\r
- */\r
-int uart_send_9bits_nowait(uint8_t num, int c);\r
-\r
-/* uart_send_9bits_wait is the same that uart_send_wait but arg is\r
- * 16 bits so data can be 9 bits wide.\r
- */\r
-int uart_send_9bits(uint8_t num, int c);\r
-\r
-\r
-\r
-/**\r
- * This function is used to register another function which will be\r
- * executed at each byte transmission (5, 6 ,7 ,8 bits)\r
- */\r
-void uart_register_tx_event(uint8_t num, void (*f)(char));\r
-\r
-/**\r
- * This function is used to register another function which will be\r
- * executed at each byte reception (5, 6 ,7 ,8 bits)\r
- */\r
-void uart_register_rx_event(uint8_t num, void (*f)(char));\r
-\r
-\r
-/**\r
- * This function is used to register another function which will be\r
- * executed at each 9 bits frame transmission. WARNING : it uses the\r
- * same internal pointer that the 8 bits event, so be carreful to \r
- * unregister 8 bits events when doing 9 bits and vice versa.\r
- */\r
-void uart_register_tx_9bits_event(uint8_t num, void (*f)(int));\r
-\r
-/**\r
- * This function is used to register another function which will be\r
- * executed at each 9 bits reception. WARNING : it uses the\r
- * same internal pointer that the 8 bits event, so be carreful to \r
- * unregister 8 bits events when doing 9 bits and vice versa.\r
- */\r
-void uart_register_rx_9bits_event(uint8_t num, void (*f)(int));\r
-\r
-/* funcs for use with fdevopen (avrlibc > 1.4.0) */\r
-int uart0_dev_send_nowait(char c, FILE* f);\r
-int uart0_dev_send(char c, FILE* f);\r
-int uart0_dev_recv_nowait(FILE* f);\r
-int uart0_dev_recv(FILE* f);\r
-\r
-int uart1_dev_send_nowait(char c, FILE* f);\r
-int uart1_dev_send(char c, FILE* f);\r
-int uart1_dev_recv_nowait(FILE* f);\r
-int uart1_dev_recv(FILE* f);\r
-\r
-int uart2_dev_send_nowait(char c, FILE* f);\r
-int uart2_dev_send(char c, FILE* f);\r
-int uart2_dev_recv_nowait(FILE* f);\r
-int uart2_dev_recv(FILE* f);\r
-\r
-int uart3_dev_send_nowait(char c, FILE* f);\r
-int uart3_dev_send(char c, FILE* f);\r
-int uart3_dev_recv_nowait(FILE* f);\r
-int uart3_dev_recv(FILE* f);\r
-\r
-\r
-#endif /* _UART_H_ */\r
-\r
/* .... same for uart 1, 2, 3 ... */\r
\r
/*\r
- * UART2 definitions\r
+ * UART1 definitions\r
*/\r
\r
-/* compile uart2 fonctions, undefine it to pass compilation */\r
-#define UART2_COMPILE\r
+/* compile uart1 fonctions, undefine it to pass compilation */\r
+#define UART1_COMPILE\r
\r
-/* enable uart2 if == 1, disable if == 0 */\r
-#define UART2_ENABLED 1\r
+/* enable uart1 if == 1, disable if == 0 */\r
+#define UART1_ENABLED 1\r
\r
-/* enable uart2 interrupts if == 1, disable if == 0 */\r
-#define UART2_INTERRUPT_ENABLED 1\r
+/* enable uart1 interrupts if == 1, disable if == 0 */\r
+#define UART1_INTERRUPT_ENABLED 1\r
\r
-#define UART2_BAUDRATE 57600\r
+#define UART1_BAUDRATE 57600\r
\r
/*\r
* if you enable this, the maximum baudrate you can reach is\r
* higher, but the precision is lower.\r
*/\r
-#define UART2_USE_DOUBLE_SPEED 1\r
+#define UART1_USE_DOUBLE_SPEED 1\r
\r
-#define UART2_RX_FIFO_SIZE 64\r
-#define UART2_TX_FIFO_SIZE 127\r
-#define UART2_NBITS 8\r
+#define UART1_RX_FIFO_SIZE 64\r
+#define UART1_TX_FIFO_SIZE 127\r
+#define UART1_NBITS 8\r
\r
-#define UART2_PARITY UART_PARTITY_NONE\r
+#define UART1_PARITY UART_PARTITY_NONE\r
\r
-#define UART2_STOP_BIT UART_STOP_BITS_1\r
+#define UART1_STOP_BIT UART_STOP_BITS_1\r
\r
/* .... same for uart 1, 2, 3 ... */\r
\r
+++ /dev/null
-/* \r
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)\r
- * \r
- * This program is free software; you can redistribute it and/or modify\r
- * it under the terms of the GNU General Public License as published by\r
- * the Free Software Foundation; either version 2 of the License, or\r
- * (at your option) any later version.\r
- *\r
- * This program is distributed in the hope that it will be useful,\r
- * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
- * GNU General Public License for more details.\r
- *\r
- * You should have received a copy of the GNU General Public License\r
- * along with this program; if not, write to the Free Software\r
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
- *\r
- * Revision : $Id: uart_defs.h,v 1.2.4.13 2009-06-29 20:28:27 zer0 Exp $\r
- *\r
- */\r
-\r
-/* Olivier MATZ, Droids-corp 2004 - 2006\r
- * Uart specific definitions\r
- */\r
-\r
-#ifndef _UART_DEFS_H_\r
-#define _UART_DEFS_H_\r
-\r
-#define UART_PARTITY_NONE 0\r
-#define UART_PARTITY_ODD 1\r
-#define UART_PARTITY_EVEN 2\r
-\r
-#define UART_STOP_BITS_1 0\r
-#define UART_STOP_BITS_2 1\r
-\r
-#if (defined UDR3)\r
-#define UART_HW_NUM 4\r
-#elif (defined UDR2)\r
-#define UART_HW_NUM 3\r
-#elif (defined UDR1)\r
-#define UART_HW_NUM 2\r
-#else /* assume 1 uart */\r
-#define UART_HW_NUM 1\r
-#endif\r
-\r
-\r
-/* For arch with only one UART, we consider that UART0 = UART */\r
-#if !defined(SIG_UART0_DATA) && !defined(SIG_USART0_DATA)\r
-#if defined SIG_UART_DATA\r
-#define SIG_UART0_DATA SIG_UART_DATA\r
-#elif defined SIG_USART_DATA\r
-#define SIG_UART0_DATA SIG_USART_DATA\r
-#endif\r
-#endif\r
-\r
-#if !defined(SIG_UART0_RECV) && !defined(SIG_USART0_RECV)\r
-#if defined SIG_UART_RECV\r
-#define SIG_UART0_RECV SIG_UART_RECV\r
-#elif defined SIG_USART_RECV\r
-#define SIG_UART0_RECV SIG_USART_RECV\r
-#endif\r
-#endif\r
-\r
-#if !defined(UDR0) && defined(UDR)\r
-#define UDR0 UDR\r
-#endif\r
-#ifndef UCSR0A\r
-#define UCSR0A UCSRA\r
-#endif\r
-#ifndef UCSR0B\r
-#define UCSR0B UCSRB\r
-#endif\r
-#ifndef UCSR0C\r
-#define UCSR0C UCSRC\r
-#endif\r
-#ifndef UBRR0L\r
-#define UBRR0L UBRRL\r
-#endif\r
-#ifndef UBRR0H\r
-#define UBRR0H UBRRH\r
-#endif\r
-#if !defined(U2X) && defined(U2X0)\r
-#define U2X U2X0\r
-#endif\r
-#if !defined(UCSZ0) && defined(UCSZ00)\r
-#define UCSZ0 UCSZ00\r
-#endif\r
-#if !defined(UCSZ1) && defined(UCSZ01)\r
-#define UCSZ1 UCSZ01\r
-#endif\r
-#if !defined(UCSZ2) && defined(UCSZ02)\r
-#define UCSZ2 UCSZ02\r
-#endif\r
-#if !defined(UPM0) && defined(UPM00)\r
-#define UPM0 UPM00\r
-#endif\r
-#if !defined(UPM1) && defined(UPM01)\r
-#define UPM1 UPM01\r
-#endif\r
-#if !defined(USBS) && defined(USBS0)\r
-#define USBS USBS0\r
-#endif\r
-#if !defined(TXEN) && defined(TXEN0)\r
-#define TXEN TXEN0\r
-#endif\r
-#if !defined(TXCIE) && defined(TXCIE0)\r
-#define TXCIE TXCIE0\r
-#endif\r
-#if !defined(RXEN) && defined(RXEN0)\r
-#define RXEN RXEN0\r
-#endif\r
-#if !defined(RXCIE) && defined(RXCIE0)\r
-#define RXCIE RXCIE0\r
-#endif\r
-#if !defined(TXC) && defined(TXC0)\r
-#define TXC TXC0\r
-#endif\r
-#if !defined(RXC) && defined(RXC0)\r
-#define RXC RXC0\r
-#endif\r
-#if !defined(RXB8) && defined(RXB80)\r
-#define RXB8 RXB80\r
-#endif\r
-#if !defined(UDRIE) && defined(UDRIE0)\r
-#define UDRIE UDRIE0\r
-#endif\r
-#if !defined(UDRE) && defined(UDRE0)\r
-#define UDRE UDRE0\r
-#endif\r
-#if !defined(U2X) && defined(U2X1)\r
-#define U2X U2X1\r
-#endif\r
-#if !defined(UCSZ1) && defined(UCSZ10)\r
-#define UCSZ0 UCSZ10\r
-#endif\r
-#if !defined(UCSZ1) && defined(UCSZ11)\r
-#define UCSZ1 UCSZ11\r
-#endif\r
-#if !defined(UCSZ2) && defined(UCSZ12)\r
-#define UCSZ2 UCSZ12\r
-#endif\r
-#if !defined(UPM1) && defined(UPM10)\r
-#define UPM0 UPM10\r
-#endif\r
-#if !defined(UPM1) && defined(UPM11)\r
-#define UPM1 UPM11\r
-#endif\r
-#if !defined(USBS) && defined(USBS1)\r
-#define USBS USBS1\r
-#endif\r
-#if !defined(TXEN) && defined(TXEN1)\r
-#define TXEN TXEN1\r
-#endif\r
-#if !defined(TXCIE) && defined(TXCIE1)\r
-#define TXCIE TXCIE1\r
-#endif\r
-#if !defined(RXEN) && defined(RXEN1)\r
-#define RXEN RXEN1\r
-#endif\r
-#if !defined(RXCIE) && defined(RXCIE1)\r
-#define RXCIE RXCIE1\r
-#endif\r
-#if !defined(TXC) && defined(TXC1)\r
-#define TXC TXC1\r
-#endif\r
-#if !defined(RXC) && defined(RXC1)\r
-#define RXC RXC1\r
-#endif\r
-#if !defined(RXB8) && defined(RXB81)\r
-#define RXB8 RXB81\r
-#endif\r
-#if !defined(UDRIE) && defined(UDRIE1)\r
-#define UDRIE UDRIE1\r
-#endif\r
-#if !defined(UDRIE) && defined(UDRIE1)\r
-#define UDRIE UDRIE1\r
-#endif\r
-#if !defined(UDRE) && defined(UDRE1)\r
-#define UDRE UDRE1\r
-#endif\r
-\r
-/* makes functions more generic, we associate USR and UCR with UCSRA\r
- * and UCSRB, respectively */\r
-#if ( ! defined UCSRA ) && ( defined USR )\r
-#define UCSRA USR\r
-#endif\r
-\r
-#if ( ! defined UCSRB ) && ( defined UCR )\r
-#define UCSRB UCR\r
-#endif\r
-\r
-/* UBRR is UBRRL */\r
-#ifndef UBRRL\r
-#define UBRRL UBRR\r
-#endif\r
-\r
-\r
-/* workaround for libc incomplete headers when using CAN AVR\r
- * (avr/iocanxx.h): USART is valid.\r
- * see http://savannah.nongnu.org/bugs/?18964\r
- */\r
-#if defined (__AVR_AT90CAN128__) || defined (__AVR_AT90CAN64__) || defined (__AVR_AT90CAN32__)\r
-\r
-#ifndef SIG_USART0_RECV\r
-#define SIG_USART0_RECV SIG_UART0_RECV\r
-#define SIG_USART1_RECV SIG_UART1_RECV\r
-#define SIG_USART0_DATA SIG_UART0_DATA\r
-#define SIG_USART1_DATA SIG_UART1_DATA\r
-#define SIG_USART0_TRANS SIG_UART0_TRANS\r
-#define SIG_USART1_TRANS SIG_UART1_TRANS\r
-#endif\r
-\r
-#endif\r
-\r
-\r
-/* if the signal USART is defined, the uC has a USART. */\r
-#if ( defined SIG_USART0_RECV ) || ( defined SIG_USART_RECV )\r
-#define UART_IS_USART 1\r
-#elif (defined USART_UDRE_vect) || (defined USART_TXC_vect) || (defined USART_RXC_vect)\r
-#define UART_IS_USART 1\r
-#elif (defined USART1_UDRE_vect) || (defined USART1_TXC_vect) || (defined USART1_RXC_vect)\r
-#define UART_IS_USART 1\r
-#else\r
-#define UART_IS_USART 0\r
-#endif\r
-\r
-/* if the U2X macro is defined, the uC has the U2X option. */\r
-#ifdef U2X\r
-#define UART_HAS_U2X 1\r
-#else\r
-#define UART_HAS_U2X 0\r
-#endif\r
-\r
-#endif //_UART_DEFS_H_\r
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: uart_dev_io.c,v 1.1.2.2 2009-04-07 20:00:47 zer0 Exp $
- *
- */
-
-/* Olivier MATZ, Droids-corp 2004 - 2009 */
-
-#include <uart.h>
-#include <uart_defs.h>
-#include <uart_private.h>
-
-#ifdef UART0_COMPILE
-int uart0_dev_send_nowait(char c, __attribute__((unused)) FILE *f)
-{
- return uart_send_nowait(0, c);
-}
-
-int uart0_dev_send(char c, __attribute__((unused)) FILE *f)
-{
- return uart_send(0, c);
-}
-
-int uart0_dev_recv_nowait(__attribute__((unused)) FILE *f)
-{
- return uart_recv_nowait(0);
-}
-
-int uart0_dev_recv(__attribute__((unused)) FILE *f)
-{
- return uart_recv(0);
-}
-#endif
-
-#ifdef UART1_COMPILE
-int uart1_dev_send_nowait(char c, __attribute__((unused)) FILE *f)
-{
- return uart_send_nowait(1, c);
-}
-
-int uart1_dev_send(char c, __attribute__((unused)) FILE *f)
-{
- return uart_send(1, c);
-}
-
-int uart1_dev_recv_nowait(__attribute__((unused)) FILE *f)
-{
- return uart_recv_nowait(1);
-}
-
-int uart1_dev_recv(__attribute__((unused)) FILE *f)
-{
- return uart_recv(1);
-}
-#endif
-
-#ifdef UART2_COMPILE
-int uart2_dev_send_nowait(char c, __attribute__((unused)) FILE *f)
-{
- return uart_send_nowait(2, c);
-}
-
-int uart2_dev_send(char c, __attribute__((unused)) FILE *f)
-{
- return uart_send(2, c);
-}
-
-int uart2_dev_recv_nowait(__attribute__((unused)) FILE *f)
-{
- return uart_recv_nowait(2);
-}
-
-int uart2_dev_recv(__attribute__((unused)) FILE *f)
-{
- return uart_recv(2);
-}
-#endif
-
-#ifdef UART3_COMPILE
-int uart3_dev_send_nowait(char c, __attribute__((unused)) FILE *f)
-{
- return uart_send_nowait(3, c);
-}
-
-int uart3_dev_send(char c, __attribute__((unused)) FILE *f)
-{
- return uart_send(3, c);
-}
-
-int uart3_dev_recv_nowait(__attribute__((unused)) FILE *f)
-{
- return uart_recv_nowait(3);
-}
-
-int uart3_dev_recv(__attribute__((unused)) FILE *f)
-{
- return uart_recv(3);
-}
-#endif
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: uart_errors.h,v 1.5.6.1 2006-11-26 21:06:02 zer0 Exp $
- *
- */
-
-/* Droids-corp 2004 - Zer0
- * Errors of the uart module
- */
-
-/** \file uart.c
- * \brief Errors of the UART module.
- *
- * \todo None
- *
- * \test None
- */
-
-
-/* check if uart configuration is correct at compilation time */
-#ifndef UART_IS_USART
-#if (UART0_PARITY == UART_PARTITY_ODD) || (UART0_PARITY == UART_PARTITY_EVEN)
-#error Currently this module does not support parity if your uC has no USART
-#endif
-
-#if (UART0_STOP_BIT == 2)
-#error Currently this module does not support another stop bit if your uC has no USART
-#endif
-
-#if (UART0_NBITS < 8)
-#error Currently this module does not support 5/6/7 bits frames if your uC has no USART
-#endif
-#endif // !UART_USART
-
-
-/* check if uart configuration is correct */
-#if !defined(UART_USART) && defined(UART_DOUBLE) // is this possible ??
-#if (UART1_PARITY == UART_PARTITY_ODD) || (UART1_PARITY == UART_PARTITY_EVEN)
-#error Currently this module does not support parity if your uC has no USART
-#endif
-
-#if (UART1_STOP_BIT == 2)
-#error Currently this module does not support another stop bit if your uC has no USART
-#endif
-
-#if (UART1_NBITS < 8)
-#error Currently this module does not support 5/6/7 bits frames if your uC has no USART
-#endif
-#endif // !UART_USART && UART_DOUBLE
-
-
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: uart_events.c,v 1.1.2.1 2008-12-27 16:29:08 zer0 Exp $
- *
- */
-
-/* Olivier MATZ, Droids-corp 2004 - 2009 */
-
-#include <uart.h>
-#include <uart_defs.h>
-#include <uart_private.h>
-
-/* This function is used to register another function which will be */
-/* executed at each byte transmission. */
-void uart_register_tx_event(uint8_t num, void (*f)(char))
-{
- uint8_t flags;
- if (num >= UART_HW_NUM)
- return;
- IRQ_LOCK(flags);
- tx_event[num] = f;
- IRQ_UNLOCK(flags);
-}
-
-/* This function is used to register another function which will be */
-/* executed at each byte reception */
-void uart_register_rx_event(uint8_t num, void (*f)(char))
-{
- uint8_t flags;
- if (num >= UART_HW_NUM)
- return;
- IRQ_LOCK(flags);
- rx_event[num] = f;
- IRQ_UNLOCK(flags);
-}
-
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: uart_getconf.c,v 1.1.2.3 2009-02-20 20:16:09 zer0 Exp $
- *
- */
-
-/* Olivier MATZ, Droids-corp 2004 - 2007 */
-
-#include <uart.h>
-#include <uart_defs.h>
-#include <uart_private.h>
-
-#if UART_IS_USART
-
-static inline uint8_t get_ucsrc(uint8_t num)
-{
-#ifdef URSEL
- uint8_t tmp;
- /* on some uC, reading UCSRxC is a bit tricky */
- switch(num) {
-#ifdef UART0_COMPILE
- case 0:
- tmp = UBRR0H;
- tmp = UCSR0C;
- break;
-#endif
-#ifdef UART1_COMPILE
- case 1:
- tmp = UBRR1H;
- tmp = UCSR1C;
- break;
-#endif
-#ifdef UART2_COMPILE
- case 2:
- tmp = UBRR2H;
- tmp = UCSR2C;
- break;
-#endif
-#ifdef UART3_COMPILE
- case 3:
- tmp = UBRR3H;
- tmp = UCSR3C;
- break;
-#endif
- default:
- tmp = 0;
- break;
- }
- return tmp;
-#else
- return *uart_regs[num].ucsrc;
-#endif /* URSEL */
-}
-
-/* return number of bits in current conf. Intr must be disabled. */
-uint8_t uart_getconf_nbits(uint8_t num)
-{
- uint8_t nbits;
-
- nbits = (get_ucsrc(num) >> UCSZ0) & 0x03;
-#ifdef CONFIG_MODULE_UART_9BITS
- if (*uart_regs[num].ucsrb & (1 << UCSZ2))
- nbits += 4;
-#endif
- nbits += 5;
- return nbits;
-}
-
-#else /* UART_IS_USART */
-
-/* return number of bits in current conf */
-uint8_t uart_getconf_nbits(uint8_t num)
-{
-#ifdef CONFIG_MODULE_UART_9BITS
- if (*uart_regs[num].ucsrb & (uint8_t)(1 << CHR9))
- return 8;
- else
- return 9;
-#else
- return 8;
-#endif
-}
-
-#endif /* UART_IS_USART */
-
-
-#if UART_IS_USART
-
-/* return number of bits in current conf */
-static inline uint16_t uart_get_baudreg(uint8_t num)
-{
- return ((uint16_t)*uart_regs[num].ubrrh << 8) |
- (uint16_t)*uart_regs[num].ubrrl;
-}
-
-#else /* UART_IS_USART */
-
-/* return number of bits in current conf */
-static inline uint16_t uart_get_baudreg(uint8_t num)
-{
- return (uint16_t)*uart_regs[num].ubrrl;
-}
-
-#endif /* UART_IS_USART */
-
-
-/* get the running uart configurtion */
-void uart_getconf(uint8_t num, struct uart_config *u)
-{
- uint8_t tmp;
- uint8_t flags;
-
- IRQ_LOCK(flags);
-
- /* XXX */
- /* enabled if RXEN is set */
- if (*uart_regs[num].ucsrb & (1 << RXEN))
- u->enabled = 1;
- else
- u->enabled = 0;
-
- /* intrp enabled if RXCIE is set */
- if (*uart_regs[num].ucsrb & (1 << RXCIE))
- u->intr_enabled = 1;
- else
- u->intr_enabled = 0;
-
- /* use double speed */
- if (UART_HAS_U2X && (*uart_regs[num].ucsra & (1 << U2X)))
- u->use_double_speed = 1;
- else
- u->use_double_speed = 0;
-
-
- /* parity */
- if (UART_IS_USART) {
- tmp = get_ucsrc(num) & ((1 << UPM1) | (1 << UPM0));
- if (tmp == ((1 << UPM1) | (1 << UPM0)))
- u->parity = UART_PARTITY_ODD;
- else if (tmp == (1 << UPM1))
- u->parity = UART_PARTITY_EVEN;
- else
- u->parity = UART_PARTITY_NONE;
- }
- else {
- u->parity = UART_PARTITY_NONE;
- }
-
- /* stop_bits */
- if (UART_IS_USART && (get_ucsrc(num) & (1 << USBS))) {
- u->stop_bits = UART_STOP_BITS_2;
- }
- else {
- u->stop_bits = UART_STOP_BITS_1;
- }
-
- /* nbits */
- u->nbits = uart_getconf_nbits(num);
- u->baudrate = (F_CPU / ((uart_get_baudreg(num)+1) * 16)) ;
-
- IRQ_UNLOCK(flags);
-}
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: uart_host.c,v 1.3.4.3 2008-12-27 16:29:08 zer0 Exp $
- *
- */
-
-/* Olivier MATZ, Droids-corp 2004 - 2009 */
-
-#include <uart.h>
-#include <uart_private.h>
-
-#include <fcntl.h>
-
-/* this file os a stub for host */
-
-void uart_init(void)
-{
-}
-
-/* global vars are initialized to 0 (NULL) */
-event *rx_event[UART_HW_NUM];
-event *tx_event[UART_HW_NUM];
-
-void uart_host_rx_event(char c)
-{
- /* only one uart */
- if (rx_event[0])
- rx_event[0](c);
-}
-
-void uart_host_tx_event(char c)
-{
- /* only one uart */
- if (tx_event[0])
- tx_event[0](c);
-}
-
-int8_t uart_setconf(uint8_t num, struct uart_config *u)
-{
- /* XXX todo */
- return 0;
-}
-
-void uart_getconf(uint8_t num, struct uart_config *u)
-{
- return;
-}
-
-int uart_recv(uint8_t num)
-{
- fcntl(0, F_SETFL, 0);
- return getchar();
-}
-
-int uart_recv_nowait(uint8_t num)
-{
- fcntl(0, F_SETFL, O_NONBLOCK);
- return getchar();
-}
-
-int uart_send_nowait(uint8_t num, char c)
-{
- return putchar(c);
-}
-
-int uart_send(uint8_t num, char c)
-{
- return putchar(c);
-}
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: uart_host.c,v 1.3.4.3 2008-12-27 16:29:08 zer0 Exp $
- *
- */
-
-/* Olivier MATZ, Droids-corp 2004 - 2010 */
-
-void uart_host_rx_event(char c);
-void uart_host_tx_event(char c);
+++ /dev/null
-/* \r
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)\r
- * \r
- * This program is free software; you can redistribute it and/or modify\r
- * it under the terms of the GNU General Public License as published by\r
- * the Free Software Foundation; either version 2 of the License, or\r
- * (at your option) any later version.\r
- *\r
- * This program is distributed in the hope that it will be useful,\r
- * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
- * GNU General Public License for more details.\r
- *\r
- * You should have received a copy of the GNU General Public License\r
- * along with this program; if not, write to the Free Software\r
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
- *\r
- * Revision : $Id: uart_private.h,v 1.1.2.5 2009-01-03 16:24:50 zer0 Exp $\r
- *\r
- */\r
-\r
-/* Olivier MATZ, Droids-corp 2004 - 2009 */\r
-\r
-#ifndef _UART_PRIVATE_H_\r
-#define _UART_PRIVATE_H_\r
-\r
-#include <aversive.h>\r
-#include <aversive/list.h>\r
-\r
-#include <uart.h>\r
-#include <uart_defs.h>\r
-#include <uart_config.h>\r
-\r
-typedef volatile uint8_t *uart_reg_t;\r
-\r
-struct regs {\r
- uart_reg_t udr;\r
- uart_reg_t ucsra;\r
- uart_reg_t ucsrb;\r
- uart_reg_t ucsrc;\r
- uart_reg_t ubrrl;\r
- uart_reg_t ubrrh;\r
-};\r
-\r
-const struct regs uart_regs[UART_HW_NUM];\r
-\r
-typedef void (event)(char);\r
-typedef void (event_9bits)(int);\r
-\r
-extern event *rx_event[UART_HW_NUM];\r
-extern event *tx_event[UART_HW_NUM];\r
-\r
-void uart_send_next_char(uint8_t num);\r
-int8_t uart_setconf(uint8_t num, struct uart_config *u);\r
-\r
-static inline char uart_get_udr(uint8_t num)\r
-{\r
- return *uart_regs[num].udr;\r
-}\r
-\r
-static inline void uart_set_udr(uint8_t num, char c)\r
-{\r
- *uart_regs[num].udr = c;\r
- /* tx event function. We suppose interrupts are already\r
- * locked, so no pb with tx_event pointer */\r
- if (tx_event[num])\r
- tx_event[num](c);\r
-}\r
-\r
-#ifdef CONFIG_MODULE_UART_9BITS\r
-static inline int uart_get_udr_9bits(uint8_t num)\r
-{\r
- int val = *uart_regs[num].udr;\r
- val |= (*uart_regs[num].ucsrb & ((1 << RXB8) ? 0x100 : 0));\r
- return val;\r
-}\r
-\r
-static inline void uart_set_udr_9bits(uint8_t num, int c)\r
-{\r
- if (c & 0x100 )\r
- *uart_regs[num].ucsrb |= (1 << RXB8);\r
- else\r
- *uart_regs[num].ucsrb &= ~(1 << RXB8);\r
- *uart_regs[num].udr = c;\r
-\r
- /* tx event function. We suppose interrupts are already\r
- * locked, so no pb with tx_event pointer */\r
- if (tx_event[num])\r
- ((event_9bits *)tx_event[num])(c);\r
-}\r
-#endif /* CONFIG_MODULE_UART_9BITS */\r
-\r
-#endif /* _UART_PRIVATE_H_ */\r
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: uart_recv.c,v 1.1.2.1 2008-12-27 16:29:08 zer0 Exp $
- *
- */
-
-/* Olivier MATZ, Droids-corp 2004 - 2009 */
-
-#include <uart.h>
-#include <uart_defs.h>
-#include <uart_private.h>
-
-/* get a char from the receive fifo */
-int uart_recv(uint8_t num)
-{
- int elt = 0;
- while ( (elt = uart_recv_nowait(num)) == -1 );
- return elt;
-}
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: uart_recv9.c,v 1.1.2.1 2008-12-27 16:29:08 zer0 Exp $
- *
- */
-
-/* Olivier MATZ, Droids-corp 2004 - 2009 */
-
-#include <uart.h>
-#include <uart_defs.h>
-#include <uart_private.h>
-
-/* get a char from the receive fifo */
-int uart_9bits_recv(uint8_t num)
-{
- int elt = 0;
- while ( (elt = uart_9bits_recv_nowait(num)) == -1 );
- return elt;
-}
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: uart_recv9_nowait.c,v 1.1.2.1 2008-12-27 16:29:08 zer0 Exp $
- *
- */
-
-/* Olivier MATZ, Droids-corp 2004 - 2009 */
-
-#include <uart.h>
-#include <uart_defs.h>
-#include <uart_private.h>
-
-/* get a char from the receive fifo */
-int uart_9bits_recv_nowait(uint8_t num)
-{
- char elt = 0;
- uint8_t flags;
-
- /* if interrupt mode is off, we have to check the status
- * register */
- if (!(*uart_regs[num].ucsrb & (1 << RXCIE))) {
- if ( !(*uart_regs[num].ucsra & (1 << RXC)) )
- return -1;
- return uart_get_udr_9bits(num);
- }
- /* else check the fifo */
- else {
- IRQ_LOCK(flags);
- if( CIRBUF_GET_LEN(&g_rx_fifo[num]) >= 2) {
- cirbuf_get_buf_tail(&g_rx_fifo[num], (char *)&elt, 2);
- cirbuf_del_buf_tail(&g_rx_fifo[num], 2);
- IRQ_UNLOCK(flags);
- return (int)elt;
- }
- IRQ_UNLOCK(flags);
- return -1;
- }
-}
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: uart_recv_nowait.c,v 1.1.2.1 2008-12-27 16:29:08 zer0 Exp $
- *
- */
-
-/* Olivier MATZ, Droids-corp 2004 - 2009 */
-
-#include <uart.h>
-#include <uart_defs.h>
-#include <uart_private.h>
-
-/* get a char from the receive fifo */
-int uart_recv_nowait(uint8_t num)
-{
- char elt = 0;
- uint8_t flags;
-
- /* if interrupt mode is off, we have to check the status
- * register */
- if (!(*uart_regs[num].ucsrb & (1 << RXCIE))) {
- if ( !(*uart_regs[num].ucsra & (1 << RXC)) )
- return -1;
- return uart_get_udr(num);
- }
- /* else check the fifo */
- else {
- IRQ_LOCK(flags);
- if( !CIRBUF_IS_EMPTY(&g_rx_fifo[num]) ) {
- elt = cirbuf_get_tail(&g_rx_fifo[num]);
- cirbuf_del_tail(&g_rx_fifo[num]);
- IRQ_UNLOCK(flags);
- return (int)elt;
- }
- IRQ_UNLOCK(flags);
- return -1;
- }
-}
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: uart_send.c,v 1.1.2.1 2008-12-27 16:29:08 zer0 Exp $
- *
- */
-
-/* Olivier MATZ, Droids-corp 2004 - 2009 */
-
-#include <uart.h>
-#include <uart_defs.h>
-#include <uart_private.h>
-
-int uart_send(uint8_t num, char c)
-{
- /* if cannot send the char */
- if (uart_send_nowait(num, c) == -1) {
-
- /* if irq lock are masked and interrupt mode is on, we
- * have to poll the status register */
- if (GLOBAL_IRQ_ARE_MASKED() && (*uart_regs[num].ucsrb & (1 << RXCIE)) ) {
- while( !(*uart_regs[num].ucsra & (1 << UDRE)) );
- /* send the next char in the fifo to free a
- * place */
- uart_send_next_char(num);
- cirbuf_add_head(&g_tx_fifo[num], c);
- }
- else {
- /* if irq are not locked, we can loop to emit */
- while(uart_send_nowait(num, c) == -1);
- }
- }
- return 0;
-}
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: uart_send9.c,v 1.1.2.1 2008-12-27 16:29:08 zer0 Exp $
- *
- */
-
-/* Olivier MATZ, Droids-corp 2004 - 2009 */
-
-#include <uart.h>
-#include <uart_defs.h>
-#include <uart_private.h>
-
-int uart_send_9bits(uint8_t num, int c)
-{
- /* if cannot send the char */
- if (uart_send_9bits_nowait(num, c) == -1) {
-
- /* if irq lock are masked and interrupt mode is on, we
- * have to poll the status register */
- if (GLOBAL_IRQ_ARE_MASKED() && (*uart_regs[num].ucsrb & (1 << RXCIE)) ) {
- while( !(*uart_regs[num].ucsra & (1 << UDRE)) );
- /* send the next char in the fifo to free two
- * places */
- uart_send_next_char(num);
- cirbuf_add_buf_head(&g_tx_fifo[num], (char *)&c, 2);
- }
- else {
- /* if irq are not locked, we can loop to emit */
- while(uart_send_9bits_nowait(num, c) == -1);
- }
- }
- return 0;
-}
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: uart_send9_nowait.c,v 1.1.2.2 2008-12-27 16:50:01 zer0 Exp $
- *
- */
-
-/* Olivier MATZ, Droids-corp 2004 - 2009 */
-
-#include <uart.h>
-#include <uart_defs.h>
-#include <uart_private.h>
-
-int uart_send_9bits_nowait(uint8_t num, int c)
-{
- uint8_t flags;
- IRQ_LOCK(flags);
-
- /* if tx intrp are disabled (RXCIE is 0) */
- if ( !(*uart_regs[num].ucsrb & (1 << RXCIE )) ) {
- /* we have to poll the status register before xmit */
- if (*uart_regs[num].ucsra & (1<<UDRE)) {
- uart_set_udr_9bits(c);
- IRQ_UNLOCK(flags);
- return 0;
- }
- else {
- IRQ_UNLOCK(flags);
- return -1;
- }
- }
-
- /* the fifo must have 2 free places */
- if( CIRBUF_GET_FREELEN(&g_tx_fifo) < 2) {
- IRQ_UNLOCK(flags);
- return -1;
- }
-
- /* uart is ready to send */
- if (CIRBUF_IS_EMPTY(&g_tx_fifo[num]) &&
- *uart_regs[num].ucsra & (1<<UDRE)) {
- uart_set_udr_9bits(c);
- sbi(*uart_regs[num].ucsrb, UDRIE); /* XXX */
- }
- else { /* not ready, put char in fifo */
- cirbuf_add_buf_head(&g_tx_fifo, (char *)&c, 2);
- }
-
- IRQ_UNLOCK(flags);
- return 0;
-}
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: uart_send_nowait.c,v 1.1.2.2 2008-12-27 16:50:01 zer0 Exp $
- *
- */
-
-/* Olivier MATZ, Droids-corp 2004 - 2009 */
-
-#include <uart.h>
-#include <uart_defs.h>
-#include <uart_private.h>
-
-
-/* send a char, or put it in the fifo if uart is not ready. Return -1
- * if fifo is full */
-int uart_send_nowait(uint8_t num, char c)
-{
- uint8_t flags;
-
- IRQ_LOCK(flags);
-
- /* if uart intrp mode is disabled (note that we look rx */
- /* intrp -- RXCIE is 0) */
- if ( !(*uart_regs[num].ucsrb & (1 << RXCIE )) ) {
- /* we have to poll the status register before xmit */
- if (*uart_regs[num].ucsra & (1<<UDRE)) {
- uart_set_udr(num, c);
- IRQ_UNLOCK(flags);
- return 0;
- }
- else {
- IRQ_UNLOCK(flags);
- return -1;
- }
- }
-
- if (CIRBUF_IS_FULL(&g_tx_fifo[num])) {
- IRQ_UNLOCK(flags);
- return -1;
- }
-
- /* uart is ready to send */
- if (CIRBUF_IS_EMPTY(&g_tx_fifo[num]) &&
- *uart_regs[num].ucsra & (1<<UDRE)) {
- uart_set_udr(num, c);
- sbi(*uart_regs[num].ucsrb, UDRIE); /* XXX */
- }
- else { /* not ready, put char in fifo */
- cirbuf_add_head(&g_tx_fifo[num], c);
- }
-
- IRQ_UNLOCK(flags);
- return 0;
-}
+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2005)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: uart_setconf.c,v 1.1.2.3 2009-01-03 16:24:50 zer0 Exp $
- *
- */
-
-/* Olivier MATZ, Droids-corp 2004 - 2009 */
-
-#include <uart.h>
-#include <uart_defs.h>
-#include <uart_private.h>
-
-/** The emission fifo of uart */
-#ifdef UART0_COMPILE
-char g_tx0_buf[UART0_TX_FIFO_SIZE];
-char g_rx0_buf[UART0_RX_FIFO_SIZE];
-#endif
-#ifdef UART1_COMPILE
-char g_tx1_buf[UART1_TX_FIFO_SIZE];
-char g_rx1_buf[UART1_RX_FIFO_SIZE];
-#endif
-#ifdef UART2_COMPILE
-char g_tx2_buf[UART2_TX_FIFO_SIZE];
-char g_rx2_buf[UART2_RX_FIFO_SIZE];
-#endif
-#ifdef UART3_COMPILE
-char g_tx3_buf[UART3_TX_FIFO_SIZE];
-char g_rx3_buf[UART3_RX_FIFO_SIZE];
-#endif
-
-#if UART_IS_USART
-
-static int8_t uart_set_nbits_parity(uint8_t num, struct uart_config * u)
-{
- uint8_t ucsrc = 0;
-
- /* number of bit in the frame */
-#ifdef CONFIG_MODULE_UART_9BITS
- if (u->nbits < 5 || u->nbits > 9) {
- return ENOTSUP;
- }
-#else
- if (u->nbits < 5 || u->nbits > 8) {
- return ENOTSUP;
- }
-#endif
-
- ucsrc |= ( ((u->nbits - 5) & 0x03) << UCSZ0 );
-#ifdef CONFIG_MODULE_UART_9BITS
- if (u->nbits == 9)
- *uart_regs[num].ucsrb |= (1 << UCSZ2);
- else
-#endif
- *uart_regs[num].ucsrb &= ~(1 << UCSZ2);
-
- /* parity */
- if (u->parity == UART_PARTITY_ODD)
- ucsrc |= ((1 << UPM0) | (1 << UPM1));
- else if (u->parity == UART_PARTITY_EVEN)
- ucsrc |= (1 << UPM1);
- else if (u->parity != UART_PARTITY_NONE) {
- return EINVAL;
- }
-
- /* nb of stop bits */
- if (u->stop_bits == UART_STOP_BITS_2)
- ucsrc |= (1 << USBS);
- else if (u->stop_bits != UART_STOP_BITS_1)
- return EINVAL;
-
-#ifdef URSEL
- /* some uC use a special bit URSEL to access to UCSRC */
- ucsrc |= (1<<URSEL);
-#endif
- *uart_regs[num].ucsrc = ucsrc;
-
- return ESUCCESS;
-}
-
-#else /* UART_IS_USART */
-
-static int8_t uart_set_nbits_parity(int8_t num, struct uart_config * u)
-{
- /* number of bit in the frame */
- if (u->nbits == 8)
- *uart_regs[num].ucsrb &= ~(1 << CHR9);
-#ifdef CONFIG_MODULE_UART_9BITS
- else if (u->nbits == 9)
- *uart_regs[num].ucsrb |= (1 << CHR9);
-#endif
- else
- return ENOTSUP;
-
- /* parity and stop */
- if (u->parity != UART_PARTITY_NONE ||
- u->stop_bits != UART_STOP_BITS_1) {
- return ENOTSUP;
- }
-
- return ESUCCESS;
-}
-#endif /* UART_IS_USART */
-
-
-#if UART_IS_USART
-
-static int8_t uart_set_baudreg(uint8_t num, uint16_t baudreg)
-{
- uint8_t lo, hi;
-
- /* set msb bit of hi to 0 (useful fot uC with URSEL, and not
- * important for the others because the baudreg will never be
- * as big */
- lo = (uint8_t)baudreg;
- hi = (uint8_t)(baudreg>>8) & 0x7F;
-
- *uart_regs[num].ubrrl = lo;
- *uart_regs[num].ubrrh = hi;
-
- return ESUCCESS;
-}
-
-#else /* UART_IS_USART */
-
-static int8_t uart_set_baudreg(uint8_t num, uint16_t baudreg)
-{
- uint8_t lo, hi;
-
- lo=(uint8_t)baudreg;
- hi=(uint8_t)(baudreg>>8);
-
- if (hi != 0)
- return EINVAL;
- *uart_regs[num].ubrrl = lo;
-
- return ESUCCESS;
-}
-#endif /* UART_IS_USART */
-
-/* configuration from uart_config.h */
-#define UART_SET_STATICCONF(x) \
- u->enabled = UART##x##_ENABLED; \
- u->intr_enabled = UART##x##_INTERRUPT_ENABLED; \
- u->use_double_speed = UART##x##_USE_DOUBLE_SPEED; \
- u->parity = UART##x##_PARITY; \
- u->stop_bits = UART##x##_STOP_BIT; \
- u->nbits = UART##x##_NBITS; \
- u->baudrate = UART##x##_BAUDRATE; \
- break
-
-int8_t uart_setconf(uint8_t num, struct uart_config *u)
-{
- uint8_t ret = ESUCCESS;
- uint16_t baudrate_reg;
- struct uart_config static_conf;
- uint8_t flags;
-
- IRQ_LOCK(flags);
-
- /* static configuration */
- if (!u) {
- u = &static_conf;
- switch (num) {
-#ifdef UART0_COMPILE
- case 0:
- UART_SET_STATICCONF(0);
-#endif
-#ifdef UART1_COMPILE
- case 1:
- UART_SET_STATICCONF(1);
-#endif
-#ifdef UART2_COMPILE
- case 2:
- UART_SET_STATICCONF(2);
-#endif
-#ifdef UART3_COMPILE
- case 3:
- UART_SET_STATICCONF(3);
-#endif
- default:
- ret = EINVAL;
- goto out;
- }
- }
-
- /* wait xmit finished (UDRE = 1) */
- while( !(*uart_regs[num].ucsra & (1<<UDRE)) );
-
- switch (num) {
-#ifdef UART0_COMPILE
- case 0:
- cirbuf_init(&g_tx_fifo[0], g_tx0_buf, 0, UART0_TX_FIFO_SIZE);
- cirbuf_init(&g_rx_fifo[0], g_rx0_buf, 0, UART0_RX_FIFO_SIZE);
- break;
-#endif
-#ifdef UART1_COMPILE
- case 1:
- cirbuf_init(&g_tx_fifo[1], g_tx1_buf, 0, UART1_TX_FIFO_SIZE);
- cirbuf_init(&g_rx_fifo[1], g_rx1_buf, 0, UART1_RX_FIFO_SIZE);
- break;
-#endif
-#ifdef UART2_COMPILE
- case 2:
- cirbuf_init(&g_tx_fifo[2], g_tx2_buf, 0, UART2_TX_FIFO_SIZE);
- cirbuf_init(&g_rx_fifo[2], g_rx2_buf, 0, UART2_RX_FIFO_SIZE);
- break;
-#endif
-#ifdef UART3_COMPILE
- case 3:
- cirbuf_init(&g_tx_fifo[3], g_tx3_buf, 0, UART3_TX_FIFO_SIZE);
- cirbuf_init(&g_rx_fifo[3], g_rx3_buf, 0, UART3_RX_FIFO_SIZE);
- break;
-#endif
- default:
- ret = EINVAL;
- goto out;
- }
- *uart_regs[num].ucsra = 0;
-
- if (u->enabled)
- *uart_regs[num].ucsrb = ((1 << TXEN) | (1 << RXEN));
- else {
- *uart_regs[num].ucsrb = 0;
- goto out; /* no more conf */
- }
-
- /* we only enable recv interrupt, the xmit intrpt will be
- * enabled in the xmit function */
- if (u->intr_enabled)
- *uart_regs[num].ucsrb |= (1 << RXCIE);
-
- if (UART_HAS_U2X) { /* if u2x is supported */
- if (u->use_double_speed) /* u2x is enabled */
- *uart_regs[num].ucsra |= (1 << U2X);
- else
- *uart_regs[num].ucsra &= ~(1 << U2X);
- }
- else if (u->use_double_speed) {
- ret = ENOTSUP;
- goto out;
- }
-
- uart_set_nbits_parity(num, u);
-
- /* baudrate */
- if(u->use_double_speed)
- baudrate_reg = (F_CPU / (u->baudrate*8l)) - 1;
- else
- baudrate_reg = (F_CPU / (u->baudrate*16l)) - 1;
-
- uart_set_baudreg(num, baudrate_reg);
-
- /* exit */
- out:
- IRQ_UNLOCK(flags);
- return ret;
-}
+++ /dev/null
-/*
- * Copyright Droids Corporation (2007)
- * Olivier MATZ <zer0@droids-corp.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: vt100.c,v 1.1.2.1 2008-01-05 22:46:28 zer0 Exp $
- *
- *
- */
-
-#include <stdlib.h>
-#include <stdio.h>
-#include <string.h>
-#include <stdarg.h>
-#include <ctype.h>
-
-#include <aversive/pgmspace.h>
-
-#include "vt100.h"
-
-static const prog_char cmd0[] = vt100_up_arr;
-static const prog_char cmd1[] = vt100_down_arr;
-static const prog_char cmd2[] = vt100_right_arr;
-static const prog_char cmd3[] = vt100_left_arr;
-static const prog_char cmd4[] = "\177";
-static const prog_char cmd5[] = "\n";
-static const prog_char cmd6[] = "\001";
-static const prog_char cmd7[] = "\005";
-static const prog_char cmd8[] = "\013";
-static const prog_char cmd9[] = "\031";
-static const prog_char cmd10[] = "\003";
-static const prog_char cmd11[] = "\006";
-static const prog_char cmd12[] = "\002";
-static const prog_char cmd13[] = vt100_suppr;
-static const prog_char cmd14[] = vt100_tab;
-static const prog_char cmd15[] = "\004";
-static const prog_char cmd16[] = "\014";
-static const prog_char cmd17[] = "\r";
-static const prog_char cmd18[] = "\033\177";
-static const prog_char cmd19[] = vt100_word_left;
-static const prog_char cmd20[] = vt100_word_right;
-static const prog_char cmd21[] = "?";
-
-const prog_char * vt100_commands[] PROGMEM = {
- cmd0, cmd1, cmd2, cmd3, cmd4, cmd5, cmd6, cmd7,
- cmd8, cmd9, cmd10, cmd11, cmd12, cmd13, cmd14,
- cmd15, cmd16, cmd17, cmd18, cmd19, cmd20,
- cmd21,
-};
-
-void
-vt100_init(struct vt100 * vt)
-{
- vt->state = VT100_INIT;
-}
-
-
-static int8_t
-match_command(char * buf, uint8_t size)
-{
- const prog_char * cmd;
- uint8_t i = 0;
-
- for (i=0 ; i<sizeof(vt100_commands)/sizeof(const prog_char *) ; i++) {
-#ifdef HOST_VERSION
- cmd = *(vt100_commands + i);
-#else
- cmd = (const prog_char *) pgm_read_word (vt100_commands + i);
-#endif
-
- if (size == strlen_P(cmd) &&
- !strncmp_P(buf, cmd, strlen_P(cmd))) {
- return i;
- }
- }
-
- return -1;
-}
-
-int8_t
-vt100_parser(struct vt100 *vt, char ch)
-{
- uint8_t size;
- uint8_t c = (uint8_t) ch;
-
- if (vt->bufpos > VT100_BUF_SIZE) {
- vt->state = VT100_INIT;
- vt->bufpos = 0;
- }
-
- vt->buf[vt->bufpos++] = c;
- size = vt->bufpos;
-
- switch (vt->state) {
- case VT100_INIT:
- if (c == 033) {
- vt->state = VT100_ESCAPE;
- }
- else {
- vt->bufpos = 0;
- goto match_command;
- }
- break;
-
- case VT100_ESCAPE:
- if (c == 0133) {
- vt->state = VT100_ESCAPE_CSI;
- }
- else if (c >= 060 && c <= 0177) { /* XXX 0177 ? */
- vt->bufpos = 0;
- vt->state = VT100_INIT;
- goto match_command;
- }
- break;
-
- case VT100_ESCAPE_CSI:
- if (c >= 0100 && c <= 0176) {
- vt->bufpos = 0;
- vt->state = VT100_INIT;
- goto match_command;
- }
- break;
-
- default:
- vt->bufpos = 0;
- break;
- }
-
- return -2;
-
- match_command:
- return match_command(vt->buf, size);
-}
+++ /dev/null
-/*
- * Copyright Droids Corporation (2007)
- * Olivier MATZ <zer0@droids-corp.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id: vt100.h,v 1.1.2.2 2009-04-07 20:01:16 zer0 Exp $
- *
- *
- */
-
-#ifndef _VT100_H_
-#define _VT100_H_
-
-#define vt100_bell "\007"
-#define vt100_bs "\010"
-#define vt100_bs_clear "\010 \010"
-#define vt100_tab "\011"
-#define vt100_crnl "\012\015"
-#define vt100_clear_right "\033[0K"
-#define vt100_clear_left "\033[1K"
-#define vt100_clear_down "\033[0J"
-#define vt100_clear_up "\033[1J"
-#define vt100_clear_line "\033[2K"
-#define vt100_clear_screen "\033[2J"
-#define vt100_up_arr "\033\133\101"
-#define vt100_down_arr "\033\133\102"
-#define vt100_right_arr "\033\133\103"
-#define vt100_left_arr "\033\133\104"
-#define vt100_multi_right "\033\133%uC"
-#define vt100_multi_left "\033\133%uD"
-#define vt100_suppr "\033\133\063\176"
-#define vt100_home "\033M\033E"
-#define vt100_word_left "\033\142"
-#define vt100_word_right "\033\146"
-
-
-/* Result of parsing : it must be synchronized with vt100_commands[]
- * in vt100.c */
-#define KEY_UP_ARR 0
-#define KEY_DOWN_ARR 1
-#define KEY_RIGHT_ARR 2
-#define KEY_LEFT_ARR 3
-#define KEY_BKSPACE 4
-#define KEY_RETURN 5
-#define KEY_CTRL_A 6
-#define KEY_CTRL_E 7
-#define KEY_CTRL_K 8
-#define KEY_CTRL_Y 9
-#define KEY_CTRL_C 10
-#define KEY_CTRL_F 11
-#define KEY_CTRL_B 12
-#define KEY_SUPPR 13
-#define KEY_TAB 14
-#define KEY_CTRL_D 15
-#define KEY_CTRL_L 16
-#define KEY_RETURN2 17
-#define KEY_META_BKSPACE 18
-#define KEY_WLEFT 19
-#define KEY_WRIGHT 20
-#define KEY_HELP 21
-
-extern const prog_char * vt100_commands[] PROGMEM;
-
-enum vt100_parser_state {
- VT100_INIT,
- VT100_ESCAPE,
- VT100_ESCAPE_CSI,
-};
-
-#define VT100_BUF_SIZE 8
-struct vt100 {
- uint8_t bufpos;
- char buf[VT100_BUF_SIZE];
- enum vt100_parser_state state;
-};
-
-/**
- * Init
- */
-void vt100_init(struct vt100 *vt);
-
-/**
- * Input a new character.
- * Return -1 if the character is not part of a control sequence
- * Return -2 if c is not the last char of a control sequence
- * Else return the index in vt100_commands[]
- */
-int8_t vt100_parser(struct vt100 *vt, char c);
-
-#endif
#include "xbee_atcmd.h"
-prog_char atcmd0_name[] = "WR";
-prog_char atcmd0_desc[] = "write-param";
-prog_char atcmd0_help[] =
+static const char PROGMEM atcmd0_name[] = "WR";
+static const char PROGMEM atcmd0_desc[] = "write-param";
+static const char PROGMEM atcmd0_help[] =
"Write parameter values to non-volatile memory.";
-prog_char atcmd1_name[] = "RE";
-prog_char atcmd1_desc[] = "restore-defaults";
-prog_char atcmd1_help[] =
+static const char PROGMEM atcmd1_name[] = "RE";
+static const char PROGMEM atcmd1_desc[] = "restore-defaults";
+static const char PROGMEM atcmd1_help[] =
"Restore module parameters to factory defaults.";
-prog_char atcmd2_name[] = "FR";
-prog_char atcmd2_desc[] = "soft-reset";
-prog_char atcmd2_help[] =
+static const char PROGMEM atcmd2_name[] = "FR";
+static const char PROGMEM atcmd2_desc[] = "soft-reset";
+static const char PROGMEM atcmd2_help[] =
"Software Reset. Responds with 'OK' then performs a "
"reset 100ms later.";
-prog_char atcmd3_name[] = "AC";
-prog_char atcmd3_desc[] = "apply-changes";
-prog_char atcmd3_help[] =
+static const char PROGMEM atcmd3_name[] = "AC";
+static const char PROGMEM atcmd3_desc[] = "apply-changes";
+static const char PROGMEM atcmd3_help[] =
"Apply Changes without exiting command mode.";
-prog_char atcmd4_name[] = "R1";
-prog_char atcmd4_desc[] = "restore-compiled";
-prog_char atcmd4_help[] =
+static const char PROGMEM atcmd4_name[] = "R1";
+static const char PROGMEM atcmd4_desc[] = "restore-compiled";
+static const char PROGMEM atcmd4_help[] =
"Restore module parameters to compiled defaults.";
-prog_char atcmd5_name[] = "VL";
-prog_char atcmd5_desc[] = "version-long";
-prog_char atcmd5_help[] =
+static const char PROGMEM atcmd5_name[] = "VL";
+static const char PROGMEM atcmd5_desc[] = "version-long";
+static const char PROGMEM atcmd5_help[] =
"Shows detailed version information including"
"application build date and time.";
-prog_char atcmd6_name[] = "DH";
-prog_char atcmd6_desc[] = "dst-addr-high";
-prog_char atcmd6_help[] =
+static const char PROGMEM atcmd6_name[] = "DH";
+static const char PROGMEM atcmd6_desc[] = "dst-addr-high";
+static const char PROGMEM atcmd6_help[] =
"Upper 32 bits of the 64-bit destination address (0 "
"to 0xFFFFFFFF, default is 0x0000FFFF).";
-prog_char atcmd7_name[] = "DL";
-prog_char atcmd7_desc[] = "dst-addr-low";
-prog_char atcmd7_help[] =
+static const char PROGMEM atcmd7_name[] = "DL";
+static const char PROGMEM atcmd7_desc[] = "dst-addr-low";
+static const char PROGMEM atcmd7_help[] =
"Lower 32 bits of the 64-bit destination address (0 "
"to 0xFFFFFFFF, default is 0x0000FFFF).";
-prog_char atcmd8_name[] = "DD";
-prog_char atcmd8_desc[] = "device-type-id";
-prog_char atcmd8_help[] =
+static const char PROGMEM atcmd8_name[] = "DD";
+static const char PROGMEM atcmd8_desc[] = "device-type-id";
+static const char PROGMEM atcmd8_help[] =
"Device Type Identifier, it can be used to differentiate "
"multiple XBee-based products (0 to 0xFFFFFFFF, read-only, "
"default is 0x40000).";
-prog_char atcmd9_name[] = "SH";
-prog_char atcmd9_desc[] = "src-addr-high";
-prog_char atcmd9_help[] =
+static const char PROGMEM atcmd9_name[] = "SH";
+static const char PROGMEM atcmd9_desc[] = "src-addr-high";
+static const char PROGMEM atcmd9_help[] =
"Upper 32 bits of the 64-bit source address (read-only).";
-prog_char atcmd10_name[] = "SL";
-prog_char atcmd10_desc[] = "src-addr-low";
-prog_char atcmd10_help[] =
+static const char PROGMEM atcmd10_name[] = "SL";
+static const char PROGMEM atcmd10_desc[] = "src-addr-low";
+static const char PROGMEM atcmd10_help[] =
"Lower 32 bits of the 64-bit source address (read-only).";
-prog_char atcmd11_name[] = "SE";
-prog_char atcmd11_desc[] = "src-endpoint";
-prog_char atcmd11_help[] =
+static const char PROGMEM atcmd11_name[] = "SE";
+static const char PROGMEM atcmd11_desc[] = "src-endpoint";
+static const char PROGMEM atcmd11_help[] =
"The application source endpoint for all data transmissions "
"(0 to 0xFF, default is 0xE8).";
-prog_char atcmd12_name[] = "DE";
-prog_char atcmd12_desc[] = "dst-endpoint";
-prog_char atcmd12_help[] =
+static const char PROGMEM atcmd12_name[] = "DE";
+static const char PROGMEM atcmd12_desc[] = "dst-endpoint";
+static const char PROGMEM atcmd12_help[] =
"The application destination endpoint for all data "
"transmissions (0 to 0xFF, default is 0xE8).";
-prog_char atcmd13_name[] = "CI";
-prog_char atcmd13_desc[] = "cluster-id";
-prog_char atcmd13_help[] =
+static const char PROGMEM atcmd13_name[] = "CI";
+static const char PROGMEM atcmd13_desc[] = "cluster-id";
+static const char PROGMEM atcmd13_help[] =
"Cluster Identifier for all data transmissions (0 to 0xFFFF, "
"default is 0x11).";
-prog_char atcmd14_name[] = "NP";
-prog_char atcmd14_desc[] = "max-rf-payload";
-prog_char atcmd14_help[] =
+static const char PROGMEM atcmd14_name[] = "NP";
+static const char PROGMEM atcmd14_desc[] = "max-rf-payload";
+static const char PROGMEM atcmd14_help[] =
"Maximum RF Payload Bytes that can be sent in a unicast "
"transmission based on the current configuration (0 to "
"0xFFFF).";
-prog_char atcmd15_name[] = "CE";
-prog_char atcmd15_desc[] = "coord-end-device";
-prog_char atcmd15_help[] =
+static const char PROGMEM atcmd15_name[] = "CE";
+static const char PROGMEM atcmd15_desc[] = "coord-end-device";
+static const char PROGMEM atcmd15_help[] =
"Coordinator/End Device, messaging mode of the module "
"(0 - Normal, 1 - Indirect coordinator, 2 - Polling, default "
"is 0).";
-prog_char atcmd16_name[] = "AP";
-prog_char atcmd16_desc[] = "api-mode";
-prog_char atcmd16_help[] =
+static const char PROGMEM atcmd16_name[] = "AP";
+static const char PROGMEM atcmd16_desc[] = "api-mode";
+static const char PROGMEM atcmd16_help[] =
"API mode (0 - off, 1 - on, 2 - on with escape sequences).";
-prog_char atcmd17_name[] = "AO";
-prog_char atcmd17_desc[] = "api-output-format";
-prog_char atcmd17_help[] =
+static const char PROGMEM atcmd17_name[] = "AO";
+static const char PROGMEM atcmd17_desc[] = "api-output-format";
+static const char PROGMEM atcmd17_help[] =
"API Output Format (0 - standard [0x90 for RX], 1 - explicit "
"addressing [0x91 for RX]).";
-prog_char atcmd18_name[] = "BD";
-prog_char atcmd18_desc[] = "baud-rate";
-prog_char atcmd18_help[] =
+static const char PROGMEM atcmd18_name[] = "BD";
+static const char PROGMEM atcmd18_desc[] = "baud-rate";
+static const char PROGMEM atcmd18_help[] =
"Baud rate of serial interface (0-8 select preset standard "
"rates, and 0x39 to 0x1c9c38 select baud rate).";
-prog_char atcmd19_name[] = "RO";
-prog_char atcmd19_desc[] = "packetization-timeout";
-prog_char atcmd19_help[] =
+static const char PROGMEM atcmd19_name[] = "RO";
+static const char PROGMEM atcmd19_desc[] = "packetization-timeout";
+static const char PROGMEM atcmd19_help[] =
"Packetization Timeout: the inter-character silence required "
"before packetization specified in character times (0 to 0xFF, "
"default is 3).";
-prog_char atcmd20_name[] = "FT";
-prog_char atcmd20_desc[] = "flow-control-thres";
-prog_char atcmd20_help[] =
+static const char PROGMEM atcmd20_name[] = "FT";
+static const char PROGMEM atcmd20_desc[] = "flow-control-thres";
+static const char PROGMEM atcmd20_help[] =
"Flow Control Threshhold. De-assert CTS and/or send XOFF when "
"FT bytes are in the UART receive buffer. Re-assert CTS when "
"less than FT - 16 bytes are in the UART receive buffer (0x11 "
"to 0xEE, default is 0xBE).";
-prog_char atcmd21_name[] = "NB";
-prog_char atcmd21_desc[] = "parity";
-prog_char atcmd21_help[] =
+static const char PROGMEM atcmd21_name[] = "NB";
+static const char PROGMEM atcmd21_desc[] = "parity";
+static const char PROGMEM atcmd21_help[] =
"Parity (0 - no parity, 1 - even parity, 2 - odd parity, 3 - "
"forced high parity, 4 - forced low parity). Default is 0.";
-prog_char atcmd22_name[] = "D7";
-prog_char atcmd22_desc[] = "dio7";
-prog_char atcmd22_help[] =
+static const char PROGMEM atcmd22_name[] = "D7";
+static const char PROGMEM atcmd22_desc[] = "dio7";
+static const char PROGMEM atcmd22_help[] =
"DIO7 Configuration (0 - unmonitored input, 1 - CTS, 3 - "
"digital input, 4 - digital output low, 5 - digital output "
"high, 6 - RS-485 low Tx, 7 - RS-485 high Tx). Default is "
"0.";
-prog_char atcmd23_name[] = "D6";
-prog_char atcmd23_desc[] = "dio6";
-prog_char atcmd23_help[] =
+static const char PROGMEM atcmd23_name[] = "D6";
+static const char PROGMEM atcmd23_desc[] = "dio6";
+static const char PROGMEM atcmd23_help[] =
"DIO6 Configuration (0 - unmonitored input, 1 - RTS, 3 - "
"digital input, 4 - digital output low, 5 - digital output "
"high). Default is 0.";
-prog_char atcmd24_name[] = "P0";
-prog_char atcmd24_desc[] = "dio10-pwm0";
-prog_char atcmd24_help[] =
+static const char PROGMEM atcmd24_name[] = "P0";
+static const char PROGMEM atcmd24_desc[] = "dio10-pwm0";
+static const char PROGMEM atcmd24_help[] =
"DIO10/PWM0 Configuration. (0 - unmonitored input, 1 - RSSI, 2 "
"- PWM0, 3 - digital input, 4 - digital output low, 5 - "
"digital output high). Default is 1.";
-prog_char atcmd25_name[] = "P1";
-prog_char atcmd25_desc[] = "dio11-pwm1";
-prog_char atcmd25_help[] =
+static const char PROGMEM atcmd25_name[] = "P1";
+static const char PROGMEM atcmd25_desc[] = "dio11-pwm1";
+static const char PROGMEM atcmd25_help[] =
"DIO11/PWM1 Configuration. (0 - unmonitored input, 2 "
"- PWM1, 3 - digital input, 4 - digital output low, 5 - "
"digital output high). Default is 0.";
-prog_char atcmd26_name[] = "P2";
-prog_char atcmd26_desc[] = "dio12";
-prog_char atcmd26_help[] =
+static const char PROGMEM atcmd26_name[] = "P2";
+static const char PROGMEM atcmd26_desc[] = "dio12";
+static const char PROGMEM atcmd26_help[] =
"DIO12 Configuration. (0 - unmonitored input, "
"3 - digital input, 4 - digital output low, 5 - "
"digital output high). Default is 0.";
-prog_char atcmd27_name[] = "RP";
-prog_char atcmd27_desc[] = "rssi-pwm";
-prog_char atcmd27_help[] =
+static const char PROGMEM atcmd27_name[] = "RP";
+static const char PROGMEM atcmd27_desc[] = "rssi-pwm";
+static const char PROGMEM atcmd27_help[] =
"Time RSSI signal will be output after last transmission. "
"When RP[] = 0xFF, output will always be on (0 - 0xFF, default "
"is 0x28[] = 4 seconds).";
-prog_char atcmd28_name[] = "1S";
-prog_char atcmd28_desc[] = "sensor-sample";
-prog_char atcmd28_help[] =
+static const char PROGMEM atcmd28_name[] = "1S";
+static const char PROGMEM atcmd28_desc[] = "sensor-sample";
+static const char PROGMEM atcmd28_help[] =
"Forces a sample to be taken on an XBee Sensor device.";
-prog_char atcmd29_name[] = "D0";
-prog_char atcmd29_desc[] = "dio0-ad0";
-prog_char atcmd29_help[] =
+static const char PROGMEM atcmd29_name[] = "D0";
+static const char PROGMEM atcmd29_desc[] = "dio0-ad0";
+static const char PROGMEM atcmd29_help[] =
"AD0/DIO0 Configuration. (0 - unmonitored input, 1 - "
"commission button enabled, 2 - analog input, 3 - digital "
"input, 4 - digital output low, 5 - digital output high). "
"Default is 1.";
-prog_char atcmd30_name[] = "D1";
-prog_char atcmd30_desc[] = "dio1-ad1";
-prog_char atcmd30_help[] =
+static const char PROGMEM atcmd30_name[] = "D1";
+static const char PROGMEM atcmd30_desc[] = "dio1-ad1";
+static const char PROGMEM atcmd30_help[] =
"AD1/DIO1 Configuration. (0 - unmonitored input, "
"2 - analog input, 3 - digital input, 4 - digital output "
"low, 5 - digital output high). Default is 0.";
-prog_char atcmd31_name[] = "D2";
-prog_char atcmd31_desc[] = "dio2-ad2";
-prog_char atcmd31_help[] =
+static const char PROGMEM atcmd31_name[] = "D2";
+static const char PROGMEM atcmd31_desc[] = "dio2-ad2";
+static const char PROGMEM atcmd31_help[] =
"AD2/DIO2 Configuration. (0 - unmonitored input, "
"2 - analog input, 3 - digital input, 4 - digital output "
"low, 5 - digital output high). Default is 0.";
-prog_char atcmd32_name[] = "D3";
-prog_char atcmd32_desc[] = "dio3-ad3";
-prog_char atcmd32_help[] =
+static const char PROGMEM atcmd32_name[] = "D3";
+static const char PROGMEM atcmd32_desc[] = "dio3-ad3";
+static const char PROGMEM atcmd32_help[] =
"AD3/DIO3 Configuration. (0 - unmonitored input, "
"2 - analog input, 3 - digital input, 4 - digital output "
"low, 5 - digital output high). Default is 0.";
-prog_char atcmd33_name[] = "D4";
-prog_char atcmd33_desc[] = "dio4-ad4";
-prog_char atcmd33_help[] =
+static const char PROGMEM atcmd33_name[] = "D4";
+static const char PROGMEM atcmd33_desc[] = "dio4-ad4";
+static const char PROGMEM atcmd33_help[] =
"AD4/DIO4 Configuration. (0 - unmonitored input, "
"2 - analog input, 3 - digital input, 4 - digital output "
"low, 5 - digital output high). Default is 0.";
-prog_char atcmd34_name[] = "D5";
-prog_char atcmd34_desc[] = "dio5-ad5";
-prog_char atcmd34_help[] =
+static const char PROGMEM atcmd34_name[] = "D5";
+static const char PROGMEM atcmd34_desc[] = "dio5-ad5";
+static const char PROGMEM atcmd34_help[] =
"AD4/DIO4 Configuration. (0 - unmonitored input, 1 - LED, "
"2 - analog input, 3 - digital input, 4 - digital output "
"low, 5 - digital output high). Default is 1.";
-prog_char atcmd35_name[] = "D8";
-prog_char atcmd35_desc[] = "dio8-sleep-rq";
-prog_char atcmd35_help[] =
+static const char PROGMEM atcmd35_name[] = "D8";
+static const char PROGMEM atcmd35_desc[] = "dio8-sleep-rq";
+static const char PROGMEM atcmd35_help[] =
"DIO8/SLEEP_RQ Configuration. (0 - unmonitored input, 1 - LED, "
"2 - analog input, 3 - digital input, 4 - digital output "
"low, 5 - digital output high). Default is 0. When used as "
"SLEEP_RQ, the D8 parameter should be configured in mode 0 "
"or 3.";
-prog_char atcmd36_name[] = "D9";
-prog_char atcmd36_desc[] = "dio9-on-sleep";
-prog_char atcmd36_help[] =
+static const char PROGMEM atcmd36_name[] = "D9";
+static const char PROGMEM atcmd36_desc[] = "dio9-on-sleep";
+static const char PROGMEM atcmd36_help[] =
"DIO9/ON_SLEEP Configuration. (0 - unmonitored input, 1 - "
"ON/SLEEP, 2 - analog input, 3 - digital input, 4 - digital "
"output low, 5 - digital output high). Default is ?.";
-prog_char atcmd37_name[] = "PR";
-prog_char atcmd37_desc[] = "pull-up-resistor";
-prog_char atcmd37_help[] =
+static const char PROGMEM atcmd37_name[] = "PR";
+static const char PROGMEM atcmd37_desc[] = "pull-up-resistor";
+static const char PROGMEM atcmd37_help[] =
"Pull-up Resistor. Bit field that configures the internal "
"pull-up resistors for the I/O lines (bit set = pull-up "
"enabled). Range is from 0 to 0x1FFF, default is 0x1FFF.";
-prog_char atcmd38_name[] = "M0";
-prog_char atcmd38_desc[] = "pwm0-out-level";
-prog_char atcmd38_help[] =
+static const char PROGMEM atcmd38_name[] = "M0";
+static const char PROGMEM atcmd38_desc[] = "pwm0-out-level";
+static const char PROGMEM atcmd38_help[] =
"PWM0 Output Level. The line should be configured as a PWM "
"output using the P0 command (0 to 0x3FF, default is 0).";
-prog_char atcmd39_name[] = "M1";
-prog_char atcmd39_desc[] = "pwm1-out-level";
-prog_char atcmd39_help[] =
+static const char PROGMEM atcmd39_name[] = "M1";
+static const char PROGMEM atcmd39_desc[] = "pwm1-out-level";
+static const char PROGMEM atcmd39_help[] =
"PWM1 Output Level. The line should be configured as a PWM "
"output using the P1 command (0 to 0x3FF, default is 0).";
-prog_char atcmd40_name[] = "LT";
-prog_char atcmd40_desc[] = "led-blink-time";
-prog_char atcmd40_help[] =
+static const char PROGMEM atcmd40_name[] = "LT";
+static const char PROGMEM atcmd40_desc[] = "led-blink-time";
+static const char PROGMEM atcmd40_help[] =
"Associate LED Blink Time (should be enabled through D5 ";
-prog_char atcmd41_name[] = "IS";
-prog_char atcmd41_desc[] = "force-sample";
-prog_char atcmd41_help[] =
+static const char PROGMEM atcmd41_name[] = "IS";
+static const char PROGMEM atcmd41_desc[] = "force-sample";
+static const char PROGMEM atcmd41_help[] =
"Forces a read of all enabled digital and "
"analog input lines.";
-prog_char atcmd42_name[] = "IC";
-prog_char atcmd42_desc[] = "digital-change-detect";
-prog_char atcmd42_help[] =
+static const char PROGMEM atcmd42_name[] = "IC";
+static const char PROGMEM atcmd42_desc[] = "digital-change-detect";
+static const char PROGMEM atcmd42_help[] =
"I/O Digital Change Detection. If a pin is enabled as a "
"digital input/output, the IC command can be used to "
"force an immediate I/O sample transmission when the DIO "
"state changes. IC is a bitmask, range is 0 to 0xFFFF, "
"default is 0";
-prog_char atcmd43_name[] = "IR";
-prog_char atcmd43_desc[] = "io-sample-rate";
-prog_char atcmd43_help[] =
+static const char PROGMEM atcmd43_name[] = "IR";
+static const char PROGMEM atcmd43_desc[] = "io-sample-rate";
+static const char PROGMEM atcmd43_help[] =
"IO Sample Rate for periodic sampling. If zero, periodic "
"sampling is disabled. Else the value is in milliseconds "
"(range 0 to 0xFFFF, default is 0).";
-prog_char atcmd44_name[] = "CB";
-prog_char atcmd44_desc[] = "comissioning-button";
-prog_char atcmd44_help[] =
+static const char PROGMEM atcmd44_name[] = "CB";
+static const char PROGMEM atcmd44_desc[] = "comissioning-button";
+static const char PROGMEM atcmd44_help[] =
"Commissioning Pushbutton, simulate commissioning button "
"in software. The parameter value should be set to the number "
"of button presses to be simulated (range is 0 to 4).";
-prog_char atcmd45_name[] = "VR";
-prog_char atcmd45_desc[] = "firmware-version";
-prog_char atcmd45_help[] =
+static const char PROGMEM atcmd45_name[] = "VR";
+static const char PROGMEM atcmd45_desc[] = "firmware-version";
+static const char PROGMEM atcmd45_help[] =
"Firmware version of the module (read only).";
-prog_char atcmd46_name[] = "HV";
-prog_char atcmd46_desc[] = "hardware-version";
-prog_char atcmd46_help[] =
+static const char PROGMEM atcmd46_name[] = "HV";
+static const char PROGMEM atcmd46_desc[] = "hardware-version";
+static const char PROGMEM atcmd46_help[] =
"Hardware version of the module (read only).";
-prog_char atcmd47_name[] = "CK";
-prog_char atcmd47_desc[] = "config-code";
-prog_char atcmd47_help[] =
+static const char PROGMEM atcmd47_name[] = "CK";
+static const char PROGMEM atcmd47_desc[] = "config-code";
+static const char PROGMEM atcmd47_help[] =
"Configuration Code, that can be used as a quick "
"check to determine if a node has been configured as "
"desired (read-only, 0-0xFFFFFFFF).";
-prog_char atcmd48_name[] = "ER";
-prog_char atcmd48_desc[] = "rf-errors";
-prog_char atcmd48_help[] =
+static const char PROGMEM atcmd48_name[] = "ER";
+static const char PROGMEM atcmd48_desc[] = "rf-errors";
+static const char PROGMEM atcmd48_help[] =
"Number of times a packet was received which contained errors "
"of some sort. Read-only, saturate at 0xFFFF.";
-prog_char atcmd49_name[] = "GD";
-prog_char atcmd49_desc[] = "good-packets";
-prog_char atcmd49_help[] =
+static const char PROGMEM atcmd49_name[] = "GD";
+static const char PROGMEM atcmd49_desc[] = "good-packets";
+static const char PROGMEM atcmd49_help[] =
"Number of good received frames. Read-only, saturate at "
"0xFFFF.";
-prog_char atcmd50_name[] = "RP";
-prog_char atcmd50_desc[] = "rssi-pwm-timer";
-prog_char atcmd50_help[] =
+static const char PROGMEM atcmd50_name[] = "RP";
+static const char PROGMEM atcmd50_desc[] = "rssi-pwm-timer";
+static const char PROGMEM atcmd50_help[] =
"RSSI PWM timer, the time in tenth of seconds that the RSSI "
"output indicating signal strength will remain active after "
"the last reception (1 to 0xff, default is 0x20 = 3.2 secs).";
-prog_char atcmd51_name[] = "TR";
-prog_char atcmd51_desc[] = "tx-errors";
-prog_char atcmd51_help[] =
+static const char PROGMEM atcmd51_name[] = "TR";
+static const char PROGMEM atcmd51_desc[] = "tx-errors";
+static const char PROGMEM atcmd51_help[] =
"Transmission Errors, the number of MAC frames that "
"exhaust MAC retries without ever receiving a MAC "
"acknowledgement message. Read-only, saturate at 0xFFFF.";
-prog_char atcmd52_name[] = "TP";
-prog_char atcmd52_desc[] = "temperature";
-prog_char atcmd52_help[] =
+static const char PROGMEM atcmd52_name[] = "TP";
+static const char PROGMEM atcmd52_desc[] = "temperature";
+static const char PROGMEM atcmd52_help[] =
"Temperature. Read module temperature in (tenths of ?) "
"Celsius. Negatives temperatures can be returned (read-only, "
"from 0xff74 [-140] to 0x0258 [600]).";
-prog_char atcmd53_name[] = "DB";
-prog_char atcmd53_desc[] = "rx-signal-strength";
-prog_char atcmd53_help[] =
+static const char PROGMEM atcmd53_name[] = "DB";
+static const char PROGMEM atcmd53_desc[] = "rx-signal-strength";
+static const char PROGMEM atcmd53_help[] =
"Received Signal Strength of the last received RF data "
"packet measured in -dBm. For example if DB returns 0x60, "
"then the RSSI of the last packet received was -96dBm "
"(read-only).";
-prog_char atcmd54_name[] = "DC";
-prog_char atcmd54_desc[] = "duty-cycle";
-prog_char atcmd54_help[] =
+static const char PROGMEM atcmd54_name[] = "DC";
+static const char PROGMEM atcmd54_desc[] = "duty-cycle";
+static const char PROGMEM atcmd54_help[] =
"Duty Cycle. Returns a current usage percentage of the "
"10% duty cycle measured over the period of 1 hour "
"(read-only, from 0 to 0x64).";
-prog_char atcmd55_name[] = "RC";
-prog_char atcmd55_desc[] = "rssi-for-channel";
-prog_char atcmd55_help[] =
+static const char PROGMEM atcmd55_name[] = "RC";
+static const char PROGMEM atcmd55_desc[] = "rssi-for-channel";
+static const char PROGMEM atcmd55_help[] =
"Reads the dBm level (RSSI) of the designated "
"channel.";
-prog_char atcmd56_name[] = "R#";
-prog_char atcmd56_desc[] = "reset-number";
-prog_char atcmd56_help[] =
+static const char PROGMEM atcmd56_name[] = "R#";
+static const char PROGMEM atcmd56_desc[] = "reset-number";
+static const char PROGMEM atcmd56_help[] =
"Tells the reason for the last module reset (0 - Power up "
"reset, 2 - Watchdog reset, 3 - Software reset, 4 - Reset "
"line reset, 5 - Brownout reset). Read-only.";
-prog_char atcmd57_name[] = "TA";
-prog_char atcmd57_desc[] = "tx-ack-errors";
-prog_char atcmd57_help[] =
+static const char PROGMEM atcmd57_name[] = "TA";
+static const char PROGMEM atcmd57_desc[] = "tx-ack-errors";
+static const char PROGMEM atcmd57_help[] =
"Transmit Acknowlegement Errors. Incremented once for "
"each failed ack retry (read-only, from 0 to 0xFFFF).";
-prog_char atcmd58_name[] = "%V";
-prog_char atcmd58_desc[] = "supply-voltage";
-prog_char atcmd58_help[] =
+static const char PROGMEM atcmd58_name[] = "%V";
+static const char PROGMEM atcmd58_desc[] = "supply-voltage";
+static const char PROGMEM atcmd58_help[] =
"Voltage on the Vcc pin in mV (read-only, from 0 to 0xF00).";
-prog_char atcmd59_name[] = "CT";
-prog_char atcmd59_desc[] = "cmd-mode-timeout";
-prog_char atcmd59_help[] =
+static const char PROGMEM atcmd59_name[] = "CT";
+static const char PROGMEM atcmd59_desc[] = "cmd-mode-timeout";
+static const char PROGMEM atcmd59_help[] =
"Command Mode Timeout: the period of inactivity (no valid "
"commands received) after which the RF module automatically "
"exits AT Command Mode and returns to Idle Mode (2 to 0x1770, "
"default is 0x64).";
-prog_char atcmd60_name[] = "CN";
-prog_char atcmd60_desc[] = "exit-cmd-mode";
-prog_char atcmd60_help[] =
+static const char PROGMEM atcmd60_name[] = "CN";
+static const char PROGMEM atcmd60_desc[] = "exit-cmd-mode";
+static const char PROGMEM atcmd60_help[] =
"Exit Command Mode.";
-prog_char atcmd61_name[] = "GT";
-prog_char atcmd61_desc[] = "guard-times";
-prog_char atcmd61_help[] =
+static const char PROGMEM atcmd61_name[] = "GT";
+static const char PROGMEM atcmd61_desc[] = "guard-times";
+static const char PROGMEM atcmd61_help[] =
"Guard Times: period of silence in ms before and after the "
"Command Sequence Characters of the AT Command Mode Sequence, "
"used to prevent inadvertent entrance into AT Command Mode "
"(0 to 0xFFFF, default is 0x3E8).";
-prog_char atcmd62_name[] = "CC";
-prog_char atcmd62_desc[] = "command-chars";
-prog_char atcmd62_help[] =
+static const char PROGMEM atcmd62_name[] = "CC";
+static const char PROGMEM atcmd62_desc[] = "command-chars";
+static const char PROGMEM atcmd62_help[] =
"Command Character used between guard times of the AT Command "
"Mode Sequence (0 to 0xFF, default is 0x2B).";
-prog_char atcmd63_name[] = "ID";
-prog_char atcmd63_desc[] = "network-id";
-prog_char atcmd63_help[] =
+static const char PROGMEM atcmd63_name[] = "ID";
+static const char PROGMEM atcmd63_desc[] = "network-id";
+static const char PROGMEM atcmd63_help[] =
"Network ID. Nodes must have the same network identifier "
"to communicate (0 to 0x7FFF, default is 0x7FFF).";
-prog_char atcmd64_name[] = "NT";
-prog_char atcmd64_desc[] = "ndisc-timeout";
-prog_char atcmd64_help[] =
+static const char PROGMEM atcmd64_name[] = "NT";
+static const char PROGMEM atcmd64_desc[] = "ndisc-timeout";
+static const char PROGMEM atcmd64_help[] =
"Node Discover Timeout, time in tenth of secs a node will "
"spend discovering other nodes when ND or DN is issued (0 "
"to 0xFC, default is 0x82).";
-prog_char atcmd65_name[] = "NI";
-prog_char atcmd65_desc[] = "node-id";
-prog_char atcmd65_help[] =
+static const char PROGMEM atcmd65_name[] = "NI";
+static const char PROGMEM atcmd65_desc[] = "node-id";
+static const char PROGMEM atcmd65_help[] =
"Node Identifier in printable ASCII characters. This string is "
"returned as part of the ATND (Network Discover) command. This "
"identifier is also used with the ATDN (Destination Node) "
"command. The string contains up to 20 byte ASCII string, "
"default is a space character.";
-prog_char atcmd66_name[] = "DN";
-prog_char atcmd66_desc[] = "disc-node";
-prog_char atcmd66_help[] = /* XXX */
+static const char PROGMEM atcmd66_name[] = "DN";
+static const char PROGMEM atcmd66_desc[] = "disc-node";
+static const char PROGMEM atcmd66_help[] = /* XXX */
"Resolves a Node Identifier string to a physical address "
"(case sensitive). 0xFFFE and the 64bits extended address are "
"returned.";
-prog_char atcmd67_name[] = "ND";
-prog_char atcmd67_desc[] = "network-discover";
-prog_char atcmd67_help[] = "Network Discovery, see doc"; /* XXX */
+static const char PROGMEM atcmd67_name[] = "ND";
+static const char PROGMEM atcmd67_desc[] = "network-discover";
+static const char PROGMEM atcmd67_help[] = "Network Discovery, see doc"; /* XXX */
-prog_char atcmd68_name[] = "NO";
-prog_char atcmd68_desc[] = "ndisc-options";
-prog_char atcmd68_help[] =
+static const char PROGMEM atcmd68_name[] = "NO";
+static const char PROGMEM atcmd68_desc[] = "ndisc-options";
+static const char PROGMEM atcmd68_help[] =
"Network Discovery Options, a bitfield value that changes the "
"behavior of the ND command (bit0 - Append DD value, bit1 - "
"Local device sends ND response frame when ND is issued). "
"Default is 0.";
-prog_char atcmd69_name[] = "EE";
-prog_char atcmd69_desc[] = "security enable";
-prog_char atcmd69_help[] =
+static const char PROGMEM atcmd69_name[] = "EE";
+static const char PROGMEM atcmd69_desc[] = "security enable";
+static const char PROGMEM atcmd69_help[] =
"Enable or disable 128-bit AES encryption (0 or 1, 0 is the "
"default).";
-prog_char atcmd70_name[] = "KY"; /* XXX */;
-prog_char atcmd70_desc[] = "security-key";
-prog_char atcmd70_help[] =
+static const char PROGMEM atcmd70_name[] = "KY"; /* XXX */;
+static const char PROGMEM atcmd70_desc[] = "security-key";
+static const char PROGMEM atcmd70_help[] =
"The 128bits security key (the command is write-only).";
-prog_char atcmd71_name[] = "MT";
-prog_char atcmd71_desc[] = "bcast-multi-xmit";
-prog_char atcmd71_help[] =
+static const char PROGMEM atcmd71_name[] = "MT";
+static const char PROGMEM atcmd71_desc[] = "bcast-multi-xmit";
+static const char PROGMEM atcmd71_help[] =
"Number of additional MAC-level broadcast transmissions. All "
"broadcast packets are transmitted MT+1 times to ensure "
"it is received (0 to 0xF, default is 3).";
-prog_char atcmd72_name[] = "RR";
-prog_char atcmd72_desc[] = "unicast-retries";
-prog_char atcmd72_help[] =
+static const char PROGMEM atcmd72_name[] = "RR";
+static const char PROGMEM atcmd72_desc[] = "unicast-retries";
+static const char PROGMEM atcmd72_help[] =
"Number of additional MAC-level packet delivery attempts for "
"unicast transactions. If RR is non-zero, packets sent from "
"the radio will request an acknowledgement, and can be resent "
"up to RR times if no acknowledgement is received. (0 to 0xF, "
"default is 10).";
-prog_char atcmd73_name[] = "PL";
-prog_char atcmd73_desc[] = "power-level";
-prog_char atcmd73_help[] =
+static const char PROGMEM atcmd73_name[] = "PL";
+static const char PROGMEM atcmd73_desc[] = "power-level";
+static const char PROGMEM atcmd73_help[] =
"Power Level of RF transmitter (0 - 1mW, 1 - 23mW, 2 - 100mW, "
"3 - 158 mW, 4 - 316 mW). Default is 4.";
-prog_char atcmd74_name[] = "SM";
-prog_char atcmd74_desc[] = "sleep-mode";
-prog_char atcmd74_help[] =
+static const char PROGMEM atcmd74_name[] = "SM";
+static const char PROGMEM atcmd74_desc[] = "sleep-mode";
+static const char PROGMEM atcmd74_help[] =
"Sleep Mode (0 - disabled, 1 - pin sleep, 4 - async cyclic "
"sleep, 5 - async cyclic sleep with pin wakeup). Default "
"is 0.";
-prog_char atcmd75_name[] = "SO";
-prog_char atcmd75_desc[] = "sleep-options";
-prog_char atcmd75_help[] =
+static const char PROGMEM atcmd75_name[] = "SO";
+static const char PROGMEM atcmd75_desc[] = "sleep-options";
+static const char PROGMEM atcmd75_help[] =
"Sleep Options bitmask (bit8 - always wake for ST time). "
"Default is 0.";
-prog_char atcmd76_name[] = "ST";
-prog_char atcmd76_desc[] = "wake-time";
-prog_char atcmd76_help[] =
+static const char PROGMEM atcmd76_name[] = "ST";
+static const char PROGMEM atcmd76_desc[] = "wake-time";
+static const char PROGMEM atcmd76_help[] =
"Wake Time: the amount of time in ms that the module will stay "
"awake after receiving RF or serial data (from 0x45 to "
"0x36EE80, default is 0x7D0 = 2 secs).";
-prog_char atcmd77_name[] = "SP";
-prog_char atcmd77_desc[] = "sleep-period";
-prog_char atcmd77_help[] =
+static const char PROGMEM atcmd77_name[] = "SP";
+static const char PROGMEM atcmd77_desc[] = "sleep-period";
+static const char PROGMEM atcmd77_help[] =
"Sleep Period: the amount of time in 10ms unit the module will "
"sleep per cycle. For a node operating as an Indirect "
"Messaging Coordinator, this command defines the amount of "
"The coordinator will hold the message for (2.5 * SP). Range "
"is from 1 to 1440000, default is 200 (2 secs).";
-prog_char atcmd78_name[] = "SN";
-prog_char atcmd78_desc[] = "num-sleep-periods";
-prog_char atcmd78_help[] =
+static const char PROGMEM atcmd78_name[] = "SN";
+static const char PROGMEM atcmd78_desc[] = "num-sleep-periods";
+static const char PROGMEM atcmd78_help[] =
"Number of Sleep Periods that must elapse between assertions "
"of the ON_SLEEP line during the wake time of asynchronous "
"cyclic sleep (1 to 0xFFFF, default is 1).";
-prog_char atcmd79_name[] = "WH";
-prog_char atcmd79_desc[] = "wake-host";
-prog_char atcmd79_help[] = "Wake Host time. If it is set to a non-zero value, it "
+static const char PROGMEM atcmd79_name[] = "WH";
+static const char PROGMEM atcmd79_desc[] = "wake-host";
+static const char PROGMEM atcmd79_help[] = "Wake Host time. If it is set to a non-zero value, it "
"specifies the time in ms that the device should allow after "
"waking from sleep before sending data out the UART or "
"transmitting an I/O sample. If serial characters are "
"received, the WH timer is stopped immediately. Range is "
"from 0 to 0xFFFF, default is 0.";
-struct xbee_atcmd_pgm xbee_atcmd_list[] = {
+const struct xbee_atcmd PROGMEM xbee_atcmd_list[] = {
{
/* "WR" */
atcmd0_name,
},
};
-struct xbee_atcmd_pgm *xbee_atcmd_lookup_name(const char *atcmd_str)
+const struct xbee_atcmd *xbee_atcmd_lookup_name(const char *atcmd_str)
{
- struct xbee_atcmd_pgm *cmd;
+ const struct xbee_atcmd *cmd;
struct xbee_atcmd copy;
for (cmd = &xbee_atcmd_list[0], memcpy_P(©, cmd, sizeof(copy));
return cmd;
}
-struct xbee_atcmd_pgm *xbee_atcmd_lookup_desc(const char *desc)
+const struct xbee_atcmd *xbee_atcmd_lookup_desc(const char *desc)
{
- struct xbee_atcmd_pgm *cmd;
+ const struct xbee_atcmd *cmd;
struct xbee_atcmd copy;
for (cmd = &xbee_atcmd_list[0], memcpy_P(©, cmd, sizeof(copy));
/* list of xbee at commands */
struct xbee_atcmd {
- prog_char *name;
- prog_char *desc;
+ PGM_P name;
+ PGM_P desc;
unsigned int flags;
- prog_char *help;
+ PGM_P help;
};
-struct xbee_atcmd_pgm {
- prog_char *name;
- prog_char *desc;
- unsigned int flags;
- prog_char *help;
-} PROGMEM;
-
-extern struct xbee_atcmd_pgm xbee_atcmd_list[];
+extern const struct xbee_atcmd PROGMEM xbee_atcmd_list[];
-struct xbee_atcmd_pgm *xbee_atcmd_lookup_name(const char *atcmd_str);
-struct xbee_atcmd_pgm *xbee_atcmd_lookup_desc(const char *desc);
+const struct xbee_atcmd *xbee_atcmd_lookup_name(const char *atcmd_str);
+const struct xbee_atcmd *xbee_atcmd_lookup_desc(const char *desc);
#endif /* _xBEE_ATCMD_H_ */
hdr.type = type;
hdr.id = channel_id;
- if (channel_id < 0 || channel_id >= XBEE_MAX_CHANNEL ||
+ if (channel_id >= XBEE_MAX_CHANNEL ||
dev->channel[channel_id].registered == 0) {
dev->stats.tx_invalid_channel ++;
return -1;
/* not enough data */
if (dev->frame_len < framelen)
continue;
- if (xbee_proto_parse_frame(dev) < 0)
+ if (xbee_proto_parse_frame(dev) < 0) {
;//XXX stats
+ }
dev->frame_len = 0;
}
}
/* protocol headers */
#define XBEE_DELIMITER 0x7E
-#define XBEE_MAX_FRAME_LEN 0x200
+#define XBEE_MAX_FRAME_LEN 0x40
struct xbee_hdr {
uint8_t delimiter;
git.droids-corp.org / protos / xbee-avr.git / commitdiff