net/sfc/base: move PF/VF config to ef10 NIC board config

Signed-off-by: Andy Moreton <amoreton@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>

diff --git a/drivers/net/sfc/base/ef10_nic.c b/drivers/net/sfc/base/ef10_nic.c
index c63aad8..c9ba41d 100644 (file)
--- a/drivers/net/sfc/base/ef10_nic.c
+++ b/drivers/net/sfc/base/ef10_nic.c
@@ -1549,6 +1549,8 @@ ef10_nic_board_cfg(
        efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
        efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
        uint32_t port;
+       uint32_t pf;
+       uint32_t vf;
        efx_rc_t rc;
 
        /* Get the (zero-based) MCDI port number */
@@ -1562,13 +1564,27 @@ ef10_nic_board_cfg(
                    &encp->enc_external_port)) != 0)
                goto fail2;
 
+       /*
+        * Get PCIe function number from firmware (used for
+        * per-function privilege and dynamic config info).
+        *  - PCIe PF: pf = PF number, vf = 0xffff.
+        *  - PCIe VF: pf = parent PF, vf = VF number.
+        */
+       if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
+               goto fail3;
+
+       encp->enc_pf = pf;
+       encp->enc_vf = vf;
+
        /* Get remaining controller-specific board config */
        if ((rc = enop->eno_board_cfg(enp)) != 0)
                if (rc != EACCES)
-                       goto fail3;
+                       goto fail4;
 
        return (0);
 
+fail4:
+       EFSYS_PROBE(fail4);
 fail3:
        EFSYS_PROBE(fail3);
 fail2:

diff --git a/drivers/net/sfc/base/hunt_nic.c b/drivers/net/sfc/base/hunt_nic.c
index 0b311b6..84fd198 100644 (file)
--- a/drivers/net/sfc/base/hunt_nic.c
+++ b/drivers/net/sfc/base/hunt_nic.c
@@ -81,8 +81,6 @@ hunt_board_cfg(
        uint32_t board_type = 0;
        ef10_link_state_t els;
        efx_port_t *epp = &(enp->en_port);
-       uint32_t pf;
-       uint32_t vf;
        uint32_t mask;
        uint32_t flags;
        uint32_t sysclk, dpcpu_clk;
@@ -100,18 +98,6 @@ hunt_board_cfg(
        EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K  == 8192);
        encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
 
-       /*
-        * Get PCIe function number from firmware (used for
-        * per-function privilege and dynamic config info).
-        *  - PCIe PF: pf = PF number, vf = 0xffff.
-        *  - PCIe VF: pf = parent PF, vf = VF number.
-        */
-       if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
-               goto fail1;
-
-       encp->enc_pf = pf;
-       encp->enc_vf = vf;
-
        /* MAC address for this function */
        if (EFX_PCI_FUNCTION_IS_PF(encp)) {
                rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
@@ -128,7 +114,7 @@ hunt_board_cfg(
                rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
        }
        if (rc != 0)
-               goto fail2;
+               goto fail1;
 
        EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
 
@@ -139,7 +125,7 @@ hunt_board_cfg(
                if (rc == EACCES)
                        board_type = 0;
                else
-                       goto fail3;
+                       goto fail2;
        }
 
        encp->enc_board_type = board_type;
@@ -147,11 +133,11 @@ hunt_board_cfg(
 
        /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
        if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
-               goto fail4;
+               goto fail3;
 
        /* Obtain the default PHY advertised capabilities */
        if ((rc = ef10_phy_get_link(enp, &els)) != 0)
-               goto fail5;
+               goto fail4;
        epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
        epp->ep_adv_cap_mask = els.els_adv_cap_mask;
 
@@ -182,7 +168,7 @@ hunt_board_cfg(
        else if ((rc == ENOTSUP) || (rc == ENOENT))
                encp->enc_bug35388_workaround = B_FALSE;
        else
-               goto fail6;
+               goto fail5;
 
        /*
         * If the bug41750 workaround is enabled, then do not test interrupts,
@@ -201,7 +187,7 @@ hunt_board_cfg(
        } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
                encp->enc_bug41750_workaround = B_FALSE;
        } else {
-               goto fail7;
+               goto fail6;
        }
        if (EFX_PCI_FUNCTION_IS_VF(encp)) {
                /* Interrupt testing does not work for VFs. See bug50084. */
@@ -239,12 +225,12 @@ hunt_board_cfg(
        } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
                encp->enc_bug26807_workaround = B_FALSE;
        } else {
-               goto fail8;
+               goto fail7;
        }
 
        /* Get clock frequencies (in MHz). */
        if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
-               goto fail9;
+               goto fail8;
 
        /*
         * The Huntington timer quantum is 1536 sysclk cycles, documented for
@@ -263,7 +249,7 @@ hunt_board_cfg(
 
        /* Check capabilities of running datapath firmware */
        if ((rc = ef10_get_datapath_caps(enp)) != 0)
-               goto fail10;
+               goto fail9;
 
        /* Alignment for receive packet DMA buffers */
        encp->enc_rx_buf_align_start = 1;
@@ -313,13 +299,13 @@ hunt_board_cfg(
         * can result in time-of-check/time-of-use bugs.
         */
        if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
-               goto fail11;
+               goto fail10;
        encp->enc_privilege_mask = mask;
 
        /* Get interrupt vector limits */
        if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
                if (EFX_PCI_FUNCTION_IS_PF(encp))
-                       goto fail12;
+                       goto fail11;
 
                /* Ignore error (cannot query vector limits from a VF). */
                base = 0;
@@ -335,7 +321,7 @@ hunt_board_cfg(
        encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
 
        if ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0)
-               goto fail13;
+               goto fail12;
        encp->enc_required_pcie_bandwidth_mbps = bandwidth;
 
        /* All Huntington devices have a PCIe Gen3, 8 lane connector */
@@ -343,8 +329,6 @@ hunt_board_cfg(
 
        return (0);
 
-fail13:
-       EFSYS_PROBE(fail13);
 fail12:
        EFSYS_PROBE(fail12);
 fail11:

diff --git a/drivers/net/sfc/base/medford2_nic.c b/drivers/net/sfc/base/medford2_nic.c
index 0b0f775..0989b93 100644 (file)
--- a/drivers/net/sfc/base/medford2_nic.c
+++ b/drivers/net/sfc/base/medford2_nic.c
@@ -53,8 +53,6 @@ medford2_board_cfg(
        uint32_t board_type = 0;
        ef10_link_state_t els;
        efx_port_t *epp = &(enp->en_port);
-       uint32_t pf;
-       uint32_t vf;
        uint32_t mask;
        uint32_t sysclk, dpcpu_clk;
        uint32_t base, nvec;
@@ -76,18 +74,6 @@ medford2_board_cfg(
        encp->enc_vi_window_shift = vi_window_shift;
 
 
-       /*
-        * Get PCIe function number from firmware (used for
-        * per-function privilege and dynamic config info).
-        *  - PCIe PF: pf = PF number, vf = 0xffff.
-        *  - PCIe VF: pf = parent PF, vf = VF number.
-        */
-       if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
-               goto fail2;
-
-       encp->enc_pf = pf;
-       encp->enc_vf = vf;
-
        /* MAC address for this function */
        if (EFX_PCI_FUNCTION_IS_PF(encp)) {
                rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
@@ -112,7 +98,7 @@ medford2_board_cfg(
                rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
        }
        if (rc != 0)
-               goto fail3;
+               goto fail2;
 
        EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
 
@@ -123,7 +109,7 @@ medford2_board_cfg(
                if (rc == EACCES)
                        board_type = 0;
                else
-                       goto fail4;
+                       goto fail3;
        }
 
        encp->enc_board_type = board_type;
@@ -131,11 +117,11 @@ medford2_board_cfg(
 
        /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
        if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
-               goto fail5;
+               goto fail4;
 
        /* Obtain the default PHY advertised capabilities */
        if ((rc = ef10_phy_get_link(enp, &els)) != 0)
-               goto fail6;
+               goto fail5;
        epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
        epp->ep_adv_cap_mask = els.els_adv_cap_mask;
 
@@ -179,11 +165,11 @@ medford2_board_cfg(
        else if ((rc == ENOTSUP) || (rc == ENOENT))
                encp->enc_bug61265_workaround = B_FALSE;
        else
-               goto fail7;
+               goto fail6;
 
        /* Get clock frequencies (in MHz). */
        if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
-               goto fail8;
+               goto fail7;
 
        /*
         * The Medford2 timer quantum is 1536 dpcpu_clk cycles, documented for
@@ -195,7 +181,7 @@ medford2_board_cfg(
 
        /* Check capabilities of running datapath firmware */
        if ((rc = ef10_get_datapath_caps(enp)) != 0)
-               goto fail9;
+               goto fail8;
 
        /* Alignment for receive packet DMA buffers */
        encp->enc_rx_buf_align_start = 1;
@@ -203,7 +189,7 @@ medford2_board_cfg(
        /* Get the RX DMA end padding alignment configuration */
        if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
                if (rc != EACCES)
-                       goto fail10;
+                       goto fail9;
 
                /* Assume largest tail padding size supported by hardware */
                end_padding = 256;
@@ -255,13 +241,13 @@ medford2_board_cfg(
         * can result in time-of-check/time-of-use bugs.
         */
        if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
-               goto fail11;
+               goto fail10;
        encp->enc_privilege_mask = mask;
 
        /* Get interrupt vector limits */
        if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
                if (EFX_PCI_FUNCTION_IS_PF(encp))
-                       goto fail12;
+                       goto fail11;
 
                /* Ignore error (cannot query vector limits from a VF). */
                base = 0;
@@ -284,14 +270,12 @@ medford2_board_cfg(
 
        rc = medford2_nic_get_required_pcie_bandwidth(enp, &bandwidth);
        if (rc != 0)
-               goto fail13;
+               goto fail12;
        encp->enc_required_pcie_bandwidth_mbps = bandwidth;
        encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
 
        return (0);
 
-fail13:
-       EFSYS_PROBE(fail13);
 fail12:
        EFSYS_PROBE(fail12);
 fail11:

diff --git a/drivers/net/sfc/base/medford_nic.c b/drivers/net/sfc/base/medford_nic.c
index cac5d29..01fab8f 100644 (file)
--- a/drivers/net/sfc/base/medford_nic.c
+++ b/drivers/net/sfc/base/medford_nic.c
@@ -51,8 +51,6 @@ medford_board_cfg(
        uint32_t board_type = 0;
        ef10_link_state_t els;
        efx_port_t *epp = &(enp->en_port);
-       uint32_t pf;
-       uint32_t vf;
        uint32_t mask;
        uint32_t sysclk, dpcpu_clk;
        uint32_t base, nvec;
@@ -75,18 +73,6 @@ medford_board_cfg(
        EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K  == 8192);
        encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
 
-       /*
-        * Get PCIe function number from firmware (used for
-        * per-function privilege and dynamic config info).
-        *  - PCIe PF: pf = PF number, vf = 0xffff.
-        *  - PCIe VF: pf = parent PF, vf = VF number.
-        */
-       if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
-               goto fail1;
-
-       encp->enc_pf = pf;
-       encp->enc_vf = vf;
-
        /* MAC address for this function */
        if (EFX_PCI_FUNCTION_IS_PF(encp)) {
                rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
@@ -111,7 +97,7 @@ medford_board_cfg(
                rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
        }
        if (rc != 0)
-               goto fail2;
+               goto fail1;
 
        EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
 
@@ -122,7 +108,7 @@ medford_board_cfg(
                if (rc == EACCES)
                        board_type = 0;
                else
-                       goto fail3;
+                       goto fail2;
        }
 
        encp->enc_board_type = board_type;
@@ -130,11 +116,11 @@ medford_board_cfg(
 
        /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
        if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
-               goto fail4;
+               goto fail3;
 
        /* Obtain the default PHY advertised capabilities */
        if ((rc = ef10_phy_get_link(enp, &els)) != 0)
-               goto fail5;
+               goto fail4;
        epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
        epp->ep_adv_cap_mask = els.els_adv_cap_mask;
 
@@ -178,11 +164,11 @@ medford_board_cfg(
        else if ((rc == ENOTSUP) || (rc == ENOENT))
                encp->enc_bug61265_workaround = B_FALSE;
        else
-               goto fail6;
+               goto fail5;
 
        /* Get clock frequencies (in MHz). */
        if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
-               goto fail7;
+               goto fail6;
 
        /*
         * The Medford timer quantum is 1536 dpcpu_clk cycles, documented for
@@ -194,7 +180,7 @@ medford_board_cfg(
 
        /* Check capabilities of running datapath firmware */
        if ((rc = ef10_get_datapath_caps(enp)) != 0)
-               goto fail8;
+               goto fail7;
 
        /* Alignment for receive packet DMA buffers */
        encp->enc_rx_buf_align_start = 1;
@@ -202,7 +188,7 @@ medford_board_cfg(
        /* Get the RX DMA end padding alignment configuration */
        if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
                if (rc != EACCES)
-                       goto fail9;
+                       goto fail8;
 
                /* Assume largest tail padding size supported by hardware */
                end_padding = 256;
@@ -254,13 +240,13 @@ medford_board_cfg(
         * can result in time-of-check/time-of-use bugs.
         */
        if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
-               goto fail10;
+               goto fail9;
        encp->enc_privilege_mask = mask;
 
        /* Get interrupt vector limits */
        if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
                if (EFX_PCI_FUNCTION_IS_PF(encp))
-                       goto fail11;
+                       goto fail10;
 
                /* Ignore error (cannot query vector limits from a VF). */
                base = 0;
@@ -283,14 +269,12 @@ medford_board_cfg(
 
        rc = medford_nic_get_required_pcie_bandwidth(enp, &bandwidth);
        if (rc != 0)
-               goto fail12;
+               goto fail11;
        encp->enc_required_pcie_bandwidth_mbps = bandwidth;
        encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
 
        return (0);
 
-fail12:
-       EFSYS_PROBE(fail12);
 fail11:
        EFSYS_PROBE(fail11);
 fail10: