common/cnxk: support inline IPsec flow action
authorSatheesh Paul <psatheesh@marvell.com>
Fri, 1 Oct 2021 13:40:09 +0000 (19:10 +0530)
committerJerin Jacob <jerinj@marvell.com>
Sat, 2 Oct 2021 13:45:00 +0000 (15:45 +0200)
Add support to configure flow rules with inline IPsec action.

Signed-off-by: Satheesh Paul <psatheesh@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
drivers/common/cnxk/roc_nix_inl.h
drivers/common/cnxk/roc_nix_inl_dev.c
drivers/common/cnxk/roc_nix_inl_priv.h
drivers/common/cnxk/roc_npc_mcam.c

index 6b8c268..ae5e022 100644 (file)
@@ -107,6 +107,9 @@ struct roc_nix_inl_dev {
        struct plt_pci_device *pci_dev;
        uint16_t ipsec_in_max_spi;
        bool selftest;
+       bool is_multi_channel;
+       uint16_t channel;
+       uint16_t chan_mask;
        bool attach_cptlf;
        /* End of input parameters */
 
index 0789f99..495dd19 100644 (file)
@@ -543,6 +543,9 @@ roc_nix_inl_dev_init(struct roc_nix_inl_dev *roc_inl_dev)
        inl_dev->pci_dev = pci_dev;
        inl_dev->ipsec_in_max_spi = roc_inl_dev->ipsec_in_max_spi;
        inl_dev->selftest = roc_inl_dev->selftest;
+       inl_dev->is_multi_channel = roc_inl_dev->is_multi_channel;
+       inl_dev->channel = roc_inl_dev->channel;
+       inl_dev->chan_mask = roc_inl_dev->chan_mask;
        inl_dev->attach_cptlf = roc_inl_dev->attach_cptlf;
 
        /* Initialize base device */
index 4729a38..3dc526f 100644 (file)
@@ -50,6 +50,9 @@ struct nix_inl_dev {
 
        /* Device arguments */
        uint8_t selftest;
+       uint16_t channel;
+       uint16_t chan_mask;
+       bool is_multi_channel;
        uint16_t ipsec_in_max_spi;
        bool attach_cptlf;
 };
index 8ccaaad..4985d22 100644 (file)
@@ -503,8 +503,11 @@ npc_mcam_alloc_and_write(struct npc *npc, struct roc_npc_flow *flow,
 {
        int use_ctr = (flow->ctr_id == NPC_COUNTER_NONE ? 0 : 1);
        struct npc_mcam_write_entry_req *req;
+       struct nix_inl_dev *inl_dev = NULL;
        struct mbox *mbox = npc->mbox;
        struct mbox_msghdr *rsp;
+       struct idev_cfg *idev;
+       uint16_t pf_func = 0;
        uint16_t ctr = ~(0);
        int rc, idx;
        int entry;
@@ -553,9 +556,30 @@ npc_mcam_alloc_and_write(struct npc *npc, struct roc_npc_flow *flow,
                req->entry_data.kw_mask[idx] = flow->mcam_mask[idx];
        }
 
+       idev = idev_get_cfg();
+       if (idev)
+               inl_dev = idev->nix_inl_dev;
+
        if (flow->nix_intf == NIX_INTF_RX) {
-               req->entry_data.kw[0] |= (uint64_t)npc->channel;
-               req->entry_data.kw_mask[0] |= (BIT_ULL(12) - 1);
+               if (inl_dev && inl_dev->is_multi_channel &&
+                   (flow->npc_action & NIX_RX_ACTIONOP_UCAST_IPSEC)) {
+                       req->entry_data.kw[0] |= (uint64_t)inl_dev->channel;
+                       req->entry_data.kw_mask[0] |=
+                               (uint64_t)inl_dev->chan_mask;
+                       pf_func = nix_inl_dev_pffunc_get();
+                       req->entry_data.action &= ~(GENMASK(19, 4));
+                       req->entry_data.action |= (uint64_t)pf_func << 4;
+
+                       flow->npc_action &= ~(GENMASK(19, 4));
+                       flow->npc_action |= (uint64_t)pf_func << 4;
+                       flow->mcam_data[0] |= (uint64_t)inl_dev->channel;
+                       flow->mcam_mask[0] |= (uint64_t)inl_dev->chan_mask;
+               } else {
+                       req->entry_data.kw[0] |= (uint64_t)npc->channel;
+                       req->entry_data.kw_mask[0] |= (BIT_ULL(12) - 1);
+                       flow->mcam_data[0] |= (uint64_t)npc->channel;
+                       flow->mcam_mask[0] |= (BIT_ULL(12) - 1);
+               }
        } else {
                uint16_t pf_func = (flow->npc_action >> 4) & 0xffff;