ixgbe/base: fix X550 CS4227 address
authorOuyang Changchun <changchun.ouyang@intel.com>
Thu, 12 Feb 2015 12:00:38 +0000 (20:00 +0800)
committerThomas Monjalon <thomas.monjalon@6wind.com>
Mon, 27 Apr 2015 08:05:59 +0000 (10:05 +0200)
Update the address of IXGBE_CS4227.

Signed-off-by: Changchun Ouyang <changchun.ouyang@intel.com>
Acked-by: Jijiang Liu <jijiang.liu@intel.com>
lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.h
lib/librte_pmd_ixgbe/ixgbe/ixgbe_x550.c

index 9a408ef..892517c 100644 (file)
@@ -82,7 +82,7 @@ POSSIBILITY OF SUCH DAMAGE.
 #define IXGBE_I2C_EEPROM_STATUS_FAIL   0x2
 #define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS    0x3
 
-#define IXGBE_CS4227                   0x9E    /* CS4227 address */
+#define IXGBE_CS4227                   0xBE    /* CS4227 address */
 #define IXGBE_CS4227_SPARE24_LSB       0x12B0  /* Reg to program EDC */
 #define IXGBE_CS4227_EDC_MODE_CX1      0x0002
 #define IXGBE_CS4227_EDC_MODE_SR       0x0004
index 763fc46..cad3bcd 100644 (file)
@@ -820,7 +820,7 @@ s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
        hw->phy.ops.reset = NULL;
 
        /* The CS4227 slice address is the base address + the port-pair reg
-        * offset. I.e. Slice 0 = 0x0000 and slice 1 = 0x1000.
+        * offset. I.e. Slice 0 = 0x12B0 and slice 1 = 0x22B0.
         */
        reg_slice = IXGBE_CS4227_SPARE24_LSB + (hw->phy.lan_id << 12);
 
@@ -833,6 +833,10 @@ s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
        ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
                                           edc_mode);
 
+       if (ret_val != IXGBE_SUCCESS)
+               ret_val = ixgbe_write_i2c_combined(hw, 0x80, reg_slice,
+                                                  edc_mode);
+
        return ret_val;
 }