#define IXGBE_I2C_EEPROM_STATUS_FAIL 0x2
#define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3
-#define IXGBE_CS4227 0x9E /* CS4227 address */
+#define IXGBE_CS4227 0xBE /* CS4227 address */
#define IXGBE_CS4227_SPARE24_LSB 0x12B0 /* Reg to program EDC */
#define IXGBE_CS4227_EDC_MODE_CX1 0x0002
#define IXGBE_CS4227_EDC_MODE_SR 0x0004
hw->phy.ops.reset = NULL;
/* The CS4227 slice address is the base address + the port-pair reg
- * offset. I.e. Slice 0 = 0x0000 and slice 1 = 0x1000.
+ * offset. I.e. Slice 0 = 0x12B0 and slice 1 = 0x22B0.
*/
reg_slice = IXGBE_CS4227_SPARE24_LSB + (hw->phy.lan_id << 12);
ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
edc_mode);
+ if (ret_val != IXGBE_SUCCESS)
+ ret_val = ixgbe_write_i2c_combined(hw, 0x80, reg_slice,
+ edc_mode);
+
return ret_val;
}