config: enable C11 memory model for armv8 with meson

This patch makes the configuration based on makefile and the
configuration based on meson to be the same.

Fixes: c6e536e38437 ("build: add more implementers IDs and PNs for ARM")
Cc: stable@dpdk.org
Signed-off-by: Gavin Hu <gavin.hu@arm.com>
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>

diff --git a/config/arm/meson.build b/config/arm/meson.build
index 3f91725..dae55d6 100644 (file)
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -47,6 +47,7 @@ flags_common_default = [
 flags_generic = [
        ['RTE_MACHINE', '"armv8a"'],
        ['RTE_MAX_LCORE', 256],
+       ['RTE_USE_C11_MEM_MODEL', true],
        ['RTE_CACHE_LINE_SIZE', 128]]
 flags_cavium = [
        ['RTE_MACHINE', '"thunderx"'],
@@ -57,11 +58,13 @@ flags_cavium = [
        ['RTE_USE_C11_MEM_MODEL', false]]
 flags_dpaa = [
        ['RTE_MACHINE', '"dpaa"'],
+       ['RTE_USE_C11_MEM_MODEL', true],
        ['RTE_CACHE_LINE_SIZE', 64],
        ['RTE_MAX_NUMA_NODES', 1],
        ['RTE_MAX_LCORE', 16]]
 flags_dpaa2 = [
        ['RTE_MACHINE', '"dpaa2"'],
+       ['RTE_USE_C11_MEM_MODEL', true],
        ['RTE_CACHE_LINE_SIZE', 64],
        ['RTE_MAX_NUMA_NODES', 1],
        ['RTE_MAX_LCORE', 16],