net/thunderx: update sq config register field

cq_limit field is added in cn88xx-pass2 and subsequent
versions. Reflect the change in the sq_config structure.
This change is backward compatible as the old pass versions
ignore this field.

Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>

diff --git a/drivers/net/thunderx/base/nicvf_hw.c b/drivers/net/thunderx/base/nicvf_hw.c
index d10d2c0..2634285 100644 (file)
--- a/drivers/net/thunderx/base/nicvf_hw.c
+++ b/drivers/net/thunderx/base/nicvf_hw.c
@@ -586,6 +586,7 @@ nicvf_qset_sq_config(struct nicvf *nic, uint16_t qidx, struct nicvf_txq *txq)
        nicvf_queue_reg_write(nic, NIC_QSET_SQ_0_7_BASE, qidx, txq->phys);
 
        /* Enable send queue  & set queue size */
+       sq_cfg.cq_limit = 0;
        sq_cfg.ena = 1;
        sq_cfg.reset = 0;
        sq_cfg.ldwb = 0;

diff --git a/drivers/net/thunderx/base/nicvf_hw_defs.h b/drivers/net/thunderx/base/nicvf_hw_defs.h
index b77f4d4..0fe673e 100644 (file)
--- a/drivers/net/thunderx/base/nicvf_hw_defs.h
+++ b/drivers/net/thunderx/base/nicvf_hw_defs.h
@@ -1084,7 +1084,8 @@ struct cq_cfg { union { struct {
 
 struct sq_cfg { union { struct {
 #if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN
-       uint64_t reserved_20_63:44;
+       uint64_t reserved_32_63:32;
+       uint64_t cq_limit:8;
        uint64_t ena:1;
        uint64_t reserved_18_18:1;
        uint64_t reset:1;
@@ -1102,7 +1103,8 @@ struct sq_cfg { union { struct {
        uint64_t reset:1;
        uint64_t reserved_18_18:1;
        uint64_t ena:1;
-       uint64_t reserved_20_63:44;
+       uint64_t cq_limit:8;
+       uint64_t reserved_32_63:32;
 #endif
        };
        uint64_t value;