net/bnxt: add conditional goto processing

The condition execute of the mapper tables have goto field that
defines the offset of the next table to be processed instead of
sequential processing of the tables, this improving the performance.
Also, modify key and mask field opcode processing

Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Mike Baucom <michael.baucom@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>

diff --git a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c
index 72a6bcd..f3b8d81 100644 (file)
--- a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c
@@ -139,7 +139,7 @@ ulp_set_vlan_in_act_prop(uint16_t port_id,
        struct ulp_rte_act_prop *act_prop = mapper_params->act_prop;
 
        if (ULP_BITMAP_ISSET(mapper_params->act->bits,
-                            BNXT_ULP_ACTION_BIT_SET_VLAN_VID)) {
+                            BNXT_ULP_ACT_BIT_SET_VLAN_VID)) {
                BNXT_TF_DBG(ERR,
                            "VLAN already set, multiple VLANs unsupported\n");
                return BNXT_TF_RC_ERROR;
@@ -148,7 +148,7 @@ ulp_set_vlan_in_act_prop(uint16_t port_id,
        port_id = rte_cpu_to_be_16(port_id);
 
        ULP_BITMAP_SET(mapper_params->act->bits,
-                      BNXT_ULP_ACTION_BIT_SET_VLAN_VID);
+                      BNXT_ULP_ACT_BIT_SET_VLAN_VID);
 
        memcpy(&act_prop->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG],
               &port_id, sizeof(port_id));
@@ -161,7 +161,7 @@ ulp_set_mark_in_act_prop(uint16_t port_id,
                         struct bnxt_ulp_mapper_create_parms *mapper_params)
 {
        if (ULP_BITMAP_ISSET(mapper_params->act->bits,
-                            BNXT_ULP_ACTION_BIT_MARK)) {
+                            BNXT_ULP_ACT_BIT_MARK)) {
                BNXT_TF_DBG(ERR,
                            "MARK already set, multiple MARKs unsupported\n");
                return BNXT_TF_RC_ERROR;

diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 206f3d5..dc21b2a 100644 (file)
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -892,26 +892,35 @@ ulp_mapper_field_process(struct bnxt_ulp_mapper_parms *parms,
        uint16_t write_idx = blob->write_idx;
        uint16_t idx, size_idx, bitlen;
        uint8_t *val = NULL;
-       uint8_t act_val[16];
+       uint8_t tmpval[16];
        uint8_t bit;
+       uint32_t src1_sel = 0;
+       enum bnxt_ulp_field_src fld_src;
+       uint8_t *fld_src_oper;
 
        bitlen = fld->field_bit_size;
-       switch (fld->field_opcode) {
-       case BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT:
-               val = fld->field_operand;
-               if (!ulp_blob_push(blob, val, bitlen)) {
-                       BNXT_TF_DBG(ERR, "%s push to blob failed\n", name);
+       /* Evaluate the condition */
+       switch (fld->field_cond_src) {
+       case BNXT_ULP_FIELD_COND_SRC_TRUE:
+               src1_sel = 1;
+               break;
+       case BNXT_ULP_FIELD_COND_SRC_CF:
+               if (!ulp_operand_read(fld->field_cond_opr,
+                                     (uint8_t *)&idx, sizeof(uint16_t))) {
+                       BNXT_TF_DBG(ERR, "%s operand read failed.\n", name);
                        return -EINVAL;
                }
-               break;
-       case BNXT_ULP_FIELD_OPC_SET_TO_ZERO:
-               if (ulp_blob_pad_push(blob, bitlen) < 0) {
-                       BNXT_TF_DBG(ERR, "%s too large for blob\n", name);
+               idx = tfp_be_to_cpu_16(idx);
+               if (idx >= BNXT_ULP_CF_IDX_LAST) {
+                       BNXT_TF_DBG(ERR, "%s invalid index %u\n", name, idx);
                        return -EINVAL;
                }
+               /* check if the computed field is set */
+               if (ULP_COMP_FLD_IDX_RD(parms, idx))
+                       src1_sel = 1;
                break;
-       case BNXT_ULP_FIELD_OPC_SET_TO_REGFILE:
-               if (!ulp_operand_read(fld->field_operand,
+       case BNXT_ULP_FIELD_COND_SRC_RF:
+               if (!ulp_operand_read(fld->field_cond_opr,
                                      (uint8_t *)&idx, sizeof(uint16_t))) {
                        BNXT_TF_DBG(ERR, "%s operand read failed\n", name);
                        return -EINVAL;
@@ -924,38 +933,78 @@ ulp_mapper_field_process(struct bnxt_ulp_mapper_parms *parms,
                                    name, idx);
                        return -EINVAL;
                }
-
-               val = ulp_blob_push_64(blob, &regval, bitlen);
-               if (!val) {
-                       BNXT_TF_DBG(ERR, "%s push to blob failed\n", name);
+               if (regval)
+                       src1_sel = 1;
+               break;
+       case BNXT_ULP_FIELD_COND_SRC_ACT_BIT:
+               if (!ulp_operand_read(fld->field_cond_opr,
+                                     (uint8_t *)&act_bit, sizeof(uint64_t))) {
+                       BNXT_TF_DBG(ERR, "%s operand read failed\n", name);
                        return -EINVAL;
                }
+               act_bit = tfp_be_to_cpu_64(act_bit);
+               if (ULP_BITMAP_ISSET(parms->act_bitmap->bits, act_bit))
+                       src1_sel = 1;
                break;
-       case BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE:
-               if (!ulp_operand_read(fld->field_operand,
-                                     (uint8_t *)&idx,
+       case BNXT_ULP_FIELD_COND_SRC_HDR_BIT:
+               if (!ulp_operand_read(fld->field_cond_opr,
+                                     (uint8_t *)&hdr_bit, sizeof(uint64_t))) {
+                       BNXT_TF_DBG(ERR, "%s operand read failed\n", name);
+                       return -EINVAL;
+               }
+               hdr_bit = tfp_be_to_cpu_64(hdr_bit);
+               if (ULP_BITMAP_ISSET(parms->hdr_bitmap->bits, hdr_bit))
+                       src1_sel = 1;
+               break;
+       case BNXT_ULP_FIELD_COND_SRC_FIELD_BIT:
+               if (!ulp_operand_read(fld->field_cond_opr, (uint8_t *)&idx,
                                      sizeof(uint16_t))) {
                        BNXT_TF_DBG(ERR, "%s operand read failed.\n", name);
                        return -EINVAL;
                }
                idx = tfp_be_to_cpu_16(idx);
-               if (ulp_mapper_glb_resource_read(parms->mapper_data,
-                                                dir,
-                                                idx, &regval)) {
-                       BNXT_TF_DBG(ERR, "%s global regfile[%d] read failed.\n",
-                                   name, idx);
+               /* get the index from the global field list */
+               if (ulp_mapper_glb_field_tbl_get(parms, idx, &bit)) {
+                       BNXT_TF_DBG(ERR, "invalid ulp_glb_field_tbl idx %d\n",
+                                   idx);
                        return -EINVAL;
                }
-               val = ulp_blob_push_64(blob, &regval, bitlen);
-               if (!val) {
+               if (bit && (ULP_INDEX_BITMAP_GET(parms->fld_bitmap->bits, bit)))
+                       src1_sel = 1;
+               break;
+       default:
+               BNXT_TF_DBG(ERR, "%s invalid field opcode 0x%x at %d\n",
+                           name, fld->field_cond_src, write_idx);
+               return -EINVAL;
+       }
+
+       /* pick the selected source */
+       if (src1_sel) {
+               fld_src = fld->field_src1;
+               fld_src_oper = fld->field_opr1;
+       } else {
+               fld_src = fld->field_src2;
+               fld_src_oper = fld->field_opr2;
+       }
+
+       /* Perform the action */
+       switch (fld_src) {
+       case BNXT_ULP_FIELD_SRC_ZERO:
+               if (ulp_blob_pad_push(blob, bitlen) < 0) {
+                       BNXT_TF_DBG(ERR, "%s too large for blob\n", name);
+                       return -EINVAL;
+               }
+               break;
+       case BNXT_ULP_FIELD_SRC_CONST:
+               val = fld_src_oper;
+               if (!ulp_blob_push(blob, val, bitlen)) {
                        BNXT_TF_DBG(ERR, "%s push to blob failed\n", name);
                        return -EINVAL;
                }
                break;
-       case BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD:
-               if (!ulp_operand_read(fld->field_operand,
-                                     (uint8_t *)&idx,
-                                     sizeof(uint16_t))) {
+       case BNXT_ULP_FIELD_SRC_CF:
+               if (!ulp_operand_read(fld_src_oper,
+                                     (uint8_t *)&idx, sizeof(uint16_t))) {
                        BNXT_TF_DBG(ERR, "%s operand read failed.\n",
                                    name);
                        return -EINVAL;
@@ -969,126 +1018,29 @@ ulp_mapper_field_process(struct bnxt_ulp_mapper_parms *parms,
                        return -EINVAL;
                }
                break;
-       case BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST:
-               if (!ulp_operand_read(fld->field_operand,
-                                     (uint8_t *)&act_bit, sizeof(uint64_t))) {
-                       BNXT_TF_DBG(ERR, "%s operand read failed\n", name);
-                       return -EINVAL;
-               }
-               act_bit = tfp_be_to_cpu_64(act_bit);
-               if (ULP_BITMAP_ISSET(parms->act_bitmap->bits, act_bit)) {
-                       /* Action bit is set so consider operand_true */
-                       if (!ulp_operand_read(fld->field_operand_true,
-                                             (uint8_t *)&idx,
-                                             sizeof(uint16_t))) {
-                               BNXT_TF_DBG(ERR,
-                                           "%s true operand read failed\n",
-                                           name);
-                               return -EINVAL;
-                       }
-                       idx = tfp_be_to_cpu_16(idx);
-                       if (idx >= BNXT_ULP_ACT_PROP_IDX_LAST) {
-                               BNXT_TF_DBG(ERR, "%s act_prop[%d] oob\n",
-                                           name, idx);
-                               return -EINVAL;
-                       }
-                       val = &parms->act_prop->act_details[idx];
-                       field_size = ulp_mapper_act_prop_size_get(idx);
-                       if (bitlen < ULP_BYTE_2_BITS(field_size)) {
-                               field_size  = field_size - ((bitlen + 7) / 8);
-                               val += field_size;
-                       }
-                       if (!ulp_blob_push(blob, val, bitlen)) {
-                               BNXT_TF_DBG(ERR, "%s push to blob failed\n",
-                                           name);
-                               return -EINVAL;
-                       }
-               } else {
-                       /* action bit is not set, use the operand false */
-                       val = fld->field_operand_false;
-                       if (!ulp_blob_push(blob, val, bitlen)) {
-                               BNXT_TF_DBG(ERR, "%s push to blob failed\n",
-                                           name);
-                               return -EINVAL;
-                       }
-               }
-               break;
-       case BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST:
-               if (!ulp_operand_read(fld->field_operand,
-                                     (uint8_t *)&act_bit, sizeof(uint64_t))) {
+       case BNXT_ULP_FIELD_SRC_RF:
+               if (!ulp_operand_read(fld_src_oper,
+                                     (uint8_t *)&idx, sizeof(uint16_t))) {
                        BNXT_TF_DBG(ERR, "%s operand read failed\n", name);
                        return -EINVAL;
                }
-               act_bit = tfp_be_to_cpu_64(act_bit);
-               if (ULP_BITMAP_ISSET(parms->act_bitmap->bits, act_bit)) {
-                       /* Action bit is set so consider operand_true */
-                       val = fld->field_operand_true;
-               } else {
-                       /* action bit is not set, use the operand false */
-                       val = fld->field_operand_false;
-               }
-               if (!ulp_blob_push(blob, val, bitlen)) {
-                       BNXT_TF_DBG(ERR, "%s push to blob failed\n",
-                                   name);
-                       return -EINVAL;
-               }
-               break;
-       case BNXT_ULP_FIELD_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF:
-               if (!ulp_operand_read(fld->field_operand,
-                                     (uint8_t *)&idx,
-                                     sizeof(uint16_t))) {
-                       BNXT_TF_DBG(ERR, "%s operand read failed.\n", name);
-                       return -EINVAL;
-               }
-               idx = tfp_be_to_cpu_16(idx);
-               if (idx >= BNXT_ULP_CF_IDX_LAST) {
-                       BNXT_TF_DBG(ERR, "%s invalid index %u\n", name, idx);
-                       return -EINVAL;
-               }
-               /* check if the computed field is set */
-               if (ULP_COMP_FLD_IDX_RD(parms, idx))
-                       val = fld->field_operand_true;
-               else
-                       val = fld->field_operand_false;
 
-               /* read the appropriate computed field */
-               if (!ulp_operand_read(val, (uint8_t *)&idx, sizeof(uint16_t))) {
-                       BNXT_TF_DBG(ERR, "%s val operand read failed\n", name);
-                       return -EINVAL;
-               }
                idx = tfp_be_to_cpu_16(idx);
-               if (idx >= BNXT_ULP_CF_IDX_LAST) {
-                       BNXT_TF_DBG(ERR, "%s invalid index %u\n", name, idx);
+               /* Uninitialized regfile entries return 0 */
+               if (!ulp_regfile_read(parms->regfile, idx, &regval)) {
+                       BNXT_TF_DBG(ERR, "%s regfile[%d] read oob\n",
+                                   name, idx);
                        return -EINVAL;
                }
-               val = ulp_blob_push_32(blob, &parms->comp_fld[idx], bitlen);
+
+               val = ulp_blob_push_64(blob, &regval, bitlen);
                if (!val) {
                        BNXT_TF_DBG(ERR, "%s push to blob failed\n", name);
                        return -EINVAL;
                }
                break;
-       case BNXT_ULP_FIELD_OPC_IF_HDR_BIT_THEN_CONST_ELSE_CONST:
-               if (!ulp_operand_read(fld->field_operand,
-                                     (uint8_t *)&hdr_bit, sizeof(uint64_t))) {
-                       BNXT_TF_DBG(ERR, "%s operand read failed\n", name);
-                       return -EINVAL;
-               }
-               hdr_bit = tfp_be_to_cpu_64(hdr_bit);
-               if (ULP_BITMAP_ISSET(parms->hdr_bitmap->bits, hdr_bit)) {
-                       /* Header bit is set so consider operand_true */
-                       val = fld->field_operand_true;
-               } else {
-                       /* Header bit is not set, use the operand false */
-                       val = fld->field_operand_false;
-               }
-               if (!ulp_blob_push(blob, val, bitlen)) {
-                       BNXT_TF_DBG(ERR, "%s push to blob failed\n",
-                                   name);
-                       return -EINVAL;
-               }
-               break;
-       case BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP:
-               if (!ulp_operand_read(fld->field_operand,
+       case BNXT_ULP_FIELD_SRC_ACT_PROP:
+               if (!ulp_operand_read(fld_src_oper,
                                      (uint8_t *)&idx, sizeof(uint16_t))) {
                        BNXT_TF_DBG(ERR, "%s operand read failed\n", name);
                        return -EINVAL;
@@ -1110,28 +1062,8 @@ ulp_mapper_field_process(struct bnxt_ulp_mapper_parms *parms,
                        return -EINVAL;
                }
                break;
-       case BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT:
-               if (!ulp_operand_read(fld->field_operand,
-                                     (uint8_t *)&act_bit, sizeof(uint64_t))) {
-                       BNXT_TF_DBG(ERR, "%s operand read failed\n", name);
-                       return -EINVAL;
-               }
-               act_bit = tfp_be_to_cpu_64(act_bit);
-               memset(act_val, 0, sizeof(act_val));
-               if (ULP_BITMAP_ISSET(parms->act_bitmap->bits, act_bit))
-                       act_val[0] = 1;
-               if (bitlen > ULP_BYTE_2_BITS(sizeof(act_val))) {
-                       BNXT_TF_DBG(ERR, "%s field size is incorrect\n", name);
-                       return -EINVAL;
-               }
-               if (!ulp_blob_push(blob, act_val, bitlen)) {
-                       BNXT_TF_DBG(ERR, "%s push to blob failed\n", name);
-                       return -EINVAL;
-               }
-               val = act_val;
-               break;
-       case BNXT_ULP_FIELD_OPC_SET_TO_ENCAP_ACT_PROP_SZ:
-               if (!ulp_operand_read(fld->field_operand,
+       case BNXT_ULP_FIELD_SRC_ACT_PROP_SZ:
+               if (!ulp_operand_read(fld_src_oper,
                                      (uint8_t *)&idx, sizeof(uint16_t))) {
                        BNXT_TF_DBG(ERR, "%s operand read failed\n", name);
                        return -EINVAL;
@@ -1145,7 +1077,7 @@ ulp_mapper_field_process(struct bnxt_ulp_mapper_parms *parms,
                val = &parms->act_prop->act_details[idx];
 
                /* get the size index next */
-               if (!ulp_operand_read(&fld->field_operand[sizeof(uint16_t)],
+               if (!ulp_operand_read(&fld_src_oper[sizeof(uint16_t)],
                                      (uint8_t *)&size_idx, sizeof(uint16_t))) {
                        BNXT_TF_DBG(ERR, "%s operand read failed\n", name);
                        return -EINVAL;
@@ -1162,8 +1094,29 @@ ulp_mapper_field_process(struct bnxt_ulp_mapper_parms *parms,
                val_size = ULP_BYTE_2_BITS(val_size);
                ulp_blob_push_encap(blob, val, val_size);
                break;
-       case BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD:
-               if (!ulp_operand_read(fld->field_operand, (uint8_t *)&idx,
+       case BNXT_ULP_FIELD_SRC_GLB_RF:
+               if (!ulp_operand_read(fld_src_oper,
+                                     (uint8_t *)&idx,
+                                     sizeof(uint16_t))) {
+                       BNXT_TF_DBG(ERR, "%s operand read failed.\n", name);
+                       return -EINVAL;
+               }
+               idx = tfp_be_to_cpu_16(idx);
+               if (ulp_mapper_glb_resource_read(parms->mapper_data,
+                                                dir,
+                                                idx, &regval)) {
+                       BNXT_TF_DBG(ERR, "%s global regfile[%d] read failed.\n",
+                                   name, idx);
+                       return -EINVAL;
+               }
+               val = ulp_blob_push_64(blob, &regval, bitlen);
+               if (!val) {
+                       BNXT_TF_DBG(ERR, "%s push to blob failed\n", name);
+                       return -EINVAL;
+               }
+               break;
+       case BNXT_ULP_FIELD_SRC_HF:
+               if (!ulp_operand_read(fld_src_oper, (uint8_t *)&idx,
                                      sizeof(uint16_t))) {
                        BNXT_TF_DBG(ERR, "%s operand read failed.\n", name);
                        return -EINVAL;
@@ -1195,9 +1148,80 @@ ulp_mapper_field_process(struct bnxt_ulp_mapper_parms *parms,
                        return -EINVAL;
                }
                break;
+       case BNXT_ULP_FIELD_SRC_HDR_BIT:
+               if (!ulp_operand_read(fld_src_oper,
+                                     (uint8_t *)&hdr_bit, sizeof(uint64_t))) {
+                       BNXT_TF_DBG(ERR, "%s operand read failed\n", name);
+                       return -EINVAL;
+               }
+               hdr_bit = tfp_be_to_cpu_64(hdr_bit);
+               memset(tmpval, 0, sizeof(tmpval));
+               if (ULP_BITMAP_ISSET(parms->hdr_bitmap->bits, hdr_bit))
+                       tmpval[0] = 1;
+               if (bitlen > ULP_BYTE_2_BITS(sizeof(tmpval))) {
+                       BNXT_TF_DBG(ERR, "%s field size is incorrect\n", name);
+                       return -EINVAL;
+               }
+               if (!ulp_blob_push(blob, tmpval, bitlen)) {
+                       BNXT_TF_DBG(ERR, "%s push to blob failed\n", name);
+                       return -EINVAL;
+               }
+               val = tmpval;
+               break;
+       case BNXT_ULP_FIELD_SRC_ACT_BIT:
+               if (!ulp_operand_read(fld_src_oper,
+                                     (uint8_t *)&act_bit, sizeof(uint64_t))) {
+                       BNXT_TF_DBG(ERR, "%s operand read failed\n", name);
+                       return -EINVAL;
+               }
+               act_bit = tfp_be_to_cpu_64(act_bit);
+               memset(tmpval, 0, sizeof(tmpval));
+               if (ULP_BITMAP_ISSET(parms->act_bitmap->bits, act_bit))
+                       tmpval[0] = 1;
+               if (bitlen > ULP_BYTE_2_BITS(sizeof(tmpval))) {
+                       BNXT_TF_DBG(ERR, "%s field size is incorrect\n", name);
+                       return -EINVAL;
+               }
+               if (!ulp_blob_push(blob, tmpval, bitlen)) {
+                       BNXT_TF_DBG(ERR, "%s push to blob failed\n", name);
+                       return -EINVAL;
+               }
+               val = tmpval;
+               break;
+       case BNXT_ULP_FIELD_SRC_FIELD_BIT:
+               if (!ulp_operand_read(fld_src_oper, (uint8_t *)&idx,
+                                     sizeof(uint16_t))) {
+                       BNXT_TF_DBG(ERR, "%s operand read failed.\n", name);
+                       return -EINVAL;
+               }
+               idx = tfp_be_to_cpu_16(idx);
+               /* get the index from the global field list */
+               if (ulp_mapper_glb_field_tbl_get(parms, idx, &bit)) {
+                       BNXT_TF_DBG(ERR, "invalid ulp_glb_field_tbl idx %d\n",
+                                   idx);
+                       return -EINVAL;
+               }
+               memset(tmpval, 0, sizeof(tmpval));
+               if (ULP_INDEX_BITMAP_GET(parms->fld_bitmap->bits, bit))
+                       tmpval[0] = 1;
+               if (bitlen > ULP_BYTE_2_BITS(sizeof(tmpval))) {
+                       BNXT_TF_DBG(ERR, "%s field size is incorrect\n", name);
+                       return -EINVAL;
+               }
+               if (!ulp_blob_push(blob, tmpval, bitlen)) {
+                       BNXT_TF_DBG(ERR, "%s push to blob failed\n", name);
+                       return -EINVAL;
+               }
+               val = tmpval;
+               break;
+       case BNXT_ULP_FIELD_SRC_SKIP:
+               /* do nothing */
+               break;
+       case BNXT_ULP_FIELD_SRC_REJECT:
+               return -EINVAL;
        default:
                BNXT_TF_DBG(ERR, "%s invalid field opcode 0x%x at %d\n",
-                           name, fld->field_opcode, write_idx);
+                           name, fld_src, write_idx);
                return -EINVAL;
        }
        return 0;
@@ -1267,7 +1291,7 @@ ulp_mapper_mark_gfid_process(struct bnxt_ulp_mapper_parms *parms,
        if (mark_op == BNXT_ULP_MARK_DB_OPC_NOP ||
            !(mark_op == BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION &&
             ULP_BITMAP_ISSET(parms->act_bitmap->bits,
-                             BNXT_ULP_ACTION_BIT_MARK)))
+                             BNXT_ULP_ACT_BIT_MARK)))
                return rc; /* no need to perform gfid process */
 
        /* Get the mark id details from action property */
@@ -1308,7 +1332,7 @@ ulp_mapper_mark_act_ptr_process(struct bnxt_ulp_mapper_parms *parms,
        if (mark_op == BNXT_ULP_MARK_DB_OPC_NOP ||
            !(mark_op == BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION &&
             ULP_BITMAP_ISSET(parms->act_bitmap->bits,
-                             BNXT_ULP_ACTION_BIT_MARK)))
+                             BNXT_ULP_ACT_BIT_MARK)))
                return rc; /* no need to perform mark action process */
 
        /* Get the mark id details from action property */
@@ -2500,7 +2524,7 @@ ulp_mapper_cond_opc_process(struct bnxt_ulp_mapper_parms *parms,
        uint64_t regval;
 
        switch (opc) {
-       case BNXT_ULP_COND_OPC_COMP_FIELD_IS_SET:
+       case BNXT_ULP_COND_OPC_CF_IS_SET:
                if (operand < BNXT_ULP_CF_IDX_LAST) {
                        *res = ULP_COMP_FLD_IDX_RD(parms, operand);
                } else {
@@ -2509,7 +2533,7 @@ ulp_mapper_cond_opc_process(struct bnxt_ulp_mapper_parms *parms,
                        rc = -EINVAL;
                }
                break;
-       case BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET:
+       case BNXT_ULP_COND_OPC_CF_NOT_SET:
                if (operand < BNXT_ULP_CF_IDX_LAST) {
                        *res = !ULP_COMP_FLD_IDX_RD(parms, operand);
                } else {
@@ -2518,8 +2542,8 @@ ulp_mapper_cond_opc_process(struct bnxt_ulp_mapper_parms *parms,
                        rc = -EINVAL;
                }
                break;
-       case BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET:
-               if (operand < BNXT_ULP_ACTION_BIT_LAST) {
+       case BNXT_ULP_COND_OPC_ACT_BIT_IS_SET:
+               if (operand < BNXT_ULP_ACT_BIT_LAST) {
                        *res = ULP_BITMAP_ISSET(parms->act_bitmap->bits,
                                                operand);
                } else {
@@ -2528,8 +2552,8 @@ ulp_mapper_cond_opc_process(struct bnxt_ulp_mapper_parms *parms,
                        rc = -EINVAL;
                }
                break;
-       case BNXT_ULP_COND_OPC_ACTION_BIT_NOT_SET:
-               if (operand < BNXT_ULP_ACTION_BIT_LAST) {
+       case BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET:
+               if (operand < BNXT_ULP_ACT_BIT_LAST) {
                        *res = !ULP_BITMAP_ISSET(parms->act_bitmap->bits,
                                               operand);
                } else {
@@ -2576,14 +2600,14 @@ ulp_mapper_cond_opc_process(struct bnxt_ulp_mapper_parms *parms,
                }
                *res = !ULP_INDEX_BITMAP_GET(parms->fld_bitmap->bits, bit);
                break;
-       case BNXT_ULP_COND_OPC_REGFILE_IS_SET:
+       case BNXT_ULP_COND_OPC_RF_IS_SET:
                if (!ulp_regfile_read(parms->regfile, operand, &regval)) {
                        BNXT_TF_DBG(ERR, "regfile[%d] read oob\n", operand);
                        return -EINVAL;
                }
                *res = regval != 0;
                break;
-       case BNXT_ULP_COND_OPC_REGFILE_NOT_SET:
+       case BNXT_ULP_COND_OPC_RF_NOT_SET:
                if (!ulp_regfile_read(parms->regfile, operand, &regval)) {
                        BNXT_TF_DBG(ERR, "regfile[%d] read oob\n", operand);
                        return -EINVAL;
@@ -2733,8 +2757,9 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid)
        enum bnxt_ulp_cond_list_opc cond_opc;
        struct bnxt_ulp_mapper_tbl_info *tbls;
        struct bnxt_ulp_mapper_tbl_info *tbl;
-       uint32_t num_tbls, i, num_cond_tbls;
+       uint32_t num_tbls, tbl_idx, num_cond_tbls;
        int32_t rc = -EINVAL, cond_rc = 0;
+       uint32_t cond_goto = 1;
 
        cond_tbls = ulp_mapper_tmpl_reject_list_get(parms, tid,
                                                    &num_cond_tbls,
@@ -2769,12 +2794,15 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid)
                return -EINVAL;
        }
 
-       for (i = 0; i < num_tbls; i++) {
-               tbl = &tbls[i];
-
+       for (tbl_idx = 0; tbl_idx < num_tbls && cond_goto;) {
+               tbl = &tbls[tbl_idx];
+               cond_goto = tbl->execute_info.cond_goto;
                /* Handle the table level opcodes to determine if required. */
-               if (ulp_mapper_tbl_memtype_opcode_process(parms, tbl))
+               if (ulp_mapper_tbl_memtype_opcode_process(parms, tbl)) {
+                       tbl_idx += 1;
                        continue;
+               }
+
                cond_tbls = ulp_mapper_tbl_execute_list_get(parms, tbl,
                                                            &num_cond_tbls,
                                                            &cond_opc);
@@ -2787,8 +2815,10 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid)
                        return rc;
                }
                /* Skip the table if False */
-               if (!cond_rc)
+               if (!cond_rc) {
+                       tbl_idx += 1;
                        continue;
+               }
 
                /* process the fdb opcode for alloc push */
                if (tbl->fdb_opcode == BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE) {
@@ -2817,6 +2847,7 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid)
                        rc = ulp_mapper_gen_tbl_process(parms, tbl);
                        break;
                case BNXT_ULP_RESOURCE_FUNC_INVALID:
+               case BNXT_ULP_RESOURCE_FUNC_BRANCH_TABLE:
                        rc = 0;
                        break;
                default:
@@ -2840,6 +2871,7 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid)
                        rc = -EINVAL;
                        goto error;
                }
+               tbl_idx += cond_goto;
        }
 
        return rc;
@@ -3081,6 +3113,7 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx,
        parms.hdr_bitmap = cparms->hdr_bitmap;
        parms.regfile = &regfile;
        parms.hdr_field = cparms->hdr_field;
+       parms.fld_bitmap = cparms->fld_bitmap;
        parms.comp_fld = cparms->comp_fld;
        parms.tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx);
        parms.ulp_ctx = ulp_ctx;

diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index f5f9ff6..8de7cec 100644 (file)
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -274,7 +274,7 @@ ulp_post_process_normal_flow(struct ulp_rte_parser_params *params)
 
        /* Update the decrement ttl computational fields */
        if (ULP_BITMAP_ISSET(params->act_bitmap.bits,
-                            BNXT_ULP_ACTION_BIT_DEC_TTL)) {
+                            BNXT_ULP_ACT_BIT_DEC_TTL)) {
                /*
                 * Check that vxlan proto is included and vxlan decap
                 * action is not set then decrement tunnel ttl.
@@ -283,7 +283,7 @@ ulp_post_process_normal_flow(struct ulp_rte_parser_params *params)
                if ((ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
                                      BNXT_ULP_HDR_BIT_T_VXLAN) &&
                    !ULP_BITMAP_ISSET(params->act_bitmap.bits,
-                                     BNXT_ULP_ACTION_BIT_VXLAN_DECAP))) {
+                                     BNXT_ULP_ACT_BIT_VXLAN_DECAP))) {
                        ULP_COMP_FLD_IDX_WR(params,
                                            BNXT_ULP_CF_IDX_ACT_T_DEC_TTL, 1);
                } else {
@@ -1439,7 +1439,7 @@ ulp_rte_mark_act_handler(const struct rte_flow_action *action_item,
                       &mark_id, BNXT_ULP_ACT_PROP_SZ_MARK);
 
                /* Update the hdr_bitmap with vxlan */
-               ULP_BITMAP_SET(act->bits, BNXT_ULP_ACTION_BIT_MARK);
+               ULP_BITMAP_SET(act->bits, BNXT_ULP_ACT_BIT_MARK);
                return BNXT_TF_RC_SUCCESS;
        }
        BNXT_TF_DBG(ERR, "Parse Error: Mark arg is invalid\n");
@@ -1455,7 +1455,7 @@ ulp_rte_rss_act_handler(const struct rte_flow_action *action_item,
 
        if (rss) {
                /* Update the hdr_bitmap with vxlan */
-               ULP_BITMAP_SET(param->act_bitmap.bits, BNXT_ULP_ACTION_BIT_RSS);
+               ULP_BITMAP_SET(param->act_bitmap.bits, BNXT_ULP_ACT_BIT_RSS);
                return BNXT_TF_RC_SUCCESS;
        }
        BNXT_TF_DBG(ERR, "Parse Error: RSS arg is invalid\n");
@@ -1728,7 +1728,7 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,
               &vxlan_size, sizeof(uint32_t));
 
        /* update the hdr_bitmap with vxlan */
-       ULP_BITMAP_SET(act->bits, BNXT_ULP_ACTION_BIT_VXLAN_ENCAP);
+       ULP_BITMAP_SET(act->bits, BNXT_ULP_ACT_BIT_VXLAN_ENCAP);
        return BNXT_TF_RC_SUCCESS;
 }
 
@@ -1740,7 +1740,7 @@ ulp_rte_vxlan_decap_act_handler(const struct rte_flow_action *action_item
 {
        /* update the hdr_bitmap with vxlan */
        ULP_BITMAP_SET(params->act_bitmap.bits,
-                      BNXT_ULP_ACTION_BIT_VXLAN_DECAP);
+                      BNXT_ULP_ACT_BIT_VXLAN_DECAP);
        /* Update computational field with tunnel decap info */
        ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_TUN_DECAP, 1);
        ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_TUN, 1);
@@ -1753,7 +1753,7 @@ ulp_rte_drop_act_handler(const struct rte_flow_action *action_item __rte_unused,
                         struct ulp_rte_parser_params *params)
 {
        /* Update the hdr_bitmap with drop */
-       ULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACTION_BIT_DROP);
+       ULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACT_BIT_DROP);
        return BNXT_TF_RC_SUCCESS;
 }
 
@@ -1779,7 +1779,7 @@ ulp_rte_count_act_handler(const struct rte_flow_action *action_item,
        }
 
        /* Update the hdr_bitmap with count */
-       ULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACTION_BIT_COUNT);
+       ULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACT_BIT_COUNT);
        return BNXT_TF_RC_SUCCESS;
 }
 
@@ -1992,7 +1992,7 @@ ulp_rte_of_pop_vlan_act_handler(const struct rte_flow_action *a __rte_unused,
                                struct ulp_rte_parser_params *params)
 {
        /* Update the act_bitmap with pop */
-       ULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACTION_BIT_POP_VLAN);
+       ULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACT_BIT_POP_VLAN);
        return BNXT_TF_RC_SUCCESS;
 }
 
@@ -2017,7 +2017,7 @@ ulp_rte_of_push_vlan_act_handler(const struct rte_flow_action *action_item,
                       &ethertype, BNXT_ULP_ACT_PROP_SZ_PUSH_VLAN);
                /* Update the hdr_bitmap with push vlan */
                ULP_BITMAP_SET(params->act_bitmap.bits,
-                              BNXT_ULP_ACTION_BIT_PUSH_VLAN);
+                              BNXT_ULP_ACT_BIT_PUSH_VLAN);
                return BNXT_TF_RC_SUCCESS;
        }
        BNXT_TF_DBG(ERR, "Parse Error: Push vlan arg is invalid\n");
@@ -2040,7 +2040,7 @@ ulp_rte_of_set_vlan_vid_act_handler(const struct rte_flow_action *action_item,
                       &vid, BNXT_ULP_ACT_PROP_SZ_SET_VLAN_VID);
                /* Update the hdr_bitmap with vlan vid */
                ULP_BITMAP_SET(params->act_bitmap.bits,
-                              BNXT_ULP_ACTION_BIT_SET_VLAN_VID);
+                              BNXT_ULP_ACT_BIT_SET_VLAN_VID);
                return BNXT_TF_RC_SUCCESS;
        }
        BNXT_TF_DBG(ERR, "Parse Error: Vlan vid arg is invalid\n");
@@ -2063,7 +2063,7 @@ ulp_rte_of_set_vlan_pcp_act_handler(const struct rte_flow_action *action_item,
                       &pcp, BNXT_ULP_ACT_PROP_SZ_SET_VLAN_PCP);
                /* Update the hdr_bitmap with vlan vid */
                ULP_BITMAP_SET(params->act_bitmap.bits,
-                              BNXT_ULP_ACTION_BIT_SET_VLAN_PCP);
+                              BNXT_ULP_ACT_BIT_SET_VLAN_PCP);
                return BNXT_TF_RC_SUCCESS;
        }
        BNXT_TF_DBG(ERR, "Parse Error: Vlan pcp arg is invalid\n");
@@ -2084,7 +2084,7 @@ ulp_rte_set_ipv4_src_act_handler(const struct rte_flow_action *action_item,
                       &set_ipv4->ipv4_addr, BNXT_ULP_ACT_PROP_SZ_SET_IPV4_SRC);
                /* Update the hdr_bitmap with set ipv4 src */
                ULP_BITMAP_SET(params->act_bitmap.bits,
-                              BNXT_ULP_ACTION_BIT_SET_IPV4_SRC);
+                              BNXT_ULP_ACT_BIT_SET_IPV4_SRC);
                return BNXT_TF_RC_SUCCESS;
        }
        BNXT_TF_DBG(ERR, "Parse Error: set ipv4 src arg is invalid\n");
@@ -2105,7 +2105,7 @@ ulp_rte_set_ipv4_dst_act_handler(const struct rte_flow_action *action_item,
                       &set_ipv4->ipv4_addr, BNXT_ULP_ACT_PROP_SZ_SET_IPV4_DST);
                /* Update the hdr_bitmap with set ipv4 dst */
                ULP_BITMAP_SET(params->act_bitmap.bits,
-                              BNXT_ULP_ACTION_BIT_SET_IPV4_DST);
+                              BNXT_ULP_ACT_BIT_SET_IPV4_DST);
                return BNXT_TF_RC_SUCCESS;
        }
        BNXT_TF_DBG(ERR, "Parse Error: set ipv4 dst arg is invalid\n");
@@ -2126,7 +2126,7 @@ ulp_rte_set_tp_src_act_handler(const struct rte_flow_action *action_item,
                       &set_tp->port, BNXT_ULP_ACT_PROP_SZ_SET_TP_SRC);
                /* Update the hdr_bitmap with set tp src */
                ULP_BITMAP_SET(params->act_bitmap.bits,
-                              BNXT_ULP_ACTION_BIT_SET_TP_SRC);
+                              BNXT_ULP_ACT_BIT_SET_TP_SRC);
                return BNXT_TF_RC_SUCCESS;
        }
 
@@ -2148,7 +2148,7 @@ ulp_rte_set_tp_dst_act_handler(const struct rte_flow_action *action_item,
                       &set_tp->port, BNXT_ULP_ACT_PROP_SZ_SET_TP_DST);
                /* Update the hdr_bitmap with set tp dst */
                ULP_BITMAP_SET(params->act_bitmap.bits,
-                              BNXT_ULP_ACTION_BIT_SET_TP_DST);
+                              BNXT_ULP_ACT_BIT_SET_TP_DST);
                return BNXT_TF_RC_SUCCESS;
        }
 
@@ -2162,7 +2162,7 @@ ulp_rte_dec_ttl_act_handler(const struct rte_flow_action *act __rte_unused,
                            struct ulp_rte_parser_params *params)
 {
        /* Update the act_bitmap with dec ttl */
-       ULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACTION_BIT_DEC_TTL);
+       ULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACT_BIT_DEC_TTL);
        return BNXT_TF_RC_SUCCESS;
 }
 
@@ -2172,6 +2172,6 @@ ulp_rte_jump_act_handler(const struct rte_flow_action *action_item __rte_unused,
                            struct ulp_rte_parser_params *params)
 {
        /* Update the act_bitmap with dec ttl */
-       ULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACTION_BIT_JUMP);
+       ULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACT_BIT_JUMP);
        return BNXT_TF_RC_SUCCESS;
 }

diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
index 4cb532a..cf11b60 100644 (file)
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
@@ -3,7 +3,7 @@
  * All rights reserved.
  */
 
-/* date: Mon Nov 23 17:33:02 2020 */
+/* date: Tue Dec  1 11:40:24 2020 */
 
 #include "ulp_template_db_enum.h"
 #include "ulp_template_db_field.h"
@@ -42,101 +42,101 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
        [2] = {
        .act_hid = BNXT_ULP_ACT_HID_0001,
        .act_sig = { .bits =
-               BNXT_ULP_ACTION_BIT_DROP |
+               BNXT_ULP_ACT_BIT_DROP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .act_tid = 1
        },
        [3] = {
        .act_hid = BNXT_ULP_ACT_HID_0400,
        .act_sig = { .bits =
-               BNXT_ULP_ACTION_BIT_POP_VLAN |
+               BNXT_ULP_ACT_BIT_POP_VLAN |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .act_tid = 1
        },
        [4] = {
        .act_hid = BNXT_ULP_ACT_HID_0331,
        .act_sig = { .bits =
-               BNXT_ULP_ACTION_BIT_DEC_TTL |
+               BNXT_ULP_ACT_BIT_DEC_TTL |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .act_tid = 1
        },
        [5] = {
        .act_hid = BNXT_ULP_ACT_HID_0010,
        .act_sig = { .bits =
-               BNXT_ULP_ACTION_BIT_VXLAN_DECAP |
+               BNXT_ULP_ACT_BIT_VXLAN_DECAP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .act_tid = 1
        },
        [6] = {
        .act_hid = BNXT_ULP_ACT_HID_0731,
        .act_sig = { .bits =
-               BNXT_ULP_ACTION_BIT_DEC_TTL |
-               BNXT_ULP_ACTION_BIT_POP_VLAN |
+               BNXT_ULP_ACT_BIT_DEC_TTL |
+               BNXT_ULP_ACT_BIT_POP_VLAN |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .act_tid = 1
        },
        [7] = {
        .act_hid = BNXT_ULP_ACT_HID_0341,
        .act_sig = { .bits =
-               BNXT_ULP_ACTION_BIT_VXLAN_DECAP |
-               BNXT_ULP_ACTION_BIT_DEC_TTL |
+               BNXT_ULP_ACT_BIT_VXLAN_DECAP |
+               BNXT_ULP_ACT_BIT_DEC_TTL |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .act_tid = 1
        },
        [8] = {
        .act_hid = BNXT_ULP_ACT_HID_0002,
        .act_sig = { .bits =
-               BNXT_ULP_ACTION_BIT_COUNT |
+               BNXT_ULP_ACT_BIT_COUNT |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .act_tid = 1
        },
        [9] = {
        .act_hid = BNXT_ULP_ACT_HID_0003,
        .act_sig = { .bits =
-               BNXT_ULP_ACTION_BIT_COUNT |
-               BNXT_ULP_ACTION_BIT_DROP |
+               BNXT_ULP_ACT_BIT_COUNT |
+               BNXT_ULP_ACT_BIT_DROP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .act_tid = 1
        },
        [10] = {
        .act_hid = BNXT_ULP_ACT_HID_0402,
        .act_sig = { .bits =
-               BNXT_ULP_ACTION_BIT_COUNT |
-               BNXT_ULP_ACTION_BIT_POP_VLAN |
+               BNXT_ULP_ACT_BIT_COUNT |
+               BNXT_ULP_ACT_BIT_POP_VLAN |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .act_tid = 1
        },
        [11] = {
        .act_hid = BNXT_ULP_ACT_HID_0333,
        .act_sig = { .bits =
-               BNXT_ULP_ACTION_BIT_COUNT |
-               BNXT_ULP_ACTION_BIT_DEC_TTL |
+               BNXT_ULP_ACT_BIT_COUNT |
+               BNXT_ULP_ACT_BIT_DEC_TTL |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .act_tid = 1
        },
        [12] = {
        .act_hid = BNXT_ULP_ACT_HID_0012,
        .act_sig = { .bits =
-               BNXT_ULP_ACTION_BIT_COUNT |
-               BNXT_ULP_ACTION_BIT_VXLAN_DECAP |
+               BNXT_ULP_ACT_BIT_COUNT |
+               BNXT_ULP_ACT_BIT_VXLAN_DECAP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .act_tid = 1
        },
        [13] = {
        .act_hid = BNXT_ULP_ACT_HID_0733,
        .act_sig = { .bits =
-               BNXT_ULP_ACTION_BIT_COUNT |
-               BNXT_ULP_ACTION_BIT_DEC_TTL |
-               BNXT_ULP_ACTION_BIT_POP_VLAN |
+               BNXT_ULP_ACT_BIT_COUNT |
+               BNXT_ULP_ACT_BIT_DEC_TTL |
+               BNXT_ULP_ACT_BIT_POP_VLAN |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .act_tid = 1
        },
        [14] = {
        .act_hid = BNXT_ULP_ACT_HID_0343,
        .act_sig = { .bits =
-               BNXT_ULP_ACTION_BIT_COUNT |
-               BNXT_ULP_ACTION_BIT_VXLAN_DECAP |
-               BNXT_ULP_ACTION_BIT_DEC_TTL |
+               BNXT_ULP_ACT_BIT_COUNT |
+               BNXT_ULP_ACT_BIT_VXLAN_DECAP |
+               BNXT_ULP_ACT_BIT_DEC_TTL |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .act_tid = 1
        }

diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
index 3cee406..9c630d1 100644 (file)
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
@@ -3,7 +3,7 @@
  * All rights reserved.
  */
 
-/* date: Mon Nov 23 17:33:02 2020 */
+/* date: Tue Dec  1 11:40:24 2020 */
 
 #include "ulp_template_db_enum.h"
 #include "ulp_template_db_field.h"
@@ -16,837 +16,1450 @@
  * maps hash id to ulp_class_match_list[] index
  */
 uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = {
-       [BNXT_ULP_CLASS_HID_00fc] = 1,
-       [BNXT_ULP_CLASS_HID_0046] = 2,
-       [BNXT_ULP_CLASS_HID_0056] = 3,
-       [BNXT_ULP_CLASS_HID_00b8] = 4,
-       [BNXT_ULP_CLASS_HID_0041] = 5,
-       [BNXT_ULP_CLASS_HID_00ab] = 6,
-       [BNXT_ULP_CLASS_HID_0053] = 7,
-       [BNXT_ULP_CLASS_HID_00a5] = 8,
-       [BNXT_ULP_CLASS_HID_0069] = 9,
-       [BNXT_ULP_CLASS_HID_009d] = 10,
-       [BNXT_ULP_CLASS_HID_0005] = 11,
-       [BNXT_ULP_CLASS_HID_006f] = 12,
-       [BNXT_ULP_CLASS_HID_00af] = 13,
-       [BNXT_ULP_CLASS_HID_00d3] = 14,
-       [BNXT_ULP_CLASS_HID_005b] = 15,
-       [BNXT_ULP_CLASS_HID_00ad] = 16,
-       [BNXT_ULP_CLASS_HID_0091] = 17,
-       [BNXT_ULP_CLASS_HID_00fb] = 18,
-       [BNXT_ULP_CLASS_HID_0063] = 19,
-       [BNXT_ULP_CLASS_HID_0097] = 20,
-       [BNXT_ULP_CLASS_HID_00cc] = 21,
-       [BNXT_ULP_CLASS_HID_00f0] = 22,
-       [BNXT_ULP_CLASS_HID_00c0] = 23,
-       [BNXT_ULP_CLASS_HID_002a] = 24,
-       [BNXT_ULP_CLASS_HID_00c7] = 25,
-       [BNXT_ULP_CLASS_HID_0029] = 26,
-       [BNXT_ULP_CLASS_HID_00d1] = 27,
-       [BNXT_ULP_CLASS_HID_003b] = 28,
-       [BNXT_ULP_CLASS_HID_00ef] = 29,
-       [BNXT_ULP_CLASS_HID_0013] = 30,
-       [BNXT_ULP_CLASS_HID_009b] = 31,
-       [BNXT_ULP_CLASS_HID_00ed] = 32,
-       [BNXT_ULP_CLASS_HID_002d] = 33,
-       [BNXT_ULP_CLASS_HID_0051] = 34,
-       [BNXT_ULP_CLASS_HID_00d9] = 35,
-       [BNXT_ULP_CLASS_HID_0023] = 36,
-       [BNXT_ULP_CLASS_HID_0017] = 37,
-       [BNXT_ULP_CLASS_HID_0079] = 38,
-       [BNXT_ULP_CLASS_HID_00e1] = 39,
-       [BNXT_ULP_CLASS_HID_0015] = 40
+       [BNXT_ULP_CLASS_HID_07e0] = 1,
+       [BNXT_ULP_CLASS_HID_01dc] = 2,
+       [BNXT_ULP_CLASS_HID_006e] = 3,
+       [BNXT_ULP_CLASS_HID_025a] = 4,
+       [BNXT_ULP_CLASS_HID_0146] = 5,
+       [BNXT_ULP_CLASS_HID_0332] = 6,
+       [BNXT_ULP_CLASS_HID_01c4] = 7,
+       [BNXT_ULP_CLASS_HID_078a] = 8,
+       [BNXT_ULP_CLASS_HID_02ed] = 9,
+       [BNXT_ULP_CLASS_HID_04d9] = 10,
+       [BNXT_ULP_CLASS_HID_036b] = 11,
+       [BNXT_ULP_CLASS_HID_0131] = 12,
+       [BNXT_ULP_CLASS_HID_0217] = 13,
+       [BNXT_ULP_CLASS_HID_03c3] = 14,
+       [BNXT_ULP_CLASS_HID_0295] = 15,
+       [BNXT_ULP_CLASS_HID_0441] = 16,
+       [BNXT_ULP_CLASS_HID_0095] = 17,
+       [BNXT_ULP_CLASS_HID_0241] = 18,
+       [BNXT_ULP_CLASS_HID_04ed] = 19,
+       [BNXT_ULP_CLASS_HID_06d9] = 20,
+       [BNXT_ULP_CLASS_HID_07bf] = 21,
+       [BNXT_ULP_CLASS_HID_016b] = 22,
+       [BNXT_ULP_CLASS_HID_0417] = 23,
+       [BNXT_ULP_CLASS_HID_05c3] = 24,
+       [BNXT_ULP_CLASS_HID_0187] = 25,
+       [BNXT_ULP_CLASS_HID_0373] = 26,
+       [BNXT_ULP_CLASS_HID_0205] = 27,
+       [BNXT_ULP_CLASS_HID_03f1] = 28,
+       [BNXT_ULP_CLASS_HID_00a1] = 29,
+       [BNXT_ULP_CLASS_HID_029d] = 30,
+       [BNXT_ULP_CLASS_HID_012f] = 31,
+       [BNXT_ULP_CLASS_HID_031b] = 32,
+       [BNXT_ULP_CLASS_HID_072f] = 33,
+       [BNXT_ULP_CLASS_HID_011b] = 34,
+       [BNXT_ULP_CLASS_HID_0387] = 35,
+       [BNXT_ULP_CLASS_HID_0573] = 36,
+       [BNXT_ULP_CLASS_HID_0649] = 37,
+       [BNXT_ULP_CLASS_HID_0005] = 38,
+       [BNXT_ULP_CLASS_HID_02a1] = 39,
+       [BNXT_ULP_CLASS_HID_049d] = 40,
+       [BNXT_ULP_CLASS_HID_01ea] = 41,
+       [BNXT_ULP_CLASS_HID_03de] = 42,
+       [BNXT_ULP_CLASS_HID_0672] = 43,
+       [BNXT_ULP_CLASS_HID_0026] = 44,
+       [BNXT_ULP_CLASS_HID_0746] = 45,
+       [BNXT_ULP_CLASS_HID_010a] = 46,
+       [BNXT_ULP_CLASS_HID_03ae] = 47,
+       [BNXT_ULP_CLASS_HID_0592] = 48,
+       [BNXT_ULP_CLASS_HID_07d0] = 49,
+       [BNXT_ULP_CLASS_HID_01ec] = 50,
+       [BNXT_ULP_CLASS_HID_005e] = 51,
+       [BNXT_ULP_CLASS_HID_026a] = 52,
+       [BNXT_ULP_CLASS_HID_0176] = 53,
+       [BNXT_ULP_CLASS_HID_0302] = 54,
+       [BNXT_ULP_CLASS_HID_01f4] = 55,
+       [BNXT_ULP_CLASS_HID_07ba] = 56,
+       [BNXT_ULP_CLASS_HID_06a7] = 57,
+       [BNXT_ULP_CLASS_HID_006b] = 58,
+       [BNXT_ULP_CLASS_HID_0725] = 59,
+       [BNXT_ULP_CLASS_HID_00e9] = 60,
+       [BNXT_ULP_CLASS_HID_05d9] = 61,
+       [BNXT_ULP_CLASS_HID_078d] = 62,
+       [BNXT_ULP_CLASS_HID_065f] = 63,
+       [BNXT_ULP_CLASS_HID_0003] = 64,
+       [BNXT_ULP_CLASS_HID_045f] = 65,
+       [BNXT_ULP_CLASS_HID_0603] = 66,
+       [BNXT_ULP_CLASS_HID_00a7] = 67,
+       [BNXT_ULP_CLASS_HID_026b] = 68,
+       [BNXT_ULP_CLASS_HID_0371] = 69,
+       [BNXT_ULP_CLASS_HID_0525] = 70,
+       [BNXT_ULP_CLASS_HID_07d9] = 71,
+       [BNXT_ULP_CLASS_HID_018d] = 72,
+       [BNXT_ULP_CLASS_HID_0177] = 73,
+       [BNXT_ULP_CLASS_HID_033b] = 74,
+       [BNXT_ULP_CLASS_HID_05df] = 75,
+       [BNXT_ULP_CLASS_HID_0783] = 76,
+       [BNXT_ULP_CLASS_HID_0069] = 77,
+       [BNXT_ULP_CLASS_HID_025d] = 78,
+       [BNXT_ULP_CLASS_HID_00ef] = 79,
+       [BNXT_ULP_CLASS_HID_06a5] = 80,
+       [BNXT_ULP_CLASS_HID_02f1] = 81,
+       [BNXT_ULP_CLASS_HID_04a5] = 82,
+       [BNXT_ULP_CLASS_HID_0377] = 83,
+       [BNXT_ULP_CLASS_HID_053b] = 84,
+       [BNXT_ULP_CLASS_HID_0601] = 85,
+       [BNXT_ULP_CLASS_HID_03df] = 86,
+       [BNXT_ULP_CLASS_HID_0269] = 87,
+       [BNXT_ULP_CLASS_HID_045d] = 88,
+       [BNXT_ULP_CLASS_HID_02dd] = 89,
+       [BNXT_ULP_CLASS_HID_04e9] = 90,
+       [BNXT_ULP_CLASS_HID_035b] = 91,
+       [BNXT_ULP_CLASS_HID_0101] = 92,
+       [BNXT_ULP_CLASS_HID_0227] = 93,
+       [BNXT_ULP_CLASS_HID_03f3] = 94,
+       [BNXT_ULP_CLASS_HID_02a5] = 95,
+       [BNXT_ULP_CLASS_HID_0471] = 96,
+       [BNXT_ULP_CLASS_HID_00a5] = 97,
+       [BNXT_ULP_CLASS_HID_0271] = 98,
+       [BNXT_ULP_CLASS_HID_04dd] = 99,
+       [BNXT_ULP_CLASS_HID_06e9] = 100,
+       [BNXT_ULP_CLASS_HID_078f] = 101,
+       [BNXT_ULP_CLASS_HID_015b] = 102,
+       [BNXT_ULP_CLASS_HID_0427] = 103,
+       [BNXT_ULP_CLASS_HID_05f3] = 104,
+       [BNXT_ULP_CLASS_HID_01b7] = 105,
+       [BNXT_ULP_CLASS_HID_0343] = 106,
+       [BNXT_ULP_CLASS_HID_0235] = 107,
+       [BNXT_ULP_CLASS_HID_03c1] = 108,
+       [BNXT_ULP_CLASS_HID_0091] = 109,
+       [BNXT_ULP_CLASS_HID_02ad] = 110,
+       [BNXT_ULP_CLASS_HID_011f] = 111,
+       [BNXT_ULP_CLASS_HID_032b] = 112,
+       [BNXT_ULP_CLASS_HID_071f] = 113,
+       [BNXT_ULP_CLASS_HID_012b] = 114,
+       [BNXT_ULP_CLASS_HID_03b7] = 115,
+       [BNXT_ULP_CLASS_HID_0543] = 116,
+       [BNXT_ULP_CLASS_HID_0679] = 117,
+       [BNXT_ULP_CLASS_HID_0035] = 118,
+       [BNXT_ULP_CLASS_HID_0291] = 119,
+       [BNXT_ULP_CLASS_HID_04ad] = 120,
+       [BNXT_ULP_CLASS_HID_01da] = 121,
+       [BNXT_ULP_CLASS_HID_03ee] = 122,
+       [BNXT_ULP_CLASS_HID_0642] = 123,
+       [BNXT_ULP_CLASS_HID_0016] = 124,
+       [BNXT_ULP_CLASS_HID_0776] = 125,
+       [BNXT_ULP_CLASS_HID_013a] = 126,
+       [BNXT_ULP_CLASS_HID_039e] = 127,
+       [BNXT_ULP_CLASS_HID_05a2] = 128,
+       [BNXT_ULP_CLASS_HID_0697] = 129,
+       [BNXT_ULP_CLASS_HID_005b] = 130,
+       [BNXT_ULP_CLASS_HID_0715] = 131,
+       [BNXT_ULP_CLASS_HID_00d9] = 132,
+       [BNXT_ULP_CLASS_HID_05e9] = 133,
+       [BNXT_ULP_CLASS_HID_07bd] = 134,
+       [BNXT_ULP_CLASS_HID_066f] = 135,
+       [BNXT_ULP_CLASS_HID_0033] = 136,
+       [BNXT_ULP_CLASS_HID_046f] = 137,
+       [BNXT_ULP_CLASS_HID_0633] = 138,
+       [BNXT_ULP_CLASS_HID_0097] = 139,
+       [BNXT_ULP_CLASS_HID_025b] = 140,
+       [BNXT_ULP_CLASS_HID_0341] = 141,
+       [BNXT_ULP_CLASS_HID_0515] = 142,
+       [BNXT_ULP_CLASS_HID_07e9] = 143,
+       [BNXT_ULP_CLASS_HID_01bd] = 144,
+       [BNXT_ULP_CLASS_HID_0147] = 145,
+       [BNXT_ULP_CLASS_HID_030b] = 146,
+       [BNXT_ULP_CLASS_HID_05ef] = 147,
+       [BNXT_ULP_CLASS_HID_07b3] = 148,
+       [BNXT_ULP_CLASS_HID_0059] = 149,
+       [BNXT_ULP_CLASS_HID_026d] = 150,
+       [BNXT_ULP_CLASS_HID_00df] = 151,
+       [BNXT_ULP_CLASS_HID_0695] = 152,
+       [BNXT_ULP_CLASS_HID_02c1] = 153,
+       [BNXT_ULP_CLASS_HID_0495] = 154,
+       [BNXT_ULP_CLASS_HID_0347] = 155,
+       [BNXT_ULP_CLASS_HID_050b] = 156,
+       [BNXT_ULP_CLASS_HID_0631] = 157,
+       [BNXT_ULP_CLASS_HID_03ef] = 158,
+       [BNXT_ULP_CLASS_HID_0259] = 159,
+       [BNXT_ULP_CLASS_HID_046d] = 160
 };
 
 /* Array for the proto matcher list */
 struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
        [1] = {
-       .class_hid = BNXT_ULP_CLASS_HID_00fc,
+       .class_hid = BNXT_ULP_CLASS_HID_07e0,
        .class_tid = 1,
        .hdr_sig_id = 0,
        .flow_sig_id = 0,
        .hdr_sig = { .bits =
                BNXT_ULP_HDR_BIT_O_ETH |
-               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
                BNXT_ULP_HDR_BIT_O_TCP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .field_sig = { .bits =
-               BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |
-               BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR |
-               BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR |
                BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT |
                BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT |
                BNXT_ULP_MATCH_TYPE_BITMASK_EM },
        },
        [2] = {
-       .class_hid = BNXT_ULP_CLASS_HID_0046,
+       .class_hid = BNXT_ULP_CLASS_HID_01dc,
        .class_tid = 1,
        .hdr_sig_id = 0,
        .flow_sig_id = 1,
        .hdr_sig = { .bits =
                BNXT_ULP_HDR_BIT_O_ETH |
-               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
                BNXT_ULP_HDR_BIT_O_TCP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .field_sig = { .bits =
-               BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |
                BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |
-               BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR |
-               BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR |
                BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT |
                BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT |
                BNXT_ULP_MATCH_TYPE_BITMASK_EM },
        },
        [3] = {
-       .class_hid = BNXT_ULP_CLASS_HID_0056,
+       .class_hid = BNXT_ULP_CLASS_HID_006e,
        .class_tid = 1,
        .hdr_sig_id = 0,
-       .flow_sig_id = 1,
+       .flow_sig_id = 2,
        .hdr_sig = { .bits =
                BNXT_ULP_HDR_BIT_O_ETH |
-               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
                BNXT_ULP_HDR_BIT_O_TCP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .field_sig = { .bits =
-               BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |
-               BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID |
-               BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR |
-               BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR |
                BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT |
                BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT |
                BNXT_ULP_MATCH_TYPE_BITMASK_EM },
        },
        [4] = {
-       .class_hid = BNXT_ULP_CLASS_HID_00b8,
+       .class_hid = BNXT_ULP_CLASS_HID_025a,
        .class_tid = 1,
        .hdr_sig_id = 0,
-       .flow_sig_id = 1,
+       .flow_sig_id = 2,
        .hdr_sig = { .bits =
                BNXT_ULP_HDR_BIT_O_ETH |
-               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
                BNXT_ULP_HDR_BIT_O_TCP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .field_sig = { .bits =
-               BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |
                BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |
-               BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID |
-               BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR |
-               BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR |
                BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT |
                BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT |
                BNXT_ULP_MATCH_TYPE_BITMASK_EM },
        },
        [5] = {
-       .class_hid = BNXT_ULP_CLASS_HID_0041,
+       .class_hid = BNXT_ULP_CLASS_HID_0146,
        .class_tid = 1,
-       .hdr_sig_id = 1,
-       .flow_sig_id = 1,
+       .hdr_sig_id = 0,
+       .flow_sig_id = 2,
        .hdr_sig = { .bits =
                BNXT_ULP_HDR_BIT_O_ETH |
-               BNXT_ULP_HDR_BIT_OO_VLAN |
-               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
                BNXT_ULP_HDR_BIT_O_TCP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .field_sig = { .bits =
-               BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
-               BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
-               BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
-               BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
-               BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID |
+               BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT |
                BNXT_ULP_MATCH_TYPE_BITMASK_EM },
        },
        [6] = {
-       .class_hid = BNXT_ULP_CLASS_HID_00ab,
+       .class_hid = BNXT_ULP_CLASS_HID_0332,
        .class_tid = 1,
-       .hdr_sig_id = 1,
-       .flow_sig_id = 1,
+       .hdr_sig_id = 0,
+       .flow_sig_id = 2,
        .hdr_sig = { .bits =
                BNXT_ULP_HDR_BIT_O_ETH |
-               BNXT_ULP_HDR_BIT_OO_VLAN |
-               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
                BNXT_ULP_HDR_BIT_O_TCP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .field_sig = { .bits =
-               BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
-               BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
-               BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
-               BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
-               BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
-               BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID |
+               BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT |
                BNXT_ULP_MATCH_TYPE_BITMASK_EM },
        },
        [7] = {
-       .class_hid = BNXT_ULP_CLASS_HID_0053,
+       .class_hid = BNXT_ULP_CLASS_HID_01c4,
        .class_tid = 1,
-       .hdr_sig_id = 1,
-       .flow_sig_id = 1,
+       .hdr_sig_id = 0,
+       .flow_sig_id = 2,
        .hdr_sig = { .bits =
                BNXT_ULP_HDR_BIT_O_ETH |
-               BNXT_ULP_HDR_BIT_OO_VLAN |
-               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
                BNXT_ULP_HDR_BIT_O_TCP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .field_sig = { .bits =
-               BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
-               BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |
-               BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
-               BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
-               BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
-               BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID |
+               BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT |
                BNXT_ULP_MATCH_TYPE_BITMASK_EM },
        },
        [8] = {
-       .class_hid = BNXT_ULP_CLASS_HID_00a5,
+       .class_hid = BNXT_ULP_CLASS_HID_078a,
        .class_tid = 1,
-       .hdr_sig_id = 1,
+       .hdr_sig_id = 0,
        .flow_sig_id = 2,
        .hdr_sig = { .bits =
                BNXT_ULP_HDR_BIT_O_ETH |
-               BNXT_ULP_HDR_BIT_OO_VLAN |
-               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
                BNXT_ULP_HDR_BIT_O_TCP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .field_sig = { .bits =
-               BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
-               BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
-               BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |
-               BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
-               BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
-               BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
-               BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID |
+               BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT |
                BNXT_ULP_MATCH_TYPE_BITMASK_EM },
        },
        [9] = {
-       .class_hid = BNXT_ULP_CLASS_HID_0069,
+       .class_hid = BNXT_ULP_CLASS_HID_02ed,
        .class_tid = 1,
        .hdr_sig_id = 1,
        .flow_sig_id = 2,
        .hdr_sig = { .bits =
                BNXT_ULP_HDR_BIT_O_ETH |
                BNXT_ULP_HDR_BIT_OO_VLAN |
-               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
                BNXT_ULP_HDR_BIT_O_TCP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .field_sig = { .bits =
-               BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
-               BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |
-               BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
-               BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |
                BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
                BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
                BNXT_ULP_MATCH_TYPE_BITMASK_EM },
        },
        [10] = {
-       .class_hid = BNXT_ULP_CLASS_HID_009d,
+       .class_hid = BNXT_ULP_CLASS_HID_04d9,
        .class_tid = 1,
        .hdr_sig_id = 1,
        .flow_sig_id = 2,
        .hdr_sig = { .bits =
                BNXT_ULP_HDR_BIT_O_ETH |
                BNXT_ULP_HDR_BIT_OO_VLAN |
-               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
                BNXT_ULP_HDR_BIT_O_TCP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .field_sig = { .bits =
-               BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
                BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
-               BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |
-               BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
-               BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |
                BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
                BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
                BNXT_ULP_MATCH_TYPE_BITMASK_EM },
        },
        [11] = {
-       .class_hid = BNXT_ULP_CLASS_HID_0005,
+       .class_hid = BNXT_ULP_CLASS_HID_036b,
        .class_tid = 1,
        .hdr_sig_id = 1,
        .flow_sig_id = 2,
        .hdr_sig = { .bits =
                BNXT_ULP_HDR_BIT_O_ETH |
                BNXT_ULP_HDR_BIT_OO_VLAN |
-               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
                BNXT_ULP_HDR_BIT_O_TCP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .field_sig = { .bits =
-               BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
-               BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |
-               BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |
-               BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
-               BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |
                BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
                BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
                BNXT_ULP_MATCH_TYPE_BITMASK_EM },
        },
        [12] = {
-       .class_hid = BNXT_ULP_CLASS_HID_006f,
+       .class_hid = BNXT_ULP_CLASS_HID_0131,
        .class_tid = 1,
        .hdr_sig_id = 1,
        .flow_sig_id = 2,
        .hdr_sig = { .bits =
                BNXT_ULP_HDR_BIT_O_ETH |
                BNXT_ULP_HDR_BIT_OO_VLAN |
-               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
                BNXT_ULP_HDR_BIT_O_TCP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .field_sig = { .bits =
-               BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
                BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
-               BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |
-               BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |
-               BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
-               BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |
                BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
                BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
                BNXT_ULP_MATCH_TYPE_BITMASK_EM },
        },
        [13] = {
-       .class_hid = BNXT_ULP_CLASS_HID_00af,
+       .class_hid = BNXT_ULP_CLASS_HID_0217,
        .class_tid = 1,
        .hdr_sig_id = 1,
        .flow_sig_id = 2,
        .hdr_sig = { .bits =
                BNXT_ULP_HDR_BIT_O_ETH |
                BNXT_ULP_HDR_BIT_OO_VLAN |
-               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
                BNXT_ULP_HDR_BIT_O_TCP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .field_sig = { .bits =
-               BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
-               BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
-               BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
-               BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |
                BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
                BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
                BNXT_ULP_MATCH_TYPE_BITMASK_EM },
        },
        [14] = {
-       .class_hid = BNXT_ULP_CLASS_HID_00d3,
+       .class_hid = BNXT_ULP_CLASS_HID_03c3,
        .class_tid = 1,
        .hdr_sig_id = 1,
-       .flow_sig_id = 2,
+       .flow_sig_id = 3,
        .hdr_sig = { .bits =
                BNXT_ULP_HDR_BIT_O_ETH |
                BNXT_ULP_HDR_BIT_OO_VLAN |
-               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
                BNXT_ULP_HDR_BIT_O_TCP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .field_sig = { .bits =
-               BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
                BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
-               BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
-               BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
-               BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |
                BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
                BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
                BNXT_ULP_MATCH_TYPE_BITMASK_EM },
        },
        [15] = {
-       .class_hid = BNXT_ULP_CLASS_HID_005b,
+       .class_hid = BNXT_ULP_CLASS_HID_0295,
        .class_tid = 1,
        .hdr_sig_id = 1,
-       .flow_sig_id = 2,
+       .flow_sig_id = 4,
        .hdr_sig = { .bits =
                BNXT_ULP_HDR_BIT_O_ETH |
                BNXT_ULP_HDR_BIT_OO_VLAN |
-               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
                BNXT_ULP_HDR_BIT_O_TCP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .field_sig = { .bits =
-               BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
                BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |
-               BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
-               BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
-               BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |
                BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
                BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
                BNXT_ULP_MATCH_TYPE_BITMASK_EM },
        },
        [16] = {
-       .class_hid = BNXT_ULP_CLASS_HID_00ad,
+       .class_hid = BNXT_ULP_CLASS_HID_0441,
        .class_tid = 1,
        .hdr_sig_id = 1,
-       .flow_sig_id = 2,
+       .flow_sig_id = 4,
        .hdr_sig = { .bits =
                BNXT_ULP_HDR_BIT_O_ETH |
                BNXT_ULP_HDR_BIT_OO_VLAN |
-               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
                BNXT_ULP_HDR_BIT_O_TCP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .field_sig = { .bits =
-               BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
                BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
                BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |
-               BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
-               BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
-               BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |
                BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
                BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
                BNXT_ULP_MATCH_TYPE_BITMASK_EM },
        },
        [17] = {
-       .class_hid = BNXT_ULP_CLASS_HID_0091,
+       .class_hid = BNXT_ULP_CLASS_HID_0095,
        .class_tid = 1,
        .hdr_sig_id = 1,
-       .flow_sig_id = 2,
+       .flow_sig_id = 4,
        .hdr_sig = { .bits =
                BNXT_ULP_HDR_BIT_O_ETH |
                BNXT_ULP_HDR_BIT_OO_VLAN |
-               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
                BNXT_ULP_HDR_BIT_O_TCP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .field_sig = { .bits =
-               BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
                BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |
-               BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
-               BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
-               BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |
                BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
                BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
                BNXT_ULP_MATCH_TYPE_BITMASK_EM },
        },
        [18] = {
-       .class_hid = BNXT_ULP_CLASS_HID_00fb,
+       .class_hid = BNXT_ULP_CLASS_HID_0241,
        .class_tid = 1,
        .hdr_sig_id = 1,
-       .flow_sig_id = 2,
+       .flow_sig_id = 4,
        .hdr_sig = { .bits =
                BNXT_ULP_HDR_BIT_O_ETH |
                BNXT_ULP_HDR_BIT_OO_VLAN |
-               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
                BNXT_ULP_HDR_BIT_O_TCP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .field_sig = { .bits =
-               BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
                BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
                BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |
-               BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
-               BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
-               BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |
                BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
                BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
                BNXT_ULP_MATCH_TYPE_BITMASK_EM },
        },
        [19] = {
-       .class_hid = BNXT_ULP_CLASS_HID_0063,
+       .class_hid = BNXT_ULP_CLASS_HID_04ed,
        .class_tid = 1,
        .hdr_sig_id = 1,
-       .flow_sig_id = 2,
+       .flow_sig_id = 4,
        .hdr_sig = { .bits =
                BNXT_ULP_HDR_BIT_O_ETH |
                BNXT_ULP_HDR_BIT_OO_VLAN |
-               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
                BNXT_ULP_HDR_BIT_O_TCP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .field_sig = { .bits =
-               BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
-               BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
                BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |
-               BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
-               BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
-               BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |
                BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
                BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
                BNXT_ULP_MATCH_TYPE_BITMASK_EM },
        },
        [20] = {
-       .class_hid = BNXT_ULP_CLASS_HID_0097,
+       .class_hid = BNXT_ULP_CLASS_HID_06d9,
        .class_tid = 1,
        .hdr_sig_id = 1,
-       .flow_sig_id = 2,
+       .flow_sig_id = 4,
        .hdr_sig = { .bits =
                BNXT_ULP_HDR_BIT_O_ETH |
                BNXT_ULP_HDR_BIT_OO_VLAN |
-               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
                BNXT_ULP_HDR_BIT_O_TCP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .field_sig = { .bits =
-               BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
                BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
-               BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
                BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |
-               BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |
-               BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |
-               BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |
                BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
                BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
                BNXT_ULP_MATCH_TYPE_BITMASK_EM },
        },
        [21] = {
-       .class_hid = BNXT_ULP_CLASS_HID_00cc,
-       .class_tid = 2,
-       .hdr_sig_id = 0,
-       .flow_sig_id = 2,
+       .class_hid = BNXT_ULP_CLASS_HID_07bf,
+       .class_tid = 1,
+       .hdr_sig_id = 1,
+       .flow_sig_id = 4,
        .hdr_sig = { .bits =
                BNXT_ULP_HDR_BIT_O_ETH |
-               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
                BNXT_ULP_HDR_BIT_O_TCP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .field_sig = { .bits =
-               BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC |
-               BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |
-               BNXT_ULP_HF2_0_BITMASK_O_TCP_SRC_PORT |
-               BNXT_ULP_HF2_0_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
                BNXT_ULP_MATCH_TYPE_BITMASK_EM },
        },
        [22] = {
-       .class_hid = BNXT_ULP_CLASS_HID_00f0,
-       .class_tid = 2,
-       .hdr_sig_id = 0,
-       .flow_sig_id = 3,
+       .class_hid = BNXT_ULP_CLASS_HID_016b,
+       .class_tid = 1,
+       .hdr_sig_id = 1,
+       .flow_sig_id = 4,
        .hdr_sig = { .bits =
                BNXT_ULP_HDR_BIT_O_ETH |
-               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
                BNXT_ULP_HDR_BIT_O_TCP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .field_sig = { .bits =
-               BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE |
-               BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC |
-               BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |
-               BNXT_ULP_HF2_0_BITMASK_O_TCP_SRC_PORT |
-               BNXT_ULP_HF2_0_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
                BNXT_ULP_MATCH_TYPE_BITMASK_EM },
        },
        [23] = {
-       .class_hid = BNXT_ULP_CLASS_HID_00c0,
-       .class_tid = 2,
-       .hdr_sig_id = 0,
-       .flow_sig_id = 3,
+       .class_hid = BNXT_ULP_CLASS_HID_0417,
+       .class_tid = 1,
+       .hdr_sig_id = 1,
+       .flow_sig_id = 4,
        .hdr_sig = { .bits =
                BNXT_ULP_HDR_BIT_O_ETH |
-               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
                BNXT_ULP_HDR_BIT_O_TCP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .field_sig = { .bits =
-               BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC |
-               BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID |
-               BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |
-               BNXT_ULP_HF2_0_BITMASK_O_TCP_SRC_PORT |
-               BNXT_ULP_HF2_0_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
                BNXT_ULP_MATCH_TYPE_BITMASK_EM },
        },
        [24] = {
-       .class_hid = BNXT_ULP_CLASS_HID_002a,
-       .class_tid = 2,
-       .hdr_sig_id = 0,
-       .flow_sig_id = 3,
+       .class_hid = BNXT_ULP_CLASS_HID_05c3,
+       .class_tid = 1,
+       .hdr_sig_id = 1,
+       .flow_sig_id = 4,
        .hdr_sig = { .bits =
                BNXT_ULP_HDR_BIT_O_ETH |
-               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
                BNXT_ULP_HDR_BIT_O_TCP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .field_sig = { .bits =
-               BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE |
-               BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC |
-               BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID |
-               BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |
-               BNXT_ULP_HF2_0_BITMASK_O_TCP_SRC_PORT |
-               BNXT_ULP_HF2_0_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
                BNXT_ULP_MATCH_TYPE_BITMASK_EM },
        },
        [25] = {
-       .class_hid = BNXT_ULP_CLASS_HID_00c7,
-       .class_tid = 2,
+       .class_hid = BNXT_ULP_CLASS_HID_0187,
+       .class_tid = 1,
        .hdr_sig_id = 1,
-       .flow_sig_id = 3,
+       .flow_sig_id = 4,
        .hdr_sig = { .bits =
                BNXT_ULP_HDR_BIT_O_ETH |
                BNXT_ULP_HDR_BIT_OO_VLAN |
-               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
                BNXT_ULP_HDR_BIT_O_TCP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .field_sig = { .bits =
-               BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
-               BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
-               BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
-               BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
                BNXT_ULP_MATCH_TYPE_BITMASK_EM },
        },
        [26] = {
-       .class_hid = BNXT_ULP_CLASS_HID_0029,
-       .class_tid = 2,
+       .class_hid = BNXT_ULP_CLASS_HID_0373,
+       .class_tid = 1,
        .hdr_sig_id = 1,
-       .flow_sig_id = 3,
+       .flow_sig_id = 4,
        .hdr_sig = { .bits =
                BNXT_ULP_HDR_BIT_O_ETH |
                BNXT_ULP_HDR_BIT_OO_VLAN |
-               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
                BNXT_ULP_HDR_BIT_O_TCP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .field_sig = { .bits =
-               BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
-               BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
-               BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
-               BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
-               BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
                BNXT_ULP_MATCH_TYPE_BITMASK_EM },
        },
        [27] = {
-       .class_hid = BNXT_ULP_CLASS_HID_00d1,
-       .class_tid = 2,
+       .class_hid = BNXT_ULP_CLASS_HID_0205,
+       .class_tid = 1,
        .hdr_sig_id = 1,
-       .flow_sig_id = 3,
+       .flow_sig_id = 4,
        .hdr_sig = { .bits =
                BNXT_ULP_HDR_BIT_O_ETH |
                BNXT_ULP_HDR_BIT_OO_VLAN |
-               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
                BNXT_ULP_HDR_BIT_O_TCP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .field_sig = { .bits =
-               BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
-               BNXT_ULP_HF2_1_BITMASK_OO_VLAN_VID |
-               BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
-               BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
-               BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
                BNXT_ULP_MATCH_TYPE_BITMASK_EM },
        },
        [28] = {
-       .class_hid = BNXT_ULP_CLASS_HID_003b,
-       .class_tid = 2,
+       .class_hid = BNXT_ULP_CLASS_HID_03f1,
+       .class_tid = 1,
        .hdr_sig_id = 1,
        .flow_sig_id = 4,
        .hdr_sig = { .bits =
                BNXT_ULP_HDR_BIT_O_ETH |
                BNXT_ULP_HDR_BIT_OO_VLAN |
-               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
                BNXT_ULP_HDR_BIT_O_TCP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .field_sig = { .bits =
-               BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
-               BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
-               BNXT_ULP_HF2_1_BITMASK_OO_VLAN_VID |
-               BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
-               BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
-               BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
                BNXT_ULP_MATCH_TYPE_BITMASK_EM },
        },
        [29] = {
-       .class_hid = BNXT_ULP_CLASS_HID_00ef,
-       .class_tid = 2,
+       .class_hid = BNXT_ULP_CLASS_HID_00a1,
+       .class_tid = 1,
        .hdr_sig_id = 1,
        .flow_sig_id = 4,
        .hdr_sig = { .bits =
                BNXT_ULP_HDR_BIT_O_ETH |
                BNXT_ULP_HDR_BIT_OO_VLAN |
-               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
                BNXT_ULP_HDR_BIT_O_TCP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .field_sig = { .bits =
-               BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
-               BNXT_ULP_HF2_1_BITMASK_OO_VLAN_TYPE |
-               BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
-               BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
-               BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
                BNXT_ULP_MATCH_TYPE_BITMASK_EM },
        },
        [30] = {
-       .class_hid = BNXT_ULP_CLASS_HID_0013,
-       .class_tid = 2,
+       .class_hid = BNXT_ULP_CLASS_HID_029d,
+       .class_tid = 1,
        .hdr_sig_id = 1,
        .flow_sig_id = 4,
        .hdr_sig = { .bits =
                BNXT_ULP_HDR_BIT_O_ETH |
                BNXT_ULP_HDR_BIT_OO_VLAN |
-               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
                BNXT_ULP_HDR_BIT_O_TCP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .field_sig = { .bits =
-               BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
-               BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
-               BNXT_ULP_HF2_1_BITMASK_OO_VLAN_TYPE |
-               BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
-               BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
-               BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
                BNXT_ULP_MATCH_TYPE_BITMASK_EM },
        },
        [31] = {
-       .class_hid = BNXT_ULP_CLASS_HID_009b,
-       .class_tid = 2,
+       .class_hid = BNXT_ULP_CLASS_HID_012f,
+       .class_tid = 1,
        .hdr_sig_id = 1,
        .flow_sig_id = 4,
        .hdr_sig = { .bits =
                BNXT_ULP_HDR_BIT_O_ETH |
                BNXT_ULP_HDR_BIT_OO_VLAN |
-               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
                BNXT_ULP_HDR_BIT_O_TCP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .field_sig = { .bits =
-               BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
-               BNXT_ULP_HF2_1_BITMASK_OO_VLAN_VID |
-               BNXT_ULP_HF2_1_BITMASK_OO_VLAN_TYPE |
-               BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
-               BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
-               BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
                BNXT_ULP_MATCH_TYPE_BITMASK_EM },
        },
        [32] = {
-       .class_hid = BNXT_ULP_CLASS_HID_00ed,
-       .class_tid = 2,
+       .class_hid = BNXT_ULP_CLASS_HID_031b,
+       .class_tid = 1,
        .hdr_sig_id = 1,
        .flow_sig_id = 4,
        .hdr_sig = { .bits =
                BNXT_ULP_HDR_BIT_O_ETH |
                BNXT_ULP_HDR_BIT_OO_VLAN |
-               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
                BNXT_ULP_HDR_BIT_O_TCP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .field_sig = { .bits =
-               BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
-               BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
-               BNXT_ULP_HF2_1_BITMASK_OO_VLAN_VID |
-               BNXT_ULP_HF2_1_BITMASK_OO_VLAN_TYPE |
-               BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
-               BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
-               BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
                BNXT_ULP_MATCH_TYPE_BITMASK_EM },
        },
        [33] = {
-       .class_hid = BNXT_ULP_CLASS_HID_002d,
-       .class_tid = 2,
+       .class_hid = BNXT_ULP_CLASS_HID_072f,
+       .class_tid = 1,
        .hdr_sig_id = 1,
        .flow_sig_id = 4,
        .hdr_sig = { .bits =
                BNXT_ULP_HDR_BIT_O_ETH |
                BNXT_ULP_HDR_BIT_OO_VLAN |
-               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
                BNXT_ULP_HDR_BIT_O_TCP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .field_sig = { .bits =
-               BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
-               BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
-               BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
-               BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
-               BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
                BNXT_ULP_MATCH_TYPE_BITMASK_EM },
        },
        [34] = {
-       .class_hid = BNXT_ULP_CLASS_HID_0051,
-       .class_tid = 2,
+       .class_hid = BNXT_ULP_CLASS_HID_011b,
+       .class_tid = 1,
        .hdr_sig_id = 1,
        .flow_sig_id = 4,
        .hdr_sig = { .bits =
                BNXT_ULP_HDR_BIT_O_ETH |
                BNXT_ULP_HDR_BIT_OO_VLAN |
-               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
                BNXT_ULP_HDR_BIT_O_TCP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .field_sig = { .bits =
-               BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
-               BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
-               BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
-               BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
-               BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
-               BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
                BNXT_ULP_MATCH_TYPE_BITMASK_EM },
        },
        [35] = {
-       .class_hid = BNXT_ULP_CLASS_HID_00d9,
-       .class_tid = 2,
+       .class_hid = BNXT_ULP_CLASS_HID_0387,
+       .class_tid = 1,
        .hdr_sig_id = 1,
        .flow_sig_id = 4,
        .hdr_sig = { .bits =
                BNXT_ULP_HDR_BIT_O_ETH |
                BNXT_ULP_HDR_BIT_OO_VLAN |
-               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
                BNXT_ULP_HDR_BIT_O_TCP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .field_sig = { .bits =
-               BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
-               BNXT_ULP_HF2_1_BITMASK_OO_VLAN_VID |
-               BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
-               BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
-               BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
-               BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
                BNXT_ULP_MATCH_TYPE_BITMASK_EM },
        },
        [36] = {
-       .class_hid = BNXT_ULP_CLASS_HID_0023,
-       .class_tid = 2,
+       .class_hid = BNXT_ULP_CLASS_HID_0573,
+       .class_tid = 1,
        .hdr_sig_id = 1,
        .flow_sig_id = 4,
        .hdr_sig = { .bits =
                BNXT_ULP_HDR_BIT_O_ETH |
                BNXT_ULP_HDR_BIT_OO_VLAN |
-               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
                BNXT_ULP_HDR_BIT_O_TCP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .field_sig = { .bits =
-               BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
-               BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
-               BNXT_ULP_HF2_1_BITMASK_OO_VLAN_VID |
-               BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
-               BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
-               BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
-               BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
                BNXT_ULP_MATCH_TYPE_BITMASK_EM },
        },
        [37] = {
-       .class_hid = BNXT_ULP_CLASS_HID_0017,
-       .class_tid = 2,
+       .class_hid = BNXT_ULP_CLASS_HID_0649,
+       .class_tid = 1,
        .hdr_sig_id = 1,
        .flow_sig_id = 4,
        .hdr_sig = { .bits =
                BNXT_ULP_HDR_BIT_O_ETH |
                BNXT_ULP_HDR_BIT_OO_VLAN |
-               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
                BNXT_ULP_HDR_BIT_O_TCP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .field_sig = { .bits =
-               BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
-               BNXT_ULP_HF2_1_BITMASK_OO_VLAN_TYPE |
-               BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
-               BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
-               BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
-               BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
                BNXT_ULP_MATCH_TYPE_BITMASK_EM },
        },
        [38] = {
-       .class_hid = BNXT_ULP_CLASS_HID_0079,
-       .class_tid = 2,
+       .class_hid = BNXT_ULP_CLASS_HID_0005,
+       .class_tid = 1,
        .hdr_sig_id = 1,
        .flow_sig_id = 4,
        .hdr_sig = { .bits =
                BNXT_ULP_HDR_BIT_O_ETH |
                BNXT_ULP_HDR_BIT_OO_VLAN |
-               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
                BNXT_ULP_HDR_BIT_O_TCP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .field_sig = { .bits =
-               BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
-               BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
-               BNXT_ULP_HF2_1_BITMASK_OO_VLAN_TYPE |
-               BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
-               BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
-               BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
-               BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
                BNXT_ULP_MATCH_TYPE_BITMASK_EM },
        },
        [39] = {
-       .class_hid = BNXT_ULP_CLASS_HID_00e1,
-       .class_tid = 2,
+       .class_hid = BNXT_ULP_CLASS_HID_02a1,
+       .class_tid = 1,
        .hdr_sig_id = 1,
        .flow_sig_id = 4,
        .hdr_sig = { .bits =
                BNXT_ULP_HDR_BIT_O_ETH |
                BNXT_ULP_HDR_BIT_OO_VLAN |
-               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
                BNXT_ULP_HDR_BIT_O_TCP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .field_sig = { .bits =
-               BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
-               BNXT_ULP_HF2_1_BITMASK_OO_VLAN_VID |
-               BNXT_ULP_HF2_1_BITMASK_OO_VLAN_TYPE |
-               BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
-               BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
-               BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
-               BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
                BNXT_ULP_MATCH_TYPE_BITMASK_EM },
        },
        [40] = {
-       .class_hid = BNXT_ULP_CLASS_HID_0015,
-       .class_tid = 2,
+       .class_hid = BNXT_ULP_CLASS_HID_049d,
+       .class_tid = 1,
        .hdr_sig_id = 1,
        .flow_sig_id = 4,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
+               BNXT_ULP_HDR_BIT_O_TCP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [41] = {
+       .class_hid = BNXT_ULP_CLASS_HID_01ea,
+       .class_tid = 1,
+       .hdr_sig_id = 2,
+       .flow_sig_id = 4,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_TCP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [42] = {
+       .class_hid = BNXT_ULP_CLASS_HID_03de,
+       .class_tid = 1,
+       .hdr_sig_id = 2,
+       .flow_sig_id = 5,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_TCP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [43] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0672,
+       .class_tid = 1,
+       .hdr_sig_id = 2,
+       .flow_sig_id = 6,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_TCP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [44] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0026,
+       .class_tid = 1,
+       .hdr_sig_id = 2,
+       .flow_sig_id = 6,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_TCP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [45] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0746,
+       .class_tid = 1,
+       .hdr_sig_id = 2,
+       .flow_sig_id = 6,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_TCP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+               BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [46] = {
+       .class_hid = BNXT_ULP_CLASS_HID_010a,
+       .class_tid = 1,
+       .hdr_sig_id = 2,
+       .flow_sig_id = 6,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_TCP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+               BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [47] = {
+       .class_hid = BNXT_ULP_CLASS_HID_03ae,
+       .class_tid = 1,
+       .hdr_sig_id = 2,
+       .flow_sig_id = 6,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_TCP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+               BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [48] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0592,
+       .class_tid = 1,
+       .hdr_sig_id = 2,
+       .flow_sig_id = 6,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_TCP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |
+               BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [49] = {
+       .class_hid = BNXT_ULP_CLASS_HID_07d0,
+       .class_tid = 1,
+       .hdr_sig_id = 3,
+       .flow_sig_id = 6,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [50] = {
+       .class_hid = BNXT_ULP_CLASS_HID_01ec,
+       .class_tid = 1,
+       .hdr_sig_id = 3,
+       .flow_sig_id = 7,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [51] = {
+       .class_hid = BNXT_ULP_CLASS_HID_005e,
+       .class_tid = 1,
+       .hdr_sig_id = 3,
+       .flow_sig_id = 8,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [52] = {
+       .class_hid = BNXT_ULP_CLASS_HID_026a,
+       .class_tid = 1,
+       .hdr_sig_id = 3,
+       .flow_sig_id = 8,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [53] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0176,
+       .class_tid = 1,
+       .hdr_sig_id = 3,
+       .flow_sig_id = 8,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID |
+               BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [54] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0302,
+       .class_tid = 1,
+       .hdr_sig_id = 3,
+       .flow_sig_id = 8,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID |
+               BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [55] = {
+       .class_hid = BNXT_ULP_CLASS_HID_01f4,
+       .class_tid = 1,
+       .hdr_sig_id = 3,
+       .flow_sig_id = 8,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID |
+               BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [56] = {
+       .class_hid = BNXT_ULP_CLASS_HID_07ba,
+       .class_tid = 1,
+       .hdr_sig_id = 3,
+       .flow_sig_id = 8,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID |
+               BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [57] = {
+       .class_hid = BNXT_ULP_CLASS_HID_06a7,
+       .class_tid = 1,
+       .hdr_sig_id = 4,
+       .flow_sig_id = 8,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_TCP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [58] = {
+       .class_hid = BNXT_ULP_CLASS_HID_006b,
+       .class_tid = 1,
+       .hdr_sig_id = 4,
+       .flow_sig_id = 8,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_TCP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [59] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0725,
+       .class_tid = 1,
+       .hdr_sig_id = 4,
+       .flow_sig_id = 8,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_TCP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [60] = {
+       .class_hid = BNXT_ULP_CLASS_HID_00e9,
+       .class_tid = 1,
+       .hdr_sig_id = 4,
+       .flow_sig_id = 8,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_TCP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [61] = {
+       .class_hid = BNXT_ULP_CLASS_HID_05d9,
+       .class_tid = 1,
+       .hdr_sig_id = 4,
+       .flow_sig_id = 8,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_TCP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [62] = {
+       .class_hid = BNXT_ULP_CLASS_HID_078d,
+       .class_tid = 1,
+       .hdr_sig_id = 4,
+       .flow_sig_id = 9,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_TCP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [63] = {
+       .class_hid = BNXT_ULP_CLASS_HID_065f,
+       .class_tid = 1,
+       .hdr_sig_id = 4,
+       .flow_sig_id = 10,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_TCP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [64] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0003,
+       .class_tid = 1,
+       .hdr_sig_id = 4,
+       .flow_sig_id = 10,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_TCP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [65] = {
+       .class_hid = BNXT_ULP_CLASS_HID_045f,
+       .class_tid = 1,
+       .hdr_sig_id = 4,
+       .flow_sig_id = 10,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_TCP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [66] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0603,
+       .class_tid = 1,
+       .hdr_sig_id = 4,
+       .flow_sig_id = 10,
        .hdr_sig = { .bits =
                BNXT_ULP_HDR_BIT_O_ETH |
                BNXT_ULP_HDR_BIT_OO_VLAN |
@@ -854,14 +1467,1933 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
                BNXT_ULP_HDR_BIT_O_TCP |
                BNXT_ULP_FLOW_DIR_BITMASK_ING },
        .field_sig = { .bits =
-               BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |
-               BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |
-               BNXT_ULP_HF2_1_BITMASK_OO_VLAN_VID |
-               BNXT_ULP_HF2_1_BITMASK_OO_VLAN_TYPE |
-               BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |
-               BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |
-               BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |
-               BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [67] = {
+       .class_hid = BNXT_ULP_CLASS_HID_00a7,
+       .class_tid = 1,
+       .hdr_sig_id = 4,
+       .flow_sig_id = 10,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_TCP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [68] = {
+       .class_hid = BNXT_ULP_CLASS_HID_026b,
+       .class_tid = 1,
+       .hdr_sig_id = 4,
+       .flow_sig_id = 10,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_TCP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [69] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0371,
+       .class_tid = 1,
+       .hdr_sig_id = 4,
+       .flow_sig_id = 10,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_TCP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [70] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0525,
+       .class_tid = 1,
+       .hdr_sig_id = 4,
+       .flow_sig_id = 10,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_TCP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [71] = {
+       .class_hid = BNXT_ULP_CLASS_HID_07d9,
+       .class_tid = 1,
+       .hdr_sig_id = 4,
+       .flow_sig_id = 10,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_TCP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [72] = {
+       .class_hid = BNXT_ULP_CLASS_HID_018d,
+       .class_tid = 1,
+       .hdr_sig_id = 4,
+       .flow_sig_id = 10,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_TCP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [73] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0177,
+       .class_tid = 1,
+       .hdr_sig_id = 4,
+       .flow_sig_id = 10,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_TCP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [74] = {
+       .class_hid = BNXT_ULP_CLASS_HID_033b,
+       .class_tid = 1,
+       .hdr_sig_id = 4,
+       .flow_sig_id = 10,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_TCP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [75] = {
+       .class_hid = BNXT_ULP_CLASS_HID_05df,
+       .class_tid = 1,
+       .hdr_sig_id = 4,
+       .flow_sig_id = 10,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_TCP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [76] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0783,
+       .class_tid = 1,
+       .hdr_sig_id = 4,
+       .flow_sig_id = 10,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_TCP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [77] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0069,
+       .class_tid = 1,
+       .hdr_sig_id = 4,
+       .flow_sig_id = 10,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_TCP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [78] = {
+       .class_hid = BNXT_ULP_CLASS_HID_025d,
+       .class_tid = 1,
+       .hdr_sig_id = 4,
+       .flow_sig_id = 10,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_TCP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [79] = {
+       .class_hid = BNXT_ULP_CLASS_HID_00ef,
+       .class_tid = 1,
+       .hdr_sig_id = 4,
+       .flow_sig_id = 10,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_TCP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [80] = {
+       .class_hid = BNXT_ULP_CLASS_HID_06a5,
+       .class_tid = 1,
+       .hdr_sig_id = 4,
+       .flow_sig_id = 10,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_TCP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [81] = {
+       .class_hid = BNXT_ULP_CLASS_HID_02f1,
+       .class_tid = 1,
+       .hdr_sig_id = 4,
+       .flow_sig_id = 10,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_TCP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [82] = {
+       .class_hid = BNXT_ULP_CLASS_HID_04a5,
+       .class_tid = 1,
+       .hdr_sig_id = 4,
+       .flow_sig_id = 10,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_TCP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [83] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0377,
+       .class_tid = 1,
+       .hdr_sig_id = 4,
+       .flow_sig_id = 10,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_TCP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [84] = {
+       .class_hid = BNXT_ULP_CLASS_HID_053b,
+       .class_tid = 1,
+       .hdr_sig_id = 4,
+       .flow_sig_id = 10,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_TCP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [85] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0601,
+       .class_tid = 1,
+       .hdr_sig_id = 4,
+       .flow_sig_id = 10,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_TCP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [86] = {
+       .class_hid = BNXT_ULP_CLASS_HID_03df,
+       .class_tid = 1,
+       .hdr_sig_id = 4,
+       .flow_sig_id = 10,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_TCP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [87] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0269,
+       .class_tid = 1,
+       .hdr_sig_id = 4,
+       .flow_sig_id = 10,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_TCP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [88] = {
+       .class_hid = BNXT_ULP_CLASS_HID_045d,
+       .class_tid = 1,
+       .hdr_sig_id = 4,
+       .flow_sig_id = 10,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_TCP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |
+               BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [89] = {
+       .class_hid = BNXT_ULP_CLASS_HID_02dd,
+       .class_tid = 1,
+       .hdr_sig_id = 5,
+       .flow_sig_id = 10,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [90] = {
+       .class_hid = BNXT_ULP_CLASS_HID_04e9,
+       .class_tid = 1,
+       .hdr_sig_id = 5,
+       .flow_sig_id = 10,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [91] = {
+       .class_hid = BNXT_ULP_CLASS_HID_035b,
+       .class_tid = 1,
+       .hdr_sig_id = 5,
+       .flow_sig_id = 10,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [92] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0101,
+       .class_tid = 1,
+       .hdr_sig_id = 5,
+       .flow_sig_id = 10,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [93] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0227,
+       .class_tid = 1,
+       .hdr_sig_id = 5,
+       .flow_sig_id = 10,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [94] = {
+       .class_hid = BNXT_ULP_CLASS_HID_03f3,
+       .class_tid = 1,
+       .hdr_sig_id = 5,
+       .flow_sig_id = 11,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [95] = {
+       .class_hid = BNXT_ULP_CLASS_HID_02a5,
+       .class_tid = 1,
+       .hdr_sig_id = 5,
+       .flow_sig_id = 12,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [96] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0471,
+       .class_tid = 1,
+       .hdr_sig_id = 5,
+       .flow_sig_id = 12,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [97] = {
+       .class_hid = BNXT_ULP_CLASS_HID_00a5,
+       .class_tid = 1,
+       .hdr_sig_id = 5,
+       .flow_sig_id = 12,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [98] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0271,
+       .class_tid = 1,
+       .hdr_sig_id = 5,
+       .flow_sig_id = 12,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [99] = {
+       .class_hid = BNXT_ULP_CLASS_HID_04dd,
+       .class_tid = 1,
+       .hdr_sig_id = 5,
+       .flow_sig_id = 12,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [100] = {
+       .class_hid = BNXT_ULP_CLASS_HID_06e9,
+       .class_tid = 1,
+       .hdr_sig_id = 5,
+       .flow_sig_id = 12,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [101] = {
+       .class_hid = BNXT_ULP_CLASS_HID_078f,
+       .class_tid = 1,
+       .hdr_sig_id = 5,
+       .flow_sig_id = 12,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [102] = {
+       .class_hid = BNXT_ULP_CLASS_HID_015b,
+       .class_tid = 1,
+       .hdr_sig_id = 5,
+       .flow_sig_id = 12,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [103] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0427,
+       .class_tid = 1,
+       .hdr_sig_id = 5,
+       .flow_sig_id = 12,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [104] = {
+       .class_hid = BNXT_ULP_CLASS_HID_05f3,
+       .class_tid = 1,
+       .hdr_sig_id = 5,
+       .flow_sig_id = 12,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [105] = {
+       .class_hid = BNXT_ULP_CLASS_HID_01b7,
+       .class_tid = 1,
+       .hdr_sig_id = 5,
+       .flow_sig_id = 12,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [106] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0343,
+       .class_tid = 1,
+       .hdr_sig_id = 5,
+       .flow_sig_id = 12,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [107] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0235,
+       .class_tid = 1,
+       .hdr_sig_id = 5,
+       .flow_sig_id = 12,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [108] = {
+       .class_hid = BNXT_ULP_CLASS_HID_03c1,
+       .class_tid = 1,
+       .hdr_sig_id = 5,
+       .flow_sig_id = 12,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [109] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0091,
+       .class_tid = 1,
+       .hdr_sig_id = 5,
+       .flow_sig_id = 12,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [110] = {
+       .class_hid = BNXT_ULP_CLASS_HID_02ad,
+       .class_tid = 1,
+       .hdr_sig_id = 5,
+       .flow_sig_id = 12,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [111] = {
+       .class_hid = BNXT_ULP_CLASS_HID_011f,
+       .class_tid = 1,
+       .hdr_sig_id = 5,
+       .flow_sig_id = 12,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [112] = {
+       .class_hid = BNXT_ULP_CLASS_HID_032b,
+       .class_tid = 1,
+       .hdr_sig_id = 5,
+       .flow_sig_id = 12,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [113] = {
+       .class_hid = BNXT_ULP_CLASS_HID_071f,
+       .class_tid = 1,
+       .hdr_sig_id = 5,
+       .flow_sig_id = 12,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [114] = {
+       .class_hid = BNXT_ULP_CLASS_HID_012b,
+       .class_tid = 1,
+       .hdr_sig_id = 5,
+       .flow_sig_id = 12,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [115] = {
+       .class_hid = BNXT_ULP_CLASS_HID_03b7,
+       .class_tid = 1,
+       .hdr_sig_id = 5,
+       .flow_sig_id = 12,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [116] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0543,
+       .class_tid = 1,
+       .hdr_sig_id = 5,
+       .flow_sig_id = 12,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [117] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0679,
+       .class_tid = 1,
+       .hdr_sig_id = 5,
+       .flow_sig_id = 12,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [118] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0035,
+       .class_tid = 1,
+       .hdr_sig_id = 5,
+       .flow_sig_id = 12,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [119] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0291,
+       .class_tid = 1,
+       .hdr_sig_id = 5,
+       .flow_sig_id = 12,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [120] = {
+       .class_hid = BNXT_ULP_CLASS_HID_04ad,
+       .class_tid = 1,
+       .hdr_sig_id = 5,
+       .flow_sig_id = 12,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV6 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [121] = {
+       .class_hid = BNXT_ULP_CLASS_HID_01da,
+       .class_tid = 1,
+       .hdr_sig_id = 6,
+       .flow_sig_id = 12,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [122] = {
+       .class_hid = BNXT_ULP_CLASS_HID_03ee,
+       .class_tid = 1,
+       .hdr_sig_id = 6,
+       .flow_sig_id = 13,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [123] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0642,
+       .class_tid = 1,
+       .hdr_sig_id = 6,
+       .flow_sig_id = 14,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [124] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0016,
+       .class_tid = 1,
+       .hdr_sig_id = 6,
+       .flow_sig_id = 14,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [125] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0776,
+       .class_tid = 1,
+       .hdr_sig_id = 6,
+       .flow_sig_id = 14,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+               BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [126] = {
+       .class_hid = BNXT_ULP_CLASS_HID_013a,
+       .class_tid = 1,
+       .hdr_sig_id = 6,
+       .flow_sig_id = 14,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+               BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [127] = {
+       .class_hid = BNXT_ULP_CLASS_HID_039e,
+       .class_tid = 1,
+       .hdr_sig_id = 6,
+       .flow_sig_id = 14,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+               BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [128] = {
+       .class_hid = BNXT_ULP_CLASS_HID_05a2,
+       .class_tid = 1,
+       .hdr_sig_id = 6,
+       .flow_sig_id = 14,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |
+               BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [129] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0697,
+       .class_tid = 1,
+       .hdr_sig_id = 7,
+       .flow_sig_id = 14,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [130] = {
+       .class_hid = BNXT_ULP_CLASS_HID_005b,
+       .class_tid = 1,
+       .hdr_sig_id = 7,
+       .flow_sig_id = 14,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [131] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0715,
+       .class_tid = 1,
+       .hdr_sig_id = 7,
+       .flow_sig_id = 14,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [132] = {
+       .class_hid = BNXT_ULP_CLASS_HID_00d9,
+       .class_tid = 1,
+       .hdr_sig_id = 7,
+       .flow_sig_id = 14,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [133] = {
+       .class_hid = BNXT_ULP_CLASS_HID_05e9,
+       .class_tid = 1,
+       .hdr_sig_id = 7,
+       .flow_sig_id = 14,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [134] = {
+       .class_hid = BNXT_ULP_CLASS_HID_07bd,
+       .class_tid = 1,
+       .hdr_sig_id = 7,
+       .flow_sig_id = 15,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [135] = {
+       .class_hid = BNXT_ULP_CLASS_HID_066f,
+       .class_tid = 1,
+       .hdr_sig_id = 7,
+       .flow_sig_id = 16,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [136] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0033,
+       .class_tid = 1,
+       .hdr_sig_id = 7,
+       .flow_sig_id = 16,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [137] = {
+       .class_hid = BNXT_ULP_CLASS_HID_046f,
+       .class_tid = 1,
+       .hdr_sig_id = 7,
+       .flow_sig_id = 16,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [138] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0633,
+       .class_tid = 1,
+       .hdr_sig_id = 7,
+       .flow_sig_id = 16,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [139] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0097,
+       .class_tid = 1,
+       .hdr_sig_id = 7,
+       .flow_sig_id = 16,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [140] = {
+       .class_hid = BNXT_ULP_CLASS_HID_025b,
+       .class_tid = 1,
+       .hdr_sig_id = 7,
+       .flow_sig_id = 16,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [141] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0341,
+       .class_tid = 1,
+       .hdr_sig_id = 7,
+       .flow_sig_id = 16,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [142] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0515,
+       .class_tid = 1,
+       .hdr_sig_id = 7,
+       .flow_sig_id = 16,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [143] = {
+       .class_hid = BNXT_ULP_CLASS_HID_07e9,
+       .class_tid = 1,
+       .hdr_sig_id = 7,
+       .flow_sig_id = 16,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [144] = {
+       .class_hid = BNXT_ULP_CLASS_HID_01bd,
+       .class_tid = 1,
+       .hdr_sig_id = 7,
+       .flow_sig_id = 16,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [145] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0147,
+       .class_tid = 1,
+       .hdr_sig_id = 7,
+       .flow_sig_id = 16,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [146] = {
+       .class_hid = BNXT_ULP_CLASS_HID_030b,
+       .class_tid = 1,
+       .hdr_sig_id = 7,
+       .flow_sig_id = 16,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [147] = {
+       .class_hid = BNXT_ULP_CLASS_HID_05ef,
+       .class_tid = 1,
+       .hdr_sig_id = 7,
+       .flow_sig_id = 16,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [148] = {
+       .class_hid = BNXT_ULP_CLASS_HID_07b3,
+       .class_tid = 1,
+       .hdr_sig_id = 7,
+       .flow_sig_id = 16,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [149] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0059,
+       .class_tid = 1,
+       .hdr_sig_id = 7,
+       .flow_sig_id = 16,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [150] = {
+       .class_hid = BNXT_ULP_CLASS_HID_026d,
+       .class_tid = 1,
+       .hdr_sig_id = 7,
+       .flow_sig_id = 16,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [151] = {
+       .class_hid = BNXT_ULP_CLASS_HID_00df,
+       .class_tid = 1,
+       .hdr_sig_id = 7,
+       .flow_sig_id = 16,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [152] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0695,
+       .class_tid = 1,
+       .hdr_sig_id = 7,
+       .flow_sig_id = 16,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [153] = {
+       .class_hid = BNXT_ULP_CLASS_HID_02c1,
+       .class_tid = 1,
+       .hdr_sig_id = 7,
+       .flow_sig_id = 16,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [154] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0495,
+       .class_tid = 1,
+       .hdr_sig_id = 7,
+       .flow_sig_id = 16,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [155] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0347,
+       .class_tid = 1,
+       .hdr_sig_id = 7,
+       .flow_sig_id = 16,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [156] = {
+       .class_hid = BNXT_ULP_CLASS_HID_050b,
+       .class_tid = 1,
+       .hdr_sig_id = 7,
+       .flow_sig_id = 16,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [157] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0631,
+       .class_tid = 1,
+       .hdr_sig_id = 7,
+       .flow_sig_id = 16,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [158] = {
+       .class_hid = BNXT_ULP_CLASS_HID_03ef,
+       .class_tid = 1,
+       .hdr_sig_id = 7,
+       .flow_sig_id = 16,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [159] = {
+       .class_hid = BNXT_ULP_CLASS_HID_0259,
+       .class_tid = 1,
+       .hdr_sig_id = 7,
+       .flow_sig_id = 16,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
+               BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+       },
+       [160] = {
+       .class_hid = BNXT_ULP_CLASS_HID_046d,
+       .class_tid = 1,
+       .hdr_sig_id = 7,
+       .flow_sig_id = 16,
+       .hdr_sig = { .bits =
+               BNXT_ULP_HDR_BIT_O_ETH |
+               BNXT_ULP_HDR_BIT_OO_VLAN |
+               BNXT_ULP_HDR_BIT_O_IPV4 |
+               BNXT_ULP_HDR_BIT_O_UDP |
+               BNXT_ULP_FLOW_DIR_BITMASK_ING },
+       .field_sig = { .bits =
+               BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |
+               BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |
+               BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |
+               BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |
+               BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |
                BNXT_ULP_MATCH_TYPE_BITMASK_EM },
        }
 };

diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
index 4963fc0..0341c43 100644 (file)
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
@@ -3,7 +3,7 @@
  * All rights reserved.
  */
 
-/* date: Mon Nov 23 17:33:02 2020 */
+/* date: Tue Dec  1 10:17:11 2020 */
 
 #ifndef ULP_TEMPLATE_DB_H_
 #define ULP_TEMPLATE_DB_H_
@@ -12,13 +12,13 @@
 #define BNXT_ULP_MAX_NUM_DEVICES 4
 #define BNXT_ULP_LOG2_MAX_NUM_DEV 2
 #define BNXT_ULP_GEN_TBL_MAX_SZ 6
-#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 256
-#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 41
-#define BNXT_ULP_CLASS_HID_LOW_PRIME 3793
+#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 2048
+#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 161
+#define BNXT_ULP_CLASS_HID_LOW_PRIME 7669
 #define BNXT_ULP_CLASS_HID_HIGH_PRIME 7919
 #define BNXT_ULP_CLASS_HID_SHFTR 24
 #define BNXT_ULP_CLASS_HID_SHFTL 23
-#define BNXT_ULP_CLASS_HID_MASK 255
+#define BNXT_ULP_CLASS_HID_MASK 2047
 #define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 2048
 #define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 15
 #define BNXT_ULP_ACT_HID_LOW_PRIME 7919
@@ -30,18 +30,18 @@
 #define BNXT_ULP_GLB_TEMPLATE_TBL_MAX_SZ 1
 #define BNXT_ULP_GLB_FIELD_TBL_SHIFT 7
 #define BNXT_ULP_HDR_SIG_ID_SHIFT 4
-#define BNXT_ULP_GLB_FIELD_TBL_SIZE 4441
-#define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 8
-#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 41
-#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 273
-#define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 14
-#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 385
+#define BNXT_ULP_GLB_FIELD_TBL_SIZE 3033
+#define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 7
+#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 38
+#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 192
+#define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 10
+#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 341
 #define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 10
-#define ULP_STINGRAY_CLASS_TMPL_LIST_SIZE 8
-#define ULP_STINGRAY_CLASS_TBL_LIST_SIZE 41
-#define ULP_STINGRAY_CLASS_KEY_INFO_LIST_SIZE 273
-#define ULP_STINGRAY_CLASS_IDENT_LIST_SIZE 14
-#define ULP_STINGRAY_CLASS_RESULT_FIELD_LIST_SIZE 385
+#define ULP_STINGRAY_CLASS_TMPL_LIST_SIZE 7
+#define ULP_STINGRAY_CLASS_TBL_LIST_SIZE 38
+#define ULP_STINGRAY_CLASS_KEY_INFO_LIST_SIZE 192
+#define ULP_STINGRAY_CLASS_IDENT_LIST_SIZE 10
+#define ULP_STINGRAY_CLASS_RESULT_FIELD_LIST_SIZE 341
 #define ULP_STINGRAY_CLASS_COND_LIST_SIZE 10
 #define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 2
 #define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 4
@@ -56,35 +56,35 @@
 #define ULP_STINGRAY_ACT_RESULT_FIELD_LIST_SIZE 65
 #define ULP_STINGRAY_ACT_COND_LIST_SIZE 2
 
-enum bnxt_ulp_action_bit {
-       BNXT_ULP_ACTION_BIT_MARK             = 0x0000000000000001,
-       BNXT_ULP_ACTION_BIT_DROP             = 0x0000000000000002,
-       BNXT_ULP_ACTION_BIT_COUNT            = 0x0000000000000004,
-       BNXT_ULP_ACTION_BIT_RSS              = 0x0000000000000008,
-       BNXT_ULP_ACTION_BIT_METER            = 0x0000000000000010,
-       BNXT_ULP_ACTION_BIT_VXLAN_DECAP      = 0x0000000000000020,
-       BNXT_ULP_ACTION_BIT_POP_MPLS         = 0x0000000000000040,
-       BNXT_ULP_ACTION_BIT_PUSH_MPLS        = 0x0000000000000080,
-       BNXT_ULP_ACTION_BIT_MAC_SWAP         = 0x0000000000000100,
-       BNXT_ULP_ACTION_BIT_SET_MAC_SRC      = 0x0000000000000200,
-       BNXT_ULP_ACTION_BIT_SET_MAC_DST      = 0x0000000000000400,
-       BNXT_ULP_ACTION_BIT_POP_VLAN         = 0x0000000000000800,
-       BNXT_ULP_ACTION_BIT_PUSH_VLAN        = 0x0000000000001000,
-       BNXT_ULP_ACTION_BIT_SET_VLAN_PCP     = 0x0000000000002000,
-       BNXT_ULP_ACTION_BIT_SET_VLAN_VID     = 0x0000000000004000,
-       BNXT_ULP_ACTION_BIT_SET_IPV4_SRC     = 0x0000000000008000,
-       BNXT_ULP_ACTION_BIT_SET_IPV4_DST     = 0x0000000000010000,
-       BNXT_ULP_ACTION_BIT_SET_IPV6_SRC     = 0x0000000000020000,
-       BNXT_ULP_ACTION_BIT_SET_IPV6_DST     = 0x0000000000040000,
-       BNXT_ULP_ACTION_BIT_DEC_TTL          = 0x0000000000080000,
-       BNXT_ULP_ACTION_BIT_SET_TP_SRC       = 0x0000000000100000,
-       BNXT_ULP_ACTION_BIT_SET_TP_DST       = 0x0000000000200000,
-       BNXT_ULP_ACTION_BIT_VXLAN_ENCAP      = 0x0000000000400000,
-       BNXT_ULP_ACTION_BIT_JUMP             = 0x0000000000800000,
-       BNXT_ULP_ACTION_BIT_SHARED           = 0x0000000001000000,
-       BNXT_ULP_ACTION_BIT_SAMPLE           = 0x0000000002000000,
-       BNXT_ULP_ACTION_BIT_SHARED_SAMPLE    = 0x0000000004000000,
-       BNXT_ULP_ACTION_BIT_LAST             = 0x0000000008000000
+enum bnxt_ulp_act_bit {
+       BNXT_ULP_ACT_BIT_MARK                = 0x0000000000000001,
+       BNXT_ULP_ACT_BIT_DROP                = 0x0000000000000002,
+       BNXT_ULP_ACT_BIT_COUNT               = 0x0000000000000004,
+       BNXT_ULP_ACT_BIT_RSS                 = 0x0000000000000008,
+       BNXT_ULP_ACT_BIT_METER               = 0x0000000000000010,
+       BNXT_ULP_ACT_BIT_VXLAN_DECAP         = 0x0000000000000020,
+       BNXT_ULP_ACT_BIT_POP_MPLS            = 0x0000000000000040,
+       BNXT_ULP_ACT_BIT_PUSH_MPLS           = 0x0000000000000080,
+       BNXT_ULP_ACT_BIT_MAC_SWAP            = 0x0000000000000100,
+       BNXT_ULP_ACT_BIT_SET_MAC_SRC         = 0x0000000000000200,
+       BNXT_ULP_ACT_BIT_SET_MAC_DST         = 0x0000000000000400,
+       BNXT_ULP_ACT_BIT_POP_VLAN            = 0x0000000000000800,
+       BNXT_ULP_ACT_BIT_PUSH_VLAN           = 0x0000000000001000,
+       BNXT_ULP_ACT_BIT_SET_VLAN_PCP        = 0x0000000000002000,
+       BNXT_ULP_ACT_BIT_SET_VLAN_VID        = 0x0000000000004000,
+       BNXT_ULP_ACT_BIT_SET_IPV4_SRC        = 0x0000000000008000,
+       BNXT_ULP_ACT_BIT_SET_IPV4_DST        = 0x0000000000010000,
+       BNXT_ULP_ACT_BIT_SET_IPV6_SRC        = 0x0000000000020000,
+       BNXT_ULP_ACT_BIT_SET_IPV6_DST        = 0x0000000000040000,
+       BNXT_ULP_ACT_BIT_DEC_TTL             = 0x0000000000080000,
+       BNXT_ULP_ACT_BIT_SET_TP_SRC          = 0x0000000000100000,
+       BNXT_ULP_ACT_BIT_SET_TP_DST          = 0x0000000000200000,
+       BNXT_ULP_ACT_BIT_VXLAN_ENCAP         = 0x0000000000400000,
+       BNXT_ULP_ACT_BIT_JUMP                = 0x0000000000800000,
+       BNXT_ULP_ACT_BIT_SHARED              = 0x0000000001000000,
+       BNXT_ULP_ACT_BIT_SAMPLE              = 0x0000000002000000,
+       BNXT_ULP_ACT_BIT_SHARED_SAMPLE       = 0x0000000004000000,
+       BNXT_ULP_ACT_BIT_LAST                = 0x0000000008000000
 };
 
 enum bnxt_ulp_hdr_bit {
@@ -188,16 +188,16 @@ enum bnxt_ulp_cond_list_opc {
 };
 
 enum bnxt_ulp_cond_opc {
-       BNXT_ULP_COND_OPC_COMP_FIELD_IS_SET = 0,
-       BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET = 1,
-       BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET = 2,
-       BNXT_ULP_COND_OPC_ACTION_BIT_NOT_SET = 3,
+       BNXT_ULP_COND_OPC_CF_IS_SET = 0,
+       BNXT_ULP_COND_OPC_CF_NOT_SET = 1,
+       BNXT_ULP_COND_OPC_ACT_BIT_IS_SET = 2,
+       BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET = 3,
        BNXT_ULP_COND_OPC_HDR_BIT_IS_SET = 4,
        BNXT_ULP_COND_OPC_HDR_BIT_NOT_SET = 5,
        BNXT_ULP_COND_OPC_FIELD_BIT_IS_SET = 6,
        BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET = 7,
-       BNXT_ULP_COND_OPC_REGFILE_IS_SET = 8,
-       BNXT_ULP_COND_OPC_REGFILE_NOT_SET = 9,
+       BNXT_ULP_COND_OPC_RF_IS_SET = 8,
+       BNXT_ULP_COND_OPC_RF_NOT_SET = 9,
        BNXT_ULP_COND_OPC_LAST = 10
 };
 
@@ -241,26 +241,31 @@ enum bnxt_ulp_fdb_type {
        BNXT_ULP_FDB_TYPE_LAST = 3
 };
 
-enum bnxt_ulp_field_opc {
-       BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT = 0,
-       BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD = 1,
-       BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD = 2,
-       BNXT_ULP_FIELD_OPC_SET_TO_REGFILE = 3,
-       BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE = 4,
-       BNXT_ULP_FIELD_OPC_SET_TO_ZERO = 5,
-       BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT = 6,
-       BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP = 7,
-       BNXT_ULP_FIELD_OPC_SET_TO_ENCAP_ACT_PROP_SZ = 8,
-       BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST = 9,
-       BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST = 10,
-       BNXT_ULP_FIELD_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF = 11,
-       BNXT_ULP_FIELD_OPC_IF_HDR_BIT_THEN_CONST_ELSE_CONST = 12,
-       BNXT_ULP_FIELD_OPC_IF_COMP_FIELD_THEN_ACT_PROP_ELSE_CONST = 13,
-       BNXT_ULP_FIELD_OPC_IF_NOT_COMP_FIELD_THEN_ACT_PROP_ELSE_CONST = 14,
-       BNXT_ULP_FIELD_OPC_IF_COMP_FIELD_THEN_CONST_ELSE_CF = 15,
-       BNXT_ULP_FIELD_OPC_IF_NOT_COMP_FIELD_THEN_CONST_ELSE_CF = 16,
-       BNXT_ULP_FIELD_OPC_IF_FIELD_BIT_THEN_ONES_ELSE_ZERO = 17,
-       BNXT_ULP_FIELD_OPC_LAST = 18
+enum bnxt_ulp_field_cond_src {
+       BNXT_ULP_FIELD_COND_SRC_TRUE = 0,
+       BNXT_ULP_FIELD_COND_SRC_CF = 1,
+       BNXT_ULP_FIELD_COND_SRC_RF = 2,
+       BNXT_ULP_FIELD_COND_SRC_ACT_BIT = 3,
+       BNXT_ULP_FIELD_COND_SRC_HDR_BIT = 4,
+       BNXT_ULP_FIELD_COND_SRC_FIELD_BIT = 5,
+       BNXT_ULP_FIELD_COND_SRC_LAST = 6
+};
+
+enum bnxt_ulp_field_src {
+       BNXT_ULP_FIELD_SRC_ZERO = 0,
+       BNXT_ULP_FIELD_SRC_CONST = 1,
+       BNXT_ULP_FIELD_SRC_CF = 2,
+       BNXT_ULP_FIELD_SRC_RF = 3,
+       BNXT_ULP_FIELD_SRC_ACT_PROP = 4,
+       BNXT_ULP_FIELD_SRC_ACT_PROP_SZ = 5,
+       BNXT_ULP_FIELD_SRC_GLB_RF = 6,
+       BNXT_ULP_FIELD_SRC_HF = 7,
+       BNXT_ULP_FIELD_SRC_HDR_BIT = 8,
+       BNXT_ULP_FIELD_SRC_ACT_BIT = 9,
+       BNXT_ULP_FIELD_SRC_FIELD_BIT = 10,
+       BNXT_ULP_FIELD_SRC_SKIP = 11,
+       BNXT_ULP_FIELD_SRC_REJECT = 12,
+       BNXT_ULP_FIELD_SRC_LAST = 13
 };
 
 enum bnxt_ulp_generic_tbl_opc {
@@ -409,7 +414,8 @@ enum bnxt_ulp_resource_func {
        BNXT_ULP_RESOURCE_FUNC_IF_TABLE = 0x84,
        BNXT_ULP_RESOURCE_FUNC_HW_FID = 0x85,
        BNXT_ULP_RESOURCE_FUNC_PARENT_FLOW = 0x86,
-       BNXT_ULP_RESOURCE_FUNC_CHILD_FLOW = 0x87
+       BNXT_ULP_RESOURCE_FUNC_CHILD_FLOW = 0x87,
+       BNXT_ULP_RESOURCE_FUNC_BRANCH_TABLE = 0x88
 };
 
 enum bnxt_ulp_resource_sub_type {
@@ -516,483 +522,603 @@ enum bnxt_ulp_act_prop_idx {
        BNXT_ULP_ACT_PROP_IDX_LAST = 269
 };
 
-enum bnxt_ulp_wh_plus_sym {
-       BNXT_ULP_WH_PLUS_SYM_PKT_TYPE_IGNORE = 0,
-       BNXT_ULP_WH_PLUS_SYM_PKT_TYPE_L2 = 0,
-       BNXT_ULP_WH_PLUS_SYM_PKT_TYPE_0_IGNORE = 0,
-       BNXT_ULP_WH_PLUS_SYM_PKT_TYPE_0_L2 = 0,
-       BNXT_ULP_WH_PLUS_SYM_PKT_TYPE_1_IGNORE = 0,
-       BNXT_ULP_WH_PLUS_SYM_PKT_TYPE_1_L2 = 0,
-       BNXT_ULP_WH_PLUS_SYM_RECYCLE_CNT_IGNORE = 0,
-       BNXT_ULP_WH_PLUS_SYM_RECYCLE_CNT_ZERO = 0,
-       BNXT_ULP_WH_PLUS_SYM_RECYCLE_CNT_ONE = 1,
-       BNXT_ULP_WH_PLUS_SYM_RECYCLE_CNT_TWO = 2,
-       BNXT_ULP_WH_PLUS_SYM_RECYCLE_CNT_THREE = 3,
-       BNXT_ULP_WH_PLUS_SYM_AGG_ERROR_IGNORE = 0,
-       BNXT_ULP_WH_PLUS_SYM_AGG_ERROR_NO = 0,
-       BNXT_ULP_WH_PLUS_SYM_AGG_ERROR_YES = 1,
-       BNXT_ULP_WH_PLUS_SYM_RESERVED_IGNORE = 0,
-       BNXT_ULP_WH_PLUS_SYM_HREC_NEXT_IGNORE = 0,
-       BNXT_ULP_WH_PLUS_SYM_HREC_NEXT_NO = 0,
-       BNXT_ULP_WH_PLUS_SYM_HREC_NEXT_YES = 1,
-       BNXT_ULP_WH_PLUS_SYM_TL2_HDR_VALID_IGNORE = 0,
-       BNXT_ULP_WH_PLUS_SYM_TL2_HDR_VALID_NO = 0,
-       BNXT_ULP_WH_PLUS_SYM_TL2_HDR_VALID_YES = 1,
-       BNXT_ULP_WH_PLUS_SYM_TL2_HDR_TYPE_IGNORE = 0,
-       BNXT_ULP_WH_PLUS_SYM_TL2_HDR_TYPE_DIX = 0,
-       BNXT_ULP_WH_PLUS_SYM_TL2_UC_MC_BC_IGNORE = 0,
-       BNXT_ULP_WH_PLUS_SYM_TL2_UC_MC_BC_UC = 0,
-       BNXT_ULP_WH_PLUS_SYM_TL2_UC_MC_BC_MC = 2,
-       BNXT_ULP_WH_PLUS_SYM_TL2_UC_MC_BC_BC = 3,
-       BNXT_ULP_WH_PLUS_SYM_TL2_VTAG_PRESENT_IGNORE = 0,
-       BNXT_ULP_WH_PLUS_SYM_TL2_VTAG_PRESENT_NO = 0,
-       BNXT_ULP_WH_PLUS_SYM_TL2_VTAG_PRESENT_YES = 1,
-       BNXT_ULP_WH_PLUS_SYM_TL2_TWO_VTAGS_IGNORE = 0,
-       BNXT_ULP_WH_PLUS_SYM_TL2_TWO_VTAGS_NO = 0,
-       BNXT_ULP_WH_PLUS_SYM_TL2_TWO_VTAGS_YES = 1,
-       BNXT_ULP_WH_PLUS_SYM_TL3_HDR_VALID_IGNORE = 0,
-       BNXT_ULP_WH_PLUS_SYM_TL3_HDR_VALID_NO = 0,
-       BNXT_ULP_WH_PLUS_SYM_TL3_HDR_VALID_YES = 1,
-       BNXT_ULP_WH_PLUS_SYM_TL3_HDR_ERROR_IGNORE = 0,
-       BNXT_ULP_WH_PLUS_SYM_TL3_HDR_ERROR_NO = 0,
-       BNXT_ULP_WH_PLUS_SYM_TL3_HDR_ERROR_YES = 1,
-       BNXT_ULP_WH_PLUS_SYM_TL3_HDR_TYPE_IGNORE = 0,
-       BNXT_ULP_WH_PLUS_SYM_TL3_HDR_TYPE_IPV4 = 0,
-       BNXT_ULP_WH_PLUS_SYM_TL3_HDR_TYPE_IPV6 = 1,
-       BNXT_ULP_WH_PLUS_SYM_TL3_HDR_ISIP_IGNORE = 0,
-       BNXT_ULP_WH_PLUS_SYM_TL3_HDR_ISIP_NO = 0,
-       BNXT_ULP_WH_PLUS_SYM_TL3_HDR_ISIP_YES = 1,
-       BNXT_ULP_WH_PLUS_SYM_TL3_IPV6_CMP_SRC_IGNORE = 0,
-       BNXT_ULP_WH_PLUS_SYM_TL3_IPV6_CMP_SRC_NO = 0,
-       BNXT_ULP_WH_PLUS_SYM_TL3_IPV6_CMP_SRC_YES = 1,
-       BNXT_ULP_WH_PLUS_SYM_TL3_IPV6_CMP_DST_IGNORE = 0,
-       BNXT_ULP_WH_PLUS_SYM_TL3_IPV6_CMP_DST_NO = 0,
-       BNXT_ULP_WH_PLUS_SYM_TL3_IPV6_CMP_DST_YES = 1,
-       BNXT_ULP_WH_PLUS_SYM_TL4_HDR_VALID_IGNORE = 0,
-       BNXT_ULP_WH_PLUS_SYM_TL4_HDR_VALID_NO = 0,
-       BNXT_ULP_WH_PLUS_SYM_TL4_HDR_VALID_YES = 1,
-       BNXT_ULP_WH_PLUS_SYM_TL4_HDR_ERROR_IGNORE = 0,
-       BNXT_ULP_WH_PLUS_SYM_TL4_HDR_ERROR_NO = 0,
-       BNXT_ULP_WH_PLUS_SYM_TL4_HDR_ERROR_YES = 1,
-       BNXT_ULP_WH_PLUS_SYM_TL4_HDR_IS_UDP_TCP_IGNORE = 0,
-       BNXT_ULP_WH_PLUS_SYM_TL4_HDR_IS_UDP_TCP_NO = 0,
-       BNXT_ULP_WH_PLUS_SYM_TL4_HDR_IS_UDP_TCP_YES = 1,
-       BNXT_ULP_WH_PLUS_SYM_TL4_HDR_TYPE_IGNORE = 0,
-       BNXT_ULP_WH_PLUS_SYM_TL4_HDR_TYPE_TCP = 0,
-       BNXT_ULP_WH_PLUS_SYM_TL4_HDR_TYPE_UDP = 1,
-       BNXT_ULP_WH_PLUS_SYM_TUN_HDR_VALID_IGNORE = 0,
-       BNXT_ULP_WH_PLUS_SYM_TUN_HDR_VALID_NO = 0,
-       BNXT_ULP_WH_PLUS_SYM_TUN_HDR_VALID_YES = 1,
-       BNXT_ULP_WH_PLUS_SYM_TUN_HDR_ERROR_IGNORE = 0,
-       BNXT_ULP_WH_PLUS_SYM_TUN_HDR_ERROR_NO = 0,
-       BNXT_ULP_WH_PLUS_SYM_TUN_HDR_ERROR_YES = 1,
-       BNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_IGNORE = 0,
-       BNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_VXLAN = 0,
-       BNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_GENEVE = 1,
-       BNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_NVGRE = 2,
-       BNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_GRE = 3,
-       BNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_IPV4 = 4,
-       BNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_IPV6 = 5,
-       BNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_PPPOE = 6,
-       BNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_MPLS = 7,
-       BNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_UPAR1 = 8,
-       BNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_UPAR2 = 9,
-       BNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_NONE = 15,
-       BNXT_ULP_WH_PLUS_SYM_TUN_HDR_FLAGS_IGNORE = 0,
-       BNXT_ULP_WH_PLUS_SYM_L2_HDR_VALID_IGNORE = 0,
-       BNXT_ULP_WH_PLUS_SYM_L2_HDR_VALID_NO = 0,
-       BNXT_ULP_WH_PLUS_SYM_L2_HDR_VALID_YES = 1,
-       BNXT_ULP_WH_PLUS_SYM_L2_HDR_ERROR_IGNORE = 0,
-       BNXT_ULP_WH_PLUS_SYM_L2_HDR_ERROR_NO = 0,
-       BNXT_ULP_WH_PLUS_SYM_L2_HDR_ERROR_YES = 1,
-       BNXT_ULP_WH_PLUS_SYM_L2_HDR_TYPE_IGNORE = 0,
-       BNXT_ULP_WH_PLUS_SYM_L2_HDR_TYPE_DIX = 0,
-       BNXT_ULP_WH_PLUS_SYM_L2_HDR_TYPE_LLC_SNAP = 1,
-       BNXT_ULP_WH_PLUS_SYM_L2_HDR_TYPE_LLC = 2,
-       BNXT_ULP_WH_PLUS_SYM_L2_UC_MC_BC_IGNORE = 0,
-       BNXT_ULP_WH_PLUS_SYM_L2_UC_MC_BC_UC = 0,
-       BNXT_ULP_WH_PLUS_SYM_L2_UC_MC_BC_MC = 2,
-       BNXT_ULP_WH_PLUS_SYM_L2_UC_MC_BC_BC = 3,
-       BNXT_ULP_WH_PLUS_SYM_L2_VTAG_PRESENT_IGNORE = 0,
-       BNXT_ULP_WH_PLUS_SYM_L2_VTAG_PRESENT_NO = 0,
-       BNXT_ULP_WH_PLUS_SYM_L2_VTAG_PRESENT_YES = 1,
-       BNXT_ULP_WH_PLUS_SYM_L2_TWO_VTAGS_IGNORE = 0,
-       BNXT_ULP_WH_PLUS_SYM_L2_TWO_VTAGS_NO = 0,
-       BNXT_ULP_WH_PLUS_SYM_L2_TWO_VTAGS_YES = 1,
-       BNXT_ULP_WH_PLUS_SYM_L3_HDR_VALID_IGNORE = 0,
-       BNXT_ULP_WH_PLUS_SYM_L3_HDR_VALID_NO = 0,
-       BNXT_ULP_WH_PLUS_SYM_L3_HDR_VALID_YES = 1,
-       BNXT_ULP_WH_PLUS_SYM_L3_HDR_ERROR_IGNORE = 0,
-       BNXT_ULP_WH_PLUS_SYM_L3_HDR_ERROR_NO = 0,
-       BNXT_ULP_WH_PLUS_SYM_L3_HDR_ERROR_YES = 1,
-       BNXT_ULP_WH_PLUS_SYM_L3_HDR_TYPE_IGNORE = 0,
-       BNXT_ULP_WH_PLUS_SYM_L3_HDR_TYPE_IPV4 = 0,
-       BNXT_ULP_WH_PLUS_SYM_L3_HDR_TYPE_IPV6 = 1,
-       BNXT_ULP_WH_PLUS_SYM_L3_HDR_TYPE_ARP = 2,
-       BNXT_ULP_WH_PLUS_SYM_L3_HDR_TYPE_PTP = 3,
-       BNXT_ULP_WH_PLUS_SYM_L3_HDR_TYPE_EAPOL = 4,
-       BNXT_ULP_WH_PLUS_SYM_L3_HDR_TYPE_ROCE = 5,
-       BNXT_ULP_WH_PLUS_SYM_L3_HDR_TYPE_FCOE = 6,
-       BNXT_ULP_WH_PLUS_SYM_L3_HDR_TYPE_UPAR1 = 7,
-       BNXT_ULP_WH_PLUS_SYM_L3_HDR_TYPE_UPAR2 = 8,
-       BNXT_ULP_WH_PLUS_SYM_L3_HDR_ISIP_IGNORE = 0,
-       BNXT_ULP_WH_PLUS_SYM_L3_HDR_ISIP_NO = 0,
-       BNXT_ULP_WH_PLUS_SYM_L3_HDR_ISIP_YES = 1,
-       BNXT_ULP_WH_PLUS_SYM_L3_IPV6_CMP_SRC_IGNORE = 0,
-       BNXT_ULP_WH_PLUS_SYM_L3_IPV6_CMP_SRC_NO = 0,
-       BNXT_ULP_WH_PLUS_SYM_L3_IPV6_CMP_SRC_YES = 1,
-       BNXT_ULP_WH_PLUS_SYM_L3_IPV6_CMP_DST_IGNORE = 0,
-       BNXT_ULP_WH_PLUS_SYM_L3_IPV6_CMP_DST_NO = 0,
-       BNXT_ULP_WH_PLUS_SYM_L3_IPV6_CMP_DST_YES = 1,
-       BNXT_ULP_WH_PLUS_SYM_L4_HDR_VALID_IGNORE = 0,
-       BNXT_ULP_WH_PLUS_SYM_L4_HDR_VALID_NO = 0,
-       BNXT_ULP_WH_PLUS_SYM_L4_HDR_VALID_YES = 1,
-       BNXT_ULP_WH_PLUS_SYM_L4_HDR_ERROR_IGNORE = 0,
-       BNXT_ULP_WH_PLUS_SYM_L4_HDR_ERROR_NO = 0,
-       BNXT_ULP_WH_PLUS_SYM_L4_HDR_ERROR_YES = 1,
-       BNXT_ULP_WH_PLUS_SYM_L4_HDR_TYPE_IGNORE = 0,
-       BNXT_ULP_WH_PLUS_SYM_L4_HDR_TYPE_TCP = 0,
-       BNXT_ULP_WH_PLUS_SYM_L4_HDR_TYPE_UDP = 1,
-       BNXT_ULP_WH_PLUS_SYM_L4_HDR_TYPE_ICMP = 2,
-       BNXT_ULP_WH_PLUS_SYM_L4_HDR_TYPE_UPAR1 = 3,
-       BNXT_ULP_WH_PLUS_SYM_L4_HDR_TYPE_UPAR2 = 4,
-       BNXT_ULP_WH_PLUS_SYM_L4_HDR_TYPE_BTH_V1 = 5,
-       BNXT_ULP_WH_PLUS_SYM_L4_HDR_IS_UDP_TCP_IGNORE = 0,
-       BNXT_ULP_WH_PLUS_SYM_L4_HDR_IS_UDP_TCP_NO = 0,
-       BNXT_ULP_WH_PLUS_SYM_L4_HDR_IS_UDP_TCP_YES = 1,
-       BNXT_ULP_WH_PLUS_SYM_POP_VLAN_NO = 0,
-       BNXT_ULP_WH_PLUS_SYM_POP_VLAN_YES = 1,
-       BNXT_ULP_WH_PLUS_SYM_DECAP_FUNC_NONE = 0,
-       BNXT_ULP_WH_PLUS_SYM_DECAP_FUNC_THRU_TL2 = 3,
-       BNXT_ULP_WH_PLUS_SYM_DECAP_FUNC_THRU_TL3 = 8,
-       BNXT_ULP_WH_PLUS_SYM_DECAP_FUNC_THRU_TL4 = 9,
-       BNXT_ULP_WH_PLUS_SYM_DECAP_FUNC_THRU_TUN = 10,
-       BNXT_ULP_WH_PLUS_SYM_DECAP_FUNC_THRU_L2 = 11,
-       BNXT_ULP_WH_PLUS_SYM_DECAP_FUNC_THRU_L3 = 12,
-       BNXT_ULP_WH_PLUS_SYM_DECAP_FUNC_THRU_L4 = 13,
-       BNXT_ULP_WH_PLUS_SYM_ECV_VALID_NO = 0,
-       BNXT_ULP_WH_PLUS_SYM_ECV_VALID_YES = 1,
-       BNXT_ULP_WH_PLUS_SYM_ECV_CUSTOM_EN_NO = 0,
-       BNXT_ULP_WH_PLUS_SYM_ECV_CUSTOM_EN_YES = 1,
-       BNXT_ULP_WH_PLUS_SYM_ECV_L2_EN_NO = 0,
-       BNXT_ULP_WH_PLUS_SYM_ECV_L2_EN_YES = 1,
-       BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_NOP = 0,
-       BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI = 1,
-       BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_1_IVLAN_PRI = 2,
-       BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_1_REMAP_DIFFSERV = 3,
-       BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI = 4,
-       BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_2_REMAP_DIFFSERV = 5,
-       BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_0_ENCAP_PRI = 6,
-       BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_0_REMAP_DIFFSERV = 7,
-       BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_0_PRI_0 = 8,
-       BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_0_PRI_1 = 8,
-       BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_0_PRI_2 = 8,
-       BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_0_PRI_3 = 8,
-       BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_0_PRI_4 = 8,
-       BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_0_PRI_5 = 8,
-       BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_0_PRI_6 = 8,
-       BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_0_PRI_7 = 8,
-       BNXT_ULP_WH_PLUS_SYM_ECV_L3_TYPE_NONE = 0,
-       BNXT_ULP_WH_PLUS_SYM_ECV_L3_TYPE_IPV4 = 4,
-       BNXT_ULP_WH_PLUS_SYM_ECV_L3_TYPE_IPV6 = 5,
-       BNXT_ULP_WH_PLUS_SYM_ECV_L3_TYPE_MPLS_8847 = 6,
-       BNXT_ULP_WH_PLUS_SYM_ECV_L3_TYPE_MPLS_8848 = 7,
-       BNXT_ULP_WH_PLUS_SYM_ECV_L4_TYPE_NONE = 0,
-       BNXT_ULP_WH_PLUS_SYM_ECV_L4_TYPE_UDP = 4,
-       BNXT_ULP_WH_PLUS_SYM_ECV_L4_TYPE_UDP_CSUM = 5,
-       BNXT_ULP_WH_PLUS_SYM_ECV_L4_TYPE_UDP_ENTROPY = 6,
-       BNXT_ULP_WH_PLUS_SYM_ECV_L4_TYPE_UDP_ENTROPY_CSUM = 7,
-       BNXT_ULP_WH_PLUS_SYM_ECV_TUN_TYPE_NONE = 0,
-       BNXT_ULP_WH_PLUS_SYM_ECV_TUN_TYPE_GENERIC = 1,
-       BNXT_ULP_WH_PLUS_SYM_ECV_TUN_TYPE_VXLAN = 2,
-       BNXT_ULP_WH_PLUS_SYM_ECV_TUN_TYPE_NGE = 3,
-       BNXT_ULP_WH_PLUS_SYM_ECV_TUN_TYPE_NVGRE = 4,
-       BNXT_ULP_WH_PLUS_SYM_ECV_TUN_TYPE_GRE = 5,
-       BNXT_ULP_WH_PLUS_SYM_EEM_ACT_REC_INT = 1,
-       BNXT_ULP_WH_PLUS_SYM_EEM_EXT_FLOW_CNTR = 0,
-       BNXT_ULP_WH_PLUS_SYM_UC_ACT_REC = 0,
-       BNXT_ULP_WH_PLUS_SYM_MC_ACT_REC = 1,
-       BNXT_ULP_WH_PLUS_SYM_ACT_REC_DROP_YES = 1,
-       BNXT_ULP_WH_PLUS_SYM_ACT_REC_DROP_NO = 0,
-       BNXT_ULP_WH_PLUS_SYM_ACT_REC_POP_VLAN_YES = 1,
-       BNXT_ULP_WH_PLUS_SYM_ACT_REC_POP_VLAN_NO = 0,
-       BNXT_ULP_WH_PLUS_SYM_ACT_REC_METER_EN_YES = 1,
-       BNXT_ULP_WH_PLUS_SYM_ACT_REC_METER_EN_NO = 0,
-       BNXT_ULP_WH_PLUS_SYM_LOOPBACK_PORT = 4,
-       BNXT_ULP_WH_PLUS_SYM_LOOPBACK_PARIF = 15,
-       BNXT_ULP_WH_PLUS_SYM_EXT_EM_MAX_KEY_SIZE = 448,
-       BNXT_ULP_WH_PLUS_SYM_MATCH_TYPE_EM = 0,
-       BNXT_ULP_WH_PLUS_SYM_MATCH_TYPE_WM = 1,
-       BNXT_ULP_WH_PLUS_SYM_IP_PROTO_ICMP = 1,
-       BNXT_ULP_WH_PLUS_SYM_IP_PROTO_IGMP = 2,
-       BNXT_ULP_WH_PLUS_SYM_IP_PROTO_IP_IN_IP = 4,
-       BNXT_ULP_WH_PLUS_SYM_IP_PROTO_TCP = 6,
-       BNXT_ULP_WH_PLUS_SYM_IP_PROTO_UDP = 17,
-       BNXT_ULP_WH_PLUS_SYM_VF_FUNC_PARIF = 15,
-       BNXT_ULP_WH_PLUS_SYM_NO = 0,
-       BNXT_ULP_WH_PLUS_SYM_YES = 1,
-       BNXT_ULP_WH_PLUS_SYM_RECYCLE_DST = 0x800
-};
-
-enum bnxt_ulp_stingray_sym {
-       BNXT_ULP_STINGRAY_SYM_PKT_TYPE_IGNORE = 0,
-       BNXT_ULP_STINGRAY_SYM_PKT_TYPE_L2 = 0,
-       BNXT_ULP_STINGRAY_SYM_PKT_TYPE_0_IGNORE = 0,
-       BNXT_ULP_STINGRAY_SYM_PKT_TYPE_0_L2 = 0,
-       BNXT_ULP_STINGRAY_SYM_PKT_TYPE_1_IGNORE = 0,
-       BNXT_ULP_STINGRAY_SYM_PKT_TYPE_1_L2 = 0,
-       BNXT_ULP_STINGRAY_SYM_RECYCLE_CNT_IGNORE = 0,
-       BNXT_ULP_STINGRAY_SYM_RECYCLE_CNT_ZERO = 0,
-       BNXT_ULP_STINGRAY_SYM_RECYCLE_CNT_ONE = 1,
-       BNXT_ULP_STINGRAY_SYM_RECYCLE_CNT_TWO = 2,
-       BNXT_ULP_STINGRAY_SYM_RECYCLE_CNT_THREE = 3,
-       BNXT_ULP_STINGRAY_SYM_AGG_ERROR_IGNORE = 0,
-       BNXT_ULP_STINGRAY_SYM_AGG_ERROR_NO = 0,
-       BNXT_ULP_STINGRAY_SYM_AGG_ERROR_YES = 1,
-       BNXT_ULP_STINGRAY_SYM_RESERVED_IGNORE = 0,
-       BNXT_ULP_STINGRAY_SYM_HREC_NEXT_IGNORE = 0,
-       BNXT_ULP_STINGRAY_SYM_HREC_NEXT_NO = 0,
-       BNXT_ULP_STINGRAY_SYM_HREC_NEXT_YES = 1,
-       BNXT_ULP_STINGRAY_SYM_TL2_HDR_VALID_IGNORE = 0,
-       BNXT_ULP_STINGRAY_SYM_TL2_HDR_VALID_NO = 0,
-       BNXT_ULP_STINGRAY_SYM_TL2_HDR_VALID_YES = 1,
-       BNXT_ULP_STINGRAY_SYM_TL2_HDR_TYPE_IGNORE = 0,
-       BNXT_ULP_STINGRAY_SYM_TL2_HDR_TYPE_DIX = 0,
-       BNXT_ULP_STINGRAY_SYM_TL2_UC_MC_BC_IGNORE = 0,
-       BNXT_ULP_STINGRAY_SYM_TL2_UC_MC_BC_UC = 0,
-       BNXT_ULP_STINGRAY_SYM_TL2_UC_MC_BC_MC = 2,
-       BNXT_ULP_STINGRAY_SYM_TL2_UC_MC_BC_BC = 3,
-       BNXT_ULP_STINGRAY_SYM_TL2_VTAG_PRESENT_IGNORE = 0,
-       BNXT_ULP_STINGRAY_SYM_TL2_VTAG_PRESENT_NO = 0,
-       BNXT_ULP_STINGRAY_SYM_TL2_VTAG_PRESENT_YES = 1,
-       BNXT_ULP_STINGRAY_SYM_TL2_TWO_VTAGS_IGNORE = 0,
-       BNXT_ULP_STINGRAY_SYM_TL2_TWO_VTAGS_NO = 0,
-       BNXT_ULP_STINGRAY_SYM_TL2_TWO_VTAGS_YES = 1,
-       BNXT_ULP_STINGRAY_SYM_TL3_HDR_VALID_IGNORE = 0,
-       BNXT_ULP_STINGRAY_SYM_TL3_HDR_VALID_NO = 0,
-       BNXT_ULP_STINGRAY_SYM_TL3_HDR_VALID_YES = 1,
-       BNXT_ULP_STINGRAY_SYM_TL3_HDR_ERROR_IGNORE = 0,
-       BNXT_ULP_STINGRAY_SYM_TL3_HDR_ERROR_NO = 0,
-       BNXT_ULP_STINGRAY_SYM_TL3_HDR_ERROR_YES = 1,
-       BNXT_ULP_STINGRAY_SYM_TL3_HDR_TYPE_IGNORE = 0,
-       BNXT_ULP_STINGRAY_SYM_TL3_HDR_TYPE_IPV4 = 0,
-       BNXT_ULP_STINGRAY_SYM_TL3_HDR_TYPE_IPV6 = 1,
-       BNXT_ULP_STINGRAY_SYM_TL3_HDR_ISIP_IGNORE = 0,
-       BNXT_ULP_STINGRAY_SYM_TL3_HDR_ISIP_NO = 0,
-       BNXT_ULP_STINGRAY_SYM_TL3_HDR_ISIP_YES = 1,
-       BNXT_ULP_STINGRAY_SYM_TL3_IPV6_CMP_SRC_IGNORE = 0,
-       BNXT_ULP_STINGRAY_SYM_TL3_IPV6_CMP_SRC_NO = 0,
-       BNXT_ULP_STINGRAY_SYM_TL3_IPV6_CMP_SRC_YES = 1,
-       BNXT_ULP_STINGRAY_SYM_TL3_IPV6_CMP_DST_IGNORE = 0,
-       BNXT_ULP_STINGRAY_SYM_TL3_IPV6_CMP_DST_NO = 0,
-       BNXT_ULP_STINGRAY_SYM_TL3_IPV6_CMP_DST_YES = 1,
-       BNXT_ULP_STINGRAY_SYM_TL4_HDR_VALID_IGNORE = 0,
-       BNXT_ULP_STINGRAY_SYM_TL4_HDR_VALID_NO = 0,
-       BNXT_ULP_STINGRAY_SYM_TL4_HDR_VALID_YES = 1,
-       BNXT_ULP_STINGRAY_SYM_TL4_HDR_ERROR_IGNORE = 0,
-       BNXT_ULP_STINGRAY_SYM_TL4_HDR_ERROR_NO = 0,
-       BNXT_ULP_STINGRAY_SYM_TL4_HDR_ERROR_YES = 1,
-       BNXT_ULP_STINGRAY_SYM_TL4_HDR_IS_UDP_TCP_IGNORE = 0,
-       BNXT_ULP_STINGRAY_SYM_TL4_HDR_IS_UDP_TCP_NO = 0,
-       BNXT_ULP_STINGRAY_SYM_TL4_HDR_IS_UDP_TCP_YES = 1,
-       BNXT_ULP_STINGRAY_SYM_TL4_HDR_TYPE_IGNORE = 0,
-       BNXT_ULP_STINGRAY_SYM_TL4_HDR_TYPE_TCP = 0,
-       BNXT_ULP_STINGRAY_SYM_TL4_HDR_TYPE_UDP = 1,
-       BNXT_ULP_STINGRAY_SYM_TUN_HDR_VALID_IGNORE = 0,
-       BNXT_ULP_STINGRAY_SYM_TUN_HDR_VALID_NO = 0,
-       BNXT_ULP_STINGRAY_SYM_TUN_HDR_VALID_YES = 1,
-       BNXT_ULP_STINGRAY_SYM_TUN_HDR_ERROR_IGNORE = 0,
-       BNXT_ULP_STINGRAY_SYM_TUN_HDR_ERROR_NO = 0,
-       BNXT_ULP_STINGRAY_SYM_TUN_HDR_ERROR_YES = 1,
-       BNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_IGNORE = 0,
-       BNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_VXLAN = 0,
-       BNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_GENEVE = 1,
-       BNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_NVGRE = 2,
-       BNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_GRE = 3,
-       BNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_IPV4 = 4,
-       BNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_IPV6 = 5,
-       BNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_PPPOE = 6,
-       BNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_MPLS = 7,
-       BNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_UPAR1 = 8,
-       BNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_UPAR2 = 9,
-       BNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_NONE = 15,
-       BNXT_ULP_STINGRAY_SYM_TUN_HDR_FLAGS_IGNORE = 0,
-       BNXT_ULP_STINGRAY_SYM_L2_HDR_VALID_IGNORE = 0,
-       BNXT_ULP_STINGRAY_SYM_L2_HDR_VALID_NO = 0,
-       BNXT_ULP_STINGRAY_SYM_L2_HDR_VALID_YES = 1,
-       BNXT_ULP_STINGRAY_SYM_L2_HDR_ERROR_IGNORE = 0,
-       BNXT_ULP_STINGRAY_SYM_L2_HDR_ERROR_NO = 0,
-       BNXT_ULP_STINGRAY_SYM_L2_HDR_ERROR_YES = 1,
-       BNXT_ULP_STINGRAY_SYM_L2_HDR_TYPE_IGNORE = 0,
-       BNXT_ULP_STINGRAY_SYM_L2_HDR_TYPE_DIX = 0,
-       BNXT_ULP_STINGRAY_SYM_L2_HDR_TYPE_LLC_SNAP = 1,
-       BNXT_ULP_STINGRAY_SYM_L2_HDR_TYPE_LLC = 2,
-       BNXT_ULP_STINGRAY_SYM_L2_UC_MC_BC_IGNORE = 0,
-       BNXT_ULP_STINGRAY_SYM_L2_UC_MC_BC_UC = 0,
-       BNXT_ULP_STINGRAY_SYM_L2_UC_MC_BC_MC = 2,
-       BNXT_ULP_STINGRAY_SYM_L2_UC_MC_BC_BC = 3,
-       BNXT_ULP_STINGRAY_SYM_L2_VTAG_PRESENT_IGNORE = 0,
-       BNXT_ULP_STINGRAY_SYM_L2_VTAG_PRESENT_NO = 0,
-       BNXT_ULP_STINGRAY_SYM_L2_VTAG_PRESENT_YES = 1,
-       BNXT_ULP_STINGRAY_SYM_L2_TWO_VTAGS_IGNORE = 0,
-       BNXT_ULP_STINGRAY_SYM_L2_TWO_VTAGS_NO = 0,
-       BNXT_ULP_STINGRAY_SYM_L2_TWO_VTAGS_YES = 1,
-       BNXT_ULP_STINGRAY_SYM_L3_HDR_VALID_IGNORE = 0,
-       BNXT_ULP_STINGRAY_SYM_L3_HDR_VALID_NO = 0,
-       BNXT_ULP_STINGRAY_SYM_L3_HDR_VALID_YES = 1,
-       BNXT_ULP_STINGRAY_SYM_L3_HDR_ERROR_IGNORE = 0,
-       BNXT_ULP_STINGRAY_SYM_L3_HDR_ERROR_NO = 0,
-       BNXT_ULP_STINGRAY_SYM_L3_HDR_ERROR_YES = 1,
-       BNXT_ULP_STINGRAY_SYM_L3_HDR_TYPE_IGNORE = 0,
-       BNXT_ULP_STINGRAY_SYM_L3_HDR_TYPE_IPV4 = 0,
-       BNXT_ULP_STINGRAY_SYM_L3_HDR_TYPE_IPV6 = 1,
-       BNXT_ULP_STINGRAY_SYM_L3_HDR_TYPE_ARP = 2,
-       BNXT_ULP_STINGRAY_SYM_L3_HDR_TYPE_PTP = 3,
-       BNXT_ULP_STINGRAY_SYM_L3_HDR_TYPE_EAPOL = 4,
-       BNXT_ULP_STINGRAY_SYM_L3_HDR_TYPE_ROCE = 5,
-       BNXT_ULP_STINGRAY_SYM_L3_HDR_TYPE_FCOE = 6,
-       BNXT_ULP_STINGRAY_SYM_L3_HDR_TYPE_UPAR1 = 7,
-       BNXT_ULP_STINGRAY_SYM_L3_HDR_TYPE_UPAR2 = 8,
-       BNXT_ULP_STINGRAY_SYM_L3_HDR_ISIP_IGNORE = 0,
-       BNXT_ULP_STINGRAY_SYM_L3_HDR_ISIP_NO = 0,
-       BNXT_ULP_STINGRAY_SYM_L3_HDR_ISIP_YES = 1,
-       BNXT_ULP_STINGRAY_SYM_L3_IPV6_CMP_SRC_IGNORE = 0,
-       BNXT_ULP_STINGRAY_SYM_L3_IPV6_CMP_SRC_NO = 0,
-       BNXT_ULP_STINGRAY_SYM_L3_IPV6_CMP_SRC_YES = 1,
-       BNXT_ULP_STINGRAY_SYM_L3_IPV6_CMP_DST_IGNORE = 0,
-       BNXT_ULP_STINGRAY_SYM_L3_IPV6_CMP_DST_NO = 0,
-       BNXT_ULP_STINGRAY_SYM_L3_IPV6_CMP_DST_YES = 1,
-       BNXT_ULP_STINGRAY_SYM_L4_HDR_VALID_IGNORE = 0,
-       BNXT_ULP_STINGRAY_SYM_L4_HDR_VALID_NO = 0,
-       BNXT_ULP_STINGRAY_SYM_L4_HDR_VALID_YES = 1,
-       BNXT_ULP_STINGRAY_SYM_L4_HDR_ERROR_IGNORE = 0,
-       BNXT_ULP_STINGRAY_SYM_L4_HDR_ERROR_NO = 0,
-       BNXT_ULP_STINGRAY_SYM_L4_HDR_ERROR_YES = 1,
-       BNXT_ULP_STINGRAY_SYM_L4_HDR_TYPE_IGNORE = 0,
-       BNXT_ULP_STINGRAY_SYM_L4_HDR_TYPE_TCP = 0,
-       BNXT_ULP_STINGRAY_SYM_L4_HDR_TYPE_UDP = 1,
-       BNXT_ULP_STINGRAY_SYM_L4_HDR_TYPE_ICMP = 2,
-       BNXT_ULP_STINGRAY_SYM_L4_HDR_TYPE_UPAR1 = 3,
-       BNXT_ULP_STINGRAY_SYM_L4_HDR_TYPE_UPAR2 = 4,
-       BNXT_ULP_STINGRAY_SYM_L4_HDR_TYPE_BTH_V1 = 5,
-       BNXT_ULP_STINGRAY_SYM_L4_HDR_IS_UDP_TCP_IGNORE = 0,
-       BNXT_ULP_STINGRAY_SYM_L4_HDR_IS_UDP_TCP_NO = 0,
-       BNXT_ULP_STINGRAY_SYM_L4_HDR_IS_UDP_TCP_YES = 1,
-       BNXT_ULP_STINGRAY_SYM_POP_VLAN_NO = 0,
-       BNXT_ULP_STINGRAY_SYM_POP_VLAN_YES = 1,
-       BNXT_ULP_STINGRAY_SYM_DECAP_FUNC_NONE = 0,
-       BNXT_ULP_STINGRAY_SYM_DECAP_FUNC_THRU_TL2 = 3,
-       BNXT_ULP_STINGRAY_SYM_DECAP_FUNC_THRU_TL3 = 8,
-       BNXT_ULP_STINGRAY_SYM_DECAP_FUNC_THRU_TL4 = 9,
-       BNXT_ULP_STINGRAY_SYM_DECAP_FUNC_THRU_TUN = 10,
-       BNXT_ULP_STINGRAY_SYM_DECAP_FUNC_THRU_L2 = 11,
-       BNXT_ULP_STINGRAY_SYM_DECAP_FUNC_THRU_L3 = 12,
-       BNXT_ULP_STINGRAY_SYM_DECAP_FUNC_THRU_L4 = 13,
-       BNXT_ULP_STINGRAY_SYM_ECV_VALID_NO = 0,
-       BNXT_ULP_STINGRAY_SYM_ECV_VALID_YES = 1,
-       BNXT_ULP_STINGRAY_SYM_ECV_CUSTOM_EN_NO = 0,
-       BNXT_ULP_STINGRAY_SYM_ECV_CUSTOM_EN_YES = 1,
-       BNXT_ULP_STINGRAY_SYM_ECV_L2_EN_NO = 0,
-       BNXT_ULP_STINGRAY_SYM_ECV_L2_EN_YES = 1,
-       BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_NOP = 0,
-       BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI = 1,
-       BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_1_IVLAN_PRI = 2,
-       BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_1_REMAP_DIFFSERV = 3,
-       BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI = 4,
-       BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_2_REMAP_DIFFSERV = 5,
-       BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_0_ENCAP_PRI = 6,
-       BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_0_REMAP_DIFFSERV = 7,
-       BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_0_PRI_0 = 8,
-       BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_0_PRI_1 = 8,
-       BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_0_PRI_2 = 8,
-       BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_0_PRI_3 = 8,
-       BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_0_PRI_4 = 8,
-       BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_0_PRI_5 = 8,
-       BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_0_PRI_6 = 8,
-       BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_0_PRI_7 = 8,
-       BNXT_ULP_STINGRAY_SYM_ECV_L3_TYPE_NONE = 0,
-       BNXT_ULP_STINGRAY_SYM_ECV_L3_TYPE_IPV4 = 4,
-       BNXT_ULP_STINGRAY_SYM_ECV_L3_TYPE_IPV6 = 5,
-       BNXT_ULP_STINGRAY_SYM_ECV_L3_TYPE_MPLS_8847 = 6,
-       BNXT_ULP_STINGRAY_SYM_ECV_L3_TYPE_MPLS_8848 = 7,
-       BNXT_ULP_STINGRAY_SYM_ECV_L4_TYPE_NONE = 0,
-       BNXT_ULP_STINGRAY_SYM_ECV_L4_TYPE_UDP = 4,
-       BNXT_ULP_STINGRAY_SYM_ECV_L4_TYPE_UDP_CSUM = 5,
-       BNXT_ULP_STINGRAY_SYM_ECV_L4_TYPE_UDP_ENTROPY = 6,
-       BNXT_ULP_STINGRAY_SYM_ECV_L4_TYPE_UDP_ENTROPY_CSUM = 7,
-       BNXT_ULP_STINGRAY_SYM_ECV_TUN_TYPE_NONE = 0,
-       BNXT_ULP_STINGRAY_SYM_ECV_TUN_TYPE_GENERIC = 1,
-       BNXT_ULP_STINGRAY_SYM_ECV_TUN_TYPE_VXLAN = 2,
-       BNXT_ULP_STINGRAY_SYM_ECV_TUN_TYPE_NGE = 3,
-       BNXT_ULP_STINGRAY_SYM_ECV_TUN_TYPE_NVGRE = 4,
-       BNXT_ULP_STINGRAY_SYM_ECV_TUN_TYPE_GRE = 5,
-       BNXT_ULP_STINGRAY_SYM_EEM_ACT_REC_INT = 0,
-       BNXT_ULP_STINGRAY_SYM_EEM_EXT_FLOW_CNTR = 1,
-       BNXT_ULP_STINGRAY_SYM_UC_ACT_REC = 0,
-       BNXT_ULP_STINGRAY_SYM_MC_ACT_REC = 1,
-       BNXT_ULP_STINGRAY_SYM_ACT_REC_DROP_YES = 1,
-       BNXT_ULP_STINGRAY_SYM_ACT_REC_DROP_NO = 0,
-       BNXT_ULP_STINGRAY_SYM_ACT_REC_POP_VLAN_YES = 1,
-       BNXT_ULP_STINGRAY_SYM_ACT_REC_POP_VLAN_NO = 0,
-       BNXT_ULP_STINGRAY_SYM_ACT_REC_METER_EN_YES = 1,
-       BNXT_ULP_STINGRAY_SYM_ACT_REC_METER_EN_NO = 0,
-       BNXT_ULP_STINGRAY_SYM_LOOPBACK_PORT = 16,
-       BNXT_ULP_STINGRAY_SYM_LOOPBACK_PARIF = 15,
-       BNXT_ULP_STINGRAY_SYM_EXT_EM_MAX_KEY_SIZE = 448,
-       BNXT_ULP_STINGRAY_SYM_MATCH_TYPE_EM = 0,
-       BNXT_ULP_STINGRAY_SYM_MATCH_TYPE_WM = 1,
-       BNXT_ULP_STINGRAY_SYM_IP_PROTO_ICMP = 1,
-       BNXT_ULP_STINGRAY_SYM_IP_PROTO_IGMP = 2,
-       BNXT_ULP_STINGRAY_SYM_IP_PROTO_IP_IN_IP = 4,
-       BNXT_ULP_STINGRAY_SYM_IP_PROTO_TCP = 6,
-       BNXT_ULP_STINGRAY_SYM_IP_PROTO_UDP = 17,
-       BNXT_ULP_STINGRAY_SYM_VF_FUNC_PARIF = 15,
-       BNXT_ULP_STINGRAY_SYM_NO = 0,
-       BNXT_ULP_STINGRAY_SYM_YES = 1,
-       BNXT_ULP_STINGRAY_SYM_RECYCLE_DST = 0x800
+enum ulp_wp_sym {
+       ULP_WP_SYM_PKT_TYPE_IGNORE = 0,
+       ULP_WP_SYM_PKT_TYPE_L2 = 0,
+       ULP_WP_SYM_PKT_TYPE_0_IGNORE = 0,
+       ULP_WP_SYM_PKT_TYPE_0_L2 = 0,
+       ULP_WP_SYM_PKT_TYPE_1_IGNORE = 0,
+       ULP_WP_SYM_PKT_TYPE_1_L2 = 0,
+       ULP_WP_SYM_RECYCLE_CNT_IGNORE = 0,
+       ULP_WP_SYM_RECYCLE_CNT_ZERO = 0,
+       ULP_WP_SYM_RECYCLE_CNT_ONE = 1,
+       ULP_WP_SYM_RECYCLE_CNT_TWO = 2,
+       ULP_WP_SYM_RECYCLE_CNT_THREE = 3,
+       ULP_WP_SYM_AGG_ERROR_IGNORE = 0,
+       ULP_WP_SYM_AGG_ERROR_NO = 0,
+       ULP_WP_SYM_AGG_ERROR_YES = 1,
+       ULP_WP_SYM_RESERVED_IGNORE = 0,
+       ULP_WP_SYM_HREC_NEXT_IGNORE = 0,
+       ULP_WP_SYM_HREC_NEXT_NO = 0,
+       ULP_WP_SYM_HREC_NEXT_YES = 1,
+       ULP_WP_SYM_TL2_HDR_VALID_IGNORE = 0,
+       ULP_WP_SYM_TL2_HDR_VALID_NO = 0,
+       ULP_WP_SYM_TL2_HDR_VALID_YES = 1,
+       ULP_WP_SYM_TL2_HDR_TYPE_IGNORE = 0,
+       ULP_WP_SYM_TL2_HDR_TYPE_DIX = 0,
+       ULP_WP_SYM_TL2_UC_MC_BC_IGNORE = 0,
+       ULP_WP_SYM_TL2_UC_MC_BC_UC = 0,
+       ULP_WP_SYM_TL2_UC_MC_BC_MC = 2,
+       ULP_WP_SYM_TL2_UC_MC_BC_BC = 3,
+       ULP_WP_SYM_TL2_VTAG_PRESENT_IGNORE = 0,
+       ULP_WP_SYM_TL2_VTAG_PRESENT_NO = 0,
+       ULP_WP_SYM_TL2_VTAG_PRESENT_YES = 1,
+       ULP_WP_SYM_TL2_TWO_VTAGS_IGNORE = 0,
+       ULP_WP_SYM_TL2_TWO_VTAGS_NO = 0,
+       ULP_WP_SYM_TL2_TWO_VTAGS_YES = 1,
+       ULP_WP_SYM_TL3_HDR_VALID_IGNORE = 0,
+       ULP_WP_SYM_TL3_HDR_VALID_NO = 0,
+       ULP_WP_SYM_TL3_HDR_VALID_YES = 1,
+       ULP_WP_SYM_TL3_HDR_ERROR_IGNORE = 0,
+       ULP_WP_SYM_TL3_HDR_ERROR_NO = 0,
+       ULP_WP_SYM_TL3_HDR_ERROR_YES = 1,
+       ULP_WP_SYM_TL3_HDR_TYPE_IGNORE = 0,
+       ULP_WP_SYM_TL3_HDR_TYPE_IPV4 = 0,
+       ULP_WP_SYM_TL3_HDR_TYPE_IPV6 = 1,
+       ULP_WP_SYM_TL3_HDR_ISIP_IGNORE = 0,
+       ULP_WP_SYM_TL3_HDR_ISIP_NO = 0,
+       ULP_WP_SYM_TL3_HDR_ISIP_YES = 1,
+       ULP_WP_SYM_TL3_IPV6_CMP_SRC_IGNORE = 0,
+       ULP_WP_SYM_TL3_IPV6_CMP_SRC_NO = 0,
+       ULP_WP_SYM_TL3_IPV6_CMP_SRC_YES = 1,
+       ULP_WP_SYM_TL3_IPV6_CMP_DST_IGNORE = 0,
+       ULP_WP_SYM_TL3_IPV6_CMP_DST_NO = 0,
+       ULP_WP_SYM_TL3_IPV6_CMP_DST_YES = 1,
+       ULP_WP_SYM_TL4_HDR_VALID_IGNORE = 0,
+       ULP_WP_SYM_TL4_HDR_VALID_NO = 0,
+       ULP_WP_SYM_TL4_HDR_VALID_YES = 1,
+       ULP_WP_SYM_TL4_HDR_ERROR_IGNORE = 0,
+       ULP_WP_SYM_TL4_HDR_ERROR_NO = 0,
+       ULP_WP_SYM_TL4_HDR_ERROR_YES = 1,
+       ULP_WP_SYM_TL4_HDR_IS_UDP_TCP_IGNORE = 0,
+       ULP_WP_SYM_TL4_HDR_IS_UDP_TCP_NO = 0,
+       ULP_WP_SYM_TL4_HDR_IS_UDP_TCP_YES = 1,
+       ULP_WP_SYM_TL4_HDR_TYPE_IGNORE = 0,
+       ULP_WP_SYM_TL4_HDR_TYPE_TCP = 0,
+       ULP_WP_SYM_TL4_HDR_TYPE_UDP = 1,
+       ULP_WP_SYM_TUN_HDR_VALID_IGNORE = 0,
+       ULP_WP_SYM_TUN_HDR_VALID_NO = 0,
+       ULP_WP_SYM_TUN_HDR_VALID_YES = 1,
+       ULP_WP_SYM_TUN_HDR_ERROR_IGNORE = 0,
+       ULP_WP_SYM_TUN_HDR_ERROR_NO = 0,
+       ULP_WP_SYM_TUN_HDR_ERROR_YES = 1,
+       ULP_WP_SYM_TUN_HDR_TYPE_IGNORE = 0,
+       ULP_WP_SYM_TUN_HDR_TYPE_VXLAN = 0,
+       ULP_WP_SYM_TUN_HDR_TYPE_GENEVE = 1,
+       ULP_WP_SYM_TUN_HDR_TYPE_NVGRE = 2,
+       ULP_WP_SYM_TUN_HDR_TYPE_GRE = 3,
+       ULP_WP_SYM_TUN_HDR_TYPE_IPV4 = 4,
+       ULP_WP_SYM_TUN_HDR_TYPE_IPV6 = 5,
+       ULP_WP_SYM_TUN_HDR_TYPE_PPPOE = 6,
+       ULP_WP_SYM_TUN_HDR_TYPE_MPLS = 7,
+       ULP_WP_SYM_TUN_HDR_TYPE_UPAR1 = 8,
+       ULP_WP_SYM_TUN_HDR_TYPE_UPAR2 = 9,
+       ULP_WP_SYM_TUN_HDR_TYPE_NONE = 15,
+       ULP_WP_SYM_TUN_HDR_FLAGS_IGNORE = 0,
+       ULP_WP_SYM_L2_HDR_VALID_IGNORE = 0,
+       ULP_WP_SYM_L2_HDR_VALID_NO = 0,
+       ULP_WP_SYM_L2_HDR_VALID_YES = 1,
+       ULP_WP_SYM_L2_HDR_ERROR_IGNORE = 0,
+       ULP_WP_SYM_L2_HDR_ERROR_NO = 0,
+       ULP_WP_SYM_L2_HDR_ERROR_YES = 1,
+       ULP_WP_SYM_L2_HDR_TYPE_IGNORE = 0,
+       ULP_WP_SYM_L2_HDR_TYPE_DIX = 0,
+       ULP_WP_SYM_L2_HDR_TYPE_LLC_SNAP = 1,
+       ULP_WP_SYM_L2_HDR_TYPE_LLC = 2,
+       ULP_WP_SYM_L2_UC_MC_BC_IGNORE = 0,
+       ULP_WP_SYM_L2_UC_MC_BC_UC = 0,
+       ULP_WP_SYM_L2_UC_MC_BC_MC = 2,
+       ULP_WP_SYM_L2_UC_MC_BC_BC = 3,
+       ULP_WP_SYM_L2_VTAG_PRESENT_IGNORE = 0,
+       ULP_WP_SYM_L2_VTAG_PRESENT_NO = 0,
+       ULP_WP_SYM_L2_VTAG_PRESENT_YES = 1,
+       ULP_WP_SYM_L2_TWO_VTAGS_IGNORE = 0,
+       ULP_WP_SYM_L2_TWO_VTAGS_NO = 0,
+       ULP_WP_SYM_L2_TWO_VTAGS_YES = 1,
+       ULP_WP_SYM_L3_HDR_VALID_IGNORE = 0,
+       ULP_WP_SYM_L3_HDR_VALID_NO = 0,
+       ULP_WP_SYM_L3_HDR_VALID_YES = 1,
+       ULP_WP_SYM_L3_HDR_ERROR_IGNORE = 0,
+       ULP_WP_SYM_L3_HDR_ERROR_NO = 0,
+       ULP_WP_SYM_L3_HDR_ERROR_YES = 1,
+       ULP_WP_SYM_L3_HDR_TYPE_IGNORE = 0,
+       ULP_WP_SYM_L3_HDR_TYPE_IPV4 = 0,
+       ULP_WP_SYM_L3_HDR_TYPE_IPV6 = 1,
+       ULP_WP_SYM_L3_HDR_TYPE_ARP = 2,
+       ULP_WP_SYM_L3_HDR_TYPE_PTP = 3,
+       ULP_WP_SYM_L3_HDR_TYPE_EAPOL = 4,
+       ULP_WP_SYM_L3_HDR_TYPE_ROCE = 5,
+       ULP_WP_SYM_L3_HDR_TYPE_FCOE = 6,
+       ULP_WP_SYM_L3_HDR_TYPE_UPAR1 = 7,
+       ULP_WP_SYM_L3_HDR_TYPE_UPAR2 = 8,
+       ULP_WP_SYM_L3_HDR_ISIP_IGNORE = 0,
+       ULP_WP_SYM_L3_HDR_ISIP_NO = 0,
+       ULP_WP_SYM_L3_HDR_ISIP_YES = 1,
+       ULP_WP_SYM_L3_IPV6_CMP_SRC_IGNORE = 0,
+       ULP_WP_SYM_L3_IPV6_CMP_SRC_NO = 0,
+       ULP_WP_SYM_L3_IPV6_CMP_SRC_YES = 1,
+       ULP_WP_SYM_L3_IPV6_CMP_DST_IGNORE = 0,
+       ULP_WP_SYM_L3_IPV6_CMP_DST_NO = 0,
+       ULP_WP_SYM_L3_IPV6_CMP_DST_YES = 1,
+       ULP_WP_SYM_L4_HDR_VALID_IGNORE = 0,
+       ULP_WP_SYM_L4_HDR_VALID_NO = 0,
+       ULP_WP_SYM_L4_HDR_VALID_YES = 1,
+       ULP_WP_SYM_L4_HDR_ERROR_IGNORE = 0,
+       ULP_WP_SYM_L4_HDR_ERROR_NO = 0,
+       ULP_WP_SYM_L4_HDR_ERROR_YES = 1,
+       ULP_WP_SYM_L4_HDR_TYPE_IGNORE = 0,
+       ULP_WP_SYM_L4_HDR_TYPE_TCP = 0,
+       ULP_WP_SYM_L4_HDR_TYPE_UDP = 1,
+       ULP_WP_SYM_L4_HDR_TYPE_ICMP = 2,
+       ULP_WP_SYM_L4_HDR_TYPE_UPAR1 = 3,
+       ULP_WP_SYM_L4_HDR_TYPE_UPAR2 = 4,
+       ULP_WP_SYM_L4_HDR_TYPE_BTH_V1 = 5,
+       ULP_WP_SYM_L4_HDR_IS_UDP_TCP_IGNORE = 0,
+       ULP_WP_SYM_L4_HDR_IS_UDP_TCP_NO = 0,
+       ULP_WP_SYM_L4_HDR_IS_UDP_TCP_YES = 1,
+       ULP_WP_SYM_POP_VLAN_NO = 0,
+       ULP_WP_SYM_POP_VLAN_YES = 1,
+       ULP_WP_SYM_DECAP_FUNC_NONE = 0,
+       ULP_WP_SYM_DECAP_FUNC_THRU_TL2 = 3,
+       ULP_WP_SYM_DECAP_FUNC_THRU_TL3 = 8,
+       ULP_WP_SYM_DECAP_FUNC_THRU_TL4 = 9,
+       ULP_WP_SYM_DECAP_FUNC_THRU_TUN = 10,
+       ULP_WP_SYM_DECAP_FUNC_THRU_L2 = 11,
+       ULP_WP_SYM_DECAP_FUNC_THRU_L3 = 12,
+       ULP_WP_SYM_DECAP_FUNC_THRU_L4 = 13,
+       ULP_WP_SYM_ECV_VALID_NO = 0,
+       ULP_WP_SYM_ECV_VALID_YES = 1,
+       ULP_WP_SYM_ECV_CUSTOM_EN_NO = 0,
+       ULP_WP_SYM_ECV_CUSTOM_EN_YES = 1,
+       ULP_WP_SYM_ECV_L2_EN_NO = 0,
+       ULP_WP_SYM_ECV_L2_EN_YES = 1,
+       ULP_WP_SYM_ECV_VTAG_TYPE_NOP = 0,
+       ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI = 1,
+       ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_IVLAN_PRI = 2,
+       ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_REMAP_DIFFSERV = 3,
+       ULP_WP_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI = 4,
+       ULP_WP_SYM_ECV_VTAG_TYPE_ADD_2_REMAP_DIFFSERV = 5,
+       ULP_WP_SYM_ECV_VTAG_TYPE_ADD_0_ENCAP_PRI = 6,
+       ULP_WP_SYM_ECV_VTAG_TYPE_ADD_0_REMAP_DIFFSERV = 7,
+       ULP_WP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_0 = 8,
+       ULP_WP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_1 = 8,
+       ULP_WP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_2 = 8,
+       ULP_WP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_3 = 8,
+       ULP_WP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_4 = 8,
+       ULP_WP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_5 = 8,
+       ULP_WP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_6 = 8,
+       ULP_WP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_7 = 8,
+       ULP_WP_SYM_ECV_L3_TYPE_NONE = 0,
+       ULP_WP_SYM_ECV_L3_TYPE_IPV4 = 4,
+       ULP_WP_SYM_ECV_L3_TYPE_IPV6 = 5,
+       ULP_WP_SYM_ECV_L3_TYPE_MPLS_8847 = 6,
+       ULP_WP_SYM_ECV_L3_TYPE_MPLS_8848 = 7,
+       ULP_WP_SYM_ECV_L4_TYPE_NONE = 0,
+       ULP_WP_SYM_ECV_L4_TYPE_UDP = 4,
+       ULP_WP_SYM_ECV_L4_TYPE_UDP_CSUM = 5,
+       ULP_WP_SYM_ECV_L4_TYPE_UDP_ENTROPY = 6,
+       ULP_WP_SYM_ECV_L4_TYPE_UDP_ENTROPY_CSUM = 7,
+       ULP_WP_SYM_ECV_TUN_TYPE_NONE = 0,
+       ULP_WP_SYM_ECV_TUN_TYPE_GENERIC = 1,
+       ULP_WP_SYM_ECV_TUN_TYPE_VXLAN = 2,
+       ULP_WP_SYM_ECV_TUN_TYPE_NGE = 3,
+       ULP_WP_SYM_ECV_TUN_TYPE_NVGRE = 4,
+       ULP_WP_SYM_ECV_TUN_TYPE_GRE = 5,
+       ULP_WP_SYM_EEM_ACT_REC_INT = 1,
+       ULP_WP_SYM_EEM_EXT_FLOW_CNTR = 0,
+       ULP_WP_SYM_UC_ACT_REC = 0,
+       ULP_WP_SYM_MC_ACT_REC = 1,
+       ULP_WP_SYM_ACT_REC_DROP_YES = 1,
+       ULP_WP_SYM_ACT_REC_DROP_NO = 0,
+       ULP_WP_SYM_ACT_REC_POP_VLAN_YES = 1,
+       ULP_WP_SYM_ACT_REC_POP_VLAN_NO = 0,
+       ULP_WP_SYM_ACT_REC_METER_EN_YES = 1,
+       ULP_WP_SYM_ACT_REC_METER_EN_NO = 0,
+       ULP_WP_SYM_LOOPBACK_PORT = 4,
+       ULP_WP_SYM_LOOPBACK_PARIF = 15,
+       ULP_WP_SYM_EXT_EM_MAX_KEY_SIZE = 448,
+       ULP_WP_SYM_MATCH_TYPE_EM = 0,
+       ULP_WP_SYM_MATCH_TYPE_WM = 1,
+       ULP_WP_SYM_IP_PROTO_ICMP = 1,
+       ULP_WP_SYM_IP_PROTO_IGMP = 2,
+       ULP_WP_SYM_IP_PROTO_IP_IN_IP = 4,
+       ULP_WP_SYM_IP_PROTO_TCP = 6,
+       ULP_WP_SYM_IP_PROTO_UDP = 17,
+       ULP_WP_SYM_VF_FUNC_PARIF = 15,
+       ULP_WP_SYM_NO = 0,
+       ULP_WP_SYM_YES = 1,
+       ULP_WP_SYM_RECYCLE_DST = 0x800
+};
+
+enum ulp_sr_sym {
+       ULP_SR_SYM_PKT_TYPE_IGNORE = 0,
+       ULP_SR_SYM_PKT_TYPE_L2 = 0,
+       ULP_SR_SYM_PKT_TYPE_0_IGNORE = 0,
+       ULP_SR_SYM_PKT_TYPE_0_L2 = 0,
+       ULP_SR_SYM_PKT_TYPE_1_IGNORE = 0,
+       ULP_SR_SYM_PKT_TYPE_1_L2 = 0,
+       ULP_SR_SYM_RECYCLE_CNT_IGNORE = 0,
+       ULP_SR_SYM_RECYCLE_CNT_ZERO = 0,
+       ULP_SR_SYM_RECYCLE_CNT_ONE = 1,
+       ULP_SR_SYM_RECYCLE_CNT_TWO = 2,
+       ULP_SR_SYM_RECYCLE_CNT_THREE = 3,
+       ULP_SR_SYM_AGG_ERROR_IGNORE = 0,
+       ULP_SR_SYM_AGG_ERROR_NO = 0,
+       ULP_SR_SYM_AGG_ERROR_YES = 1,
+       ULP_SR_SYM_RESERVED_IGNORE = 0,
+       ULP_SR_SYM_HREC_NEXT_IGNORE = 0,
+       ULP_SR_SYM_HREC_NEXT_NO = 0,
+       ULP_SR_SYM_HREC_NEXT_YES = 1,
+       ULP_SR_SYM_TL2_HDR_VALID_IGNORE = 0,
+       ULP_SR_SYM_TL2_HDR_VALID_NO = 0,
+       ULP_SR_SYM_TL2_HDR_VALID_YES = 1,
+       ULP_SR_SYM_TL2_HDR_TYPE_IGNORE = 0,
+       ULP_SR_SYM_TL2_HDR_TYPE_DIX = 0,
+       ULP_SR_SYM_TL2_UC_MC_BC_IGNORE = 0,
+       ULP_SR_SYM_TL2_UC_MC_BC_UC = 0,
+       ULP_SR_SYM_TL2_UC_MC_BC_MC = 2,
+       ULP_SR_SYM_TL2_UC_MC_BC_BC = 3,
+       ULP_SR_SYM_TL2_VTAG_PRESENT_IGNORE = 0,
+       ULP_SR_SYM_TL2_VTAG_PRESENT_NO = 0,
+       ULP_SR_SYM_TL2_VTAG_PRESENT_YES = 1,
+       ULP_SR_SYM_TL2_TWO_VTAGS_IGNORE = 0,
+       ULP_SR_SYM_TL2_TWO_VTAGS_NO = 0,
+       ULP_SR_SYM_TL2_TWO_VTAGS_YES = 1,
+       ULP_SR_SYM_TL3_HDR_VALID_IGNORE = 0,
+       ULP_SR_SYM_TL3_HDR_VALID_NO = 0,
+       ULP_SR_SYM_TL3_HDR_VALID_YES = 1,
+       ULP_SR_SYM_TL3_HDR_ERROR_IGNORE = 0,
+       ULP_SR_SYM_TL3_HDR_ERROR_NO = 0,
+       ULP_SR_SYM_TL3_HDR_ERROR_YES = 1,
+       ULP_SR_SYM_TL3_HDR_TYPE_IGNORE = 0,
+       ULP_SR_SYM_TL3_HDR_TYPE_IPV4 = 0,
+       ULP_SR_SYM_TL3_HDR_TYPE_IPV6 = 1,
+       ULP_SR_SYM_TL3_HDR_ISIP_IGNORE = 0,
+       ULP_SR_SYM_TL3_HDR_ISIP_NO = 0,
+       ULP_SR_SYM_TL3_HDR_ISIP_YES = 1,
+       ULP_SR_SYM_TL3_IPV6_CMP_SRC_IGNORE = 0,
+       ULP_SR_SYM_TL3_IPV6_CMP_SRC_NO = 0,
+       ULP_SR_SYM_TL3_IPV6_CMP_SRC_YES = 1,
+       ULP_SR_SYM_TL3_IPV6_CMP_DST_IGNORE = 0,
+       ULP_SR_SYM_TL3_IPV6_CMP_DST_NO = 0,
+       ULP_SR_SYM_TL3_IPV6_CMP_DST_YES = 1,
+       ULP_SR_SYM_TL4_HDR_VALID_IGNORE = 0,
+       ULP_SR_SYM_TL4_HDR_VALID_NO = 0,
+       ULP_SR_SYM_TL4_HDR_VALID_YES = 1,
+       ULP_SR_SYM_TL4_HDR_ERROR_IGNORE = 0,
+       ULP_SR_SYM_TL4_HDR_ERROR_NO = 0,
+       ULP_SR_SYM_TL4_HDR_ERROR_YES = 1,
+       ULP_SR_SYM_TL4_HDR_IS_UDP_TCP_IGNORE = 0,
+       ULP_SR_SYM_TL4_HDR_IS_UDP_TCP_NO = 0,
+       ULP_SR_SYM_TL4_HDR_IS_UDP_TCP_YES = 1,
+       ULP_SR_SYM_TL4_HDR_TYPE_IGNORE = 0,
+       ULP_SR_SYM_TL4_HDR_TYPE_TCP = 0,
+       ULP_SR_SYM_TL4_HDR_TYPE_UDP = 1,
+       ULP_SR_SYM_TUN_HDR_VALID_IGNORE = 0,
+       ULP_SR_SYM_TUN_HDR_VALID_NO = 0,
+       ULP_SR_SYM_TUN_HDR_VALID_YES = 1,
+       ULP_SR_SYM_TUN_HDR_ERROR_IGNORE = 0,
+       ULP_SR_SYM_TUN_HDR_ERROR_NO = 0,
+       ULP_SR_SYM_TUN_HDR_ERROR_YES = 1,
+       ULP_SR_SYM_TUN_HDR_TYPE_IGNORE = 0,
+       ULP_SR_SYM_TUN_HDR_TYPE_VXLAN = 0,
+       ULP_SR_SYM_TUN_HDR_TYPE_GENEVE = 1,
+       ULP_SR_SYM_TUN_HDR_TYPE_NVGRE = 2,
+       ULP_SR_SYM_TUN_HDR_TYPE_GRE = 3,
+       ULP_SR_SYM_TUN_HDR_TYPE_IPV4 = 4,
+       ULP_SR_SYM_TUN_HDR_TYPE_IPV6 = 5,
+       ULP_SR_SYM_TUN_HDR_TYPE_PPPOE = 6,
+       ULP_SR_SYM_TUN_HDR_TYPE_MPLS = 7,
+       ULP_SR_SYM_TUN_HDR_TYPE_UPAR1 = 8,
+       ULP_SR_SYM_TUN_HDR_TYPE_UPAR2 = 9,
+       ULP_SR_SYM_TUN_HDR_TYPE_NONE = 15,
+       ULP_SR_SYM_TUN_HDR_FLAGS_IGNORE = 0,
+       ULP_SR_SYM_L2_HDR_VALID_IGNORE = 0,
+       ULP_SR_SYM_L2_HDR_VALID_NO = 0,
+       ULP_SR_SYM_L2_HDR_VALID_YES = 1,
+       ULP_SR_SYM_L2_HDR_ERROR_IGNORE = 0,
+       ULP_SR_SYM_L2_HDR_ERROR_NO = 0,
+       ULP_SR_SYM_L2_HDR_ERROR_YES = 1,
+       ULP_SR_SYM_L2_HDR_TYPE_IGNORE = 0,
+       ULP_SR_SYM_L2_HDR_TYPE_DIX = 0,
+       ULP_SR_SYM_L2_HDR_TYPE_LLC_SNAP = 1,
+       ULP_SR_SYM_L2_HDR_TYPE_LLC = 2,
+       ULP_SR_SYM_L2_UC_MC_BC_IGNORE = 0,
+       ULP_SR_SYM_L2_UC_MC_BC_UC = 0,
+       ULP_SR_SYM_L2_UC_MC_BC_MC = 2,
+       ULP_SR_SYM_L2_UC_MC_BC_BC = 3,
+       ULP_SR_SYM_L2_VTAG_PRESENT_IGNORE = 0,
+       ULP_SR_SYM_L2_VTAG_PRESENT_NO = 0,
+       ULP_SR_SYM_L2_VTAG_PRESENT_YES = 1,
+       ULP_SR_SYM_L2_TWO_VTAGS_IGNORE = 0,
+       ULP_SR_SYM_L2_TWO_VTAGS_NO = 0,
+       ULP_SR_SYM_L2_TWO_VTAGS_YES = 1,
+       ULP_SR_SYM_L3_HDR_VALID_IGNORE = 0,
+       ULP_SR_SYM_L3_HDR_VALID_NO = 0,
+       ULP_SR_SYM_L3_HDR_VALID_YES = 1,
+       ULP_SR_SYM_L3_HDR_ERROR_IGNORE = 0,
+       ULP_SR_SYM_L3_HDR_ERROR_NO = 0,
+       ULP_SR_SYM_L3_HDR_ERROR_YES = 1,
+       ULP_SR_SYM_L3_HDR_TYPE_IGNORE = 0,
+       ULP_SR_SYM_L3_HDR_TYPE_IPV4 = 0,
+       ULP_SR_SYM_L3_HDR_TYPE_IPV6 = 1,
+       ULP_SR_SYM_L3_HDR_TYPE_ARP = 2,
+       ULP_SR_SYM_L3_HDR_TYPE_PTP = 3,
+       ULP_SR_SYM_L3_HDR_TYPE_EAPOL = 4,
+       ULP_SR_SYM_L3_HDR_TYPE_ROCE = 5,
+       ULP_SR_SYM_L3_HDR_TYPE_FCOE = 6,
+       ULP_SR_SYM_L3_HDR_TYPE_UPAR1 = 7,
+       ULP_SR_SYM_L3_HDR_TYPE_UPAR2 = 8,
+       ULP_SR_SYM_L3_HDR_ISIP_IGNORE = 0,
+       ULP_SR_SYM_L3_HDR_ISIP_NO = 0,
+       ULP_SR_SYM_L3_HDR_ISIP_YES = 1,
+       ULP_SR_SYM_L3_IPV6_CMP_SRC_IGNORE = 0,
+       ULP_SR_SYM_L3_IPV6_CMP_SRC_NO = 0,
+       ULP_SR_SYM_L3_IPV6_CMP_SRC_YES = 1,
+       ULP_SR_SYM_L3_IPV6_CMP_DST_IGNORE = 0,
+       ULP_SR_SYM_L3_IPV6_CMP_DST_NO = 0,
+       ULP_SR_SYM_L3_IPV6_CMP_DST_YES = 1,
+       ULP_SR_SYM_L4_HDR_VALID_IGNORE = 0,
+       ULP_SR_SYM_L4_HDR_VALID_NO = 0,
+       ULP_SR_SYM_L4_HDR_VALID_YES = 1,
+       ULP_SR_SYM_L4_HDR_ERROR_IGNORE = 0,
+       ULP_SR_SYM_L4_HDR_ERROR_NO = 0,
+       ULP_SR_SYM_L4_HDR_ERROR_YES = 1,
+       ULP_SR_SYM_L4_HDR_TYPE_IGNORE = 0,
+       ULP_SR_SYM_L4_HDR_TYPE_TCP = 0,
+       ULP_SR_SYM_L4_HDR_TYPE_UDP = 1,
+       ULP_SR_SYM_L4_HDR_TYPE_ICMP = 2,
+       ULP_SR_SYM_L4_HDR_TYPE_UPAR1 = 3,
+       ULP_SR_SYM_L4_HDR_TYPE_UPAR2 = 4,
+       ULP_SR_SYM_L4_HDR_TYPE_BTH_V1 = 5,
+       ULP_SR_SYM_L4_HDR_IS_UDP_TCP_IGNORE = 0,
+       ULP_SR_SYM_L4_HDR_IS_UDP_TCP_NO = 0,
+       ULP_SR_SYM_L4_HDR_IS_UDP_TCP_YES = 1,
+       ULP_SR_SYM_POP_VLAN_NO = 0,
+       ULP_SR_SYM_POP_VLAN_YES = 1,
+       ULP_SR_SYM_DECAP_FUNC_NONE = 0,
+       ULP_SR_SYM_DECAP_FUNC_THRU_TL2 = 3,
+       ULP_SR_SYM_DECAP_FUNC_THRU_TL3 = 8,
+       ULP_SR_SYM_DECAP_FUNC_THRU_TL4 = 9,
+       ULP_SR_SYM_DECAP_FUNC_THRU_TUN = 10,
+       ULP_SR_SYM_DECAP_FUNC_THRU_L2 = 11,
+       ULP_SR_SYM_DECAP_FUNC_THRU_L3 = 12,
+       ULP_SR_SYM_DECAP_FUNC_THRU_L4 = 13,
+       ULP_SR_SYM_ECV_VALID_NO = 0,
+       ULP_SR_SYM_ECV_VALID_YES = 1,
+       ULP_SR_SYM_ECV_CUSTOM_EN_NO = 0,
+       ULP_SR_SYM_ECV_CUSTOM_EN_YES = 1,
+       ULP_SR_SYM_ECV_L2_EN_NO = 0,
+       ULP_SR_SYM_ECV_L2_EN_YES = 1,
+       ULP_SR_SYM_ECV_VTAG_TYPE_NOP = 0,
+       ULP_SR_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI = 1,
+       ULP_SR_SYM_ECV_VTAG_TYPE_ADD_1_IVLAN_PRI = 2,
+       ULP_SR_SYM_ECV_VTAG_TYPE_ADD_1_REMAP_DIFFSERV = 3,
+       ULP_SR_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI = 4,
+       ULP_SR_SYM_ECV_VTAG_TYPE_ADD_2_REMAP_DIFFSERV = 5,
+       ULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_ENCAP_PRI = 6,
+       ULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_REMAP_DIFFSERV = 7,
+       ULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_0 = 8,
+       ULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_1 = 8,
+       ULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_2 = 8,
+       ULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_3 = 8,
+       ULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_4 = 8,
+       ULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_5 = 8,
+       ULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_6 = 8,
+       ULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_7 = 8,
+       ULP_SR_SYM_ECV_L3_TYPE_NONE = 0,
+       ULP_SR_SYM_ECV_L3_TYPE_IPV4 = 4,
+       ULP_SR_SYM_ECV_L3_TYPE_IPV6 = 5,
+       ULP_SR_SYM_ECV_L3_TYPE_MPLS_8847 = 6,
+       ULP_SR_SYM_ECV_L3_TYPE_MPLS_8848 = 7,
+       ULP_SR_SYM_ECV_L4_TYPE_NONE = 0,
+       ULP_SR_SYM_ECV_L4_TYPE_UDP = 4,
+       ULP_SR_SYM_ECV_L4_TYPE_UDP_CSUM = 5,
+       ULP_SR_SYM_ECV_L4_TYPE_UDP_ENTROPY = 6,
+       ULP_SR_SYM_ECV_L4_TYPE_UDP_ENTROPY_CSUM = 7,
+       ULP_SR_SYM_ECV_TUN_TYPE_NONE = 0,
+       ULP_SR_SYM_ECV_TUN_TYPE_GENERIC = 1,
+       ULP_SR_SYM_ECV_TUN_TYPE_VXLAN = 2,
+       ULP_SR_SYM_ECV_TUN_TYPE_NGE = 3,
+       ULP_SR_SYM_ECV_TUN_TYPE_NVGRE = 4,
+       ULP_SR_SYM_ECV_TUN_TYPE_GRE = 5,
+       ULP_SR_SYM_EEM_ACT_REC_INT = 0,
+       ULP_SR_SYM_EEM_EXT_FLOW_CNTR = 1,
+       ULP_SR_SYM_UC_ACT_REC = 0,
+       ULP_SR_SYM_MC_ACT_REC = 1,
+       ULP_SR_SYM_ACT_REC_DROP_YES = 1,
+       ULP_SR_SYM_ACT_REC_DROP_NO = 0,
+       ULP_SR_SYM_ACT_REC_POP_VLAN_YES = 1,
+       ULP_SR_SYM_ACT_REC_POP_VLAN_NO = 0,
+       ULP_SR_SYM_ACT_REC_METER_EN_YES = 1,
+       ULP_SR_SYM_ACT_REC_METER_EN_NO = 0,
+       ULP_SR_SYM_LOOPBACK_PORT = 16,
+       ULP_SR_SYM_LOOPBACK_PARIF = 15,
+       ULP_SR_SYM_EXT_EM_MAX_KEY_SIZE = 448,
+       ULP_SR_SYM_MATCH_TYPE_EM = 0,
+       ULP_SR_SYM_MATCH_TYPE_WM = 1,
+       ULP_SR_SYM_IP_PROTO_ICMP = 1,
+       ULP_SR_SYM_IP_PROTO_IGMP = 2,
+       ULP_SR_SYM_IP_PROTO_IP_IN_IP = 4,
+       ULP_SR_SYM_IP_PROTO_TCP = 6,
+       ULP_SR_SYM_IP_PROTO_UDP = 17,
+       ULP_SR_SYM_VF_FUNC_PARIF = 15,
+       ULP_SR_SYM_NO = 0,
+       ULP_SR_SYM_YES = 1,
+       ULP_SR_SYM_RECYCLE_DST = 0x800
 };
 
 enum bnxt_ulp_class_hid {
-       BNXT_ULP_CLASS_HID_00fc = 0x00fc,
-       BNXT_ULP_CLASS_HID_0046 = 0x0046,
-       BNXT_ULP_CLASS_HID_0056 = 0x0056,
-       BNXT_ULP_CLASS_HID_00b8 = 0x00b8,
-       BNXT_ULP_CLASS_HID_0041 = 0x0041,
-       BNXT_ULP_CLASS_HID_00ab = 0x00ab,
-       BNXT_ULP_CLASS_HID_0053 = 0x0053,
-       BNXT_ULP_CLASS_HID_00a5 = 0x00a5,
-       BNXT_ULP_CLASS_HID_0069 = 0x0069,
-       BNXT_ULP_CLASS_HID_009d = 0x009d,
+       BNXT_ULP_CLASS_HID_07e0 = 0x07e0,
+       BNXT_ULP_CLASS_HID_01dc = 0x01dc,
+       BNXT_ULP_CLASS_HID_006e = 0x006e,
+       BNXT_ULP_CLASS_HID_025a = 0x025a,
+       BNXT_ULP_CLASS_HID_0146 = 0x0146,
+       BNXT_ULP_CLASS_HID_0332 = 0x0332,
+       BNXT_ULP_CLASS_HID_01c4 = 0x01c4,
+       BNXT_ULP_CLASS_HID_078a = 0x078a,
+       BNXT_ULP_CLASS_HID_02ed = 0x02ed,
+       BNXT_ULP_CLASS_HID_04d9 = 0x04d9,
+       BNXT_ULP_CLASS_HID_036b = 0x036b,
+       BNXT_ULP_CLASS_HID_0131 = 0x0131,
+       BNXT_ULP_CLASS_HID_0217 = 0x0217,
+       BNXT_ULP_CLASS_HID_03c3 = 0x03c3,
+       BNXT_ULP_CLASS_HID_0295 = 0x0295,
+       BNXT_ULP_CLASS_HID_0441 = 0x0441,
+       BNXT_ULP_CLASS_HID_0095 = 0x0095,
+       BNXT_ULP_CLASS_HID_0241 = 0x0241,
+       BNXT_ULP_CLASS_HID_04ed = 0x04ed,
+       BNXT_ULP_CLASS_HID_06d9 = 0x06d9,
+       BNXT_ULP_CLASS_HID_07bf = 0x07bf,
+       BNXT_ULP_CLASS_HID_016b = 0x016b,
+       BNXT_ULP_CLASS_HID_0417 = 0x0417,
+       BNXT_ULP_CLASS_HID_05c3 = 0x05c3,
+       BNXT_ULP_CLASS_HID_0187 = 0x0187,
+       BNXT_ULP_CLASS_HID_0373 = 0x0373,
+       BNXT_ULP_CLASS_HID_0205 = 0x0205,
+       BNXT_ULP_CLASS_HID_03f1 = 0x03f1,
+       BNXT_ULP_CLASS_HID_00a1 = 0x00a1,
+       BNXT_ULP_CLASS_HID_029d = 0x029d,
+       BNXT_ULP_CLASS_HID_012f = 0x012f,
+       BNXT_ULP_CLASS_HID_031b = 0x031b,
+       BNXT_ULP_CLASS_HID_072f = 0x072f,
+       BNXT_ULP_CLASS_HID_011b = 0x011b,
+       BNXT_ULP_CLASS_HID_0387 = 0x0387,
+       BNXT_ULP_CLASS_HID_0573 = 0x0573,
+       BNXT_ULP_CLASS_HID_0649 = 0x0649,
        BNXT_ULP_CLASS_HID_0005 = 0x0005,
-       BNXT_ULP_CLASS_HID_006f = 0x006f,
-       BNXT_ULP_CLASS_HID_00af = 0x00af,
-       BNXT_ULP_CLASS_HID_00d3 = 0x00d3,
-       BNXT_ULP_CLASS_HID_005b = 0x005b,
-       BNXT_ULP_CLASS_HID_00ad = 0x00ad,
-       BNXT_ULP_CLASS_HID_0091 = 0x0091,
-       BNXT_ULP_CLASS_HID_00fb = 0x00fb,
-       BNXT_ULP_CLASS_HID_0063 = 0x0063,
-       BNXT_ULP_CLASS_HID_0097 = 0x0097,
-       BNXT_ULP_CLASS_HID_00cc = 0x00cc,
-       BNXT_ULP_CLASS_HID_00f0 = 0x00f0,
-       BNXT_ULP_CLASS_HID_00c0 = 0x00c0,
-       BNXT_ULP_CLASS_HID_002a = 0x002a,
-       BNXT_ULP_CLASS_HID_00c7 = 0x00c7,
-       BNXT_ULP_CLASS_HID_0029 = 0x0029,
-       BNXT_ULP_CLASS_HID_00d1 = 0x00d1,
-       BNXT_ULP_CLASS_HID_003b = 0x003b,
+       BNXT_ULP_CLASS_HID_02a1 = 0x02a1,
+       BNXT_ULP_CLASS_HID_049d = 0x049d,
+       BNXT_ULP_CLASS_HID_01ea = 0x01ea,
+       BNXT_ULP_CLASS_HID_03de = 0x03de,
+       BNXT_ULP_CLASS_HID_0672 = 0x0672,
+       BNXT_ULP_CLASS_HID_0026 = 0x0026,
+       BNXT_ULP_CLASS_HID_0746 = 0x0746,
+       BNXT_ULP_CLASS_HID_010a = 0x010a,
+       BNXT_ULP_CLASS_HID_03ae = 0x03ae,
+       BNXT_ULP_CLASS_HID_0592 = 0x0592,
+       BNXT_ULP_CLASS_HID_07d0 = 0x07d0,
+       BNXT_ULP_CLASS_HID_01ec = 0x01ec,
+       BNXT_ULP_CLASS_HID_005e = 0x005e,
+       BNXT_ULP_CLASS_HID_026a = 0x026a,
+       BNXT_ULP_CLASS_HID_0176 = 0x0176,
+       BNXT_ULP_CLASS_HID_0302 = 0x0302,
+       BNXT_ULP_CLASS_HID_01f4 = 0x01f4,
+       BNXT_ULP_CLASS_HID_07ba = 0x07ba,
+       BNXT_ULP_CLASS_HID_06a7 = 0x06a7,
+       BNXT_ULP_CLASS_HID_006b = 0x006b,
+       BNXT_ULP_CLASS_HID_0725 = 0x0725,
+       BNXT_ULP_CLASS_HID_00e9 = 0x00e9,
+       BNXT_ULP_CLASS_HID_05d9 = 0x05d9,
+       BNXT_ULP_CLASS_HID_078d = 0x078d,
+       BNXT_ULP_CLASS_HID_065f = 0x065f,
+       BNXT_ULP_CLASS_HID_0003 = 0x0003,
+       BNXT_ULP_CLASS_HID_045f = 0x045f,
+       BNXT_ULP_CLASS_HID_0603 = 0x0603,
+       BNXT_ULP_CLASS_HID_00a7 = 0x00a7,
+       BNXT_ULP_CLASS_HID_026b = 0x026b,
+       BNXT_ULP_CLASS_HID_0371 = 0x0371,
+       BNXT_ULP_CLASS_HID_0525 = 0x0525,
+       BNXT_ULP_CLASS_HID_07d9 = 0x07d9,
+       BNXT_ULP_CLASS_HID_018d = 0x018d,
+       BNXT_ULP_CLASS_HID_0177 = 0x0177,
+       BNXT_ULP_CLASS_HID_033b = 0x033b,
+       BNXT_ULP_CLASS_HID_05df = 0x05df,
+       BNXT_ULP_CLASS_HID_0783 = 0x0783,
+       BNXT_ULP_CLASS_HID_0069 = 0x0069,
+       BNXT_ULP_CLASS_HID_025d = 0x025d,
        BNXT_ULP_CLASS_HID_00ef = 0x00ef,
-       BNXT_ULP_CLASS_HID_0013 = 0x0013,
-       BNXT_ULP_CLASS_HID_009b = 0x009b,
-       BNXT_ULP_CLASS_HID_00ed = 0x00ed,
-       BNXT_ULP_CLASS_HID_002d = 0x002d,
-       BNXT_ULP_CLASS_HID_0051 = 0x0051,
+       BNXT_ULP_CLASS_HID_06a5 = 0x06a5,
+       BNXT_ULP_CLASS_HID_02f1 = 0x02f1,
+       BNXT_ULP_CLASS_HID_04a5 = 0x04a5,
+       BNXT_ULP_CLASS_HID_0377 = 0x0377,
+       BNXT_ULP_CLASS_HID_053b = 0x053b,
+       BNXT_ULP_CLASS_HID_0601 = 0x0601,
+       BNXT_ULP_CLASS_HID_03df = 0x03df,
+       BNXT_ULP_CLASS_HID_0269 = 0x0269,
+       BNXT_ULP_CLASS_HID_045d = 0x045d,
+       BNXT_ULP_CLASS_HID_02dd = 0x02dd,
+       BNXT_ULP_CLASS_HID_04e9 = 0x04e9,
+       BNXT_ULP_CLASS_HID_035b = 0x035b,
+       BNXT_ULP_CLASS_HID_0101 = 0x0101,
+       BNXT_ULP_CLASS_HID_0227 = 0x0227,
+       BNXT_ULP_CLASS_HID_03f3 = 0x03f3,
+       BNXT_ULP_CLASS_HID_02a5 = 0x02a5,
+       BNXT_ULP_CLASS_HID_0471 = 0x0471,
+       BNXT_ULP_CLASS_HID_00a5 = 0x00a5,
+       BNXT_ULP_CLASS_HID_0271 = 0x0271,
+       BNXT_ULP_CLASS_HID_04dd = 0x04dd,
+       BNXT_ULP_CLASS_HID_06e9 = 0x06e9,
+       BNXT_ULP_CLASS_HID_078f = 0x078f,
+       BNXT_ULP_CLASS_HID_015b = 0x015b,
+       BNXT_ULP_CLASS_HID_0427 = 0x0427,
+       BNXT_ULP_CLASS_HID_05f3 = 0x05f3,
+       BNXT_ULP_CLASS_HID_01b7 = 0x01b7,
+       BNXT_ULP_CLASS_HID_0343 = 0x0343,
+       BNXT_ULP_CLASS_HID_0235 = 0x0235,
+       BNXT_ULP_CLASS_HID_03c1 = 0x03c1,
+       BNXT_ULP_CLASS_HID_0091 = 0x0091,
+       BNXT_ULP_CLASS_HID_02ad = 0x02ad,
+       BNXT_ULP_CLASS_HID_011f = 0x011f,
+       BNXT_ULP_CLASS_HID_032b = 0x032b,
+       BNXT_ULP_CLASS_HID_071f = 0x071f,
+       BNXT_ULP_CLASS_HID_012b = 0x012b,
+       BNXT_ULP_CLASS_HID_03b7 = 0x03b7,
+       BNXT_ULP_CLASS_HID_0543 = 0x0543,
+       BNXT_ULP_CLASS_HID_0679 = 0x0679,
+       BNXT_ULP_CLASS_HID_0035 = 0x0035,
+       BNXT_ULP_CLASS_HID_0291 = 0x0291,
+       BNXT_ULP_CLASS_HID_04ad = 0x04ad,
+       BNXT_ULP_CLASS_HID_01da = 0x01da,
+       BNXT_ULP_CLASS_HID_03ee = 0x03ee,
+       BNXT_ULP_CLASS_HID_0642 = 0x0642,
+       BNXT_ULP_CLASS_HID_0016 = 0x0016,
+       BNXT_ULP_CLASS_HID_0776 = 0x0776,
+       BNXT_ULP_CLASS_HID_013a = 0x013a,
+       BNXT_ULP_CLASS_HID_039e = 0x039e,
+       BNXT_ULP_CLASS_HID_05a2 = 0x05a2,
+       BNXT_ULP_CLASS_HID_0697 = 0x0697,
+       BNXT_ULP_CLASS_HID_005b = 0x005b,
+       BNXT_ULP_CLASS_HID_0715 = 0x0715,
        BNXT_ULP_CLASS_HID_00d9 = 0x00d9,
-       BNXT_ULP_CLASS_HID_0023 = 0x0023,
-       BNXT_ULP_CLASS_HID_0017 = 0x0017,
-       BNXT_ULP_CLASS_HID_0079 = 0x0079,
-       BNXT_ULP_CLASS_HID_00e1 = 0x00e1,
-       BNXT_ULP_CLASS_HID_0015 = 0x0015
+       BNXT_ULP_CLASS_HID_05e9 = 0x05e9,
+       BNXT_ULP_CLASS_HID_07bd = 0x07bd,
+       BNXT_ULP_CLASS_HID_066f = 0x066f,
+       BNXT_ULP_CLASS_HID_0033 = 0x0033,
+       BNXT_ULP_CLASS_HID_046f = 0x046f,
+       BNXT_ULP_CLASS_HID_0633 = 0x0633,
+       BNXT_ULP_CLASS_HID_0097 = 0x0097,
+       BNXT_ULP_CLASS_HID_025b = 0x025b,
+       BNXT_ULP_CLASS_HID_0341 = 0x0341,
+       BNXT_ULP_CLASS_HID_0515 = 0x0515,
+       BNXT_ULP_CLASS_HID_07e9 = 0x07e9,
+       BNXT_ULP_CLASS_HID_01bd = 0x01bd,
+       BNXT_ULP_CLASS_HID_0147 = 0x0147,
+       BNXT_ULP_CLASS_HID_030b = 0x030b,
+       BNXT_ULP_CLASS_HID_05ef = 0x05ef,
+       BNXT_ULP_CLASS_HID_07b3 = 0x07b3,
+       BNXT_ULP_CLASS_HID_0059 = 0x0059,
+       BNXT_ULP_CLASS_HID_026d = 0x026d,
+       BNXT_ULP_CLASS_HID_00df = 0x00df,
+       BNXT_ULP_CLASS_HID_0695 = 0x0695,
+       BNXT_ULP_CLASS_HID_02c1 = 0x02c1,
+       BNXT_ULP_CLASS_HID_0495 = 0x0495,
+       BNXT_ULP_CLASS_HID_0347 = 0x0347,
+       BNXT_ULP_CLASS_HID_050b = 0x050b,
+       BNXT_ULP_CLASS_HID_0631 = 0x0631,
+       BNXT_ULP_CLASS_HID_03ef = 0x03ef,
+       BNXT_ULP_CLASS_HID_0259 = 0x0259,
+       BNXT_ULP_CLASS_HID_046d = 0x046d
 };
 
 enum bnxt_ulp_act_hid {
@@ -1013,11 +1139,11 @@ enum bnxt_ulp_act_hid {
 };
 
 enum bnxt_ulp_df_tpl {
-       BNXT_ULP_DF_TPL_PORT_TO_VS = 3,
-       BNXT_ULP_DF_TPL_VS_TO_PORT = 4,
-       BNXT_ULP_DF_TPL_VFREP_TO_VF = 5,
-       BNXT_ULP_DF_TPL_VF_TO_VFREP = 6,
-       BNXT_ULP_DF_TPL_LOOPBACK_ACTION_REC = 7
+       BNXT_ULP_DF_TPL_PORT_TO_VS = 2,
+       BNXT_ULP_DF_TPL_VS_TO_PORT = 3,
+       BNXT_ULP_DF_TPL_VFREP_TO_VF = 4,
+       BNXT_ULP_DF_TPL_VF_TO_VFREP = 5,
+       BNXT_ULP_DF_TPL_LOOPBACK_ACTION_REC = 6
 };
 
 #endif

diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h
index 29c9247..b0c32b4 100644 (file)
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h
@@ -3,108 +3,108 @@
  * All rights reserved.
  */
 
-/* date: Wed Nov 18 12:19:40 2020 */
+/* date: Tue Dec  1 10:17:11 2020 */
 
 #ifndef ULP_HDR_FIELD_ENUMS_H_
 #define ULP_HDR_FIELD_ENUMS_H_
 
 enum bnxt_ulp_glb_hf {
-       BNXT_ULP_GLB_HF_WM,
-       BNXT_ULP_GLB_HF_SVIF_INDEX,
-       BNXT_ULP_GLB_HF_O_ETH_DMAC,
-       BNXT_ULP_GLB_HF_I_ETH_DMAC,
-       BNXT_ULP_GLB_HF_O_ETH_SMAC,
-       BNXT_ULP_GLB_HF_I_ETH_SMAC,
-       BNXT_ULP_GLB_HF_O_ETH_TYPE,
-       BNXT_ULP_GLB_HF_I_ETH_TYPE,
-       BNXT_ULP_GLB_HF_O_IPV4_VER,
-       BNXT_ULP_GLB_HF_I_IPV4_VER,
-       BNXT_ULP_GLB_HF_O_IPV4_TOS,
-       BNXT_ULP_GLB_HF_I_IPV4_TOS,
-       BNXT_ULP_GLB_HF_O_IPV4_LEN,
-       BNXT_ULP_GLB_HF_I_IPV4_LEN,
-       BNXT_ULP_GLB_HF_O_IPV4_FRAG_ID,
-       BNXT_ULP_GLB_HF_I_IPV4_FRAG_ID,
-       BNXT_ULP_GLB_HF_O_IPV4_FRAG_OFF,
-       BNXT_ULP_GLB_HF_I_IPV4_FRAG_OFF,
-       BNXT_ULP_GLB_HF_O_IPV4_TTL,
-       BNXT_ULP_GLB_HF_I_IPV4_TTL,
-       BNXT_ULP_GLB_HF_O_IPV4_PROTO_ID,
-       BNXT_ULP_GLB_HF_I_IPV4_PROTO_ID,
-       BNXT_ULP_GLB_HF_O_IPV4_CSUM,
-       BNXT_ULP_GLB_HF_I_IPV4_CSUM,
-       BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR,
-       BNXT_ULP_GLB_HF_I_IPV4_SRC_ADDR,
-       BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR,
-       BNXT_ULP_GLB_HF_I_IPV4_DST_ADDR,
-       BNXT_ULP_GLB_HF_O_IPV6_VER,
-       BNXT_ULP_GLB_HF_I_IPV6_VER,
-       BNXT_ULP_GLB_HF_O_IPV6_TC,
-       BNXT_ULP_GLB_HF_I_IPV6_TC,
-       BNXT_ULP_GLB_HF_O_IPV6_FLOW_LABEL,
-       BNXT_ULP_GLB_HF_I_IPV6_FLOW_LABEL,
-       BNXT_ULP_GLB_HF_O_IPV6_PAYLOAD_LEN,
-       BNXT_ULP_GLB_HF_I_IPV6_PAYLOAD_LEN,
-       BNXT_ULP_GLB_HF_O_IPV6_PROTO_ID,
-       BNXT_ULP_GLB_HF_I_IPV6_PROTO_ID,
-       BNXT_ULP_GLB_HF_O_IPV6_TTL,
-       BNXT_ULP_GLB_HF_I_IPV6_TTL,
-       BNXT_ULP_GLB_HF_O_IPV6_SRC_ADDR,
-       BNXT_ULP_GLB_HF_I_IPV6_SRC_ADDR,
-       BNXT_ULP_GLB_HF_O_IPV6_DST_ADDR,
-       BNXT_ULP_GLB_HF_I_IPV6_DST_ADDR,
-       BNXT_ULP_GLB_HF_O_L3_PROTO_ID,
-       BNXT_ULP_GLB_HF_I_L3_PROTO_ID,
-       BNXT_ULP_GLB_HF_O_L3_SRC_ADDR,
-       BNXT_ULP_GLB_HF_I_L3_SRC_ADDR,
-       BNXT_ULP_GLB_HF_O_L3_DST_ADDR,
-       BNXT_ULP_GLB_HF_I_L3_DST_ADDR,
-       BNXT_ULP_GLB_HF_O_L4_SRC_PORT,
-       BNXT_ULP_GLB_HF_I_L4_SRC_PORT,
-       BNXT_ULP_GLB_HF_O_L4_DST_PORT,
-       BNXT_ULP_GLB_HF_I_L4_DST_PORT,
-       BNXT_ULP_GLB_HF_O_TCP_SRC_PORT,
-       BNXT_ULP_GLB_HF_I_TCP_SRC_PORT,
-       BNXT_ULP_GLB_HF_O_TCP_DST_PORT,
-       BNXT_ULP_GLB_HF_I_TCP_DST_PORT,
-       BNXT_ULP_GLB_HF_O_TCP_SENT_SEQ,
-       BNXT_ULP_GLB_HF_I_TCP_SENT_SEQ,
-       BNXT_ULP_GLB_HF_O_TCP_RECV_ACK,
-       BNXT_ULP_GLB_HF_I_TCP_RECV_ACK,
-       BNXT_ULP_GLB_HF_O_TCP_DATA_OFF,
-       BNXT_ULP_GLB_HF_I_TCP_DATA_OFF,
-       BNXT_ULP_GLB_HF_O_TCP_TCP_FLAGS,
-       BNXT_ULP_GLB_HF_I_TCP_TCP_FLAGS,
-       BNXT_ULP_GLB_HF_O_TCP_RX_WIN,
-       BNXT_ULP_GLB_HF_I_TCP_RX_WIN,
-       BNXT_ULP_GLB_HF_O_TCP_CSUM,
-       BNXT_ULP_GLB_HF_I_TCP_CSUM,
-       BNXT_ULP_GLB_HF_O_TCP_URP,
-       BNXT_ULP_GLB_HF_I_TCP_URP,
-       BNXT_ULP_GLB_HF_O_UDP_SRC_PORT,
-       BNXT_ULP_GLB_HF_I_UDP_SRC_PORT,
-       BNXT_ULP_GLB_HF_O_UDP_DST_PORT,
-       BNXT_ULP_GLB_HF_I_UDP_DST_PORT,
-       BNXT_ULP_GLB_HF_O_UDP_LENGTH,
-       BNXT_ULP_GLB_HF_I_UDP_LENGTH,
-       BNXT_ULP_GLB_HF_O_UDP_CSUM,
-       BNXT_ULP_GLB_HF_I_UDP_CSUM,
-       BNXT_ULP_GLB_HF_OO_VLAN_CFI_PRI,
-       BNXT_ULP_GLB_HF_OI_VLAN_CFI_PRI,
-       BNXT_ULP_GLB_HF_IO_VLAN_CFI_PRI,
-       BNXT_ULP_GLB_HF_II_VLAN_CFI_PRI,
-       BNXT_ULP_GLB_HF_OO_VLAN_VID,
-       BNXT_ULP_GLB_HF_OI_VLAN_VID,
-       BNXT_ULP_GLB_HF_IO_VLAN_VID,
-       BNXT_ULP_GLB_HF_II_VLAN_VID,
-       BNXT_ULP_GLB_HF_OO_VLAN_TYPE,
-       BNXT_ULP_GLB_HF_OI_VLAN_TYPE,
-       BNXT_ULP_GLB_HF_IO_VLAN_TYPE,
-       BNXT_ULP_GLB_HF_II_VLAN_TYPE,
-       BNXT_ULP_GLB_HF_T_VXLAN_FLAGS,
-       BNXT_ULP_GLB_HF_T_VXLAN_RSVD0,
-       BNXT_ULP_GLB_HF_T_VXLAN_VNI,
-       BNXT_ULP_GLB_HF_T_VXLAN_RSVD1
+       BNXT_ULP_GLB_HF_ID_WM,
+       BNXT_ULP_GLB_HF_ID_SVIF_INDEX,
+       BNXT_ULP_GLB_HF_ID_O_ETH_DMAC,
+       BNXT_ULP_GLB_HF_ID_I_ETH_DMAC,
+       BNXT_ULP_GLB_HF_ID_O_ETH_SMAC,
+       BNXT_ULP_GLB_HF_ID_I_ETH_SMAC,
+       BNXT_ULP_GLB_HF_ID_O_ETH_TYPE,
+       BNXT_ULP_GLB_HF_ID_I_ETH_TYPE,
+       BNXT_ULP_GLB_HF_ID_O_IPV4_VER,
+       BNXT_ULP_GLB_HF_ID_I_IPV4_VER,
+       BNXT_ULP_GLB_HF_ID_O_IPV4_TOS,
+       BNXT_ULP_GLB_HF_ID_I_IPV4_TOS,
+       BNXT_ULP_GLB_HF_ID_O_IPV4_LEN,
+       BNXT_ULP_GLB_HF_ID_I_IPV4_LEN,
+       BNXT_ULP_GLB_HF_ID_O_IPV4_FRAG_ID,
+       BNXT_ULP_GLB_HF_ID_I_IPV4_FRAG_ID,
+       BNXT_ULP_GLB_HF_ID_O_IPV4_FRAG_OFF,
+       BNXT_ULP_GLB_HF_ID_I_IPV4_FRAG_OFF,
+       BNXT_ULP_GLB_HF_ID_O_IPV4_TTL,
+       BNXT_ULP_GLB_HF_ID_I_IPV4_TTL,
+       BNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID,
+       BNXT_ULP_GLB_HF_ID_I_IPV4_PROTO_ID,
+       BNXT_ULP_GLB_HF_ID_O_IPV4_CSUM,
+       BNXT_ULP_GLB_HF_ID_I_IPV4_CSUM,
+       BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR,
+       BNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR,
+       BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR,
+       BNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR,
+       BNXT_ULP_GLB_HF_ID_O_IPV6_VER,
+       BNXT_ULP_GLB_HF_ID_I_IPV6_VER,
+       BNXT_ULP_GLB_HF_ID_O_IPV6_TC,
+       BNXT_ULP_GLB_HF_ID_I_IPV6_TC,
+       BNXT_ULP_GLB_HF_ID_O_IPV6_FLOW_LABEL,
+       BNXT_ULP_GLB_HF_ID_I_IPV6_FLOW_LABEL,
+       BNXT_ULP_GLB_HF_ID_O_IPV6_PAYLOAD_LEN,
+       BNXT_ULP_GLB_HF_ID_I_IPV6_PAYLOAD_LEN,
+       BNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID,
+       BNXT_ULP_GLB_HF_ID_I_IPV6_PROTO_ID,
+       BNXT_ULP_GLB_HF_ID_O_IPV6_TTL,
+       BNXT_ULP_GLB_HF_ID_I_IPV6_TTL,
+       BNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR,
+       BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR,
+       BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR,
+       BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR,
+       BNXT_ULP_GLB_HF_ID_O_L3_PROTO_ID,
+       BNXT_ULP_GLB_HF_ID_I_L3_PROTO_ID,
+       BNXT_ULP_GLB_HF_ID_O_L3_SRC_ADDR,
+       BNXT_ULP_GLB_HF_ID_I_L3_SRC_ADDR,
+       BNXT_ULP_GLB_HF_ID_O_L3_DST_ADDR,
+       BNXT_ULP_GLB_HF_ID_I_L3_DST_ADDR,
+       BNXT_ULP_GLB_HF_ID_O_L4_SRC_PORT,
+       BNXT_ULP_GLB_HF_ID_I_L4_SRC_PORT,
+       BNXT_ULP_GLB_HF_ID_O_L4_DST_PORT,
+       BNXT_ULP_GLB_HF_ID_I_L4_DST_PORT,
+       BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT,
+       BNXT_ULP_GLB_HF_ID_I_TCP_SRC_PORT,
+       BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT,
+       BNXT_ULP_GLB_HF_ID_I_TCP_DST_PORT,
+       BNXT_ULP_GLB_HF_ID_O_TCP_SENT_SEQ,
+       BNXT_ULP_GLB_HF_ID_I_TCP_SENT_SEQ,
+       BNXT_ULP_GLB_HF_ID_O_TCP_RECV_ACK,
+       BNXT_ULP_GLB_HF_ID_I_TCP_RECV_ACK,
+       BNXT_ULP_GLB_HF_ID_O_TCP_DATA_OFF,
+       BNXT_ULP_GLB_HF_ID_I_TCP_DATA_OFF,
+       BNXT_ULP_GLB_HF_ID_O_TCP_TCP_FLAGS,
+       BNXT_ULP_GLB_HF_ID_I_TCP_TCP_FLAGS,
+       BNXT_ULP_GLB_HF_ID_O_TCP_RX_WIN,
+       BNXT_ULP_GLB_HF_ID_I_TCP_RX_WIN,
+       BNXT_ULP_GLB_HF_ID_O_TCP_CSUM,
+       BNXT_ULP_GLB_HF_ID_I_TCP_CSUM,
+       BNXT_ULP_GLB_HF_ID_O_TCP_URP,
+       BNXT_ULP_GLB_HF_ID_I_TCP_URP,
+       BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT,
+       BNXT_ULP_GLB_HF_ID_I_UDP_SRC_PORT,
+       BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT,
+       BNXT_ULP_GLB_HF_ID_I_UDP_DST_PORT,
+       BNXT_ULP_GLB_HF_ID_O_UDP_LENGTH,
+       BNXT_ULP_GLB_HF_ID_I_UDP_LENGTH,
+       BNXT_ULP_GLB_HF_ID_O_UDP_CSUM,
+       BNXT_ULP_GLB_HF_ID_I_UDP_CSUM,
+       BNXT_ULP_GLB_HF_ID_OO_VLAN_CFI_PRI,
+       BNXT_ULP_GLB_HF_ID_OI_VLAN_CFI_PRI,
+       BNXT_ULP_GLB_HF_ID_IO_VLAN_CFI_PRI,
+       BNXT_ULP_GLB_HF_ID_II_VLAN_CFI_PRI,
+       BNXT_ULP_GLB_HF_ID_OO_VLAN_VID,
+       BNXT_ULP_GLB_HF_ID_OI_VLAN_VID,
+       BNXT_ULP_GLB_HF_ID_IO_VLAN_VID,
+       BNXT_ULP_GLB_HF_ID_II_VLAN_VID,
+       BNXT_ULP_GLB_HF_ID_OO_VLAN_TYPE,
+       BNXT_ULP_GLB_HF_ID_OI_VLAN_TYPE,
+       BNXT_ULP_GLB_HF_ID_IO_VLAN_TYPE,
+       BNXT_ULP_GLB_HF_ID_II_VLAN_TYPE,
+       BNXT_ULP_GLB_HF_ID_T_VXLAN_FLAGS,
+       BNXT_ULP_GLB_HF_ID_T_VXLAN_RSVD0,
+       BNXT_ULP_GLB_HF_ID_T_VXLAN_VNI,
+       BNXT_ULP_GLB_HF_ID_T_VXLAN_RSVD1
 };
 
 enum bnxt_ulp_hf1_0_bitmask {
@@ -113,25 +113,23 @@ enum bnxt_ulp_hf1_0_bitmask {
        BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC         = 0x2000000000000000,
        BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC         = 0x1000000000000000,
        BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE         = 0x0800000000000000,
-       BNXT_ULP_HF1_0_BITMASK_O_IPV4_VER         = 0x0400000000000000,
-       BNXT_ULP_HF1_0_BITMASK_O_IPV4_TOS         = 0x0200000000000000,
-       BNXT_ULP_HF1_0_BITMASK_O_IPV4_LEN         = 0x0100000000000000,
-       BNXT_ULP_HF1_0_BITMASK_O_IPV4_FRAG_ID     = 0x0080000000000000,
-       BNXT_ULP_HF1_0_BITMASK_O_IPV4_FRAG_OFF    = 0x0040000000000000,
-       BNXT_ULP_HF1_0_BITMASK_O_IPV4_TTL         = 0x0020000000000000,
-       BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID    = 0x0010000000000000,
-       BNXT_ULP_HF1_0_BITMASK_O_IPV4_CSUM        = 0x0008000000000000,
-       BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR    = 0x0004000000000000,
-       BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR    = 0x0002000000000000,
-       BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT     = 0x0001000000000000,
-       BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT     = 0x0000800000000000,
-       BNXT_ULP_HF1_0_BITMASK_O_TCP_SENT_SEQ     = 0x0000400000000000,
-       BNXT_ULP_HF1_0_BITMASK_O_TCP_RECV_ACK     = 0x0000200000000000,
-       BNXT_ULP_HF1_0_BITMASK_O_TCP_DATA_OFF     = 0x0000100000000000,
-       BNXT_ULP_HF1_0_BITMASK_O_TCP_TCP_FLAGS    = 0x0000080000000000,
-       BNXT_ULP_HF1_0_BITMASK_O_TCP_RX_WIN       = 0x0000040000000000,
-       BNXT_ULP_HF1_0_BITMASK_O_TCP_CSUM         = 0x0000020000000000,
-       BNXT_ULP_HF1_0_BITMASK_O_TCP_URP          = 0x0000010000000000
+       BNXT_ULP_HF1_0_BITMASK_O_IPV6_VER         = 0x0400000000000000,
+       BNXT_ULP_HF1_0_BITMASK_O_IPV6_TC          = 0x0200000000000000,
+       BNXT_ULP_HF1_0_BITMASK_O_IPV6_FLOW_LABEL  = 0x0100000000000000,
+       BNXT_ULP_HF1_0_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
+       BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID    = 0x0040000000000000,
+       BNXT_ULP_HF1_0_BITMASK_O_IPV6_TTL         = 0x0020000000000000,
+       BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR    = 0x0010000000000000,
+       BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR    = 0x0008000000000000,
+       BNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT     = 0x0004000000000000,
+       BNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT     = 0x0002000000000000,
+       BNXT_ULP_HF1_0_BITMASK_O_TCP_SENT_SEQ     = 0x0001000000000000,
+       BNXT_ULP_HF1_0_BITMASK_O_TCP_RECV_ACK     = 0x0000800000000000,
+       BNXT_ULP_HF1_0_BITMASK_O_TCP_DATA_OFF     = 0x0000400000000000,
+       BNXT_ULP_HF1_0_BITMASK_O_TCP_TCP_FLAGS    = 0x0000200000000000,
+       BNXT_ULP_HF1_0_BITMASK_O_TCP_RX_WIN       = 0x0000100000000000,
+       BNXT_ULP_HF1_0_BITMASK_O_TCP_CSUM         = 0x0000080000000000,
+       BNXT_ULP_HF1_0_BITMASK_O_TCP_URP          = 0x0000040000000000
 };
 
 enum bnxt_ulp_hf1_1_bitmask {
@@ -143,81 +141,169 @@ enum bnxt_ulp_hf1_1_bitmask {
        BNXT_ULP_HF1_1_BITMASK_OO_VLAN_CFI_PRI    = 0x0400000000000000,
        BNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID        = 0x0200000000000000,
        BNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE       = 0x0100000000000000,
-       BNXT_ULP_HF1_1_BITMASK_O_IPV4_VER         = 0x0080000000000000,
-       BNXT_ULP_HF1_1_BITMASK_O_IPV4_TOS         = 0x0040000000000000,
-       BNXT_ULP_HF1_1_BITMASK_O_IPV4_LEN         = 0x0020000000000000,
-       BNXT_ULP_HF1_1_BITMASK_O_IPV4_FRAG_ID     = 0x0010000000000000,
-       BNXT_ULP_HF1_1_BITMASK_O_IPV4_FRAG_OFF    = 0x0008000000000000,
-       BNXT_ULP_HF1_1_BITMASK_O_IPV4_TTL         = 0x0004000000000000,
-       BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID    = 0x0002000000000000,
-       BNXT_ULP_HF1_1_BITMASK_O_IPV4_CSUM        = 0x0001000000000000,
-       BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR    = 0x0000800000000000,
-       BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR    = 0x0000400000000000,
-       BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT     = 0x0000200000000000,
-       BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT     = 0x0000100000000000,
-       BNXT_ULP_HF1_1_BITMASK_O_TCP_SENT_SEQ     = 0x0000080000000000,
-       BNXT_ULP_HF1_1_BITMASK_O_TCP_RECV_ACK     = 0x0000040000000000,
-       BNXT_ULP_HF1_1_BITMASK_O_TCP_DATA_OFF     = 0x0000020000000000,
-       BNXT_ULP_HF1_1_BITMASK_O_TCP_TCP_FLAGS    = 0x0000010000000000,
-       BNXT_ULP_HF1_1_BITMASK_O_TCP_RX_WIN       = 0x0000008000000000,
-       BNXT_ULP_HF1_1_BITMASK_O_TCP_CSUM         = 0x0000004000000000,
-       BNXT_ULP_HF1_1_BITMASK_O_TCP_URP          = 0x0000002000000000
+       BNXT_ULP_HF1_1_BITMASK_O_IPV6_VER         = 0x0080000000000000,
+       BNXT_ULP_HF1_1_BITMASK_O_IPV6_TC          = 0x0040000000000000,
+       BNXT_ULP_HF1_1_BITMASK_O_IPV6_FLOW_LABEL  = 0x0020000000000000,
+       BNXT_ULP_HF1_1_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
+       BNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID    = 0x0008000000000000,
+       BNXT_ULP_HF1_1_BITMASK_O_IPV6_TTL         = 0x0004000000000000,
+       BNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR    = 0x0002000000000000,
+       BNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR    = 0x0001000000000000,
+       BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT     = 0x0000800000000000,
+       BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT     = 0x0000400000000000,
+       BNXT_ULP_HF1_1_BITMASK_O_TCP_SENT_SEQ     = 0x0000200000000000,
+       BNXT_ULP_HF1_1_BITMASK_O_TCP_RECV_ACK     = 0x0000100000000000,
+       BNXT_ULP_HF1_1_BITMASK_O_TCP_DATA_OFF     = 0x0000080000000000,
+       BNXT_ULP_HF1_1_BITMASK_O_TCP_TCP_FLAGS    = 0x0000040000000000,
+       BNXT_ULP_HF1_1_BITMASK_O_TCP_RX_WIN       = 0x0000020000000000,
+       BNXT_ULP_HF1_1_BITMASK_O_TCP_CSUM         = 0x0000010000000000,
+       BNXT_ULP_HF1_1_BITMASK_O_TCP_URP          = 0x0000008000000000
 };
 
-enum bnxt_ulp_hf2_0_bitmask {
-       BNXT_ULP_HF2_0_BITMASK_WM                 = 0x8000000000000000,
-       BNXT_ULP_HF2_0_BITMASK_SVIF_INDEX         = 0x4000000000000000,
-       BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC         = 0x2000000000000000,
-       BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC         = 0x1000000000000000,
-       BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE         = 0x0800000000000000,
-       BNXT_ULP_HF2_0_BITMASK_O_IPV4_VER         = 0x0400000000000000,
-       BNXT_ULP_HF2_0_BITMASK_O_IPV4_TOS         = 0x0200000000000000,
-       BNXT_ULP_HF2_0_BITMASK_O_IPV4_LEN         = 0x0100000000000000,
-       BNXT_ULP_HF2_0_BITMASK_O_IPV4_FRAG_ID     = 0x0080000000000000,
-       BNXT_ULP_HF2_0_BITMASK_O_IPV4_FRAG_OFF    = 0x0040000000000000,
-       BNXT_ULP_HF2_0_BITMASK_O_IPV4_TTL         = 0x0020000000000000,
-       BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID    = 0x0010000000000000,
-       BNXT_ULP_HF2_0_BITMASK_O_IPV4_CSUM        = 0x0008000000000000,
-       BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR    = 0x0004000000000000,
-       BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR    = 0x0002000000000000,
-       BNXT_ULP_HF2_0_BITMASK_O_TCP_SRC_PORT     = 0x0001000000000000,
-       BNXT_ULP_HF2_0_BITMASK_O_TCP_DST_PORT     = 0x0000800000000000,
-       BNXT_ULP_HF2_0_BITMASK_O_TCP_SENT_SEQ     = 0x0000400000000000,
-       BNXT_ULP_HF2_0_BITMASK_O_TCP_RECV_ACK     = 0x0000200000000000,
-       BNXT_ULP_HF2_0_BITMASK_O_TCP_DATA_OFF     = 0x0000100000000000,
-       BNXT_ULP_HF2_0_BITMASK_O_TCP_TCP_FLAGS    = 0x0000080000000000,
-       BNXT_ULP_HF2_0_BITMASK_O_TCP_RX_WIN       = 0x0000040000000000,
-       BNXT_ULP_HF2_0_BITMASK_O_TCP_CSUM         = 0x0000020000000000,
-       BNXT_ULP_HF2_0_BITMASK_O_TCP_URP          = 0x0000010000000000
+enum bnxt_ulp_hf1_2_bitmask {
+       BNXT_ULP_HF1_2_BITMASK_WM                 = 0x8000000000000000,
+       BNXT_ULP_HF1_2_BITMASK_SVIF_INDEX         = 0x4000000000000000,
+       BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC         = 0x2000000000000000,
+       BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC         = 0x1000000000000000,
+       BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE         = 0x0800000000000000,
+       BNXT_ULP_HF1_2_BITMASK_O_IPV4_VER         = 0x0400000000000000,
+       BNXT_ULP_HF1_2_BITMASK_O_IPV4_TOS         = 0x0200000000000000,
+       BNXT_ULP_HF1_2_BITMASK_O_IPV4_LEN         = 0x0100000000000000,
+       BNXT_ULP_HF1_2_BITMASK_O_IPV4_FRAG_ID     = 0x0080000000000000,
+       BNXT_ULP_HF1_2_BITMASK_O_IPV4_FRAG_OFF    = 0x0040000000000000,
+       BNXT_ULP_HF1_2_BITMASK_O_IPV4_TTL         = 0x0020000000000000,
+       BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID    = 0x0010000000000000,
+       BNXT_ULP_HF1_2_BITMASK_O_IPV4_CSUM        = 0x0008000000000000,
+       BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR    = 0x0004000000000000,
+       BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR    = 0x0002000000000000,
+       BNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT     = 0x0001000000000000,
+       BNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT     = 0x0000800000000000,
+       BNXT_ULP_HF1_2_BITMASK_O_TCP_SENT_SEQ     = 0x0000400000000000,
+       BNXT_ULP_HF1_2_BITMASK_O_TCP_RECV_ACK     = 0x0000200000000000,
+       BNXT_ULP_HF1_2_BITMASK_O_TCP_DATA_OFF     = 0x0000100000000000,
+       BNXT_ULP_HF1_2_BITMASK_O_TCP_TCP_FLAGS    = 0x0000080000000000,
+       BNXT_ULP_HF1_2_BITMASK_O_TCP_RX_WIN       = 0x0000040000000000,
+       BNXT_ULP_HF1_2_BITMASK_O_TCP_CSUM         = 0x0000020000000000,
+       BNXT_ULP_HF1_2_BITMASK_O_TCP_URP          = 0x0000010000000000
 };
 
-enum bnxt_ulp_hf2_1_bitmask {
-       BNXT_ULP_HF2_1_BITMASK_WM                 = 0x8000000000000000,
-       BNXT_ULP_HF2_1_BITMASK_SVIF_INDEX         = 0x4000000000000000,
-       BNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC         = 0x2000000000000000,
-       BNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC         = 0x1000000000000000,
-       BNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE         = 0x0800000000000000,
-       BNXT_ULP_HF2_1_BITMASK_OO_VLAN_CFI_PRI    = 0x0400000000000000,
-       BNXT_ULP_HF2_1_BITMASK_OO_VLAN_VID        = 0x0200000000000000,
-       BNXT_ULP_HF2_1_BITMASK_OO_VLAN_TYPE       = 0x0100000000000000,
-       BNXT_ULP_HF2_1_BITMASK_O_IPV4_VER         = 0x0080000000000000,
-       BNXT_ULP_HF2_1_BITMASK_O_IPV4_TOS         = 0x0040000000000000,
-       BNXT_ULP_HF2_1_BITMASK_O_IPV4_LEN         = 0x0020000000000000,
-       BNXT_ULP_HF2_1_BITMASK_O_IPV4_FRAG_ID     = 0x0010000000000000,
-       BNXT_ULP_HF2_1_BITMASK_O_IPV4_FRAG_OFF    = 0x0008000000000000,
-       BNXT_ULP_HF2_1_BITMASK_O_IPV4_TTL         = 0x0004000000000000,
-       BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID    = 0x0002000000000000,
-       BNXT_ULP_HF2_1_BITMASK_O_IPV4_CSUM        = 0x0001000000000000,
-       BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR    = 0x0000800000000000,
-       BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR    = 0x0000400000000000,
-       BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT     = 0x0000200000000000,
-       BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT     = 0x0000100000000000,
-       BNXT_ULP_HF2_1_BITMASK_O_TCP_SENT_SEQ     = 0x0000080000000000,
-       BNXT_ULP_HF2_1_BITMASK_O_TCP_RECV_ACK     = 0x0000040000000000,
-       BNXT_ULP_HF2_1_BITMASK_O_TCP_DATA_OFF     = 0x0000020000000000,
-       BNXT_ULP_HF2_1_BITMASK_O_TCP_TCP_FLAGS    = 0x0000010000000000,
-       BNXT_ULP_HF2_1_BITMASK_O_TCP_RX_WIN       = 0x0000008000000000,
-       BNXT_ULP_HF2_1_BITMASK_O_TCP_CSUM         = 0x0000004000000000,
-       BNXT_ULP_HF2_1_BITMASK_O_TCP_URP          = 0x0000002000000000
+enum bnxt_ulp_hf1_3_bitmask {
+       BNXT_ULP_HF1_3_BITMASK_WM                 = 0x8000000000000000,
+       BNXT_ULP_HF1_3_BITMASK_SVIF_INDEX         = 0x4000000000000000,
+       BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC         = 0x2000000000000000,
+       BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC         = 0x1000000000000000,
+       BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE         = 0x0800000000000000,
+       BNXT_ULP_HF1_3_BITMASK_O_IPV6_VER         = 0x0400000000000000,
+       BNXT_ULP_HF1_3_BITMASK_O_IPV6_TC          = 0x0200000000000000,
+       BNXT_ULP_HF1_3_BITMASK_O_IPV6_FLOW_LABEL  = 0x0100000000000000,
+       BNXT_ULP_HF1_3_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
+       BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID    = 0x0040000000000000,
+       BNXT_ULP_HF1_3_BITMASK_O_IPV6_TTL         = 0x0020000000000000,
+       BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR    = 0x0010000000000000,
+       BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR    = 0x0008000000000000,
+       BNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT     = 0x0004000000000000,
+       BNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT     = 0x0002000000000000,
+       BNXT_ULP_HF1_3_BITMASK_O_UDP_LENGTH       = 0x0001000000000000,
+       BNXT_ULP_HF1_3_BITMASK_O_UDP_CSUM         = 0x0000800000000000
+};
+
+enum bnxt_ulp_hf1_4_bitmask {
+       BNXT_ULP_HF1_4_BITMASK_WM                 = 0x8000000000000000,
+       BNXT_ULP_HF1_4_BITMASK_SVIF_INDEX         = 0x4000000000000000,
+       BNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC         = 0x2000000000000000,
+       BNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC         = 0x1000000000000000,
+       BNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE         = 0x0800000000000000,
+       BNXT_ULP_HF1_4_BITMASK_OO_VLAN_CFI_PRI    = 0x0400000000000000,
+       BNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID        = 0x0200000000000000,
+       BNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE       = 0x0100000000000000,
+       BNXT_ULP_HF1_4_BITMASK_O_IPV4_VER         = 0x0080000000000000,
+       BNXT_ULP_HF1_4_BITMASK_O_IPV4_TOS         = 0x0040000000000000,
+       BNXT_ULP_HF1_4_BITMASK_O_IPV4_LEN         = 0x0020000000000000,
+       BNXT_ULP_HF1_4_BITMASK_O_IPV4_FRAG_ID     = 0x0010000000000000,
+       BNXT_ULP_HF1_4_BITMASK_O_IPV4_FRAG_OFF    = 0x0008000000000000,
+       BNXT_ULP_HF1_4_BITMASK_O_IPV4_TTL         = 0x0004000000000000,
+       BNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID    = 0x0002000000000000,
+       BNXT_ULP_HF1_4_BITMASK_O_IPV4_CSUM        = 0x0001000000000000,
+       BNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR    = 0x0000800000000000,
+       BNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR    = 0x0000400000000000,
+       BNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT     = 0x0000200000000000,
+       BNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT     = 0x0000100000000000,
+       BNXT_ULP_HF1_4_BITMASK_O_TCP_SENT_SEQ     = 0x0000080000000000,
+       BNXT_ULP_HF1_4_BITMASK_O_TCP_RECV_ACK     = 0x0000040000000000,
+       BNXT_ULP_HF1_4_BITMASK_O_TCP_DATA_OFF     = 0x0000020000000000,
+       BNXT_ULP_HF1_4_BITMASK_O_TCP_TCP_FLAGS    = 0x0000010000000000,
+       BNXT_ULP_HF1_4_BITMASK_O_TCP_RX_WIN       = 0x0000008000000000,
+       BNXT_ULP_HF1_4_BITMASK_O_TCP_CSUM         = 0x0000004000000000,
+       BNXT_ULP_HF1_4_BITMASK_O_TCP_URP          = 0x0000002000000000
+};
+
+enum bnxt_ulp_hf1_5_bitmask {
+       BNXT_ULP_HF1_5_BITMASK_WM                 = 0x8000000000000000,
+       BNXT_ULP_HF1_5_BITMASK_SVIF_INDEX         = 0x4000000000000000,
+       BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC         = 0x2000000000000000,
+       BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC         = 0x1000000000000000,
+       BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE         = 0x0800000000000000,
+       BNXT_ULP_HF1_5_BITMASK_OO_VLAN_CFI_PRI    = 0x0400000000000000,
+       BNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID        = 0x0200000000000000,
+       BNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE       = 0x0100000000000000,
+       BNXT_ULP_HF1_5_BITMASK_O_IPV6_VER         = 0x0080000000000000,
+       BNXT_ULP_HF1_5_BITMASK_O_IPV6_TC          = 0x0040000000000000,
+       BNXT_ULP_HF1_5_BITMASK_O_IPV6_FLOW_LABEL  = 0x0020000000000000,
+       BNXT_ULP_HF1_5_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
+       BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID    = 0x0008000000000000,
+       BNXT_ULP_HF1_5_BITMASK_O_IPV6_TTL         = 0x0004000000000000,
+       BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR    = 0x0002000000000000,
+       BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR    = 0x0001000000000000,
+       BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT     = 0x0000800000000000,
+       BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT     = 0x0000400000000000,
+       BNXT_ULP_HF1_5_BITMASK_O_UDP_LENGTH       = 0x0000200000000000,
+       BNXT_ULP_HF1_5_BITMASK_O_UDP_CSUM         = 0x0000100000000000
+};
+
+enum bnxt_ulp_hf1_6_bitmask {
+       BNXT_ULP_HF1_6_BITMASK_WM                 = 0x8000000000000000,
+       BNXT_ULP_HF1_6_BITMASK_SVIF_INDEX         = 0x4000000000000000,
+       BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC         = 0x2000000000000000,
+       BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC         = 0x1000000000000000,
+       BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE         = 0x0800000000000000,
+       BNXT_ULP_HF1_6_BITMASK_O_IPV4_VER         = 0x0400000000000000,
+       BNXT_ULP_HF1_6_BITMASK_O_IPV4_TOS         = 0x0200000000000000,
+       BNXT_ULP_HF1_6_BITMASK_O_IPV4_LEN         = 0x0100000000000000,
+       BNXT_ULP_HF1_6_BITMASK_O_IPV4_FRAG_ID     = 0x0080000000000000,
+       BNXT_ULP_HF1_6_BITMASK_O_IPV4_FRAG_OFF    = 0x0040000000000000,
+       BNXT_ULP_HF1_6_BITMASK_O_IPV4_TTL         = 0x0020000000000000,
+       BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID    = 0x0010000000000000,
+       BNXT_ULP_HF1_6_BITMASK_O_IPV4_CSUM        = 0x0008000000000000,
+       BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR    = 0x0004000000000000,
+       BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR    = 0x0002000000000000,
+       BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT     = 0x0001000000000000,
+       BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT     = 0x0000800000000000,
+       BNXT_ULP_HF1_6_BITMASK_O_UDP_LENGTH       = 0x0000400000000000,
+       BNXT_ULP_HF1_6_BITMASK_O_UDP_CSUM         = 0x0000200000000000
+};
+
+enum bnxt_ulp_hf1_7_bitmask {
+       BNXT_ULP_HF1_7_BITMASK_WM                 = 0x8000000000000000,
+       BNXT_ULP_HF1_7_BITMASK_SVIF_INDEX         = 0x4000000000000000,
+       BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC         = 0x2000000000000000,
+       BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC         = 0x1000000000000000,
+       BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE         = 0x0800000000000000,
+       BNXT_ULP_HF1_7_BITMASK_OO_VLAN_CFI_PRI    = 0x0400000000000000,
+       BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID        = 0x0200000000000000,
+       BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE       = 0x0100000000000000,
+       BNXT_ULP_HF1_7_BITMASK_O_IPV4_VER         = 0x0080000000000000,
+       BNXT_ULP_HF1_7_BITMASK_O_IPV4_TOS         = 0x0040000000000000,
+       BNXT_ULP_HF1_7_BITMASK_O_IPV4_LEN         = 0x0020000000000000,
+       BNXT_ULP_HF1_7_BITMASK_O_IPV4_FRAG_ID     = 0x0010000000000000,
+       BNXT_ULP_HF1_7_BITMASK_O_IPV4_FRAG_OFF    = 0x0008000000000000,
+       BNXT_ULP_HF1_7_BITMASK_O_IPV4_TTL         = 0x0004000000000000,
+       BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID    = 0x0002000000000000,
+       BNXT_ULP_HF1_7_BITMASK_O_IPV4_CSUM        = 0x0001000000000000,
+       BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR    = 0x0000800000000000,
+       BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR    = 0x0000400000000000,
+       BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT     = 0x0000200000000000,
+       BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT     = 0x0000100000000000,
+       BNXT_ULP_HF1_7_BITMASK_O_UDP_LENGTH       = 0x0000080000000000,
+       BNXT_ULP_HF1_7_BITMASK_O_UDP_CSUM         = 0x0000040000000000
 };
 #endif

diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c
index 9f90af2..c1b3c7b 100644 (file)
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c
@@ -3,7 +3,7 @@
  * All rights reserved.
  */
 
-/* date: Mon Nov 23 17:33:02 2020 */
+/* date: Tue Dec  1 17:07:12 2020 */
 
 #include "ulp_template_db_enum.h"
 #include "ulp_template_db_field.h"
@@ -32,6 +32,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
                BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
        .direction = TF_DIR_RX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
                .cond_start_idx = 0,
                .cond_nums = 1 },
@@ -53,6 +54,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
        .direction = TF_DIR_RX,
        .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
                .cond_start_idx = 1,
                .cond_nums = 1 },
@@ -74,6 +76,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
        .direction = TF_DIR_RX,
        .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 2,
                .cond_nums = 0 },
@@ -95,6 +98,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
        .direction = TF_DIR_RX,
        .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT,
        .execute_info = {
+               .cond_goto = 0,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 2,
                .cond_nums = 0 },
@@ -112,12 +116,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 
 struct bnxt_ulp_mapper_cond_info ulp_stingray_act_cond_list[] = {
        {
-       .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET,
-       .cond_operand = BNXT_ULP_ACTION_BIT_COUNT
+       .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+       .cond_operand = BNXT_ULP_ACT_BIT_COUNT
        },
        {
-       .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET,
-       .cond_operand = BNXT_ULP_ACTION_BIT_PUSH_VLAN
+       .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+       .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN
        }
 };
 
@@ -126,559 +130,580 @@ struct bnxt_ulp_mapper_field_info ulp_stingray_act_result_field_list[] = {
        {
        .description = "count",
        .field_bit_size = 64,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        /* act_tid: 1, stingray, table: int_vtag_encap_record.0 */
        {
        .description = "ecv_tun_type",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "ecv_l4_type",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "ecv_l3_type",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "ecv_l2_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "ecv_vtag_type",
        .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {
-               BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               ULP_SR_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
        },
        {
        .description = "ecv_custom_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "ecv_valid",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               1}
        },
        {
        .description = "vtag_tpid",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+       .field_opr1 = {
                (BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff,
-               BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff}
        },
        {
        .description = "vtag_vid",
        .field_bit_size = 12,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+       .field_opr1 = {
                (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
-               BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
        },
        {
        .description = "vtag_de",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "vtag_pcp",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+       .field_opr1 = {
                (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
-               BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
        },
        {
        .description = "spare",
        .field_bit_size = 80,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        /* act_tid: 1, stingray, table: int_full_act_record.0 */
        {
        .description = "flow_cntr_ptr",
        .field_bit_size = 14,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
        },
        {
        .description = "age_enable",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "agg_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "rate_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "flow_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT,
-       .field_operand = {
-               ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 32) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 24) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 16) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 8) & 0xff,
-               (uint64_t)BNXT_ULP_ACTION_BIT_COUNT & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+       .field_opr1 = {
+               ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,
+               (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}
        },
        {
        .description = "tcpflags_key",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_mir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_match",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "encap_ptr",
        .field_bit_size = 11,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}
        },
        {
        .description = "dst_ip_ptr",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff}
        },
        {
        .description = "tcp_dst_port",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST,
-       .field_operand = {
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 56) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 48) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 40) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 32) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 24) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 16) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 8) & 0xff,
-               (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
-       .field_operand_true = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,
+       .field_cond_opr = {
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+               (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+       .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+       .field_opr1 = {
                (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,
-               BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},
+       .field_src2 = BNXT_ULP_FIELD_SRC_CONST
        },
        {
        .description = "src_ip_ptr",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff}
        },
        {
        .description = "tcp_src_port",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST,
-       .field_operand = {
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 56) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 48) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 40) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 32) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 24) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 16) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 8) & 0xff,
-               (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
-       .field_operand_true = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,
+       .field_cond_opr = {
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+               (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+       .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+       .field_opr1 = {
                (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,
-               BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},
+       .field_src2 = BNXT_ULP_FIELD_SRC_CONST
        },
        {
        .description = "meter_id",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "l3_rdir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tl3_rdir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "l3_ttl_dec",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+       .field_opr1 = {
                (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
-               BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
        },
        {
        .description = "tl3_ttl_dec",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+       .field_opr1 = {
                (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
-               BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
        },
        {
        .description = "decap_func",
        .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST,
-       .field_operand = {
-               ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 56) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 48) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 40) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 32) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 24) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 16) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 8) & 0xff,
-               (uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
-       .field_operand_true = {0x0a, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,
+       .field_cond_opr = {
+               ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff,
+               (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff},
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               ULP_SR_SYM_DECAP_FUNC_THRU_TUN},
+       .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr2 = {
+               ULP_SR_SYM_DECAP_FUNC_NONE}
        },
        {
        .description = "vnic_or_vport",
        .field_bit_size = 12,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+       .field_opr1 = {
                (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
-               BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
        },
        {
        .description = "pop_vlan",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT,
-       .field_operand = {
-               ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 56) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 48) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 40) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 32) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 24) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 16) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 8) & 0xff,
-               (uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+       .field_opr1 = {
+               ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff,
+               (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff}
        },
        {
        .description = "meter",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "mirror",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "drop",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT,
-       .field_operand = {
-               ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 56) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 48) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 40) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 32) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 24) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 16) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 8) & 0xff,
-               (uint64_t)BNXT_ULP_ACTION_BIT_DROP & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+       .field_opr1 = {
+               ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
+               (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
        },
        {
        .description = "hit",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "type",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        /* act_tid: 1, stingray, table: ext_full_act_record.0 */
        {
        .description = "flow_cntr_ptr",
        .field_bit_size = 14,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
        },
        {
        .description = "age_enable",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "agg_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "rate_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "flow_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT,
-       .field_operand = {
-               ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 32) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 24) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 16) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 8) & 0xff,
-               (uint64_t)BNXT_ULP_ACTION_BIT_COUNT & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+       .field_opr1 = {
+               ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,
+               (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}
        },
        {
        .description = "flow_cntr_ext",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_key",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_mir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_match",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "encap_ptr",
        .field_bit_size = 11,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "encap_rec_int",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "dst_ip_ptr",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff}
        },
        {
        .description = "tcp_dst_port",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST,
-       .field_operand = {
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 56) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 48) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 40) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 32) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 24) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 16) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 8) & 0xff,
-               (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
-       .field_operand_true = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,
+       .field_cond_opr = {
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+               (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+       .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+       .field_opr1 = {
                (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,
-               BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},
+       .field_src2 = BNXT_ULP_FIELD_SRC_CONST
        },
        {
        .description = "src_ip_ptr",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff}
        },
        {
        .description = "tcp_src_port",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST,
-       .field_operand = {
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 56) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 48) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 40) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 32) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 24) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 16) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 8) & 0xff,
-               (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
-       .field_operand_true = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,
+       .field_cond_opr = {
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+               (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+       .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+       .field_opr1 = {
                (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,
-               BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},
+       .field_src2 = BNXT_ULP_FIELD_SRC_CONST
        },
        {
        .description = "meter_id",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "l3_rdir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tl3_rdir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "l3_ttl_dec",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+       .field_opr1 = {
                (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
-               BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
        },
        {
        .description = "tl3_ttl_dec",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+       .field_opr1 = {
                (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
-               BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
        },
        {
        .description = "decap_func",
        .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST,
-       .field_operand = {
-               ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 56) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 48) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 40) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 32) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 24) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 16) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 8) & 0xff,
-               (uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
-       .field_operand_true = {0x0a, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,
+       .field_cond_opr = {
+               ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff,
+               (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff},
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               ULP_SR_SYM_DECAP_FUNC_THRU_TUN},
+       .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr2 = {
+               ULP_SR_SYM_DECAP_FUNC_NONE}
        },
        {
        .description = "vnic_or_vport",
        .field_bit_size = 12,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+       .field_opr1 = {
                (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
-               BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
        },
        {
        .description = "pop_vlan",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT,
-       .field_operand = {
-               ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 56) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 48) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 40) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 32) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 24) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 16) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 8) & 0xff,
-               (uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+       .field_opr1 = {
+               ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff,
+               (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff}
        },
        {
        .description = "meter",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "mirror",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "drop",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT,
-       .field_operand = {
-               ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 56) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 48) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 40) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 32) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 24) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 16) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 8) & 0xff,
-               (uint64_t)BNXT_ULP_ACTION_BIT_DROP & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+       .field_opr1 = {
+               ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
+               (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
        }
 };

diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c
index c836e2f..a0cab17 100644 (file)
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c
@@ -3,7 +3,7 @@
  * All rights reserved.
  */
 
-/* date: Mon Nov 23 17:33:02 2020 */
+/* date: Wed Dec  2 12:05:11 2020 */
 
 #include "ulp_template_db_enum.h"
 #include "ulp_template_db_field.h"
@@ -15,7 +15,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_stingray_class_tmpl_list[] = {
        /* class_tid: 1, stingray, ingress */
        [1] = {
        .device_name = BNXT_ULP_DEVICE_ID_STINGRAY,
-       .num_tbls = 6,
+       .num_tbls = 9,
        .start_tbl_idx = 0,
        .reject_info = {
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
@@ -26,17 +26,17 @@ struct bnxt_ulp_mapper_tmpl_info ulp_stingray_class_tmpl_list[] = {
        [2] = {
        .device_name = BNXT_ULP_DEVICE_ID_STINGRAY,
        .num_tbls = 6,
-       .start_tbl_idx = 6,
+       .start_tbl_idx = 9,
        .reject_info = {
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
-               .cond_start_idx = 2,
+               .cond_start_idx = 4,
                .cond_nums = 0 }
        },
-       /* class_tid: 3, stingray, ingress */
+       /* class_tid: 3, stingray, egress */
        [3] = {
        .device_name = BNXT_ULP_DEVICE_ID_STINGRAY,
-       .num_tbls = 6,
-       .start_tbl_idx = 12,
+       .num_tbls = 8,
+       .start_tbl_idx = 15,
        .reject_info = {
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
                .cond_start_idx = 4,
@@ -45,18 +45,18 @@ struct bnxt_ulp_mapper_tmpl_info ulp_stingray_class_tmpl_list[] = {
        /* class_tid: 4, stingray, egress */
        [4] = {
        .device_name = BNXT_ULP_DEVICE_ID_STINGRAY,
-       .num_tbls = 8,
-       .start_tbl_idx = 18,
+       .num_tbls = 7,
+       .start_tbl_idx = 23,
        .reject_info = {
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
-               .cond_start_idx = 4,
+               .cond_start_idx = 10,
                .cond_nums = 0 }
        },
        /* class_tid: 5, stingray, egress */
        [5] = {
        .device_name = BNXT_ULP_DEVICE_ID_STINGRAY,
        .num_tbls = 7,
-       .start_tbl_idx = 26,
+       .start_tbl_idx = 30,
        .reject_info = {
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
                .cond_start_idx = 10,
@@ -65,18 +65,8 @@ struct bnxt_ulp_mapper_tmpl_info ulp_stingray_class_tmpl_list[] = {
        /* class_tid: 6, stingray, egress */
        [6] = {
        .device_name = BNXT_ULP_DEVICE_ID_STINGRAY,
-       .num_tbls = 7,
-       .start_tbl_idx = 33,
-       .reject_info = {
-               .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
-               .cond_start_idx = 10,
-               .cond_nums = 0 }
-       },
-       /* class_tid: 7, stingray, egress */
-       [7] = {
-       .device_name = BNXT_ULP_DEVICE_ID_STINGRAY,
        .num_tbls = 1,
-       .start_tbl_idx = 40,
+       .start_tbl_idx = 37,
        .reject_info = {
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
                .cond_start_idx = 10,
@@ -85,13 +75,35 @@ struct bnxt_ulp_mapper_tmpl_info ulp_stingray_class_tmpl_list[] = {
 };
 
 struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
+       { /* class_tid: 1, stingray, table: l2_cntxt_tcam_cache.rd */
+       .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+       .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+       .resource_sub_type =
+               BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+       .direction = TF_DIR_RX,
+       .execute_info = {
+               .cond_goto = 2,
+               .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+               .cond_start_idx = 0,
+               .cond_nums = 1 },
+       .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+       .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+       .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+       .key_start_idx = 0,
+       .blob_key_bit_size = 8,
+       .key_bit_size = 8,
+       .key_num_fields = 1,
+       .ident_start_idx = 0,
+       .ident_nums = 1
+       },
        { /* class_tid: 1, stingray, table: l2_cntxt_tcam.0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
        .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
        .direction = TF_DIR_RX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
-               .cond_start_idx = 0,
+               .cond_start_idx = 1,
                .cond_nums = 0 },
        .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE,
        .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
@@ -99,7 +111,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
        .pri_opcode  = BNXT_ULP_PRI_OPC_CONST,
        .pri_operand = 0,
-       .key_start_idx = 0,
+       .key_start_idx = 1,
        .blob_key_bit_size = 167,
        .key_bit_size = 167,
        .key_num_fields = 13,
@@ -107,7 +119,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
        .result_bit_size = 64,
        .result_num_fields = 13,
        .encap_num_fields = 0,
-       .ident_start_idx = 0,
+       .ident_start_idx = 1,
        .ident_nums = 1
        },
        { /* class_tid: 1, stingray, table: profile_tcam_cache.rd */
@@ -117,27 +129,40 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
                BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
        .direction = TF_DIR_RX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
-               .cond_start_idx = 0,
+               .cond_start_idx = 1,
                .cond_nums = 0 },
        .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_FLOW_SIG_ID_MATCH,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-       .key_start_idx = 13,
+       .key_start_idx = 14,
        .blob_key_bit_size = 14,
        .key_bit_size = 14,
        .key_num_fields = 3,
-       .ident_start_idx = 1,
+       .ident_start_idx = 2,
        .ident_nums = 3
        },
+       { /* class_tid: 1, stingray, table: branch.0 */
+       .resource_func = BNXT_ULP_RESOURCE_FUNC_BRANCH_TABLE,
+       .direction = TF_DIR_RX,
+       .execute_info = {
+               .cond_goto = 3,
+               .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+               .cond_start_idx = 1,
+               .cond_nums = 1 },
+       .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+       .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH
+       },
        { /* class_tid: 1, stingray, table: profile_tcam.0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
        .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
        .direction = TF_DIR_RX,
        .execute_info = {
-               .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
-               .cond_start_idx = 0,
-               .cond_nums = 1 },
+               .cond_goto = 1,
+               .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+               .cond_start_idx = 2,
+               .cond_nums = 0 },
        .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
        .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
@@ -145,7 +170,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
        .fdb_operand = BNXT_ULP_RF_IDX_RID,
        .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
        .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
-       .key_start_idx = 16,
+       .key_start_idx = 17,
        .blob_key_bit_size = 81,
        .key_bit_size = 81,
        .key_num_fields = 43,
@@ -153,7 +178,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
        .result_bit_size = 38,
        .result_num_fields = 8,
        .encap_num_fields = 0,
-       .ident_start_idx = 4,
+       .ident_start_idx = 5,
        .ident_nums = 1
        },
        { /* class_tid: 1, stingray, table: profile_tcam_cache.wr */
@@ -163,13 +188,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
                BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
        .direction = TF_DIR_RX,
        .execute_info = {
-               .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
-               .cond_start_idx = 1,
-               .cond_nums = 1 },
+               .cond_goto = 1,
+               .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+               .cond_start_idx = 2,
+               .cond_nums = 0 },
        .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-       .key_start_idx = 59,
+       .key_start_idx = 60,
        .blob_key_bit_size = 14,
        .key_bit_size = 14,
        .key_num_fields = 3,
@@ -178,194 +204,71 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
        .result_num_fields = 5,
        .encap_num_fields = 0
        },
-       { /* class_tid: 1, stingray, table: eem.ext_0 */
-       .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE,
-       .resource_type = TF_MEM_EXTERNAL,
-       .direction = TF_DIR_RX,
-       .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT,
-       .execute_info = {
-               .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
-               .cond_start_idx = 2,
-               .cond_nums = 0 },
-       .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-       .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-       .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
-       .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
-       .key_start_idx = 62,
-       .blob_key_bit_size = 448,
-       .key_bit_size = 448,
-       .key_num_fields = 10,
-       .result_start_idx = 26,
-       .result_bit_size = 64,
-       .result_num_fields = 9,
-       .encap_num_fields = 0
-       },
        { /* class_tid: 1, stingray, table: em.int_0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
        .resource_type = TF_MEM_INTERNAL,
        .direction = TF_DIR_RX,
        .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,
        .execute_info = {
-               .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+               .cond_goto = 1,
+               .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
                .cond_start_idx = 2,
-               .cond_nums = 0 },
+               .cond_nums = 1 },
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
        .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
        .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
-       .key_start_idx = 72,
+       .key_start_idx = 63,
        .blob_key_bit_size = 176,
        .key_bit_size = 176,
        .key_num_fields = 10,
-       .result_start_idx = 35,
+       .result_start_idx = 26,
        .result_bit_size = 64,
        .result_num_fields = 9,
        .encap_num_fields = 0
        },
-       { /* class_tid: 2, stingray, table: l2_cntxt_tcam.0 */
-       .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
-       .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
-       .direction = TF_DIR_RX,
-       .execute_info = {
-               .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
-               .cond_start_idx = 2,
-               .cond_nums = 0 },
-       .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE,
-       .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
-       .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-       .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-       .pri_opcode  = BNXT_ULP_PRI_OPC_CONST,
-       .pri_operand = 0,
-       .key_start_idx = 82,
-       .blob_key_bit_size = 167,
-       .key_bit_size = 167,
-       .key_num_fields = 13,
-       .result_start_idx = 44,
-       .result_bit_size = 64,
-       .result_num_fields = 13,
-       .encap_num_fields = 0,
-       .ident_start_idx = 5,
-       .ident_nums = 1
-       },
-       { /* class_tid: 2, stingray, table: profile_tcam_cache.rd */
-       .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
-       .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
-       .resource_sub_type =
-               BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
-       .direction = TF_DIR_RX,
-       .execute_info = {
-               .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
-               .cond_start_idx = 2,
-               .cond_nums = 0 },
-       .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
-       .accept_opcode = BNXT_ULP_ACCEPT_OPC_FLOW_SIG_ID_MATCH,
-       .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-       .key_start_idx = 95,
-       .blob_key_bit_size = 14,
-       .key_bit_size = 14,
-       .key_num_fields = 3,
-       .ident_start_idx = 6,
-       .ident_nums = 3
-       },
-       { /* class_tid: 2, stingray, table: profile_tcam.0 */
-       .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
-       .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
-       .direction = TF_DIR_RX,
-       .execute_info = {
-               .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
-               .cond_start_idx = 2,
-               .cond_nums = 1 },
-       .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
-       .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
-       .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-       .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE,
-       .fdb_operand = BNXT_ULP_RF_IDX_RID,
-       .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
-       .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
-       .key_start_idx = 98,
-       .blob_key_bit_size = 81,
-       .key_bit_size = 81,
-       .key_num_fields = 43,
-       .result_start_idx = 57,
-       .result_bit_size = 38,
-       .result_num_fields = 8,
-       .encap_num_fields = 0,
-       .ident_start_idx = 9,
-       .ident_nums = 1
-       },
-       { /* class_tid: 2, stingray, table: profile_tcam_cache.wr */
-       .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
-       .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
-       .resource_sub_type =
-               BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
-       .direction = TF_DIR_RX,
-       .execute_info = {
-               .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
-               .cond_start_idx = 3,
-               .cond_nums = 1 },
-       .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
-       .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-       .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-       .key_start_idx = 141,
-       .blob_key_bit_size = 14,
-       .key_bit_size = 14,
-       .key_num_fields = 3,
-       .result_start_idx = 65,
-       .result_bit_size = 66,
-       .result_num_fields = 5,
-       .encap_num_fields = 0
-       },
-       { /* class_tid: 2, stingray, table: eem.ext_0 */
+       { /* class_tid: 1, stingray, table: eem.ext_0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE,
        .resource_type = TF_MEM_EXTERNAL,
        .direction = TF_DIR_RX,
        .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT,
        .execute_info = {
-               .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
-               .cond_start_idx = 4,
-               .cond_nums = 0 },
+               .cond_goto = 1,
+               .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+               .cond_start_idx = 3,
+               .cond_nums = 1 },
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
        .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
        .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
-       .key_start_idx = 144,
+       .key_start_idx = 73,
        .blob_key_bit_size = 448,
        .key_bit_size = 448,
        .key_num_fields = 10,
-       .result_start_idx = 70,
+       .result_start_idx = 35,
        .result_bit_size = 64,
        .result_num_fields = 9,
        .encap_num_fields = 0
        },
-       { /* class_tid: 2, stingray, table: em.int_0 */
-       .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
-       .resource_type = TF_MEM_INTERNAL,
+       { /* class_tid: 1, stingray, table: last */
+       .resource_func = BNXT_ULP_RESOURCE_FUNC_BRANCH_TABLE,
        .direction = TF_DIR_RX,
-       .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,
        .execute_info = {
+               .cond_goto = 0,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 4,
                .cond_nums = 0 },
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-       .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-       .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
-       .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
-       .key_start_idx = 154,
-       .blob_key_bit_size = 176,
-       .key_bit_size = 176,
-       .key_num_fields = 10,
-       .result_start_idx = 79,
-       .result_bit_size = 64,
-       .result_num_fields = 9,
-       .encap_num_fields = 0
+       .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH
        },
-       { /* class_tid: 3, stingray, table: int_full_act_record.0 */
+       { /* class_tid: 2, stingray, table: int_full_act_record.0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
        .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
        .resource_sub_type =
                BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
        .direction = TF_DIR_RX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 4,
                .cond_nums = 0 },
@@ -374,16 +277,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
        .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
-       .result_start_idx = 88,
+       .result_start_idx = 44,
        .result_bit_size = 128,
        .result_num_fields = 26,
        .encap_num_fields = 0
        },
-       { /* class_tid: 3, stingray, table: l2_cntxt_tcam.0 */
+       { /* class_tid: 2, stingray, table: l2_cntxt_tcam.0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
        .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
        .direction = TF_DIR_RX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 4,
                .cond_nums = 0 },
@@ -396,44 +300,46 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
        .pri_operand = 0,
        .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
        .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
-       .key_start_idx = 164,
+       .key_start_idx = 83,
        .blob_key_bit_size = 167,
        .key_bit_size = 167,
        .key_num_fields = 13,
-       .result_start_idx = 114,
+       .result_start_idx = 70,
        .result_bit_size = 64,
        .result_num_fields = 13,
        .encap_num_fields = 0,
-       .ident_start_idx = 10,
+       .ident_start_idx = 6,
        .ident_nums = 1
        },
-       { /* class_tid: 3, stingray, table: l2_cntxt_tcam_cache.wr */
+       { /* class_tid: 2, stingray, table: l2_cntxt_tcam_cache.wr */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
        .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
        .resource_sub_type =
                BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
        .direction = TF_DIR_RX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 4,
                .cond_nums = 0 },
        .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-       .key_start_idx = 177,
+       .key_start_idx = 96,
        .blob_key_bit_size = 8,
        .key_bit_size = 8,
        .key_num_fields = 1,
-       .result_start_idx = 127,
+       .result_start_idx = 83,
        .result_bit_size = 62,
        .result_num_fields = 4,
        .encap_num_fields = 0
        },
-       { /* class_tid: 3, stingray, table: parif_def_lkup_arec_ptr.0 */
+       { /* class_tid: 2, stingray, table: parif_def_lkup_arec_ptr.0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
        .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,
        .direction = TF_DIR_RX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 4,
                .cond_nums = 0 },
@@ -441,16 +347,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
        .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-       .result_start_idx = 131,
+       .result_start_idx = 87,
        .result_bit_size = 32,
        .result_num_fields = 1,
        .encap_num_fields = 0
        },
-       { /* class_tid: 3, stingray, table: parif_def_arec_ptr.0 */
+       { /* class_tid: 2, stingray, table: parif_def_arec_ptr.0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
        .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
        .direction = TF_DIR_RX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 4,
                .cond_nums = 0 },
@@ -458,16 +365,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
        .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-       .result_start_idx = 132,
+       .result_start_idx = 88,
        .result_bit_size = 32,
        .result_num_fields = 1,
        .encap_num_fields = 0
        },
-       { /* class_tid: 3, stingray, table: parif_def_err_arec_ptr.0 */
+       { /* class_tid: 2, stingray, table: parif_def_err_arec_ptr.0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
        .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
        .direction = TF_DIR_RX,
        .execute_info = {
+               .cond_goto = 0,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 4,
                .cond_nums = 0 },
@@ -475,18 +383,19 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
        .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-       .result_start_idx = 133,
+       .result_start_idx = 89,
        .result_bit_size = 32,
        .result_num_fields = 1,
        .encap_num_fields = 0
        },
-       { /* class_tid: 4, stingray, table: int_full_act_record.0 */
+       { /* class_tid: 3, stingray, table: int_full_act_record.0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
        .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
        .resource_sub_type =
                BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
        .direction = TF_DIR_TX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 4,
                .cond_nums = 0 },
@@ -495,16 +404,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
        .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
-       .result_start_idx = 134,
+       .result_start_idx = 90,
        .result_bit_size = 128,
        .result_num_fields = 26,
        .encap_num_fields = 0
        },
-       { /* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.vfr_0 */
+       { /* class_tid: 3, stingray, table: l2_cntxt_tcam_bypass.vfr_0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
        .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
        .direction = TF_DIR_TX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
                .cond_start_idx = 4,
                .cond_nums = 1 },
@@ -516,42 +426,44 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
        .pri_operand = 0,
        .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
        .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
-       .key_start_idx = 178,
+       .key_start_idx = 97,
        .blob_key_bit_size = 167,
        .key_bit_size = 167,
        .key_num_fields = 13,
-       .result_start_idx = 160,
+       .result_start_idx = 116,
        .result_bit_size = 64,
        .result_num_fields = 13,
        .encap_num_fields = 0,
-       .ident_start_idx = 11,
+       .ident_start_idx = 7,
        .ident_nums = 0
        },
-       { /* class_tid: 4, stingray, table: l2_cntxt_tcam_cache.rd */
+       { /* class_tid: 3, stingray, table: l2_cntxt_tcam_cache.rd */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
        .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
        .resource_sub_type =
                BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
        .direction = TF_DIR_TX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
                .cond_start_idx = 5,
                .cond_nums = 1 },
        .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-       .key_start_idx = 191,
+       .key_start_idx = 110,
        .blob_key_bit_size = 8,
        .key_bit_size = 8,
        .key_num_fields = 1,
-       .ident_start_idx = 11,
+       .ident_start_idx = 7,
        .ident_nums = 1
        },
-       { /* class_tid: 4, stingray, table: l2_cntxt_tcam.0 */
+       { /* class_tid: 3, stingray, table: l2_cntxt_tcam.0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
        .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
        .direction = TF_DIR_TX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
                .cond_start_idx = 6,
                .cond_nums = 2 },
@@ -562,44 +474,46 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
        .fdb_operand = BNXT_ULP_RF_IDX_RID,
        .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
        .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
-       .key_start_idx = 192,
+       .key_start_idx = 111,
        .blob_key_bit_size = 167,
        .key_bit_size = 167,
        .key_num_fields = 13,
-       .result_start_idx = 173,
+       .result_start_idx = 129,
        .result_bit_size = 64,
        .result_num_fields = 13,
        .encap_num_fields = 0,
-       .ident_start_idx = 12,
+       .ident_start_idx = 8,
        .ident_nums = 1
        },
-       { /* class_tid: 4, stingray, table: l2_cntxt_tcam_cache.wr */
+       { /* class_tid: 3, stingray, table: l2_cntxt_tcam_cache.wr */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
        .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
        .resource_sub_type =
                BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
        .direction = TF_DIR_TX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
                .cond_start_idx = 8,
                .cond_nums = 2 },
        .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-       .key_start_idx = 205,
+       .key_start_idx = 124,
        .blob_key_bit_size = 8,
        .key_bit_size = 8,
        .key_num_fields = 1,
-       .result_start_idx = 186,
+       .result_start_idx = 142,
        .result_bit_size = 62,
        .result_num_fields = 4,
        .encap_num_fields = 0
        },
-       { /* class_tid: 4, stingray, table: parif_def_lkup_arec_ptr.0 */
+       { /* class_tid: 3, stingray, table: parif_def_lkup_arec_ptr.0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
        .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,
        .direction = TF_DIR_TX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 10,
                .cond_nums = 0 },
@@ -607,16 +521,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
        .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-       .result_start_idx = 190,
+       .result_start_idx = 146,
        .result_bit_size = 32,
        .result_num_fields = 1,
        .encap_num_fields = 0
        },
-       { /* class_tid: 4, stingray, table: parif_def_arec_ptr.0 */
+       { /* class_tid: 3, stingray, table: parif_def_arec_ptr.0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
        .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
        .direction = TF_DIR_TX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 10,
                .cond_nums = 0 },
@@ -624,16 +539,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
        .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-       .result_start_idx = 191,
+       .result_start_idx = 147,
        .result_bit_size = 32,
        .result_num_fields = 1,
        .encap_num_fields = 0
        },
-       { /* class_tid: 4, stingray, table: parif_def_err_arec_ptr.0 */
+       { /* class_tid: 3, stingray, table: parif_def_err_arec_ptr.0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
        .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
        .direction = TF_DIR_TX,
        .execute_info = {
+               .cond_goto = 0,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 10,
                .cond_nums = 0 },
@@ -641,18 +557,19 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
        .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-       .result_start_idx = 192,
+       .result_start_idx = 148,
        .result_bit_size = 32,
        .result_num_fields = 1,
        .encap_num_fields = 0
        },
-       { /* class_tid: 5, stingray, table: int_vtag_encap_record.egr0 */
+       { /* class_tid: 4, stingray, table: int_vtag_encap_record.egr0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
        .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
        .resource_sub_type =
                BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
        .direction = TF_DIR_TX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 10,
                .cond_nums = 0 },
@@ -661,18 +578,19 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
        .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
-       .result_start_idx = 193,
+       .result_start_idx = 149,
        .result_bit_size = 0,
        .result_num_fields = 0,
        .encap_num_fields = 12
        },
-       { /* class_tid: 5, stingray, table: int_full_act_record.egr0 */
+       { /* class_tid: 4, stingray, table: int_full_act_record.egr0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
        .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
        .resource_sub_type =
                BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
        .direction = TF_DIR_TX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 10,
                .cond_nums = 0 },
@@ -681,16 +599,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
        .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
-       .result_start_idx = 205,
+       .result_start_idx = 161,
        .result_bit_size = 128,
        .result_num_fields = 26,
        .encap_num_fields = 0
        },
-       { /* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.egr0 */
+       { /* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.egr0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
        .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
        .direction = TF_DIR_TX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 10,
                .cond_nums = 0 },
@@ -701,48 +620,50 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
        .fdb_operand = BNXT_ULP_RF_IDX_RID,
        .pri_opcode  = BNXT_ULP_PRI_OPC_CONST,
        .pri_operand = 0,
-       .key_start_idx = 206,
+       .key_start_idx = 125,
        .blob_key_bit_size = 167,
        .key_bit_size = 167,
        .key_num_fields = 13,
-       .result_start_idx = 231,
+       .result_start_idx = 187,
        .result_bit_size = 64,
        .result_num_fields = 13,
        .encap_num_fields = 0,
-       .ident_start_idx = 13,
+       .ident_start_idx = 9,
        .ident_nums = 0
        },
-       { /* class_tid: 5, stingray, table: l2_cntxt_tcam_cache.wr_egr0 */
+       { /* class_tid: 4, stingray, table: l2_cntxt_tcam_cache.wr_egr0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
        .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
        .resource_sub_type =
                BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
        .direction = TF_DIR_TX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 10,
                .cond_nums = 0 },
        .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-       .key_start_idx = 219,
+       .key_start_idx = 138,
        .blob_key_bit_size = 8,
        .key_bit_size = 8,
        .key_num_fields = 1,
-       .result_start_idx = 244,
+       .result_start_idx = 200,
        .result_bit_size = 62,
        .result_num_fields = 4,
        .encap_num_fields = 0,
-       .ident_start_idx = 13,
+       .ident_start_idx = 9,
        .ident_nums = 0
        },
-       { /* class_tid: 5, stingray, table: int_full_act_record.ing0 */
+       { /* class_tid: 4, stingray, table: int_full_act_record.ing0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
        .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
        .resource_sub_type =
                BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
        .direction = TF_DIR_RX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 10,
                .cond_nums = 0 },
@@ -751,16 +672,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
        .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
-       .result_start_idx = 248,
+       .result_start_idx = 204,
        .result_bit_size = 128,
        .result_num_fields = 26,
        .encap_num_fields = 0
        },
-       { /* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.dtagged_ing0 */
+       { /* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.dtagged_ing0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
        .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
        .direction = TF_DIR_RX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 10,
                .cond_nums = 0 },
@@ -772,22 +694,23 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
        .pri_operand = 0,
        .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
        .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
-       .key_start_idx = 220,
+       .key_start_idx = 139,
        .blob_key_bit_size = 167,
        .key_bit_size = 167,
        .key_num_fields = 13,
-       .result_start_idx = 274,
+       .result_start_idx = 230,
        .result_bit_size = 64,
        .result_num_fields = 13,
        .encap_num_fields = 0,
-       .ident_start_idx = 13,
+       .ident_start_idx = 9,
        .ident_nums = 0
        },
-       { /* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.stagged_ing0 */
+       { /* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.stagged_ing0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
        .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
        .direction = TF_DIR_RX,
        .execute_info = {
+               .cond_goto = 0,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 10,
                .cond_nums = 0 },
@@ -799,22 +722,23 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
        .pri_operand = 0,
        .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
        .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
-       .key_start_idx = 233,
+       .key_start_idx = 152,
        .blob_key_bit_size = 167,
        .key_bit_size = 167,
        .key_num_fields = 13,
-       .result_start_idx = 287,
+       .result_start_idx = 243,
        .result_bit_size = 64,
        .result_num_fields = 13,
        .encap_num_fields = 0,
-       .ident_start_idx = 13,
+       .ident_start_idx = 9,
        .ident_nums = 0
        },
-       { /* class_tid: 6, stingray, table: l2_cntxt_tcam.egr */
+       { /* class_tid: 5, stingray, table: l2_cntxt_tcam.egr */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
        .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
        .direction = TF_DIR_TX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 10,
                .cond_nums = 0 },
@@ -825,44 +749,46 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
        .fdb_operand = BNXT_ULP_RF_IDX_RID,
        .pri_opcode  = BNXT_ULP_PRI_OPC_CONST,
        .pri_operand = 0,
-       .key_start_idx = 246,
+       .key_start_idx = 165,
        .blob_key_bit_size = 167,
        .key_bit_size = 167,
        .key_num_fields = 13,
-       .result_start_idx = 300,
+       .result_start_idx = 256,
        .result_bit_size = 64,
        .result_num_fields = 13,
        .encap_num_fields = 0,
-       .ident_start_idx = 13,
+       .ident_start_idx = 9,
        .ident_nums = 1
        },
-       { /* class_tid: 6, stingray, table: l2_cntxt_tcam_cache.egr_wr */
+       { /* class_tid: 5, stingray, table: l2_cntxt_tcam_cache.egr_wr */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
        .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
        .resource_sub_type =
                BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
        .direction = TF_DIR_TX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 10,
                .cond_nums = 0 },
        .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-       .key_start_idx = 259,
+       .key_start_idx = 178,
        .blob_key_bit_size = 8,
        .key_bit_size = 8,
        .key_num_fields = 1,
-       .result_start_idx = 313,
+       .result_start_idx = 269,
        .result_bit_size = 62,
        .result_num_fields = 4,
        .encap_num_fields = 0
        },
-       { /* class_tid: 6, stingray, table: parif_def_lkup_arec_ptr.egr */
+       { /* class_tid: 5, stingray, table: parif_def_lkup_arec_ptr.egr */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
        .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,
        .direction = TF_DIR_TX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 10,
                .cond_nums = 0 },
@@ -870,16 +796,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
        .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF,
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-       .result_start_idx = 317,
+       .result_start_idx = 273,
        .result_bit_size = 32,
        .result_num_fields = 1,
        .encap_num_fields = 0
        },
-       { /* class_tid: 6, stingray, table: parif_def_arec_ptr.egr */
+       { /* class_tid: 5, stingray, table: parif_def_arec_ptr.egr */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
        .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
        .direction = TF_DIR_TX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 10,
                .cond_nums = 0 },
@@ -887,16 +814,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
        .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF,
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-       .result_start_idx = 318,
+       .result_start_idx = 274,
        .result_bit_size = 32,
        .result_num_fields = 1,
        .encap_num_fields = 0
        },
-       { /* class_tid: 6, stingray, table: parif_def_err_arec_ptr.egr */
+       { /* class_tid: 5, stingray, table: parif_def_err_arec_ptr.egr */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
        .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
        .direction = TF_DIR_TX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 10,
                .cond_nums = 0 },
@@ -904,18 +832,19 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
        .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF,
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-       .result_start_idx = 319,
+       .result_start_idx = 275,
        .result_bit_size = 32,
        .result_num_fields = 1,
        .encap_num_fields = 0
        },
-       { /* class_tid: 6, stingray, table: int_full_act_record.ing */
+       { /* class_tid: 5, stingray, table: int_full_act_record.ing */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
        .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
        .resource_sub_type =
                BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
        .direction = TF_DIR_RX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 10,
                .cond_nums = 0 },
@@ -924,16 +853,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
        .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,
-       .result_start_idx = 320,
+       .result_start_idx = 276,
        .result_bit_size = 128,
        .result_num_fields = 26,
        .encap_num_fields = 0
        },
-       { /* class_tid: 6, stingray, table: l2_cntxt_tcam_bypass.ing */
+       { /* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.ing */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
        .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
        .direction = TF_DIR_RX,
        .execute_info = {
+               .cond_goto = 0,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 10,
                .cond_nums = 0 },
@@ -945,24 +875,25 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
        .pri_operand = 0,
        .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
        .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
-       .key_start_idx = 260,
+       .key_start_idx = 179,
        .blob_key_bit_size = 167,
        .key_bit_size = 167,
        .key_num_fields = 13,
-       .result_start_idx = 346,
+       .result_start_idx = 302,
        .result_bit_size = 64,
        .result_num_fields = 13,
        .encap_num_fields = 0,
-       .ident_start_idx = 14,
+       .ident_start_idx = 10,
        .ident_nums = 0
        },
-       { /* class_tid: 7, stingray, table: int_full_act_record.0 */
+       { /* class_tid: 6, stingray, table: int_full_act_record.0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
        .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
        .resource_sub_type =
                BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
        .direction = TF_DIR_TX,
        .execute_info = {
+               .cond_goto = 0,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 10,
                .cond_nums = 0 },
@@ -971,7 +902,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
        .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
-       .result_start_idx = 359,
+       .result_start_idx = 315,
        .result_bit_size = 128,
        .result_num_fields = 26,
        .encap_num_fields = 0
@@ -980,246 +911,279 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 
 struct bnxt_ulp_mapper_cond_info ulp_stingray_class_cond_list[] = {
        {
-       .cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET,
-       .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT
+       .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET,
+       .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC
        },
        {
-       .cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET,
+       .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
        .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT
        },
        {
-       .cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET,
-       .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT
+       .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+       .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
        },
        {
-       .cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET,
-       .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT
+       .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+       .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
        },
        {
-       .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_IS_SET,
+       .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
        .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
        },
        {
-       .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET,
+       .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,
        .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
        },
        {
-       .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET,
+       .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,
        .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
        },
        {
-       .cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET,
+       .cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET,
        .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT
        },
        {
-       .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET,
+       .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,
        .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
        },
        {
-       .cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET,
+       .cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET,
        .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT
        }
 };
 
 struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = {
+       /* class_tid: 1, stingray, table: l2_cntxt_tcam_cache.rd */
+       {
+       .field_info_mask = {
+               .description = "svif",
+               .field_bit_size = 8,
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+               },
+       .field_info_spec = {
+               .description = "svif",
+               .field_bit_size = 8,
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+               }
+       },
        /* class_tid: 1, stingray, table: l2_cntxt_tcam.0 */
        {
        .field_info_mask = {
                .description = "l2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_OO_VLAN_VID >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_OO_VLAN_VID & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}
                },
        .field_info_spec = {
                .description = "l2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_OO_VLAN_VID >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_OO_VLAN_VID & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "l2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "mac0_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_ETH_DMAC >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_ETH_DMAC & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
                },
        .field_info_spec = {
                .description = "mac0_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_ETH_DMAC >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_ETH_DMAC & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_SVIF_INDEX >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_SVIF_INDEX & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
                },
        .field_info_spec = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_SVIF_INDEX >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_SVIF_INDEX & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "sparif",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "sparif",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "mac1_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "mac1_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "l2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+               .field_opr1 = {
                        (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tun_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tun_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "key_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "key_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       1}
                }
        },
        /* class_tid: 1, stingray, table: profile_tcam_cache.rd */
@@ -1227,52 +1191,54 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = {
        .field_info_mask = {
                .description = "recycle_cnt",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "recycle_cnt",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "prof_func_id",
                .field_bit_size = 7,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "prof_func_id",
                .field_bit_size = 7,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,
-               .field_operand = {
-               (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
-                       BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+                       BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "hdr_sig_id",
                .field_bit_size = 5,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "hdr_sig_id",
                .field_bit_size = 5,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+               .field_opr1 = {
                        (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
                }
        },
        /* class_tid: 1, stingray, table: profile_tcam.0 */
@@ -1280,580 +1246,684 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = {
        .field_info_mask = {
                .description = "l4_hdr_is_udp_tcp",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l4_hdr_is_udp_tcp",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l4_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "l4_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
+               .field_cond_opr = {
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+                       (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       ULP_SR_SYM_L4_HDR_TYPE_TCP},
+               .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr2 = {
+                       ULP_SR_SYM_L4_HDR_TYPE_UDP}
                }
        },
        {
        .field_info_mask = {
                .description = "l4_hdr_error",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "l4_hdr_error",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l4_hdr_valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "l4_hdr_valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {
-                       BNXT_ULP_STINGRAY_SYM_L4_HDR_VALID_YES,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       ULP_SR_SYM_L4_HDR_VALID_YES}
                }
        },
        {
        .field_info_mask = {
                .description = "l3_ipv6_cmp_dst",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l3_ipv6_cmp_dst",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l3_ipv6_cmp_src",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l3_ipv6_cmp_src",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l3_hdr_isIP",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l3_hdr_isIP",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l3_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "l3_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
+               .field_cond_opr = {
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+                       (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       ULP_SR_SYM_L3_HDR_TYPE_IPV4},
+               .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr2 = {
+                       ULP_SR_SYM_L3_HDR_TYPE_IPV6}
                }
        },
        {
        .field_info_mask = {
                .description = "l3_hdr_error",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "l3_hdr_error",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l3_hdr_valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "l3_hdr_valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {
-                       BNXT_ULP_STINGRAY_SYM_L3_HDR_VALID_YES,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       ULP_SR_SYM_L3_HDR_VALID_YES}
                }
        },
        {
        .field_info_mask = {
                .description = "l2_two_vtags",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "l2_two_vtags",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_vtag_present",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "l2_vtag_present",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+               .field_opr1 = {
                        (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "l2_uc_mc_bc",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "l2_uc_mc_bc",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_hdr_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "l2_hdr_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_hdr_error",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "l2_hdr_error",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_hdr_valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "l2_hdr_valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {
-                       BNXT_ULP_STINGRAY_SYM_L2_HDR_VALID_YES,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       ULP_SR_SYM_L2_HDR_VALID_YES}
                }
        },
        {
        .field_info_mask = {
                .description = "tun_hdr_flags",
                .field_bit_size = 3,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tun_hdr_flags",
                .field_bit_size = 3,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tun_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tun_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tun_hdr_err",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tun_hdr_err",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tun_hdr_valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "tun_hdr_valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl4_hdr_is_udp_tcp",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl4_hdr_is_udp_tcp",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl4_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl4_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl4_hdr_error",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl4_hdr_error",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl4_hdr_valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "tl4_hdr_valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl3_ipv6_cmp_dst",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl3_ipv6_cmp_dst",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl3_ipv6_cmp_src",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl3_ipv6_cmp_src",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl3_hdr_isIP",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl3_hdr_isIP",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl3_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl3_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl3_hdr_error",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl3_hdr_error",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl3_hdr_valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "tl3_hdr_valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_two_vtags",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_two_vtags",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_vtag_present",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_vtag_present",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_uc_mc_bc",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_uc_mc_bc",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_hdr_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_hdr_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_hdr_valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "tl2_hdr_valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "hrec_next",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "hrec_next",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "reserved",
                .field_bit_size = 9,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "reserved",
                .field_bit_size = 9,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "prof_func_id",
                .field_bit_size = 7,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "prof_func_id",
                .field_bit_size = 7,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,
-               .field_operand = {
-               (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
-                       BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+                       BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "agg_error",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "agg_error",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "recycle_cnt",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "recycle_cnt",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "pkt_type_0",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "pkt_type_0",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "pkt_type_1",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "pkt_type_1",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       1}
                }
        },
        /* class_tid: 1, stingray, table: profile_tcam_cache.wr */
@@ -1861,3165 +1931,2188 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = {
        .field_info_mask = {
                .description = "recycle_cnt",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "recycle_cnt",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "prof_func_id",
                .field_bit_size = 7,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "prof_func_id",
                .field_bit_size = 7,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,
-               .field_operand = {
-               (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
-                       BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+                       BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "hdr_sig_id",
                .field_bit_size = 5,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "hdr_sig_id",
                .field_bit_size = 5,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+               .field_opr1 = {
                        (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
                }
        },
-       /* class_tid: 1, stingray, table: eem.ext_0 */
+       /* class_tid: 1, stingray, table: em.int_0 */
        {
        .field_info_mask = {
                .description = "spare",
-               .field_bit_size = 275,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_bit_size = 3,
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "spare",
-               .field_bit_size = 275,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_bit_size = 3,
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "local_cos",
                .field_bit_size = 3,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "local_cos",
                .field_bit_size = 3,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "o_l4.dport",
                .field_bit_size = 16,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff,
+                       0xff}
                },
        .field_info_spec = {
                .description = "o_l4.dport",
                .field_bit_size = 16,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
+               .field_cond_opr = {
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+                       (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+               .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},
+               .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr2 = {
+                       (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "o_l4.sport",
                .field_bit_size = 16,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff,
+                       0xff}
                },
        .field_info_spec = {
                .description = "o_l4.sport",
                .field_bit_size = 16,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
+               .field_cond_opr = {
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+                       (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+               .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},
+               .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr2 = {
+                       (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "o_ipv4.ip_proto",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "o_ipv4.ip_proto",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {
-                       BNXT_ULP_STINGRAY_SYM_IP_PROTO_TCP,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
+               .field_cond_opr = {
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+                       (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       ULP_SR_SYM_IP_PROTO_TCP},
+               .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr2 = {
+                       ULP_SR_SYM_IP_PROTO_UDP}
                }
        },
        {
        .field_info_mask = {
                .description = "o_ipv4.dst",
                .field_bit_size = 32,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
                },
        .field_info_spec = {
                .description = "o_ipv4.dst",
                .field_bit_size = 32,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "o_ipv4.src",
                .field_bit_size = 32,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
                },
        .field_info_spec = {
                .description = "o_ipv4.src",
                .field_bit_size = 32,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "o_eth.smac",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff,
+                       0xff,
+                       0xff,
+                       0xff,
+                       0xff,
+                       0xff}
                },
        .field_info_spec = {
                .description = "o_eth.smac",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_cntxt_id",
                .field_bit_size = 10,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff,
+                       0xff}
                },
        .field_info_spec = {
                .description = "l2_cntxt_id",
                .field_bit_size = 10,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+               .field_opr1 = {
                        (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
-                       BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "em_profile_id",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "em_profile_id",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+               .field_opr1 = {
                        (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
-                       BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
                }
        },
-       /* class_tid: 1, stingray, table: em.int_0 */
+       /* class_tid: 1, stingray, table: eem.ext_0 */
        {
        .field_info_mask = {
-               .description = "spare",
-               .field_bit_size = 3,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "spare",
-               .field_bit_size = 3,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "local_cos",
-               .field_bit_size = 3,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "local_cos",
-               .field_bit_size = 3,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "o_l4.dport",
-               .field_bit_size = 16,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               },
-       .field_info_spec = {
-               .description = "o_l4.dport",
-               .field_bit_size = 16,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "o_l4.sport",
-               .field_bit_size = 16,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               },
-       .field_info_spec = {
-               .description = "o_l4.sport",
-               .field_bit_size = 16,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "o_ipv4.ip_proto",
-               .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "o_ipv4.ip_proto",
-               .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {
-                       BNXT_ULP_STINGRAY_SYM_IP_PROTO_TCP,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "o_ipv4.dst",
-               .field_bit_size = 32,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               },
-       .field_info_spec = {
-               .description = "o_ipv4.dst",
-               .field_bit_size = 32,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "o_ipv4.src",
-               .field_bit_size = 32,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               },
-       .field_info_spec = {
-               .description = "o_ipv4.src",
-               .field_bit_size = 32,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "o_eth.smac",
-               .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "o_eth.smac",
-               .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "l2_cntxt_id",
-               .field_bit_size = 10,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "l2_cntxt_id",
-               .field_bit_size = 10,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-               .field_operand = {
-                       (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
-                       BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "em_profile_id",
-               .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "em_profile_id",
-               .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-               .field_operand = {
-                       (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
-                       BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       /* class_tid: 2, stingray, table: l2_cntxt_tcam.0 */
-       {
-       .field_info_mask = {
-               .description = "l2_ivlan_vid",
-               .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_OO_VLAN_VID >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_OO_VLAN_VID & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               },
-       .field_info_spec = {
-               .description = "l2_ivlan_vid",
-               .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_OO_VLAN_VID >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_OO_VLAN_VID & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "l2_ovlan_vid",
-               .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "l2_ovlan_vid",
-               .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "mac0_addr",
-               .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_ETH_DMAC >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_ETH_DMAC & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               },
-       .field_info_spec = {
-               .description = "mac0_addr",
-               .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_ETH_DMAC >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_ETH_DMAC & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "svif",
-               .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_SVIF_INDEX >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_SVIF_INDEX & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               },
-       .field_info_spec = {
-               .description = "svif",
-               .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_SVIF_INDEX >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_SVIF_INDEX & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "sparif",
-               .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "sparif",
-               .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tl2_ivlan_vid",
-               .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "tl2_ivlan_vid",
-               .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tl2_ovlan_vid",
-               .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "tl2_ovlan_vid",
-               .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "mac1_addr",
-               .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "mac1_addr",
-               .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "l2_num_vtags",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "l2_num_vtags",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tl2_num_vtags",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "tl2_num_vtags",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tun_hdr_type",
-               .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "tun_hdr_type",
-               .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "key_type",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "key_type",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "valid",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "valid",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       /* class_tid: 2, stingray, table: profile_tcam_cache.rd */
-       {
-       .field_info_mask = {
-               .description = "recycle_cnt",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "recycle_cnt",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "prof_func_id",
-               .field_bit_size = 7,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "prof_func_id",
-               .field_bit_size = 7,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,
-               .field_operand = {
-               (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
-                       BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "hdr_sig_id",
-               .field_bit_size = 5,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "hdr_sig_id",
-               .field_bit_size = 5,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       /* class_tid: 2, stingray, table: profile_tcam.0 */
-       {
-       .field_info_mask = {
-               .description = "l4_hdr_is_udp_tcp",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "l4_hdr_is_udp_tcp",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "l4_hdr_type",
-               .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "l4_hdr_type",
-               .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "l4_hdr_error",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "l4_hdr_error",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "l4_hdr_valid",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "l4_hdr_valid",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {
-                       BNXT_ULP_STINGRAY_SYM_L4_HDR_VALID_YES,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "l3_ipv6_cmp_dst",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "l3_ipv6_cmp_dst",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "l3_ipv6_cmp_src",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "l3_ipv6_cmp_src",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "l3_hdr_isIP",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "l3_hdr_isIP",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "l3_hdr_type",
-               .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "l3_hdr_type",
-               .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "l3_hdr_error",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "l3_hdr_error",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "l3_hdr_valid",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "l3_hdr_valid",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {
-                       BNXT_ULP_STINGRAY_SYM_L3_HDR_VALID_YES,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "l2_two_vtags",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "l2_two_vtags",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "l2_vtag_present",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "l2_vtag_present",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "l2_uc_mc_bc",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "l2_uc_mc_bc",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "l2_hdr_type",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "l2_hdr_type",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "l2_hdr_error",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "l2_hdr_error",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "l2_hdr_valid",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "l2_hdr_valid",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {
-                       BNXT_ULP_STINGRAY_SYM_L2_HDR_VALID_YES,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tun_hdr_flags",
-               .field_bit_size = 3,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "tun_hdr_flags",
-               .field_bit_size = 3,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tun_hdr_type",
-               .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "tun_hdr_type",
-               .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tun_hdr_err",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "tun_hdr_err",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tun_hdr_valid",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "tun_hdr_valid",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tl4_hdr_is_udp_tcp",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "tl4_hdr_is_udp_tcp",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tl4_hdr_type",
-               .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "tl4_hdr_type",
-               .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tl4_hdr_error",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "tl4_hdr_error",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tl4_hdr_valid",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "tl4_hdr_valid",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tl3_ipv6_cmp_dst",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "tl3_ipv6_cmp_dst",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tl3_ipv6_cmp_src",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "tl3_ipv6_cmp_src",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tl3_hdr_isIP",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "tl3_hdr_isIP",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tl3_hdr_type",
-               .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "tl3_hdr_type",
-               .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tl3_hdr_error",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "tl3_hdr_error",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tl3_hdr_valid",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "tl3_hdr_valid",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tl2_two_vtags",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "tl2_two_vtags",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tl2_vtag_present",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "tl2_vtag_present",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tl2_uc_mc_bc",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "tl2_uc_mc_bc",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tl2_hdr_type",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "tl2_hdr_type",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tl2_hdr_valid",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "tl2_hdr_valid",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "hrec_next",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "hrec_next",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "reserved",
-               .field_bit_size = 9,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "reserved",
-               .field_bit_size = 9,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "prof_func_id",
-               .field_bit_size = 7,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "prof_func_id",
-               .field_bit_size = 7,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,
-               .field_operand = {
-               (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
-                       BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "agg_error",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "agg_error",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "recycle_cnt",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "recycle_cnt",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "pkt_type_0",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "pkt_type_0",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "pkt_type_1",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "pkt_type_1",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "valid",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "valid",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       /* class_tid: 2, stingray, table: profile_tcam_cache.wr */
-       {
-       .field_info_mask = {
-               .description = "recycle_cnt",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "recycle_cnt",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "prof_func_id",
-               .field_bit_size = 7,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "prof_func_id",
-               .field_bit_size = 7,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,
-               .field_operand = {
-               (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
-                       BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "hdr_sig_id",
-               .field_bit_size = 5,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "hdr_sig_id",
-               .field_bit_size = 5,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       /* class_tid: 2, stingray, table: eem.ext_0 */
-       {
-       .field_info_mask = {
-               .description = "spare",
-               .field_bit_size = 275,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
                .description = "spare",
                .field_bit_size = 275,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "local_cos",
-               .field_bit_size = 3,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "local_cos",
-               .field_bit_size = 3,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "o_l4.dport",
-               .field_bit_size = 16,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               },
-       .field_info_spec = {
-               .description = "o_l4.dport",
-               .field_bit_size = 16,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "o_l4.sport",
-               .field_bit_size = 16,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               },
-       .field_info_spec = {
-               .description = "o_l4.sport",
-               .field_bit_size = 16,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "o_ipv4.ip_proto",
-               .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "o_ipv4.ip_proto",
-               .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {
-                       BNXT_ULP_STINGRAY_SYM_IP_PROTO_TCP,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "o_ipv4.dst",
-               .field_bit_size = 32,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               },
-       .field_info_spec = {
-               .description = "o_ipv4.dst",
-               .field_bit_size = 32,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "o_ipv4.src",
-               .field_bit_size = 32,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "o_ipv4.src",
-               .field_bit_size = 32,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "o_eth.smac",
-               .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "o_eth.smac",
-               .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "l2_cntxt_id",
-               .field_bit_size = 10,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "l2_cntxt_id",
-               .field_bit_size = 10,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-               .field_operand = {
-                       (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
-                       BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "em_profile_id",
-               .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "em_profile_id",
-               .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-               .field_operand = {
-                       (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
-                       BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       /* class_tid: 2, stingray, table: em.int_0 */
-       {
-       .field_info_mask = {
-               .description = "spare",
-               .field_bit_size = 3,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "spare",
-               .field_bit_size = 3,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_bit_size = 275,
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "local_cos",
                .field_bit_size = 3,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "local_cos",
                .field_bit_size = 3,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "o_l4.dport",
                .field_bit_size = 16,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff,
+                       0xff}
                },
        .field_info_spec = {
                .description = "o_l4.dport",
                .field_bit_size = 16,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
+               .field_cond_opr = {
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+                       (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+               .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},
+               .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr2 = {
+                       (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "o_l4.sport",
                .field_bit_size = 16,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff,
+                       0xff}
                },
        .field_info_spec = {
                .description = "o_l4.sport",
                .field_bit_size = 16,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
+               .field_cond_opr = {
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+                       (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+               .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},
+               .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr2 = {
+                       (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "o_ipv4.ip_proto",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "o_ipv4.ip_proto",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {
-                       BNXT_ULP_STINGRAY_SYM_IP_PROTO_TCP,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
+               .field_cond_opr = {
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+                       (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       ULP_SR_SYM_IP_PROTO_TCP},
+               .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr2 = {
+                       ULP_SR_SYM_IP_PROTO_UDP}
                }
        },
        {
        .field_info_mask = {
                .description = "o_ipv4.dst",
                .field_bit_size = 32,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
                },
        .field_info_spec = {
                .description = "o_ipv4.dst",
                .field_bit_size = 32,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "o_ipv4.src",
                .field_bit_size = 32,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
                },
        .field_info_spec = {
                .description = "o_ipv4.src",
                .field_bit_size = 32,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "o_eth.smac",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff,
+                       0xff,
+                       0xff,
+                       0xff,
+                       0xff,
+                       0xff}
                },
        .field_info_spec = {
                .description = "o_eth.smac",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_cntxt_id",
                .field_bit_size = 10,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff,
+                       0xff}
                },
        .field_info_spec = {
                .description = "l2_cntxt_id",
                .field_bit_size = 10,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+               .field_opr1 = {
                        (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
-                       BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "em_profile_id",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "em_profile_id",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+               .field_opr1 = {
                        (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
-                       BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
                }
        },
-       /* class_tid: 3, stingray, table: l2_cntxt_tcam.0 */
+       /* class_tid: 2, stingray, table: l2_cntxt_tcam.0 */
        {
        .field_info_mask = {
                .description = "l2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "mac0_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "mac0_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+               .field_opr1 = {
                        (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "sparif",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "sparif",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "mac1_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "mac1_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tun_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tun_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "key_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "key_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       1}
                }
        },
-       /* class_tid: 3, stingray, table: l2_cntxt_tcam_cache.wr */
+       /* class_tid: 2, stingray, table: l2_cntxt_tcam_cache.wr */
        {
        .field_info_mask = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+               .field_opr1 = {
                        (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
                }
        },
-       /* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.vfr_0 */
+       /* class_tid: 3, stingray, table: l2_cntxt_tcam_bypass.vfr_0 */
        {
        .field_info_mask = {
                .description = "l2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "mac0_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "mac0_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+               .field_opr1 = {
                        (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "sparif",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "sparif",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "mac1_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "mac1_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tun_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tun_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "key_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "key_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       1}
                }
        },
-       /* class_tid: 4, stingray, table: l2_cntxt_tcam_cache.rd */
+       /* class_tid: 3, stingray, table: l2_cntxt_tcam_cache.rd */
        {
        .field_info_mask = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+               .field_opr1 = {
                        (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
                }
        },
-       /* class_tid: 4, stingray, table: l2_cntxt_tcam.0 */
+       /* class_tid: 3, stingray, table: l2_cntxt_tcam.0 */
        {
        .field_info_mask = {
                .description = "l2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "mac0_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "mac0_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+               .field_opr1 = {
                        (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "sparif",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "sparif",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "mac1_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "mac1_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tun_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tun_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "key_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "key_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       1}
                }
        },
-       /* class_tid: 4, stingray, table: l2_cntxt_tcam_cache.wr */
+       /* class_tid: 3, stingray, table: l2_cntxt_tcam_cache.wr */
        {
        .field_info_mask = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+               .field_opr1 = {
                        (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
                }
        },
-       /* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.egr0 */
+       /* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.egr0 */
        {
        .field_info_mask = {
                .description = "l2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "mac0_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "mac0_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+               .field_opr1 = {
                        (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "sparif",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "sparif",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "mac1_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "mac1_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tun_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tun_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "key_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "key_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       1}
                }
        },
-       /* class_tid: 5, stingray, table: l2_cntxt_tcam_cache.wr_egr0 */
+       /* class_tid: 4, stingray, table: l2_cntxt_tcam_cache.wr_egr0 */
        {
        .field_info_mask = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+               .field_opr1 = {
                        (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
                }
        },
-       /* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.dtagged_ing0 */
+       /* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.dtagged_ing0 */
        {
        .field_info_mask = {
                .description = "l2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff,
+                       0xff}
                },
        .field_info_spec = {
                .description = "l2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+               .field_opr1 = {
                        (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "mac0_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "mac0_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+               .field_opr1 = {
                        (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "sparif",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "sparif",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "mac1_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "mac1_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "l2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       2}
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tun_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "tun_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {
-                       BNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_NONE,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       ULP_SR_SYM_TUN_HDR_TYPE_NONE}
                }
        },
        {
        .field_info_mask = {
                .description = "key_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "key_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       1}
                }
        },
-       /* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.stagged_ing0 */
+       /* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.stagged_ing0 */
        {
        .field_info_mask = {
                .description = "l2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff,
+                       0xff}
                },
        .field_info_spec = {
                .description = "l2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+               .field_opr1 = {
                        (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "l2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "mac0_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "mac0_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+               .field_opr1 = {
                        (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "sparif",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "sparif",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "mac1_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "mac1_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "l2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       1}
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tun_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "tun_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {
-                       BNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_NONE,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       ULP_SR_SYM_TUN_HDR_TYPE_NONE}
                }
        },
        {
        .field_info_mask = {
                .description = "key_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "key_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       1}
                }
        },
-       /* class_tid: 6, stingray, table: l2_cntxt_tcam.egr */
+       /* class_tid: 5, stingray, table: l2_cntxt_tcam.egr */
        {
        .field_info_mask = {
                .description = "l2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "mac0_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "mac0_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+               .field_opr1 = {
                        (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "sparif",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "sparif",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "mac1_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "mac1_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tun_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tun_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "key_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "key_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       1}
                }
        },
-       /* class_tid: 6, stingray, table: l2_cntxt_tcam_cache.egr_wr */
+       /* class_tid: 5, stingray, table: l2_cntxt_tcam_cache.egr_wr */
        {
        .field_info_mask = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+               .field_opr1 = {
                        (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
                }
        },
-       /* class_tid: 6, stingray, table: l2_cntxt_tcam_bypass.ing */
+       /* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.ing */
        {
        .field_info_mask = {
                .description = "l2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "mac0_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "mac0_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+               .field_opr1 = {
                        (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "sparif",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "sparif",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "mac1_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "mac1_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tun_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tun_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "key_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "key_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       1}
                }
        }
 };
@@ -5029,2372 +4122,2300 @@ struct bnxt_ulp_mapper_field_info ulp_stingray_class_result_field_list[] = {
        {
        .description = "l2_cntxt_id",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
        },
        {
        .description = "prof_func_id",
        .field_bit_size = 7,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+       .field_opr1 = {
                (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
-               BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}
        },
        {
        .description = "l2_byp_lkup_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "parif",
        .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+       .field_opr1 = {
                (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
-               BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
        },
        {
        .description = "allowed_pri",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "default_pri",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "allowed_tpid",
        .field_bit_size = 6,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "default_tpid",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "bd_act_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "sp_rec_ptr",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "byp_sp_lkup",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               1}
        },
        {
        .description = "pri_anti_spoof_ctl",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tpid_anti_spoof_ctl",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        /* class_tid: 1, stingray, table: profile_tcam.0 */
        {
        .description = "wc_key_id",
        .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               3}
        },
        {
        .description = "wc_profile_id",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "wc_search_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "em_key_mask",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {
-               (0x007d >> 8) & 0xff,
-               0x007d & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               (125 >> 8) & 0xff,
+               125 & 0xff}
        },
        {
        .description = "em_key_id",
        .field_bit_size = 5,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               3}
        },
        {
        .description = "em_profile_id",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
        },
        {
        .description = "em_search_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               1}
        },
        {
        .description = "pl_byp_lkup_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        /* class_tid: 1, stingray, table: profile_tcam_cache.wr */
        {
        .description = "rid",
        .field_bit_size = 32,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_RID & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_RID & 0xff}
        },
        {
        .description = "profile_tcam_index",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
        },
        {
        .description = "em_profile_id",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
        },
        {
        .description = "wm_profile_id",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "flow_sig_id",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+       .field_opr1 = {
                (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
-               BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       /* class_tid: 1, stingray, table: eem.ext_0 */
-       {
-       .description = "act_rec_ptr",
-       .field_bit_size = 33,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
-               (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       {
-       .description = "ext_flow_cntr",
-       .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {
-               BNXT_ULP_STINGRAY_SYM_EEM_EXT_FLOW_CNTR,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       {
-       .description = "act_rec_int",
-       .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-       },
-       {
-       .description = "act_rec_size",
-       .field_bit_size = 5,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
-               (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       {
-       .description = "key_size",
-       .field_bit_size = 9,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {
-               (0x00ad >> 8) & 0xff,
-               0x00ad & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       {
-       .description = "reserved",
-       .field_bit_size = 11,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-       },
-       {
-       .description = "strength",
-       .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       {
-       .description = "l1_cacheable",
-       .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-       },
-       {
-       .description = "valid",
-       .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
        },
        /* class_tid: 1, stingray, table: em.int_0 */
        {
        .description = "act_rec_ptr",
        .field_bit_size = 33,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
        },
        {
        .description = "ext_flow_cntr",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "act_rec_int",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "act_rec_size",
        .field_bit_size = 5,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "key_size",
        .field_bit_size = 9,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "reserved",
        .field_bit_size = 11,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "strength",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               3}
        },
        {
        .description = "l1_cacheable",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "valid",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       /* class_tid: 2, stingray, table: l2_cntxt_tcam.0 */
-       {
-       .description = "l2_cntxt_id",
-       .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
-               (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       {
-       .description = "prof_func_id",
-       .field_bit_size = 7,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,
-       .field_operand = {
-               (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
-               BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       {
-       .description = "l2_byp_lkup_en",
-       .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-       },
-       {
-       .description = "parif",
-       .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-       .field_operand = {
-               (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
-               BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       {
-       .description = "allowed_pri",
-       .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-       },
-       {
-       .description = "default_pri",
-       .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-       },
-       {
-       .description = "allowed_tpid",
-       .field_bit_size = 6,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-       },
-       {
-       .description = "default_tpid",
-       .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-       },
-       {
-       .description = "bd_act_en",
-       .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-       },
-       {
-       .description = "sp_rec_ptr",
-       .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-       },
-       {
-       .description = "byp_sp_lkup",
-       .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       {
-       .description = "pri_anti_spoof_ctl",
-       .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-       },
-       {
-       .description = "tpid_anti_spoof_ctl",
-       .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-       },
-       /* class_tid: 2, stingray, table: profile_tcam.0 */
-       {
-       .description = "wc_key_id",
-       .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       {
-       .description = "wc_profile_id",
-       .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-       },
-       {
-       .description = "wc_search_en",
-       .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-       },
-       {
-       .description = "em_key_mask",
-       .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {
-               (0x0079 >> 8) & 0xff,
-               0x0079 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       {
-       .description = "em_key_id",
-       .field_bit_size = 5,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       {
-       .description = "em_profile_id",
-       .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
-               (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       {
-       .description = "em_search_en",
-       .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       {
-       .description = "pl_byp_lkup_en",
-       .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-       },
-       /* class_tid: 2, stingray, table: profile_tcam_cache.wr */
-       {
-       .description = "rid",
-       .field_bit_size = 32,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
-               (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_RID & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       {
-       .description = "profile_tcam_index",
-       .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
-               (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       {
-       .description = "em_profile_id",
-       .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
-               (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       {
-       .description = "wm_profile_id",
-       .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-       },
-       {
-       .description = "flow_sig_id",
-       .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-       .field_operand = {
-               (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
-               BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               1}
        },
-       /* class_tid: 2, stingray, table: eem.ext_0 */
+       /* class_tid: 1, stingray, table: eem.ext_0 */
        {
        .description = "act_rec_ptr",
        .field_bit_size = 33,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
        },
        {
        .description = "ext_flow_cntr",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {
-               BNXT_ULP_STINGRAY_SYM_EEM_EXT_FLOW_CNTR,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               ULP_SR_SYM_EEM_EXT_FLOW_CNTR}
        },
        {
        .description = "act_rec_int",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "act_rec_size",
        .field_bit_size = 5,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       {
-       .description = "key_size",
-       .field_bit_size = 9,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {
-               (0x00ad >> 8) & 0xff,
-               0x00ad & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       {
-       .description = "reserved",
-       .field_bit_size = 11,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-       },
-       {
-       .description = "strength",
-       .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       {
-       .description = "l1_cacheable",
-       .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-       },
-       {
-       .description = "valid",
-       .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       /* class_tid: 2, stingray, table: em.int_0 */
-       {
-       .description = "act_rec_ptr",
-       .field_bit_size = 33,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
-               (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       {
-       .description = "ext_flow_cntr",
-       .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-       },
-       {
-       .description = "act_rec_int",
-       .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-       },
-       {
-       .description = "act_rec_size",
-       .field_bit_size = 5,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff}
        },
        {
        .description = "key_size",
        .field_bit_size = 9,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               (173 >> 8) & 0xff,
+               173 & 0xff}
        },
        {
        .description = "reserved",
        .field_bit_size = 11,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "strength",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               3}
        },
        {
        .description = "l1_cacheable",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "valid",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               1}
        },
-       /* class_tid: 3, stingray, table: int_full_act_record.0 */
+       /* class_tid: 2, stingray, table: int_full_act_record.0 */
        {
        .description = "flow_cntr_ptr",
        .field_bit_size = 14,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "age_enable",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "agg_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "rate_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "flow_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_key",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_mir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_match",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "encap_ptr",
        .field_bit_size = 11,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "dst_ip_ptr",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcp_dst_port",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "src_ip_ptr",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcp_src_port",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "meter_id",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "l3_rdir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tl3_rdir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "l3_ttl_dec",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tl3_ttl_dec",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "decap_func",
        .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "vnic_or_vport",
        .field_bit_size = 12,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+       .field_opr1 = {
                (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff,
-               BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff}
        },
        {
        .description = "pop_vlan",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "meter",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "mirror",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "drop",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "hit",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "type",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
-       /* class_tid: 3, stingray, table: l2_cntxt_tcam.0 */
+       /* class_tid: 2, stingray, table: l2_cntxt_tcam.0 */
        {
        .description = "l2_cntxt_id",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
        },
        {
        .description = "prof_func_id",
        .field_bit_size = 7,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+       .field_opr1 = {
                (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
-               BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
        },
        {
        .description = "l2_byp_lkup_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "parif",
        .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+       .field_opr1 = {
                (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
-               BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
        },
        {
        .description = "allowed_pri",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "default_pri",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "allowed_tpid",
        .field_bit_size = 6,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "default_tpid",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "bd_act_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "sp_rec_ptr",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "byp_sp_lkup",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               1}
        },
        {
        .description = "pri_anti_spoof_ctl",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tpid_anti_spoof_ctl",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
-       /* class_tid: 3, stingray, table: l2_cntxt_tcam_cache.wr */
+       /* class_tid: 2, stingray, table: l2_cntxt_tcam_cache.wr */
        {
        .description = "rid",
        .field_bit_size = 32,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_RID & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_RID & 0xff}
        },
        {
        .description = "l2_cntxt_tcam_index",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
        },
        {
        .description = "l2_cntxt_id",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
        },
        {
        .description = "src_property_ptr",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
-       /* class_tid: 3, stingray, table: parif_def_lkup_arec_ptr.0 */
+       /* class_tid: 2, stingray, table: parif_def_lkup_arec_ptr.0 */
        {
        .description = "act_rec_ptr",
        .field_bit_size = 32,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
        },
-       /* class_tid: 3, stingray, table: parif_def_arec_ptr.0 */
+       /* class_tid: 2, stingray, table: parif_def_arec_ptr.0 */
        {
        .description = "act_rec_ptr",
        .field_bit_size = 32,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
        },
-       /* class_tid: 3, stingray, table: parif_def_err_arec_ptr.0 */
+       /* class_tid: 2, stingray, table: parif_def_err_arec_ptr.0 */
        {
        .description = "act_rec_ptr",
        .field_bit_size = 32,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
        },
-       /* class_tid: 4, stingray, table: int_full_act_record.0 */
+       /* class_tid: 3, stingray, table: int_full_act_record.0 */
        {
        .description = "flow_cntr_ptr",
        .field_bit_size = 14,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "age_enable",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "agg_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "rate_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "flow_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_key",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_mir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_match",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "encap_ptr",
        .field_bit_size = 11,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "dst_ip_ptr",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcp_dst_port",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "src_ip_ptr",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcp_src_port",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "meter_id",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "l3_rdir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tl3_rdir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "l3_ttl_dec",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tl3_ttl_dec",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "decap_func",
        .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "vnic_or_vport",
        .field_bit_size = 12,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+       .field_opr1 = {
                (BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff,
-               BNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff}
        },
        {
        .description = "pop_vlan",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "meter",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "mirror",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "drop",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "hit",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "type",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
-       /* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.vfr_0 */
+       /* class_tid: 3, stingray, table: l2_cntxt_tcam_bypass.vfr_0 */
        {
        .description = "act_record_ptr",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "reserved",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "l2_byp_lkup_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "parif",
        .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+       .field_opr1 = {
                (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
-               BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
        },
        {
        .description = "allowed_pri",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "default_pri",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "allowed_tpid",
        .field_bit_size = 6,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "default_tpid",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "bd_act_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               1}
        },
        {
        .description = "sp_rec_ptr",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "byp_sp_lkup",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               1}
        },
        {
        .description = "pri_anti_spoof_ctl",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tpid_anti_spoof_ctl",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
-       /* class_tid: 4, stingray, table: l2_cntxt_tcam.0 */
+       /* class_tid: 3, stingray, table: l2_cntxt_tcam.0 */
        {
        .description = "l2_cntxt_id",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
        },
        {
        .description = "prof_func_id",
        .field_bit_size = 7,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+       .field_opr1 = {
                (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
-               BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
        },
        {
        .description = "l2_byp_lkup_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "parif",
        .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+       .field_opr1 = {
                (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
-               BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
        },
        {
        .description = "allowed_pri",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "default_pri",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "allowed_tpid",
        .field_bit_size = 6,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "default_tpid",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "bd_act_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "sp_rec_ptr",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "byp_sp_lkup",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               1}
        },
        {
        .description = "pri_anti_spoof_ctl",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tpid_anti_spoof_ctl",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
-       /* class_tid: 4, stingray, table: l2_cntxt_tcam_cache.wr */
+       /* class_tid: 3, stingray, table: l2_cntxt_tcam_cache.wr */
        {
        .description = "rid",
        .field_bit_size = 32,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_RID & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_RID & 0xff}
        },
        {
        .description = "l2_cntxt_tcam_index",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
        },
        {
        .description = "l2_cntxt_id",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
        },
        {
        .description = "src_property_ptr",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
-       /* class_tid: 4, stingray, table: parif_def_lkup_arec_ptr.0 */
+       /* class_tid: 3, stingray, table: parif_def_lkup_arec_ptr.0 */
        {
        .description = "act_rec_ptr",
        .field_bit_size = 32,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
        },
-       /* class_tid: 4, stingray, table: parif_def_arec_ptr.0 */
+       /* class_tid: 3, stingray, table: parif_def_arec_ptr.0 */
        {
        .description = "act_rec_ptr",
        .field_bit_size = 32,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
        },
-       /* class_tid: 4, stingray, table: parif_def_err_arec_ptr.0 */
+       /* class_tid: 3, stingray, table: parif_def_err_arec_ptr.0 */
        {
        .description = "act_rec_ptr",
        .field_bit_size = 32,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
        },
-       /* class_tid: 5, stingray, table: int_vtag_encap_record.egr0 */
+       /* class_tid: 4, stingray, table: int_vtag_encap_record.egr0 */
        {
        .description = "ecv_tun_type",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "ecv_l4_type",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "ecv_l3_type",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "ecv_l2_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "ecv_vtag_type",
        .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {
-               BNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               ULP_SR_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
        },
        {
        .description = "ecv_custom_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "ecv_valid",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               1}
        },
        {
        .description = "vtag_tpid",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x81, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               0x81,
+               0x00}
        },
        {
        .description = "vtag_vid",
        .field_bit_size = 12,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+       .field_opr1 = {
                (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
-               BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
        },
        {
        .description = "vtag_de",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "vtag_pcp",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "spare",
        .field_bit_size = 80,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
-       /* class_tid: 5, stingray, table: int_full_act_record.egr0 */
+       /* class_tid: 4, stingray, table: int_full_act_record.egr0 */
        {
        .description = "flow_cntr_ptr",
        .field_bit_size = 14,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "age_enable",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "agg_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "rate_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "flow_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_key",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_mir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_match",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "encap_ptr",
        .field_bit_size = 11,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}
        },
        {
        .description = "dst_ip_ptr",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcp_dst_port",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "src_ip_ptr",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcp_src_port",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "meter_id",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "l3_rdir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tl3_rdir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "l3_ttl_dec",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tl3_ttl_dec",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "decap_func",
        .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "vnic_or_vport",
        .field_bit_size = 12,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {
-               (BNXT_ULP_STINGRAY_SYM_LOOPBACK_PORT >> 8) & 0xff,
-               BNXT_ULP_STINGRAY_SYM_LOOPBACK_PORT & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               (ULP_SR_SYM_LOOPBACK_PORT >> 8) & 0xff,
+               ULP_SR_SYM_LOOPBACK_PORT & 0xff}
        },
        {
        .description = "pop_vlan",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "meter",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "mirror",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "drop",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "hit",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "type",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
-       /* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.egr0 */
+       /* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.egr0 */
        {
        .description = "act_record_ptr",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "reserved",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "l2_byp_lkup_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "parif",
        .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "allowed_pri",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "default_pri",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "allowed_tpid",
        .field_bit_size = 6,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "default_tpid",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "bd_act_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               1}
        },
        {
        .description = "sp_rec_ptr",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "byp_sp_lkup",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               1}
        },
        {
        .description = "pri_anti_spoof_ctl",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tpid_anti_spoof_ctl",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
-       /* class_tid: 5, stingray, table: l2_cntxt_tcam_cache.wr_egr0 */
+       /* class_tid: 4, stingray, table: l2_cntxt_tcam_cache.wr_egr0 */
        {
        .description = "rid",
        .field_bit_size = 32,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_RID & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_RID & 0xff}
        },
        {
        .description = "l2_cntxt_tcam_index",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
        },
        {
        .description = "l2_cntxt_id",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "src_property_ptr",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
-       /* class_tid: 5, stingray, table: int_full_act_record.ing0 */
+       /* class_tid: 4, stingray, table: int_full_act_record.ing0 */
        {
        .description = "flow_cntr_ptr",
        .field_bit_size = 14,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "age_enable",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "agg_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "rate_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "flow_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_key",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_mir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_match",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "encap_ptr",
        .field_bit_size = 11,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "dst_ip_ptr",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcp_dst_port",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "src_ip_ptr",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcp_src_port",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "meter_id",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "l3_rdir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tl3_rdir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "l3_ttl_dec",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tl3_ttl_dec",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "decap_func",
        .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "vnic_or_vport",
        .field_bit_size = 12,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+       .field_opr1 = {
                (BNXT_ULP_CF_IDX_VF_FUNC_VNIC >> 8) & 0xff,
-               BNXT_ULP_CF_IDX_VF_FUNC_VNIC & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_CF_IDX_VF_FUNC_VNIC & 0xff}
        },
        {
        .description = "pop_vlan",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               1}
        },
        {
        .description = "meter",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "mirror",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "drop",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "hit",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "type",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
-       /* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.dtagged_ing0 */
+       /* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.dtagged_ing0 */
        {
        .description = "act_record_ptr",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
        },
        {
        .description = "reserved",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "l2_byp_lkup_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "parif",
        .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "allowed_pri",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "default_pri",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "allowed_tpid",
        .field_bit_size = 6,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "default_tpid",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "bd_act_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "sp_rec_ptr",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "byp_sp_lkup",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               1}
        },
        {
        .description = "pri_anti_spoof_ctl",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tpid_anti_spoof_ctl",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
-       /* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.stagged_ing0 */
+       /* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.stagged_ing0 */
        {
        .description = "act_record_ptr",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
        },
        {
        .description = "reserved",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "l2_byp_lkup_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "parif",
        .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "allowed_pri",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "default_pri",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "allowed_tpid",
        .field_bit_size = 6,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "default_tpid",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "bd_act_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "sp_rec_ptr",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "byp_sp_lkup",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               1}
        },
        {
        .description = "pri_anti_spoof_ctl",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tpid_anti_spoof_ctl",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
-       /* class_tid: 6, stingray, table: l2_cntxt_tcam.egr */
+       /* class_tid: 5, stingray, table: l2_cntxt_tcam.egr */
        {
        .description = "l2_cntxt_id",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
        },
        {
        .description = "prof_func_id",
        .field_bit_size = 7,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+       .field_opr1 = {
                (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
-               BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
        },
        {
        .description = "l2_byp_lkup_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "parif",
        .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+       .field_opr1 = {
                (BNXT_ULP_CF_IDX_VF_FUNC_PARIF >> 8) & 0xff,
-               BNXT_ULP_CF_IDX_VF_FUNC_PARIF & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_CF_IDX_VF_FUNC_PARIF & 0xff}
        },
        {
        .description = "allowed_pri",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "default_pri",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "allowed_tpid",
        .field_bit_size = 6,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "default_tpid",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "bd_act_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "sp_rec_ptr",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "byp_sp_lkup",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               1}
        },
        {
        .description = "pri_anti_spoof_ctl",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tpid_anti_spoof_ctl",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
-       /* class_tid: 6, stingray, table: l2_cntxt_tcam_cache.egr_wr */
+       /* class_tid: 5, stingray, table: l2_cntxt_tcam_cache.egr_wr */
        {
        .description = "rid",
        .field_bit_size = 32,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_RID & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_RID & 0xff}
        },
        {
        .description = "l2_cntxt_tcam_index",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
        },
        {
        .description = "l2_cntxt_id",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
        },
        {
        .description = "src_property_ptr",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
-       /* class_tid: 6, stingray, table: parif_def_lkup_arec_ptr.egr */
+       /* class_tid: 5, stingray, table: parif_def_lkup_arec_ptr.egr */
        {
        .description = "act_rec_ptr",
        .field_bit_size = 32,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+       .field_opr1 = {
                (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
-               BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
        },
-       /* class_tid: 6, stingray, table: parif_def_arec_ptr.egr */
+       /* class_tid: 5, stingray, table: parif_def_arec_ptr.egr */
        {
        .description = "act_rec_ptr",
        .field_bit_size = 32,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+       .field_opr1 = {
                (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
-               BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
        },
-       /* class_tid: 6, stingray, table: parif_def_err_arec_ptr.egr */
+       /* class_tid: 5, stingray, table: parif_def_err_arec_ptr.egr */
        {
        .description = "act_rec_ptr",
        .field_bit_size = 32,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+       .field_opr1 = {
                (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
-               BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
        },
-       /* class_tid: 6, stingray, table: int_full_act_record.ing */
+       /* class_tid: 5, stingray, table: int_full_act_record.ing */
        {
        .description = "flow_cntr_ptr",
        .field_bit_size = 14,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "age_enable",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "agg_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "rate_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "flow_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_key",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_mir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_match",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "encap_ptr",
        .field_bit_size = 11,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "dst_ip_ptr",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcp_dst_port",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "src_ip_ptr",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcp_src_port",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "meter_id",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "l3_rdir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tl3_rdir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "l3_ttl_dec",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tl3_ttl_dec",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "decap_func",
        .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "vnic_or_vport",
        .field_bit_size = 12,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+       .field_opr1 = {
                (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff,
-               BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff}
        },
        {
        .description = "pop_vlan",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "meter",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "mirror",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "drop",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "hit",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "type",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
-       /* class_tid: 6, stingray, table: l2_cntxt_tcam_bypass.ing */
+       /* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.ing */
        {
        .description = "act_record_ptr",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
        },
        {
        .description = "reserved",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "l2_byp_lkup_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "parif",
        .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "allowed_pri",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "default_pri",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "allowed_tpid",
        .field_bit_size = 6,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "default_tpid",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "bd_act_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "sp_rec_ptr",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "byp_sp_lkup",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               1}
        },
        {
        .description = "pri_anti_spoof_ctl",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tpid_anti_spoof_ctl",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
-       /* class_tid: 7, stingray, table: int_full_act_record.0 */
+       /* class_tid: 6, stingray, table: int_full_act_record.0 */
        {
        .description = "flow_cntr_ptr",
        .field_bit_size = 14,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "age_enable",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "agg_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "rate_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "flow_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_key",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_mir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_match",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "encap_ptr",
        .field_bit_size = 11,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "dst_ip_ptr",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcp_dst_port",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "src_ip_ptr",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcp_src_port",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "meter_id",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "l3_rdir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tl3_rdir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "l3_ttl_dec",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tl3_ttl_dec",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "decap_func",
        .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "vnic_or_vport",
        .field_bit_size = 12,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {
-               (BNXT_ULP_STINGRAY_SYM_LOOPBACK_PORT >> 8) & 0xff,
-               BNXT_ULP_STINGRAY_SYM_LOOPBACK_PORT & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               (ULP_SR_SYM_LOOPBACK_PORT >> 8) & 0xff,
+               ULP_SR_SYM_LOOPBACK_PORT & 0xff}
        },
        {
        .description = "pop_vlan",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "meter",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "mirror",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "drop",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "hit",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "type",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        }
 };
 
 struct bnxt_ulp_mapper_ident_info ulp_stingray_class_ident_list[] = {
+       /* class_tid: 1, stingray, table: l2_cntxt_tcam_cache.rd */
+       {
+       .description = "l2_cntxt_id",
+       .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+       .ident_bit_size = 10,
+       .ident_bit_pos = 42
+       },
        /* class_tid: 1, stingray, table: l2_cntxt_tcam.0 */
        {
        .description = "l2_cntxt_id",
@@ -7406,12 +6427,6 @@ struct bnxt_ulp_mapper_ident_info ulp_stingray_class_ident_list[] = {
        },
        /* class_tid: 1, stingray, table: profile_tcam_cache.rd */
        {
-       .description = "flow_sig_id",
-       .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
-       .ident_bit_size = 8,
-       .ident_bit_pos = 58
-       },
-       {
        .description = "profile_tcam_index",
        .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
        .ident_bit_size = 10,
@@ -7423,44 +6438,13 @@ struct bnxt_ulp_mapper_ident_info ulp_stingray_class_ident_list[] = {
        .ident_bit_size = 8,
        .ident_bit_pos = 42
        },
-       /* class_tid: 1, stingray, table: profile_tcam.0 */
-       {
-       .description = "em_profile_id",
-       .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
-       .ident_type = TF_IDENT_TYPE_EM_PROF,
-       .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
-       .ident_bit_size = 8,
-       .ident_bit_pos = 28
-       },
-       /* class_tid: 2, stingray, table: l2_cntxt_tcam.0 */
-       {
-       .description = "l2_cntxt_id",
-       .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
-       .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
-       .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
-       .ident_bit_size = 10,
-       .ident_bit_pos = 0
-       },
-       /* class_tid: 2, stingray, table: profile_tcam_cache.rd */
-       {
-       .description = "profile_tcam_index",
-       .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
-       .ident_bit_size = 10,
-       .ident_bit_pos = 32
-       },
        {
        .description = "flow_sig_id",
        .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
        .ident_bit_size = 8,
        .ident_bit_pos = 58
        },
-       {
-       .description = "em_profile_id",
-       .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
-       .ident_bit_size = 8,
-       .ident_bit_pos = 42
-       },
-       /* class_tid: 2, stingray, table: profile_tcam.0 */
+       /* class_tid: 1, stingray, table: profile_tcam.0 */
        {
        .description = "em_profile_id",
        .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -7469,7 +6453,7 @@ struct bnxt_ulp_mapper_ident_info ulp_stingray_class_ident_list[] = {
        .ident_bit_size = 8,
        .ident_bit_pos = 28
        },
-       /* class_tid: 3, stingray, table: l2_cntxt_tcam.0 */
+       /* class_tid: 2, stingray, table: l2_cntxt_tcam.0 */
        {
        .description = "l2_cntxt_id",
        .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -7478,14 +6462,14 @@ struct bnxt_ulp_mapper_ident_info ulp_stingray_class_ident_list[] = {
        .ident_bit_size = 10,
        .ident_bit_pos = 0
        },
-       /* class_tid: 4, stingray, table: l2_cntxt_tcam_cache.rd */
+       /* class_tid: 3, stingray, table: l2_cntxt_tcam_cache.rd */
        {
        .description = "l2_cntxt_id",
        .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
        .ident_bit_size = 10,
        .ident_bit_pos = 42
        },
-       /* class_tid: 4, stingray, table: l2_cntxt_tcam.0 */
+       /* class_tid: 3, stingray, table: l2_cntxt_tcam.0 */
        {
        .description = "l2_cntxt_id",
        .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -7494,7 +6478,7 @@ struct bnxt_ulp_mapper_ident_info ulp_stingray_class_ident_list[] = {
        .ident_bit_size = 10,
        .ident_bit_pos = 0
        },
-       /* class_tid: 6, stingray, table: l2_cntxt_tcam.egr */
+       /* class_tid: 5, stingray, table: l2_cntxt_tcam.egr */
        {
        .description = "l2_cntxt_id",
        .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,

diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c
index 30a71de..ff003b2 100644 (file)
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c
@@ -3,7 +3,7 @@
  * All rights reserved.
  */
 
-/* date: Mon Nov 23 17:33:02 2020 */
+/* date: Tue Dec  1 10:17:11 2020 */
 
 #include "ulp_template_db_enum.h"
 #include "ulp_template_db_field.h"
@@ -209,11 +209,11 @@ uint32_t ulp_glb_template_tbl[] = {
 struct bnxt_ulp_shared_act_info ulp_shared_act_info[] = {
        [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MIRROR_TBL << 1 |
                BNXT_ULP_DIRECTION_INGRESS] = {
-       .act_bitmask             = BNXT_ULP_ACTION_BIT_SHARED_SAMPLE
+       .act_bitmask             = BNXT_ULP_ACT_BIT_SHARED_SAMPLE
        },
        [BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MIRROR_TBL << 1 |
                BNXT_ULP_DIRECTION_EGRESS] = {
-       .act_bitmask             = BNXT_ULP_ACTION_BIT_SHARED_SAMPLE
+       .act_bitmask             = BNXT_ULP_ACT_BIT_SHARED_SAMPLE
        }
 };
 
@@ -312,78 +312,176 @@ uint8_t ulp_glb_field_tbl[] = {
        [2050] = 2,
        [2052] = 3,
        [2054] = 4,
-       [2056] = 5,
-       [2058] = 6,
-       [2060] = 7,
-       [2062] = 8,
-       [2064] = 9,
-       [2066] = 10,
-       [2068] = 11,
-       [2070] = 12,
-       [2072] = 13,
-       [2074] = 14,
-       [2102] = 15,
-       [2104] = 16,
-       [2106] = 17,
-       [2108] = 18,
-       [2110] = 19,
-       [2112] = 20,
-       [2114] = 21,
-       [2116] = 22,
-       [2118] = 23,
+       [2076] = 5,
+       [2078] = 6,
+       [2080] = 7,
+       [2082] = 8,
+       [2084] = 9,
+       [2086] = 10,
+       [2088] = 11,
+       [2090] = 12,
+       [2102] = 13,
+       [2104] = 14,
+       [2106] = 15,
+       [2108] = 16,
+       [2110] = 17,
+       [2112] = 18,
+       [2114] = 19,
+       [2116] = 20,
+       [2118] = 21,
        [2176] = 0,
        [2177] = 1,
        [2178] = 2,
        [2180] = 3,
        [2182] = 4,
-       [2184] = 8,
-       [2186] = 9,
-       [2188] = 10,
-       [2190] = 11,
-       [2192] = 12,
-       [2194] = 13,
-       [2196] = 14,
-       [2198] = 15,
-       [2200] = 16,
-       [2202] = 17,
-       [2230] = 18,
-       [2232] = 19,
-       [2234] = 20,
-       [2236] = 21,
-       [2238] = 22,
-       [2240] = 23,
-       [2242] = 24,
-       [2244] = 25,
-       [2246] = 26,
+       [2204] = 8,
+       [2206] = 9,
+       [2208] = 10,
+       [2210] = 11,
+       [2212] = 12,
+       [2214] = 13,
+       [2216] = 14,
+       [2218] = 15,
+       [2230] = 16,
+       [2232] = 17,
+       [2234] = 18,
+       [2236] = 19,
+       [2238] = 20,
+       [2240] = 21,
+       [2242] = 22,
+       [2244] = 23,
+       [2246] = 24,
        [2256] = 5,
        [2260] = 6,
        [2264] = 7,
-       [4352] = 0,
-       [4353] = 1,
-       [4354] = 2,
-       [4356] = 3,
-       [4358] = 4,
-       [4360] = 8,
-       [4362] = 9,
-       [4364] = 10,
-       [4366] = 11,
-       [4368] = 12,
-       [4370] = 13,
-       [4372] = 14,
-       [4374] = 15,
-       [4376] = 16,
-       [4378] = 17,
-       [4406] = 18,
-       [4408] = 19,
-       [4410] = 20,
-       [4412] = 21,
-       [4414] = 22,
-       [4416] = 23,
-       [4418] = 24,
-       [4420] = 25,
-       [4422] = 26,
-       [4432] = 5,
-       [4436] = 6,
-       [4440] = 7
+       [2304] = 0,
+       [2305] = 1,
+       [2306] = 2,
+       [2308] = 3,
+       [2310] = 4,
+       [2312] = 5,
+       [2314] = 6,
+       [2316] = 7,
+       [2318] = 8,
+       [2320] = 9,
+       [2322] = 10,
+       [2324] = 11,
+       [2326] = 12,
+       [2328] = 13,
+       [2330] = 14,
+       [2358] = 15,
+       [2360] = 16,
+       [2362] = 17,
+       [2364] = 18,
+       [2366] = 19,
+       [2368] = 20,
+       [2370] = 21,
+       [2372] = 22,
+       [2374] = 23,
+       [2432] = 0,
+       [2433] = 1,
+       [2434] = 2,
+       [2436] = 3,
+       [2438] = 4,
+       [2460] = 5,
+       [2462] = 6,
+       [2464] = 7,
+       [2466] = 8,
+       [2468] = 9,
+       [2470] = 10,
+       [2472] = 11,
+       [2474] = 12,
+       [2504] = 13,
+       [2506] = 14,
+       [2508] = 15,
+       [2510] = 16,
+       [2560] = 0,
+       [2561] = 1,
+       [2562] = 2,
+       [2564] = 3,
+       [2566] = 4,
+       [2568] = 8,
+       [2570] = 9,
+       [2572] = 10,
+       [2574] = 11,
+       [2576] = 12,
+       [2578] = 13,
+       [2580] = 14,
+       [2582] = 15,
+       [2584] = 16,
+       [2586] = 17,
+       [2614] = 18,
+       [2616] = 19,
+       [2618] = 20,
+       [2620] = 21,
+       [2622] = 22,
+       [2624] = 23,
+       [2626] = 24,
+       [2628] = 25,
+       [2630] = 26,
+       [2640] = 5,
+       [2644] = 6,
+       [2648] = 7,
+       [2688] = 0,
+       [2689] = 1,
+       [2690] = 2,
+       [2692] = 3,
+       [2694] = 4,
+       [2716] = 8,
+       [2718] = 9,
+       [2720] = 10,
+       [2722] = 11,
+       [2724] = 12,
+       [2726] = 13,
+       [2728] = 14,
+       [2730] = 15,
+       [2760] = 16,
+       [2762] = 17,
+       [2764] = 18,
+       [2766] = 19,
+       [2768] = 5,
+       [2772] = 6,
+       [2776] = 7,
+       [2816] = 0,
+       [2817] = 1,
+       [2818] = 2,
+       [2820] = 3,
+       [2822] = 4,
+       [2824] = 5,
+       [2826] = 6,
+       [2828] = 7,
+       [2830] = 8,
+       [2832] = 9,
+       [2834] = 10,
+       [2836] = 11,
+       [2838] = 12,
+       [2840] = 13,
+       [2842] = 14,
+       [2888] = 15,
+       [2890] = 16,
+       [2892] = 17,
+       [2894] = 18,
+       [2944] = 0,
+       [2945] = 1,
+       [2946] = 2,
+       [2948] = 3,
+       [2950] = 4,
+       [2952] = 8,
+       [2954] = 9,
+       [2956] = 10,
+       [2958] = 11,
+       [2960] = 12,
+       [2962] = 13,
+       [2964] = 14,
+       [2966] = 15,
+       [2968] = 16,
+       [2970] = 17,
+       [3016] = 18,
+       [3018] = 19,
+       [3020] = 20,
+       [3022] = 21,
+       [3024] = 5,
+       [3028] = 6,
+       [3032] = 7
 };
 

diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c
index 32f36d1..56ebee9 100644 (file)
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c
@@ -3,7 +3,7 @@
  * All rights reserved.
  */
 
-/* date: Wed Nov 18 12:19:40 2020 */
+/* date: Tue Dec  1 17:07:12 2020 */
 
 #include "ulp_template_db_enum.h"
 #include "ulp_template_db_field.h"
@@ -32,6 +32,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
                BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
        .direction = TF_DIR_RX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
                .cond_start_idx = 0,
                .cond_nums = 1 },
@@ -53,6 +54,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
        .direction = TF_DIR_RX,
        .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
                .cond_start_idx = 1,
                .cond_nums = 1 },
@@ -74,6 +76,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
        .direction = TF_DIR_RX,
        .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 2,
                .cond_nums = 0 },
@@ -95,6 +98,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
        .direction = TF_DIR_RX,
        .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT,
        .execute_info = {
+               .cond_goto = 0,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 2,
                .cond_nums = 0 },
@@ -112,12 +116,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
 
 struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = {
        {
-       .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET,
-       .cond_operand = BNXT_ULP_ACTION_BIT_COUNT
+       .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+       .cond_operand = BNXT_ULP_ACT_BIT_COUNT
        },
        {
-       .cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET,
-       .cond_operand = BNXT_ULP_ACTION_BIT_PUSH_VLAN
+       .cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
+       .cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN
        }
 };
 
@@ -126,557 +130,578 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {
        {
        .description = "count",
        .field_bit_size = 64,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        /* act_tid: 1, wh_plus, table: int_vtag_encap_record.0 */
        {
        .description = "ecv_tun_type",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "ecv_l4_type",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "ecv_l3_type",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "ecv_l2_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "ecv_vtag_type",
        .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {
-               BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
        },
        {
        .description = "ecv_custom_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "ecv_valid",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "vtag_tpid",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+       .field_opr1 = {
                (BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff,
-               BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff}
        },
        {
        .description = "vtag_vid",
        .field_bit_size = 12,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+       .field_opr1 = {
                (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
-               BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
        },
        {
        .description = "vtag_de",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "vtag_pcp",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+       .field_opr1 = {
                (BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
-               BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
        },
        {
        .description = "spare",
        .field_bit_size = 80,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        /* act_tid: 1, wh_plus, table: int_full_act_record.0 */
        {
        .description = "flow_cntr_ptr",
        .field_bit_size = 14,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
        },
        {
        .description = "age_enable",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "agg_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "rate_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "flow_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT,
-       .field_operand = {
-               ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 32) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 24) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 16) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 8) & 0xff,
-               (uint64_t)BNXT_ULP_ACTION_BIT_COUNT & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+       .field_opr1 = {
+               ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,
+               (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}
        },
        {
        .description = "tcpflags_key",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_mir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_match",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "encap_ptr",
        .field_bit_size = 11,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}
        },
        {
        .description = "dst_ip_ptr",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff}
        },
        {
        .description = "tcp_dst_port",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST,
-       .field_operand = {
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 56) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 48) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 40) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 32) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 24) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 16) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 8) & 0xff,
-               (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
-       .field_operand_true = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,
+       .field_cond_opr = {
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+               (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+       .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+       .field_opr1 = {
                (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,
-               BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},
+       .field_src2 = BNXT_ULP_FIELD_SRC_CONST
        },
        {
        .description = "src_ip_ptr",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff}
        },
        {
        .description = "tcp_src_port",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST,
-       .field_operand = {
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 56) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 48) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 40) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 32) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 24) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 16) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 8) & 0xff,
-               (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
-       .field_operand_true = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,
+       .field_cond_opr = {
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+               (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+       .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+       .field_opr1 = {
                (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,
-               BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},
+       .field_src2 = BNXT_ULP_FIELD_SRC_CONST
        },
        {
        .description = "meter_id",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "l3_rdir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tl3_rdir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "l3_ttl_dec",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+       .field_opr1 = {
                (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
-               BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
        },
        {
        .description = "tl3_ttl_dec",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+       .field_opr1 = {
                (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
-               BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
        },
        {
        .description = "decap_func",
        .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST,
-       .field_operand = {
-               ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 56) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 48) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 40) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 32) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 24) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 16) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 8) & 0xff,
-               (uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
-       .field_operand_true = {0x0a, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,
+       .field_cond_opr = {
+               ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff,
+               (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff},
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               ULP_WP_SYM_DECAP_FUNC_THRU_TUN},
+       .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr2 = {
+               ULP_WP_SYM_DECAP_FUNC_NONE}
        },
        {
        .description = "vnic_or_vport",
        .field_bit_size = 12,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+       .field_opr1 = {
                (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
-               BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
        },
        {
        .description = "pop_vlan",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT,
-       .field_operand = {
-               ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 56) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 48) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 40) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 32) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 24) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 16) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 8) & 0xff,
-               (uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+       .field_opr1 = {
+               ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff,
+               (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff}
        },
        {
        .description = "meter",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "mirror",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "drop",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT,
-       .field_operand = {
-               ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 56) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 48) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 40) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 32) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 24) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 16) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 8) & 0xff,
-               (uint64_t)BNXT_ULP_ACTION_BIT_DROP & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+       .field_opr1 = {
+               ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
+               (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
        },
        {
        .description = "hit",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "type",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        /* act_tid: 1, wh_plus, table: ext_full_act_record.0 */
        {
        .description = "flow_cntr_ptr",
        .field_bit_size = 14,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
        },
        {
        .description = "age_enable",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "agg_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "rate_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "flow_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT,
-       .field_operand = {
-               ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 32) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 24) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 16) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 8) & 0xff,
-               (uint64_t)BNXT_ULP_ACTION_BIT_COUNT & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+       .field_opr1 = {
+               ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,
+               (uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}
        },
        {
        .description = "flow_cntr_ext",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_key",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_mir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_match",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "encap_ptr",
        .field_bit_size = 11,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "encap_rec_int",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "dst_ip_ptr",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff}
        },
        {
        .description = "tcp_dst_port",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST,
-       .field_operand = {
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 56) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 48) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 40) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 32) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 24) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 16) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 8) & 0xff,
-               (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
-       .field_operand_true = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,
+       .field_cond_opr = {
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
+               (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
+       .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+       .field_opr1 = {
                (BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,
-               BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},
+       .field_src2 = BNXT_ULP_FIELD_SRC_CONST
        },
        {
        .description = "src_ip_ptr",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff}
        },
        {
        .description = "tcp_src_port",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST,
-       .field_operand = {
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 56) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 48) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 40) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 32) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 24) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 16) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 8) & 0xff,
-               (uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
-       .field_operand_true = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,
+       .field_cond_opr = {
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
+               (uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
+       .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+       .field_opr1 = {
                (BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,
-               BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},
+       .field_src2 = BNXT_ULP_FIELD_SRC_CONST
        },
        {
        .description = "meter_id",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "l3_rdir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tl3_rdir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "l3_ttl_dec",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+       .field_opr1 = {
                (BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
-               BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
        },
        {
        .description = "tl3_ttl_dec",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+       .field_opr1 = {
                (BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
-               BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
        },
        {
        .description = "decap_func",
        .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST,
-       .field_operand = {
-               ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 56) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 48) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 40) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 32) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 24) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 16) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 8) & 0xff,
-               (uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
-       .field_operand_true = {0x0a, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,
+       .field_cond_opr = {
+               ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff,
+               (uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff},
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               ULP_WP_SYM_DECAP_FUNC_THRU_TUN},
+       .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr2 = {
+               ULP_WP_SYM_DECAP_FUNC_NONE}
        },
        {
        .description = "vnic_or_vport",
        .field_bit_size = 12,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
+       .field_opr1 = {
                (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
-               BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
        },
        {
        .description = "pop_vlan",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT,
-       .field_operand = {
-               ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 56) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 48) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 40) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 32) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 24) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 16) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 8) & 0xff,
-               (uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+       .field_opr1 = {
+               ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff,
+               (uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff}
        },
        {
        .description = "meter",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "mirror",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "drop",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT,
-       .field_operand = {
-               ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 56) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 48) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 40) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 32) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 24) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 16) & 0xff,
-               ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 8) & 0xff,
-               (uint64_t)BNXT_ULP_ACTION_BIT_DROP & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
+       .field_opr1 = {
+               ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
+               ((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
+               (uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
        }
 };

diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c
index e870628..bf5cd64 100644 (file)
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c
@@ -3,7 +3,7 @@
  * All rights reserved.
  */
 
-/* date: Mon Nov 23 17:33:02 2020 */
+/* date: Wed Dec  2 12:05:11 2020 */
 
 #include "ulp_template_db_enum.h"
 #include "ulp_template_db_field.h"
@@ -15,7 +15,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = {
        /* class_tid: 1, wh_plus, ingress */
        [1] = {
        .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
-       .num_tbls = 6,
+       .num_tbls = 9,
        .start_tbl_idx = 0,
        .reject_info = {
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
@@ -26,17 +26,17 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = {
        [2] = {
        .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
        .num_tbls = 6,
-       .start_tbl_idx = 6,
+       .start_tbl_idx = 9,
        .reject_info = {
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
-               .cond_start_idx = 2,
+               .cond_start_idx = 4,
                .cond_nums = 0 }
        },
-       /* class_tid: 3, wh_plus, ingress */
+       /* class_tid: 3, wh_plus, egress */
        [3] = {
        .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
-       .num_tbls = 6,
-       .start_tbl_idx = 12,
+       .num_tbls = 8,
+       .start_tbl_idx = 15,
        .reject_info = {
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
                .cond_start_idx = 4,
@@ -45,18 +45,18 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = {
        /* class_tid: 4, wh_plus, egress */
        [4] = {
        .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
-       .num_tbls = 8,
-       .start_tbl_idx = 18,
+       .num_tbls = 7,
+       .start_tbl_idx = 23,
        .reject_info = {
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
-               .cond_start_idx = 4,
+               .cond_start_idx = 10,
                .cond_nums = 0 }
        },
        /* class_tid: 5, wh_plus, egress */
        [5] = {
        .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
        .num_tbls = 7,
-       .start_tbl_idx = 26,
+       .start_tbl_idx = 30,
        .reject_info = {
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
                .cond_start_idx = 10,
@@ -65,18 +65,8 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = {
        /* class_tid: 6, wh_plus, egress */
        [6] = {
        .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
-       .num_tbls = 7,
-       .start_tbl_idx = 33,
-       .reject_info = {
-               .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
-               .cond_start_idx = 10,
-               .cond_nums = 0 }
-       },
-       /* class_tid: 7, wh_plus, egress */
-       [7] = {
-       .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
        .num_tbls = 1,
-       .start_tbl_idx = 40,
+       .start_tbl_idx = 37,
        .reject_info = {
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
                .cond_start_idx = 10,
@@ -85,13 +75,35 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = {
 };
 
 struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
+       { /* class_tid: 1, wh_plus, table: l2_cntxt_tcam_cache.rd */
+       .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
+       .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+       .resource_sub_type =
+               BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
+       .direction = TF_DIR_RX,
+       .execute_info = {
+               .cond_goto = 2,
+               .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+               .cond_start_idx = 0,
+               .cond_nums = 1 },
+       .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
+       .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+       .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
+       .key_start_idx = 0,
+       .blob_key_bit_size = 8,
+       .key_bit_size = 8,
+       .key_num_fields = 1,
+       .ident_start_idx = 0,
+       .ident_nums = 1
+       },
        { /* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
        .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
        .direction = TF_DIR_RX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
-               .cond_start_idx = 0,
+               .cond_start_idx = 1,
                .cond_nums = 0 },
        .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE,
        .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
@@ -99,7 +111,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
        .pri_opcode  = BNXT_ULP_PRI_OPC_CONST,
        .pri_operand = 0,
-       .key_start_idx = 0,
+       .key_start_idx = 1,
        .blob_key_bit_size = 167,
        .key_bit_size = 167,
        .key_num_fields = 13,
@@ -107,7 +119,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
        .result_bit_size = 64,
        .result_num_fields = 13,
        .encap_num_fields = 0,
-       .ident_start_idx = 0,
+       .ident_start_idx = 1,
        .ident_nums = 1
        },
        { /* class_tid: 1, wh_plus, table: profile_tcam_cache.rd */
@@ -117,27 +129,40 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
                BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
        .direction = TF_DIR_RX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
-               .cond_start_idx = 0,
+               .cond_start_idx = 1,
                .cond_nums = 0 },
        .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_FLOW_SIG_ID_MATCH,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-       .key_start_idx = 13,
+       .key_start_idx = 14,
        .blob_key_bit_size = 14,
        .key_bit_size = 14,
        .key_num_fields = 3,
-       .ident_start_idx = 1,
+       .ident_start_idx = 2,
        .ident_nums = 3
        },
+       { /* class_tid: 1, wh_plus, table: branch.0 */
+       .resource_func = BNXT_ULP_RESOURCE_FUNC_BRANCH_TABLE,
+       .direction = TF_DIR_RX,
+       .execute_info = {
+               .cond_goto = 3,
+               .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+               .cond_start_idx = 1,
+               .cond_nums = 1 },
+       .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
+       .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH
+       },
        { /* class_tid: 1, wh_plus, table: profile_tcam.0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
        .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
        .direction = TF_DIR_RX,
        .execute_info = {
-               .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
-               .cond_start_idx = 0,
-               .cond_nums = 1 },
+               .cond_goto = 1,
+               .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+               .cond_start_idx = 2,
+               .cond_nums = 0 },
        .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
        .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
@@ -145,7 +170,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
        .fdb_operand = BNXT_ULP_RF_IDX_RID,
        .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
        .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
-       .key_start_idx = 16,
+       .key_start_idx = 17,
        .blob_key_bit_size = 81,
        .key_bit_size = 81,
        .key_num_fields = 43,
@@ -153,7 +178,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
        .result_bit_size = 38,
        .result_num_fields = 8,
        .encap_num_fields = 0,
-       .ident_start_idx = 4,
+       .ident_start_idx = 5,
        .ident_nums = 1
        },
        { /* class_tid: 1, wh_plus, table: profile_tcam_cache.wr */
@@ -163,13 +188,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
                BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
        .direction = TF_DIR_RX,
        .execute_info = {
-               .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
-               .cond_start_idx = 1,
-               .cond_nums = 1 },
+               .cond_goto = 1,
+               .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+               .cond_start_idx = 2,
+               .cond_nums = 0 },
        .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-       .key_start_idx = 59,
+       .key_start_idx = 60,
        .blob_key_bit_size = 14,
        .key_bit_size = 14,
        .key_num_fields = 3,
@@ -178,194 +204,71 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
        .result_num_fields = 5,
        .encap_num_fields = 0
        },
-       { /* class_tid: 1, wh_plus, table: eem.ext_0 */
-       .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE,
-       .resource_type = TF_MEM_EXTERNAL,
-       .direction = TF_DIR_RX,
-       .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT,
-       .execute_info = {
-               .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
-               .cond_start_idx = 2,
-               .cond_nums = 0 },
-       .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-       .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-       .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
-       .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
-       .key_start_idx = 62,
-       .blob_key_bit_size = 448,
-       .key_bit_size = 448,
-       .key_num_fields = 10,
-       .result_start_idx = 26,
-       .result_bit_size = 64,
-       .result_num_fields = 9,
-       .encap_num_fields = 0
-       },
        { /* class_tid: 1, wh_plus, table: em.int_0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
        .resource_type = TF_MEM_INTERNAL,
        .direction = TF_DIR_RX,
        .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,
        .execute_info = {
-               .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
+               .cond_goto = 1,
+               .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
                .cond_start_idx = 2,
-               .cond_nums = 0 },
+               .cond_nums = 1 },
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
        .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
        .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
-       .key_start_idx = 72,
+       .key_start_idx = 63,
        .blob_key_bit_size = 176,
        .key_bit_size = 176,
        .key_num_fields = 10,
-       .result_start_idx = 35,
+       .result_start_idx = 26,
        .result_bit_size = 64,
        .result_num_fields = 9,
        .encap_num_fields = 0
        },
-       { /* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */
-       .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
-       .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
-       .direction = TF_DIR_RX,
-       .execute_info = {
-               .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
-               .cond_start_idx = 2,
-               .cond_nums = 0 },
-       .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE,
-       .tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,
-       .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-       .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-       .pri_opcode  = BNXT_ULP_PRI_OPC_CONST,
-       .pri_operand = 0,
-       .key_start_idx = 82,
-       .blob_key_bit_size = 167,
-       .key_bit_size = 167,
-       .key_num_fields = 13,
-       .result_start_idx = 44,
-       .result_bit_size = 64,
-       .result_num_fields = 13,
-       .encap_num_fields = 0,
-       .ident_start_idx = 5,
-       .ident_nums = 1
-       },
-       { /* class_tid: 2, wh_plus, table: profile_tcam_cache.rd */
-       .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
-       .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
-       .resource_sub_type =
-               BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
-       .direction = TF_DIR_RX,
-       .execute_info = {
-               .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
-               .cond_start_idx = 2,
-               .cond_nums = 0 },
-       .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
-       .accept_opcode = BNXT_ULP_ACCEPT_OPC_FLOW_SIG_ID_MATCH,
-       .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-       .key_start_idx = 95,
-       .blob_key_bit_size = 14,
-       .key_bit_size = 14,
-       .key_num_fields = 3,
-       .ident_start_idx = 6,
-       .ident_nums = 3
-       },
-       { /* class_tid: 2, wh_plus, table: profile_tcam.0 */
-       .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
-       .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
-       .direction = TF_DIR_RX,
-       .execute_info = {
-               .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
-               .cond_start_idx = 2,
-               .cond_nums = 1 },
-       .tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,
-       .tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
-       .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-       .fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE,
-       .fdb_operand = BNXT_ULP_RF_IDX_RID,
-       .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
-       .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
-       .key_start_idx = 98,
-       .blob_key_bit_size = 81,
-       .key_bit_size = 81,
-       .key_num_fields = 43,
-       .result_start_idx = 57,
-       .result_bit_size = 38,
-       .result_num_fields = 8,
-       .encap_num_fields = 0,
-       .ident_start_idx = 9,
-       .ident_nums = 1
-       },
-       { /* class_tid: 2, wh_plus, table: profile_tcam_cache.wr */
-       .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
-       .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
-       .resource_sub_type =
-               BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,
-       .direction = TF_DIR_RX,
-       .execute_info = {
-               .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
-               .cond_start_idx = 3,
-               .cond_nums = 1 },
-       .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
-       .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-       .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-       .key_start_idx = 141,
-       .blob_key_bit_size = 14,
-       .key_bit_size = 14,
-       .key_num_fields = 3,
-       .result_start_idx = 65,
-       .result_bit_size = 66,
-       .result_num_fields = 5,
-       .encap_num_fields = 0
-       },
-       { /* class_tid: 2, wh_plus, table: eem.ext_0 */
+       { /* class_tid: 1, wh_plus, table: eem.ext_0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE,
        .resource_type = TF_MEM_EXTERNAL,
        .direction = TF_DIR_RX,
        .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT,
        .execute_info = {
-               .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
-               .cond_start_idx = 4,
-               .cond_nums = 0 },
+               .cond_goto = 1,
+               .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
+               .cond_start_idx = 3,
+               .cond_nums = 1 },
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
        .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
        .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
-       .key_start_idx = 144,
+       .key_start_idx = 73,
        .blob_key_bit_size = 448,
        .key_bit_size = 448,
        .key_num_fields = 10,
-       .result_start_idx = 70,
+       .result_start_idx = 35,
        .result_bit_size = 64,
        .result_num_fields = 9,
        .encap_num_fields = 0
        },
-       { /* class_tid: 2, wh_plus, table: em.int_0 */
-       .resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
-       .resource_type = TF_MEM_INTERNAL,
+       { /* class_tid: 1, wh_plus, table: last */
+       .resource_func = BNXT_ULP_RESOURCE_FUNC_BRANCH_TABLE,
        .direction = TF_DIR_RX,
-       .mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,
        .execute_info = {
+               .cond_goto = 0,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 4,
                .cond_nums = 0 },
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
-       .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-       .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,
-       .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
-       .key_start_idx = 154,
-       .blob_key_bit_size = 176,
-       .key_bit_size = 176,
-       .key_num_fields = 10,
-       .result_start_idx = 79,
-       .result_bit_size = 64,
-       .result_num_fields = 9,
-       .encap_num_fields = 0
+       .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH
        },
-       { /* class_tid: 3, wh_plus, table: int_full_act_record.0 */
+       { /* class_tid: 2, wh_plus, table: int_full_act_record.0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
        .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
        .resource_sub_type =
                BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
        .direction = TF_DIR_RX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 4,
                .cond_nums = 0 },
@@ -374,16 +277,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
        .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
-       .result_start_idx = 88,
+       .result_start_idx = 44,
        .result_bit_size = 128,
        .result_num_fields = 26,
        .encap_num_fields = 0
        },
-       { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */
+       { /* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
        .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
        .direction = TF_DIR_RX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 4,
                .cond_nums = 0 },
@@ -396,44 +300,46 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
        .pri_operand = 0,
        .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
        .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
-       .key_start_idx = 164,
+       .key_start_idx = 83,
        .blob_key_bit_size = 167,
        .key_bit_size = 167,
        .key_num_fields = 13,
-       .result_start_idx = 114,
+       .result_start_idx = 70,
        .result_bit_size = 64,
        .result_num_fields = 13,
        .encap_num_fields = 0,
-       .ident_start_idx = 10,
+       .ident_start_idx = 6,
        .ident_nums = 1
        },
-       { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */
+       { /* class_tid: 2, wh_plus, table: l2_cntxt_tcam_cache.wr */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
        .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
        .resource_sub_type =
                BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
        .direction = TF_DIR_RX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 4,
                .cond_nums = 0 },
        .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-       .key_start_idx = 177,
+       .key_start_idx = 96,
        .blob_key_bit_size = 8,
        .key_bit_size = 8,
        .key_num_fields = 1,
-       .result_start_idx = 127,
+       .result_start_idx = 83,
        .result_bit_size = 62,
        .result_num_fields = 4,
        .encap_num_fields = 0
        },
-       { /* class_tid: 3, wh_plus, table: parif_def_lkup_arec_ptr.0 */
+       { /* class_tid: 2, wh_plus, table: parif_def_lkup_arec_ptr.0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
        .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,
        .direction = TF_DIR_RX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 4,
                .cond_nums = 0 },
@@ -441,16 +347,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
        .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-       .result_start_idx = 131,
+       .result_start_idx = 87,
        .result_bit_size = 32,
        .result_num_fields = 1,
        .encap_num_fields = 0
        },
-       { /* class_tid: 3, wh_plus, table: parif_def_arec_ptr.0 */
+       { /* class_tid: 2, wh_plus, table: parif_def_arec_ptr.0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
        .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
        .direction = TF_DIR_RX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 4,
                .cond_nums = 0 },
@@ -458,16 +365,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
        .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-       .result_start_idx = 132,
+       .result_start_idx = 88,
        .result_bit_size = 32,
        .result_num_fields = 1,
        .encap_num_fields = 0
        },
-       { /* class_tid: 3, wh_plus, table: parif_def_err_arec_ptr.0 */
+       { /* class_tid: 2, wh_plus, table: parif_def_err_arec_ptr.0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
        .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
        .direction = TF_DIR_RX,
        .execute_info = {
+               .cond_goto = 0,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 4,
                .cond_nums = 0 },
@@ -475,18 +383,19 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
        .tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-       .result_start_idx = 133,
+       .result_start_idx = 89,
        .result_bit_size = 32,
        .result_num_fields = 1,
        .encap_num_fields = 0
        },
-       { /* class_tid: 4, wh_plus, table: int_full_act_record.0 */
+       { /* class_tid: 3, wh_plus, table: int_full_act_record.0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
        .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
        .resource_sub_type =
                BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
        .direction = TF_DIR_TX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 4,
                .cond_nums = 0 },
@@ -495,16 +404,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
        .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
-       .result_start_idx = 134,
+       .result_start_idx = 90,
        .result_bit_size = 128,
        .result_num_fields = 26,
        .encap_num_fields = 0
        },
-       { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.vfr_0 */
+       { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_bypass.vfr_0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
        .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
        .direction = TF_DIR_TX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
                .cond_start_idx = 4,
                .cond_nums = 1 },
@@ -516,42 +426,44 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
        .pri_operand = 0,
        .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
        .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
-       .key_start_idx = 178,
+       .key_start_idx = 97,
        .blob_key_bit_size = 167,
        .key_bit_size = 167,
        .key_num_fields = 13,
-       .result_start_idx = 160,
+       .result_start_idx = 116,
        .result_bit_size = 64,
        .result_num_fields = 13,
        .encap_num_fields = 0,
-       .ident_start_idx = 11,
+       .ident_start_idx = 7,
        .ident_nums = 0
        },
-       { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd */
+       { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.rd */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
        .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
        .resource_sub_type =
                BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
        .direction = TF_DIR_TX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
                .cond_start_idx = 5,
                .cond_nums = 1 },
        .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-       .key_start_idx = 191,
+       .key_start_idx = 110,
        .blob_key_bit_size = 8,
        .key_bit_size = 8,
        .key_num_fields = 1,
-       .ident_start_idx = 11,
+       .ident_start_idx = 7,
        .ident_nums = 1
        },
-       { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam.0 */
+       { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
        .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
        .direction = TF_DIR_TX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
                .cond_start_idx = 6,
                .cond_nums = 2 },
@@ -562,44 +474,46 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
        .fdb_operand = BNXT_ULP_RF_IDX_RID,
        .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
        .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
-       .key_start_idx = 192,
+       .key_start_idx = 111,
        .blob_key_bit_size = 167,
        .key_bit_size = 167,
        .key_num_fields = 13,
-       .result_start_idx = 173,
+       .result_start_idx = 129,
        .result_bit_size = 64,
        .result_num_fields = 13,
        .encap_num_fields = 0,
-       .ident_start_idx = 12,
+       .ident_start_idx = 8,
        .ident_nums = 1
        },
-       { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr */
+       { /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
        .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
        .resource_sub_type =
                BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
        .direction = TF_DIR_TX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
                .cond_start_idx = 8,
                .cond_nums = 2 },
        .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-       .key_start_idx = 205,
+       .key_start_idx = 124,
        .blob_key_bit_size = 8,
        .key_bit_size = 8,
        .key_num_fields = 1,
-       .result_start_idx = 186,
+       .result_start_idx = 142,
        .result_bit_size = 62,
        .result_num_fields = 4,
        .encap_num_fields = 0
        },
-       { /* class_tid: 4, wh_plus, table: parif_def_lkup_arec_ptr.0 */
+       { /* class_tid: 3, wh_plus, table: parif_def_lkup_arec_ptr.0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
        .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,
        .direction = TF_DIR_TX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 10,
                .cond_nums = 0 },
@@ -607,16 +521,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
        .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-       .result_start_idx = 190,
+       .result_start_idx = 146,
        .result_bit_size = 32,
        .result_num_fields = 1,
        .encap_num_fields = 0
        },
-       { /* class_tid: 4, wh_plus, table: parif_def_arec_ptr.0 */
+       { /* class_tid: 3, wh_plus, table: parif_def_arec_ptr.0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
        .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
        .direction = TF_DIR_TX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 10,
                .cond_nums = 0 },
@@ -624,16 +539,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
        .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-       .result_start_idx = 191,
+       .result_start_idx = 147,
        .result_bit_size = 32,
        .result_num_fields = 1,
        .encap_num_fields = 0
        },
-       { /* class_tid: 4, wh_plus, table: parif_def_err_arec_ptr.0 */
+       { /* class_tid: 3, wh_plus, table: parif_def_err_arec_ptr.0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
        .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
        .direction = TF_DIR_TX,
        .execute_info = {
+               .cond_goto = 0,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 10,
                .cond_nums = 0 },
@@ -641,18 +557,19 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
        .tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-       .result_start_idx = 192,
+       .result_start_idx = 148,
        .result_bit_size = 32,
        .result_num_fields = 1,
        .encap_num_fields = 0
        },
-       { /* class_tid: 5, wh_plus, table: int_vtag_encap_record.egr0 */
+       { /* class_tid: 4, wh_plus, table: int_vtag_encap_record.egr0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
        .resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,
        .resource_sub_type =
                BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
        .direction = TF_DIR_TX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 10,
                .cond_nums = 0 },
@@ -661,18 +578,19 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
        .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
-       .result_start_idx = 193,
+       .result_start_idx = 149,
        .result_bit_size = 0,
        .result_num_fields = 0,
        .encap_num_fields = 12
        },
-       { /* class_tid: 5, wh_plus, table: int_full_act_record.egr0 */
+       { /* class_tid: 4, wh_plus, table: int_full_act_record.egr0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
        .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
        .resource_sub_type =
                BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
        .direction = TF_DIR_TX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 10,
                .cond_nums = 0 },
@@ -681,16 +599,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
        .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
-       .result_start_idx = 205,
+       .result_start_idx = 161,
        .result_bit_size = 128,
        .result_num_fields = 26,
        .encap_num_fields = 0
        },
-       { /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */
+       { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
        .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
        .direction = TF_DIR_TX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 10,
                .cond_nums = 0 },
@@ -701,48 +620,50 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
        .fdb_operand = BNXT_ULP_RF_IDX_RID,
        .pri_opcode  = BNXT_ULP_PRI_OPC_CONST,
        .pri_operand = 0,
-       .key_start_idx = 206,
+       .key_start_idx = 125,
        .blob_key_bit_size = 167,
        .key_bit_size = 167,
        .key_num_fields = 13,
-       .result_start_idx = 231,
+       .result_start_idx = 187,
        .result_bit_size = 64,
        .result_num_fields = 13,
        .encap_num_fields = 0,
-       .ident_start_idx = 13,
+       .ident_start_idx = 9,
        .ident_nums = 0
        },
-       { /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */
+       { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
        .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
        .resource_sub_type =
                BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
        .direction = TF_DIR_TX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 10,
                .cond_nums = 0 },
        .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-       .key_start_idx = 219,
+       .key_start_idx = 138,
        .blob_key_bit_size = 8,
        .key_bit_size = 8,
        .key_num_fields = 1,
-       .result_start_idx = 244,
+       .result_start_idx = 200,
        .result_bit_size = 62,
        .result_num_fields = 4,
        .encap_num_fields = 0,
-       .ident_start_idx = 13,
+       .ident_start_idx = 9,
        .ident_nums = 0
        },
-       { /* class_tid: 5, wh_plus, table: int_full_act_record.ing0 */
+       { /* class_tid: 4, wh_plus, table: int_full_act_record.ing0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
        .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
        .resource_sub_type =
                BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
        .direction = TF_DIR_RX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 10,
                .cond_nums = 0 },
@@ -751,16 +672,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
        .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
-       .result_start_idx = 248,
+       .result_start_idx = 204,
        .result_bit_size = 128,
        .result_num_fields = 26,
        .encap_num_fields = 0
        },
-       { /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.dtagged_ing0 */
+       { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.dtagged_ing0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
        .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
        .direction = TF_DIR_RX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 10,
                .cond_nums = 0 },
@@ -772,22 +694,23 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
        .pri_operand = 0,
        .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
        .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
-       .key_start_idx = 220,
+       .key_start_idx = 139,
        .blob_key_bit_size = 167,
        .key_bit_size = 167,
        .key_num_fields = 13,
-       .result_start_idx = 274,
+       .result_start_idx = 230,
        .result_bit_size = 64,
        .result_num_fields = 13,
        .encap_num_fields = 0,
-       .ident_start_idx = 13,
+       .ident_start_idx = 9,
        .ident_nums = 0
        },
-       { /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */
+       { /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
        .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
        .direction = TF_DIR_RX,
        .execute_info = {
+               .cond_goto = 0,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 10,
                .cond_nums = 0 },
@@ -799,22 +722,23 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
        .pri_operand = 0,
        .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
        .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
-       .key_start_idx = 233,
+       .key_start_idx = 152,
        .blob_key_bit_size = 167,
        .key_bit_size = 167,
        .key_num_fields = 13,
-       .result_start_idx = 287,
+       .result_start_idx = 243,
        .result_bit_size = 64,
        .result_num_fields = 13,
        .encap_num_fields = 0,
-       .ident_start_idx = 13,
+       .ident_start_idx = 9,
        .ident_nums = 0
        },
-       { /* class_tid: 6, wh_plus, table: l2_cntxt_tcam.egr */
+       { /* class_tid: 5, wh_plus, table: l2_cntxt_tcam.egr */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
        .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
        .direction = TF_DIR_TX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 10,
                .cond_nums = 0 },
@@ -825,44 +749,46 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
        .fdb_operand = BNXT_ULP_RF_IDX_RID,
        .pri_opcode  = BNXT_ULP_PRI_OPC_CONST,
        .pri_operand = 0,
-       .key_start_idx = 246,
+       .key_start_idx = 165,
        .blob_key_bit_size = 167,
        .key_bit_size = 167,
        .key_num_fields = 13,
-       .result_start_idx = 300,
+       .result_start_idx = 256,
        .result_bit_size = 64,
        .result_num_fields = 13,
        .encap_num_fields = 0,
-       .ident_start_idx = 13,
+       .ident_start_idx = 9,
        .ident_nums = 1
        },
-       { /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */
+       { /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,
        .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
        .resource_sub_type =
                BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,
        .direction = TF_DIR_TX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 10,
                .cond_nums = 0 },
        .tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-       .key_start_idx = 259,
+       .key_start_idx = 178,
        .blob_key_bit_size = 8,
        .key_bit_size = 8,
        .key_num_fields = 1,
-       .result_start_idx = 313,
+       .result_start_idx = 269,
        .result_bit_size = 62,
        .result_num_fields = 4,
        .encap_num_fields = 0
        },
-       { /* class_tid: 6, wh_plus, table: parif_def_lkup_arec_ptr.egr */
+       { /* class_tid: 5, wh_plus, table: parif_def_lkup_arec_ptr.egr */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
        .resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,
        .direction = TF_DIR_TX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 10,
                .cond_nums = 0 },
@@ -870,16 +796,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
        .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF,
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-       .result_start_idx = 317,
+       .result_start_idx = 273,
        .result_bit_size = 32,
        .result_num_fields = 1,
        .encap_num_fields = 0
        },
-       { /* class_tid: 6, wh_plus, table: parif_def_arec_ptr.egr */
+       { /* class_tid: 5, wh_plus, table: parif_def_arec_ptr.egr */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
        .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
        .direction = TF_DIR_TX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 10,
                .cond_nums = 0 },
@@ -887,16 +814,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
        .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF,
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-       .result_start_idx = 318,
+       .result_start_idx = 274,
        .result_bit_size = 32,
        .result_num_fields = 1,
        .encap_num_fields = 0
        },
-       { /* class_tid: 6, wh_plus, table: parif_def_err_arec_ptr.egr */
+       { /* class_tid: 5, wh_plus, table: parif_def_err_arec_ptr.egr */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
        .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
        .direction = TF_DIR_TX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 10,
                .cond_nums = 0 },
@@ -904,18 +832,19 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
        .tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF,
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
-       .result_start_idx = 319,
+       .result_start_idx = 275,
        .result_bit_size = 32,
        .result_num_fields = 1,
        .encap_num_fields = 0
        },
-       { /* class_tid: 6, wh_plus, table: int_full_act_record.ing */
+       { /* class_tid: 5, wh_plus, table: int_full_act_record.ing */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
        .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
        .resource_sub_type =
                BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
        .direction = TF_DIR_RX,
        .execute_info = {
+               .cond_goto = 1,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 10,
                .cond_nums = 0 },
@@ -924,16 +853,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,
        .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,
-       .result_start_idx = 320,
+       .result_start_idx = 276,
        .result_bit_size = 128,
        .result_num_fields = 26,
        .encap_num_fields = 0
        },
-       { /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_bypass.ing */
+       { /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.ing */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
        .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
        .direction = TF_DIR_RX,
        .execute_info = {
+               .cond_goto = 0,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 10,
                .cond_nums = 0 },
@@ -945,24 +875,25 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
        .pri_operand = 0,
        .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
        .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
-       .key_start_idx = 260,
+       .key_start_idx = 179,
        .blob_key_bit_size = 167,
        .key_bit_size = 167,
        .key_num_fields = 13,
-       .result_start_idx = 346,
+       .result_start_idx = 302,
        .result_bit_size = 64,
        .result_num_fields = 13,
        .encap_num_fields = 0,
-       .ident_start_idx = 14,
+       .ident_start_idx = 10,
        .ident_nums = 0
        },
-       { /* class_tid: 7, wh_plus, table: int_full_act_record.0 */
+       { /* class_tid: 6, wh_plus, table: int_full_act_record.0 */
        .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
        .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
        .resource_sub_type =
                BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,
        .direction = TF_DIR_TX,
        .execute_info = {
+               .cond_goto = 0,
                .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
                .cond_start_idx = 10,
                .cond_nums = 0 },
@@ -971,7 +902,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
        .accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
        .fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
        .mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
-       .result_start_idx = 359,
+       .result_start_idx = 315,
        .result_bit_size = 128,
        .result_num_fields = 26,
        .encap_num_fields = 0
@@ -980,246 +911,279 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 
 struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = {
        {
-       .cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET,
-       .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT
+       .cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET,
+       .cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC
        },
        {
-       .cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET,
+       .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
        .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT
        },
        {
-       .cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET,
-       .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT
+       .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+       .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
        },
        {
-       .cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET,
-       .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT
+       .cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,
+       .cond_operand = BNXT_ULP_HDR_BIT_O_IPV4
        },
        {
-       .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_IS_SET,
+       .cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,
        .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
        },
        {
-       .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET,
+       .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,
        .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
        },
        {
-       .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET,
+       .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,
        .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
        },
        {
-       .cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET,
+       .cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET,
        .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT
        },
        {
-       .cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET,
+       .cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,
        .cond_operand = BNXT_ULP_CF_IDX_VFR_MODE
        },
        {
-       .cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET,
+       .cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET,
        .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT
        }
 };
 
 struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
+       /* class_tid: 1, wh_plus, table: l2_cntxt_tcam_cache.rd */
+       {
+       .field_info_mask = {
+               .description = "svif",
+               .field_bit_size = 8,
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+               },
+       .field_info_spec = {
+               .description = "svif",
+               .field_bit_size = 8,
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
+               }
+       },
        /* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */
        {
        .field_info_mask = {
                .description = "l2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_OO_VLAN_VID >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_OO_VLAN_VID & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}
                },
        .field_info_spec = {
                .description = "l2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_OO_VLAN_VID >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_OO_VLAN_VID & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "l2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "mac0_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_ETH_DMAC >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_ETH_DMAC & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
                },
        .field_info_spec = {
                .description = "mac0_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_ETH_DMAC >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_ETH_DMAC & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_SVIF_INDEX >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_SVIF_INDEX & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
                },
        .field_info_spec = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_SVIF_INDEX >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_SVIF_INDEX & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "sparif",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "sparif",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "mac1_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "mac1_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "l2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+               .field_opr1 = {
                        (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tun_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tun_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "key_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "key_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       1}
                }
        },
        /* class_tid: 1, wh_plus, table: profile_tcam_cache.rd */
@@ -1227,52 +1191,54 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
        .field_info_mask = {
                .description = "recycle_cnt",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "recycle_cnt",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "prof_func_id",
                .field_bit_size = 7,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "prof_func_id",
                .field_bit_size = 7,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,
-               .field_operand = {
-               (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
-                       BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+                       BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "hdr_sig_id",
                .field_bit_size = 5,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "hdr_sig_id",
                .field_bit_size = 5,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+               .field_opr1 = {
                        (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
                }
        },
        /* class_tid: 1, wh_plus, table: profile_tcam.0 */
@@ -1280,580 +1246,684 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
        .field_info_mask = {
                .description = "l4_hdr_is_udp_tcp",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l4_hdr_is_udp_tcp",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l4_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "l4_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
+               .field_cond_opr = {
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+                       (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       ULP_WP_SYM_L4_HDR_TYPE_TCP},
+               .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr2 = {
+                       ULP_WP_SYM_L4_HDR_TYPE_UDP}
                }
        },
        {
        .field_info_mask = {
                .description = "l4_hdr_error",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "l4_hdr_error",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l4_hdr_valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "l4_hdr_valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {
-                       BNXT_ULP_WH_PLUS_SYM_L4_HDR_VALID_YES,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       ULP_WP_SYM_L4_HDR_VALID_YES}
                }
        },
        {
        .field_info_mask = {
                .description = "l3_ipv6_cmp_dst",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l3_ipv6_cmp_dst",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l3_ipv6_cmp_src",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l3_ipv6_cmp_src",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l3_hdr_isIP",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l3_hdr_isIP",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l3_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "l3_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
+               .field_cond_opr = {
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,
+                       (uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       ULP_WP_SYM_L3_HDR_TYPE_IPV4},
+               .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr2 = {
+                       ULP_WP_SYM_L3_HDR_TYPE_IPV6}
                }
        },
        {
        .field_info_mask = {
                .description = "l3_hdr_error",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "l3_hdr_error",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l3_hdr_valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "l3_hdr_valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {
-                       BNXT_ULP_WH_PLUS_SYM_L3_HDR_VALID_YES,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       ULP_WP_SYM_L3_HDR_VALID_YES}
                }
        },
        {
        .field_info_mask = {
                .description = "l2_two_vtags",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "l2_two_vtags",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_vtag_present",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "l2_vtag_present",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+               .field_opr1 = {
                        (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "l2_uc_mc_bc",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "l2_uc_mc_bc",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_hdr_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "l2_hdr_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_hdr_error",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "l2_hdr_error",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_hdr_valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "l2_hdr_valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {
-                       BNXT_ULP_WH_PLUS_SYM_L2_HDR_VALID_YES,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       ULP_WP_SYM_L2_HDR_VALID_YES}
                }
        },
        {
        .field_info_mask = {
                .description = "tun_hdr_flags",
                .field_bit_size = 3,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tun_hdr_flags",
                .field_bit_size = 3,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tun_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tun_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tun_hdr_err",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tun_hdr_err",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tun_hdr_valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "tun_hdr_valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl4_hdr_is_udp_tcp",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl4_hdr_is_udp_tcp",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl4_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl4_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl4_hdr_error",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl4_hdr_error",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl4_hdr_valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "tl4_hdr_valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl3_ipv6_cmp_dst",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl3_ipv6_cmp_dst",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl3_ipv6_cmp_src",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl3_ipv6_cmp_src",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl3_hdr_isIP",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl3_hdr_isIP",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl3_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl3_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl3_hdr_error",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl3_hdr_error",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl3_hdr_valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "tl3_hdr_valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_two_vtags",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_two_vtags",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_vtag_present",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_vtag_present",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_uc_mc_bc",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_uc_mc_bc",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_hdr_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_hdr_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_hdr_valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "tl2_hdr_valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "hrec_next",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "hrec_next",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "reserved",
                .field_bit_size = 9,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "reserved",
                .field_bit_size = 9,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "prof_func_id",
                .field_bit_size = 7,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "prof_func_id",
                .field_bit_size = 7,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,
-               .field_operand = {
-               (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
-                       BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
+                       BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "agg_error",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "agg_error",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "recycle_cnt",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "recycle_cnt",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "pkt_type_0",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "pkt_type_0",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "pkt_type_1",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "pkt_type_1",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       1}
                }
        },
        /* class_tid: 1, wh_plus, table: profile_tcam_cache.wr */
@@ -1861,3165 +1931,2188 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {
        .field_info_mask = {
                .description = "recycle_cnt",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "recycle_cnt",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "prof_func_id",
                .field_bit_size = 7,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "prof_func_id",
                .field_bit_size = 7,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,
-               .field_operand = {
-               (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
-                       BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+                       BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "hdr_sig_id",
                .field_bit_size = 5,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "hdr_sig_id",
                .field_bit_size = 5,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+               .field_opr1 = {
                        (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}
                }
        },
-       /* class_tid: 1, wh_plus, table: eem.ext_0 */
+       /* class_tid: 1, wh_plus, table: em.int_0 */
        {
        .field_info_mask = {
                .description = "spare",
-               .field_bit_size = 275,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_bit_size = 3,
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "spare",
-               .field_bit_size = 275,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_bit_size = 3,
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "local_cos",
                .field_bit_size = 3,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "local_cos",
                .field_bit_size = 3,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "o_l4.dport",
                .field_bit_size = 16,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff,
+                       0xff}
                },
        .field_info_spec = {
                .description = "o_l4.dport",
                .field_bit_size = 16,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
+               .field_cond_opr = {
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+                       (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+               .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},
+               .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr2 = {
+                       (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "o_l4.sport",
                .field_bit_size = 16,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff,
+                       0xff}
                },
        .field_info_spec = {
                .description = "o_l4.sport",
                .field_bit_size = 16,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
+               .field_cond_opr = {
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+                       (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+               .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},
+               .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr2 = {
+                       (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "o_ipv4.ip_proto",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "o_ipv4.ip_proto",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {
-                       BNXT_ULP_WH_PLUS_SYM_IP_PROTO_TCP,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
+               .field_cond_opr = {
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+                       (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       ULP_WP_SYM_IP_PROTO_TCP},
+               .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr2 = {
+                       ULP_WP_SYM_IP_PROTO_UDP}
                }
        },
        {
        .field_info_mask = {
                .description = "o_ipv4.dst",
                .field_bit_size = 32,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
                },
        .field_info_spec = {
                .description = "o_ipv4.dst",
                .field_bit_size = 32,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "o_ipv4.src",
                .field_bit_size = 32,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
                },
        .field_info_spec = {
                .description = "o_ipv4.src",
                .field_bit_size = 32,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "o_eth.smac",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff,
+                       0xff,
+                       0xff,
+                       0xff,
+                       0xff,
+                       0xff}
                },
        .field_info_spec = {
                .description = "o_eth.smac",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_cntxt_id",
                .field_bit_size = 10,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff,
+                       0xff}
                },
        .field_info_spec = {
                .description = "l2_cntxt_id",
                .field_bit_size = 10,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+               .field_opr1 = {
                        (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
-                       BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "em_profile_id",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "em_profile_id",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-               .field_operand = {
-               (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
-                       BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+               .field_opr1 = {
+                       (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
+                       BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
                }
        },
-       /* class_tid: 1, wh_plus, table: em.int_0 */
+       /* class_tid: 1, wh_plus, table: eem.ext_0 */
        {
        .field_info_mask = {
-               .description = "spare",
-               .field_bit_size = 3,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "spare",
-               .field_bit_size = 3,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "local_cos",
-               .field_bit_size = 3,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "local_cos",
-               .field_bit_size = 3,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "o_l4.dport",
-               .field_bit_size = 16,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               },
-       .field_info_spec = {
-               .description = "o_l4.dport",
-               .field_bit_size = 16,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "o_l4.sport",
-               .field_bit_size = 16,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               },
-       .field_info_spec = {
-               .description = "o_l4.sport",
-               .field_bit_size = 16,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "o_ipv4.ip_proto",
-               .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "o_ipv4.ip_proto",
-               .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {
-                       BNXT_ULP_WH_PLUS_SYM_IP_PROTO_TCP,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "o_ipv4.dst",
-               .field_bit_size = 32,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               },
-       .field_info_spec = {
-               .description = "o_ipv4.dst",
-               .field_bit_size = 32,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "o_ipv4.src",
-               .field_bit_size = 32,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               },
-       .field_info_spec = {
-               .description = "o_ipv4.src",
-               .field_bit_size = 32,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "o_eth.smac",
-               .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "o_eth.smac",
-               .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "l2_cntxt_id",
-               .field_bit_size = 10,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "l2_cntxt_id",
-               .field_bit_size = 10,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-               .field_operand = {
-                       (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
-                       BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "em_profile_id",
-               .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "em_profile_id",
-               .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-               .field_operand = {
-                       (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
-                       BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       /* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */
-       {
-       .field_info_mask = {
-               .description = "l2_ivlan_vid",
-               .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_OO_VLAN_VID >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_OO_VLAN_VID & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               },
-       .field_info_spec = {
-               .description = "l2_ivlan_vid",
-               .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_OO_VLAN_VID >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_OO_VLAN_VID & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "l2_ovlan_vid",
-               .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "l2_ovlan_vid",
-               .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "mac0_addr",
-               .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_ETH_DMAC >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_ETH_DMAC & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               },
-       .field_info_spec = {
-               .description = "mac0_addr",
-               .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_ETH_DMAC >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_ETH_DMAC & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "svif",
-               .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_SVIF_INDEX >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_SVIF_INDEX & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               },
-       .field_info_spec = {
-               .description = "svif",
-               .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_SVIF_INDEX >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_SVIF_INDEX & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "sparif",
-               .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "sparif",
-               .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tl2_ivlan_vid",
-               .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "tl2_ivlan_vid",
-               .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tl2_ovlan_vid",
-               .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "tl2_ovlan_vid",
-               .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "mac1_addr",
-               .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "mac1_addr",
-               .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "l2_num_vtags",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "l2_num_vtags",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tl2_num_vtags",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "tl2_num_vtags",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tun_hdr_type",
-               .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "tun_hdr_type",
-               .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "key_type",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "key_type",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "valid",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "valid",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       /* class_tid: 2, wh_plus, table: profile_tcam_cache.rd */
-       {
-       .field_info_mask = {
-               .description = "recycle_cnt",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "recycle_cnt",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "prof_func_id",
-               .field_bit_size = 7,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "prof_func_id",
-               .field_bit_size = 7,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,
-               .field_operand = {
-               (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
-                       BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "hdr_sig_id",
-               .field_bit_size = 5,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "hdr_sig_id",
-               .field_bit_size = 5,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       /* class_tid: 2, wh_plus, table: profile_tcam.0 */
-       {
-       .field_info_mask = {
-               .description = "l4_hdr_is_udp_tcp",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "l4_hdr_is_udp_tcp",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "l4_hdr_type",
-               .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "l4_hdr_type",
-               .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "l4_hdr_error",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "l4_hdr_error",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "l4_hdr_valid",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "l4_hdr_valid",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {
-                       BNXT_ULP_WH_PLUS_SYM_L4_HDR_VALID_YES,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "l3_ipv6_cmp_dst",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "l3_ipv6_cmp_dst",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "l3_ipv6_cmp_src",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "l3_ipv6_cmp_src",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "l3_hdr_isIP",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "l3_hdr_isIP",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "l3_hdr_type",
-               .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "l3_hdr_type",
-               .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "l3_hdr_error",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "l3_hdr_error",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "l3_hdr_valid",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "l3_hdr_valid",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {
-                       BNXT_ULP_WH_PLUS_SYM_L3_HDR_VALID_YES,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "l2_two_vtags",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "l2_two_vtags",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "l2_vtag_present",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "l2_vtag_present",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "l2_uc_mc_bc",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "l2_uc_mc_bc",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "l2_hdr_type",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "l2_hdr_type",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "l2_hdr_error",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "l2_hdr_error",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "l2_hdr_valid",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "l2_hdr_valid",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {
-                       BNXT_ULP_WH_PLUS_SYM_L2_HDR_VALID_YES,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tun_hdr_flags",
-               .field_bit_size = 3,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "tun_hdr_flags",
-               .field_bit_size = 3,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tun_hdr_type",
-               .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "tun_hdr_type",
-               .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tun_hdr_err",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "tun_hdr_err",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tun_hdr_valid",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "tun_hdr_valid",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tl4_hdr_is_udp_tcp",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "tl4_hdr_is_udp_tcp",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tl4_hdr_type",
-               .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "tl4_hdr_type",
-               .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tl4_hdr_error",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "tl4_hdr_error",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tl4_hdr_valid",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "tl4_hdr_valid",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tl3_ipv6_cmp_dst",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "tl3_ipv6_cmp_dst",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tl3_ipv6_cmp_src",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "tl3_ipv6_cmp_src",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tl3_hdr_isIP",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "tl3_hdr_isIP",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tl3_hdr_type",
-               .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "tl3_hdr_type",
-               .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tl3_hdr_error",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "tl3_hdr_error",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tl3_hdr_valid",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "tl3_hdr_valid",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tl2_two_vtags",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "tl2_two_vtags",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tl2_vtag_present",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "tl2_vtag_present",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tl2_uc_mc_bc",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "tl2_uc_mc_bc",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tl2_hdr_type",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "tl2_hdr_type",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "tl2_hdr_valid",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "tl2_hdr_valid",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "hrec_next",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "hrec_next",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "reserved",
-               .field_bit_size = 9,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "reserved",
-               .field_bit_size = 9,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "prof_func_id",
-               .field_bit_size = 7,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "prof_func_id",
-               .field_bit_size = 7,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,
-               .field_operand = {
-               (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
-                       BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "agg_error",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "agg_error",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "recycle_cnt",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "recycle_cnt",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "pkt_type_0",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               },
-       .field_info_spec = {
-               .description = "pkt_type_0",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "pkt_type_1",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "pkt_type_1",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "valid",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "valid",
-               .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       /* class_tid: 2, wh_plus, table: profile_tcam_cache.wr */
-       {
-       .field_info_mask = {
-               .description = "recycle_cnt",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "recycle_cnt",
-               .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "prof_func_id",
-               .field_bit_size = 7,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "prof_func_id",
-               .field_bit_size = 7,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,
-               .field_operand = {
-               (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
-                       BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "hdr_sig_id",
-               .field_bit_size = 5,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "hdr_sig_id",
-               .field_bit_size = 5,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       /* class_tid: 2, wh_plus, table: eem.ext_0 */
-       {
-       .field_info_mask = {
-               .description = "spare",
-               .field_bit_size = 275,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
                .description = "spare",
                .field_bit_size = 275,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "local_cos",
-               .field_bit_size = 3,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "local_cos",
-               .field_bit_size = 3,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "o_l4.dport",
-               .field_bit_size = 16,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               },
-       .field_info_spec = {
-               .description = "o_l4.dport",
-               .field_bit_size = 16,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "o_l4.sport",
-               .field_bit_size = 16,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               },
-       .field_info_spec = {
-               .description = "o_l4.sport",
-               .field_bit_size = 16,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "o_ipv4.ip_proto",
-               .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "o_ipv4.ip_proto",
-               .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {
-                       BNXT_ULP_WH_PLUS_SYM_IP_PROTO_TCP,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "o_ipv4.dst",
-               .field_bit_size = 32,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               },
-       .field_info_spec = {
-               .description = "o_ipv4.dst",
-               .field_bit_size = 32,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "o_ipv4.src",
-               .field_bit_size = 32,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "o_ipv4.src",
-               .field_bit_size = 32,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "o_eth.smac",
-               .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "o_eth.smac",
-               .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "l2_cntxt_id",
-               .field_bit_size = 10,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "l2_cntxt_id",
-               .field_bit_size = 10,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-               .field_operand = {
-                       (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
-                       BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       {
-       .field_info_mask = {
-               .description = "em_profile_id",
-               .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
-               },
-       .field_info_spec = {
-               .description = "em_profile_id",
-               .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-               .field_operand = {
-                       (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
-                       BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-               }
-       },
-       /* class_tid: 2, wh_plus, table: em.int_0 */
-       {
-       .field_info_mask = {
-               .description = "spare",
-               .field_bit_size = 3,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "spare",
-               .field_bit_size = 3,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_bit_size = 275,
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "local_cos",
                .field_bit_size = 3,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "local_cos",
                .field_bit_size = 3,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "o_l4.dport",
                .field_bit_size = 16,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff,
+                       0xff}
                },
        .field_info_spec = {
                .description = "o_l4.dport",
                .field_bit_size = 16,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
+               .field_cond_opr = {
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+                       (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+               .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},
+               .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr2 = {
+                       (BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "o_l4.sport",
                .field_bit_size = 16,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff,
+                       0xff}
                },
        .field_info_spec = {
                .description = "o_l4.sport",
                .field_bit_size = 16,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
+               .field_cond_opr = {
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+                       (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+               .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},
+               .field_src2 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr2 = {
+                       (BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "o_ipv4.ip_proto",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "o_ipv4.ip_proto",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {
-                       BNXT_ULP_WH_PLUS_SYM_IP_PROTO_TCP,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,
+               .field_cond_opr = {
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,
+                       ((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,
+                       (uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       ULP_WP_SYM_IP_PROTO_TCP},
+               .field_src2 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr2 = {
+                       ULP_WP_SYM_IP_PROTO_UDP}
                }
        },
        {
        .field_info_mask = {
                .description = "o_ipv4.dst",
                .field_bit_size = 32,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
                },
        .field_info_spec = {
                .description = "o_ipv4.dst",
                .field_bit_size = 32,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,
-               .field_operand = {
-                       (BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff,
-                       BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "o_ipv4.src",
                .field_bit_size = 32,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
                },
        .field_info_spec = {
                .description = "o_ipv4.src",
                .field_bit_size = 32,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_HF,
+               .field_opr1 = {
+                       (BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,
+                       BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "o_eth.smac",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff,
+                       0xff,
+                       0xff,
+                       0xff,
+                       0xff,
+                       0xff}
                },
        .field_info_spec = {
                .description = "o_eth.smac",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_cntxt_id",
                .field_bit_size = 10,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff,
+                       0xff}
                },
        .field_info_spec = {
                .description = "l2_cntxt_id",
                .field_bit_size = 10,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+               .field_opr1 = {
                        (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
-                       BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "em_profile_id",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "em_profile_id",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+               .field_opr1 = {
                        (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
-                       BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
                }
        },
-       /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */
+       /* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */
        {
        .field_info_mask = {
                .description = "l2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "mac0_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "mac0_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+               .field_opr1 = {
                        (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "sparif",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "sparif",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "mac1_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "mac1_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tun_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tun_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "key_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "key_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       1}
                }
        },
-       /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */
+       /* class_tid: 2, wh_plus, table: l2_cntxt_tcam_cache.wr */
        {
        .field_info_mask = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+               .field_opr1 = {
                        (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}
                }
        },
-       /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.vfr_0 */
+       /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_bypass.vfr_0 */
        {
        .field_info_mask = {
                .description = "l2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "mac0_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "mac0_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+               .field_opr1 = {
                        (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "sparif",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "sparif",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "mac1_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "mac1_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tun_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tun_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "key_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "key_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       1}
                }
        },
-       /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd */
+       /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.rd */
        {
        .field_info_mask = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+               .field_opr1 = {
                        (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
                }
        },
-       /* class_tid: 4, wh_plus, table: l2_cntxt_tcam.0 */
+       /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */
        {
        .field_info_mask = {
                .description = "l2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "mac0_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "mac0_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+               .field_opr1 = {
                        (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "sparif",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "sparif",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "mac1_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "mac1_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tun_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tun_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "key_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "key_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       1}
                }
        },
-       /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr */
+       /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */
        {
        .field_info_mask = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+               .field_opr1 = {
                        (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
                }
        },
-       /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */
+       /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */
        {
        .field_info_mask = {
                .description = "l2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "mac0_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "mac0_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+               .field_opr1 = {
                        (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "sparif",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "sparif",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "mac1_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "mac1_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tun_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tun_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "key_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "key_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       1}
                }
        },
-       /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */
+       /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */
        {
        .field_info_mask = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+               .field_opr1 = {
                        (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
                }
        },
-       /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.dtagged_ing0 */
+       /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.dtagged_ing0 */
        {
        .field_info_mask = {
                .description = "l2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff,
+                       0xff}
                },
        .field_info_spec = {
                .description = "l2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+               .field_opr1 = {
                        (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "mac0_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "mac0_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+               .field_opr1 = {
                        (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "sparif",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "sparif",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "mac1_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "mac1_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "l2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       2}
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tun_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "tun_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {
-                       BNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_NONE,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       ULP_WP_SYM_TUN_HDR_TYPE_NONE}
                }
        },
        {
        .field_info_mask = {
                .description = "key_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "key_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       1}
                }
        },
-       /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */
+       /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */
        {
        .field_info_mask = {
                .description = "l2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff,
+                       0xff}
                },
        .field_info_spec = {
                .description = "l2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+               .field_opr1 = {
                        (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "l2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "mac0_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "mac0_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+               .field_opr1 = {
                        (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "sparif",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "sparif",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "mac1_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "mac1_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "l2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       1}
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tun_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "tun_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {
-                       BNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_NONE,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       ULP_WP_SYM_TUN_HDR_TYPE_NONE}
                }
        },
        {
        .field_info_mask = {
                .description = "key_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "key_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       1}
                }
        },
-       /* class_tid: 6, wh_plus, table: l2_cntxt_tcam.egr */
+       /* class_tid: 5, wh_plus, table: l2_cntxt_tcam.egr */
        {
        .field_info_mask = {
                .description = "l2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "mac0_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "mac0_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+               .field_opr1 = {
                        (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "sparif",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "sparif",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "mac1_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "mac1_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tun_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tun_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "key_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "key_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       1}
                }
        },
-       /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */
+       /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */
        {
        .field_info_mask = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+               .field_opr1 = {
                        (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
                }
        },
-       /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_bypass.ing */
+       /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.ing */
        {
        .field_info_mask = {
                .description = "l2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "mac0_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "mac0_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "svif",
                .field_bit_size = 8,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-               .field_operand = {
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+               .field_opr1 = {
                        (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
-                       BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+                       BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}
                }
        },
        {
        .field_info_mask = {
                .description = "sparif",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "sparif",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_ivlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_ovlan_vid",
                .field_bit_size = 12,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "mac1_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "mac1_addr",
                .field_bit_size = 48,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "l2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "l2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tl2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tl2_num_vtags",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "tun_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                },
        .field_info_spec = {
                .description = "tun_hdr_type",
                .field_bit_size = 4,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "key_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "key_type",
                .field_bit_size = 2,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
                }
        },
        {
        .field_info_mask = {
                .description = "valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       0xff}
                },
        .field_info_spec = {
                .description = "valid",
                .field_bit_size = 1,
-               .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-               .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+               .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+               .field_opr1 = {
+                       1}
                }
        }
 };
@@ -5029,2380 +4122,2308 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {
        {
        .description = "l2_cntxt_id",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
        },
        {
        .description = "prof_func_id",
        .field_bit_size = 7,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+       .field_opr1 = {
                (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
-               BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}
        },
        {
        .description = "l2_byp_lkup_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "parif",
        .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+       .field_opr1 = {
                (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
-               BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
        },
        {
        .description = "allowed_pri",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "default_pri",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "allowed_tpid",
        .field_bit_size = 6,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "default_tpid",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "bd_act_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "sp_rec_ptr",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "byp_sp_lkup",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               1}
        },
        {
        .description = "pri_anti_spoof_ctl",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tpid_anti_spoof_ctl",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        /* class_tid: 1, wh_plus, table: profile_tcam.0 */
        {
        .description = "wc_key_id",
        .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               3}
        },
        {
        .description = "wc_profile_id",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "wc_search_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "em_key_mask",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {
-               (0x007d >> 8) & 0xff,
-               0x007d & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               (125 >> 8) & 0xff,
+               125 & 0xff}
        },
        {
        .description = "em_key_id",
        .field_bit_size = 5,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               3}
        },
        {
        .description = "em_profile_id",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
        },
        {
        .description = "em_search_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               1}
        },
        {
        .description = "pl_byp_lkup_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        /* class_tid: 1, wh_plus, table: profile_tcam_cache.wr */
        {
        .description = "rid",
        .field_bit_size = 32,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_RID & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_RID & 0xff}
        },
        {
        .description = "profile_tcam_index",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}
        },
        {
        .description = "em_profile_id",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}
        },
        {
        .description = "wm_profile_id",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "flow_sig_id",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+       .field_opr1 = {
                (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
-               BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       /* class_tid: 1, wh_plus, table: eem.ext_0 */
-       {
-       .description = "act_rec_ptr",
-       .field_bit_size = 33,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
-               (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       {
-       .description = "ext_flow_cntr",
-       .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-       },
-       {
-       .description = "act_rec_int",
-       .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {
-               BNXT_ULP_WH_PLUS_SYM_EEM_ACT_REC_INT,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       {
-       .description = "act_rec_size",
-       .field_bit_size = 5,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
-               (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       {
-       .description = "key_size",
-       .field_bit_size = 9,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {
-               (0x00ad >> 8) & 0xff,
-               0x00ad & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       {
-       .description = "reserved",
-       .field_bit_size = 11,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-       },
-       {
-       .description = "strength",
-       .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       {
-       .description = "l1_cacheable",
-       .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-       },
-       {
-       .description = "valid",
-       .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}
        },
        /* class_tid: 1, wh_plus, table: em.int_0 */
        {
        .description = "act_rec_ptr",
        .field_bit_size = 33,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
        },
        {
        .description = "ext_flow_cntr",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "act_rec_int",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "act_rec_size",
        .field_bit_size = 5,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "key_size",
        .field_bit_size = 9,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "reserved",
        .field_bit_size = 11,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "strength",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               3}
        },
        {
        .description = "l1_cacheable",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "valid",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       /* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */
-       {
-       .description = "l2_cntxt_id",
-       .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
-               (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       {
-       .description = "prof_func_id",
-       .field_bit_size = 7,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,
-       .field_operand = {
-               (BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,
-               BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       {
-       .description = "l2_byp_lkup_en",
-       .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-       },
-       {
-       .description = "parif",
-       .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-       .field_operand = {
-               (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
-               BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       {
-       .description = "allowed_pri",
-       .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-       },
-       {
-       .description = "default_pri",
-       .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-       },
-       {
-       .description = "allowed_tpid",
-       .field_bit_size = 6,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-       },
-       {
-       .description = "default_tpid",
-       .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-       },
-       {
-       .description = "bd_act_en",
-       .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-       },
-       {
-       .description = "sp_rec_ptr",
-       .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-       },
-       {
-       .description = "byp_sp_lkup",
-       .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       {
-       .description = "pri_anti_spoof_ctl",
-       .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-       },
-       {
-       .description = "tpid_anti_spoof_ctl",
-       .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-       },
-       /* class_tid: 2, wh_plus, table: profile_tcam.0 */
-       {
-       .description = "wc_key_id",
-       .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       {
-       .description = "wc_profile_id",
-       .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-       },
-       {
-       .description = "wc_search_en",
-       .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-       },
-       {
-       .description = "em_key_mask",
-       .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {
-               (0x0079 >> 8) & 0xff,
-               0x0079 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       {
-       .description = "em_key_id",
-       .field_bit_size = 5,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       {
-       .description = "em_profile_id",
-       .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
-               (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       {
-       .description = "em_search_en",
-       .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       {
-       .description = "pl_byp_lkup_en",
-       .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-       },
-       /* class_tid: 2, wh_plus, table: profile_tcam_cache.wr */
-       {
-       .description = "rid",
-       .field_bit_size = 32,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
-               (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_RID & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       {
-       .description = "profile_tcam_index",
-       .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
-               (BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       {
-       .description = "em_profile_id",
-       .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
-               (BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       {
-       .description = "wm_profile_id",
-       .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-       },
-       {
-       .description = "flow_sig_id",
-       .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-       .field_operand = {
-               (BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,
-               BNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               1}
        },
-       /* class_tid: 2, wh_plus, table: eem.ext_0 */
+       /* class_tid: 1, wh_plus, table: eem.ext_0 */
        {
        .description = "act_rec_ptr",
        .field_bit_size = 33,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
        },
        {
        .description = "ext_flow_cntr",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "act_rec_int",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {
-               BNXT_ULP_WH_PLUS_SYM_EEM_ACT_REC_INT,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               ULP_WP_SYM_EEM_ACT_REC_INT}
        },
        {
        .description = "act_rec_size",
        .field_bit_size = 5,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       {
-       .description = "key_size",
-       .field_bit_size = 9,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {
-               (0x00ad >> 8) & 0xff,
-               0x00ad & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       {
-       .description = "reserved",
-       .field_bit_size = 11,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-       },
-       {
-       .description = "strength",
-       .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       {
-       .description = "l1_cacheable",
-       .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-       },
-       {
-       .description = "valid",
-       .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       /* class_tid: 2, wh_plus, table: em.int_0 */
-       {
-       .description = "act_rec_ptr",
-       .field_bit_size = 33,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
-               (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-       },
-       {
-       .description = "ext_flow_cntr",
-       .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-       },
-       {
-       .description = "act_rec_int",
-       .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
-       },
-       {
-       .description = "act_rec_size",
-       .field_bit_size = 5,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+               BNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff}
        },
        {
        .description = "key_size",
        .field_bit_size = 9,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               (173 >> 8) & 0xff,
+               173 & 0xff}
        },
        {
        .description = "reserved",
        .field_bit_size = 11,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "strength",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               3}
        },
        {
        .description = "l1_cacheable",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "valid",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               1}
        },
-       /* class_tid: 3, wh_plus, table: int_full_act_record.0 */
+       /* class_tid: 2, wh_plus, table: int_full_act_record.0 */
        {
        .description = "flow_cntr_ptr",
        .field_bit_size = 14,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "age_enable",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "agg_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "rate_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "flow_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_key",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_mir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_match",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "encap_ptr",
        .field_bit_size = 11,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "dst_ip_ptr",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcp_dst_port",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "src_ip_ptr",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcp_src_port",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "meter_id",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "l3_rdir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tl3_rdir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "l3_ttl_dec",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tl3_ttl_dec",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "decap_func",
        .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "vnic_or_vport",
        .field_bit_size = 12,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+       .field_opr1 = {
                (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff,
-               BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff}
        },
        {
        .description = "pop_vlan",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "meter",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "mirror",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "drop",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "hit",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "type",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
-       /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */
+       /* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */
        {
        .description = "l2_cntxt_id",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
        },
        {
        .description = "prof_func_id",
        .field_bit_size = 7,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+       .field_opr1 = {
                (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
-               BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
        },
        {
        .description = "l2_byp_lkup_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "parif",
        .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+       .field_opr1 = {
                (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
-               BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}
        },
        {
        .description = "allowed_pri",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "default_pri",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "allowed_tpid",
        .field_bit_size = 6,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "default_tpid",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "bd_act_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "sp_rec_ptr",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "byp_sp_lkup",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               1}
        },
        {
        .description = "pri_anti_spoof_ctl",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tpid_anti_spoof_ctl",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
-       /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */
+       /* class_tid: 2, wh_plus, table: l2_cntxt_tcam_cache.wr */
        {
        .description = "rid",
        .field_bit_size = 32,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_RID & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_RID & 0xff}
        },
        {
        .description = "l2_cntxt_tcam_index",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
        },
        {
        .description = "l2_cntxt_id",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
        },
        {
        .description = "src_property_ptr",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
-       /* class_tid: 3, wh_plus, table: parif_def_lkup_arec_ptr.0 */
+       /* class_tid: 2, wh_plus, table: parif_def_lkup_arec_ptr.0 */
        {
        .description = "act_rec_ptr",
        .field_bit_size = 32,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
        },
-       /* class_tid: 3, wh_plus, table: parif_def_arec_ptr.0 */
+       /* class_tid: 2, wh_plus, table: parif_def_arec_ptr.0 */
        {
        .description = "act_rec_ptr",
        .field_bit_size = 32,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
        },
-       /* class_tid: 3, wh_plus, table: parif_def_err_arec_ptr.0 */
+       /* class_tid: 2, wh_plus, table: parif_def_err_arec_ptr.0 */
        {
        .description = "act_rec_ptr",
        .field_bit_size = 32,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
        },
-       /* class_tid: 4, wh_plus, table: int_full_act_record.0 */
+       /* class_tid: 3, wh_plus, table: int_full_act_record.0 */
        {
        .description = "flow_cntr_ptr",
        .field_bit_size = 14,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "age_enable",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "agg_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "rate_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "flow_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_key",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_mir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_match",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "encap_ptr",
        .field_bit_size = 11,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "dst_ip_ptr",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcp_dst_port",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "src_ip_ptr",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcp_src_port",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "meter_id",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "l3_rdir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tl3_rdir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "l3_ttl_dec",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tl3_ttl_dec",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "decap_func",
        .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "vnic_or_vport",
        .field_bit_size = 12,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+       .field_opr1 = {
                (BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff,
-               BNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff}
        },
        {
        .description = "pop_vlan",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "meter",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "mirror",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "drop",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "hit",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "type",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
-       /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.vfr_0 */
+       /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_bypass.vfr_0 */
        {
        .description = "act_record_ptr",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "reserved",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "l2_byp_lkup_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               1}
        },
        {
        .description = "parif",
        .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+       .field_opr1 = {
                (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
-               BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
        },
        {
        .description = "allowed_pri",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "default_pri",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "allowed_tpid",
        .field_bit_size = 6,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "default_tpid",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "bd_act_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               1}
        },
        {
        .description = "sp_rec_ptr",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "byp_sp_lkup",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               1}
        },
        {
        .description = "pri_anti_spoof_ctl",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tpid_anti_spoof_ctl",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
-       /* class_tid: 4, wh_plus, table: l2_cntxt_tcam.0 */
+       /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */
        {
        .description = "l2_cntxt_id",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
        },
        {
        .description = "prof_func_id",
        .field_bit_size = 7,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+       .field_opr1 = {
                (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
-               BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
        },
        {
        .description = "l2_byp_lkup_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "parif",
        .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+       .field_opr1 = {
                (BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,
-               BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}
        },
        {
        .description = "allowed_pri",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "default_pri",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "allowed_tpid",
        .field_bit_size = 6,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "default_tpid",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "bd_act_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "sp_rec_ptr",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "byp_sp_lkup",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               1}
        },
        {
        .description = "pri_anti_spoof_ctl",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tpid_anti_spoof_ctl",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
-       /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr */
+       /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */
        {
        .description = "rid",
        .field_bit_size = 32,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_RID & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_RID & 0xff}
        },
        {
        .description = "l2_cntxt_tcam_index",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
        },
        {
        .description = "l2_cntxt_id",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
        },
        {
        .description = "src_property_ptr",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
-       /* class_tid: 4, wh_plus, table: parif_def_lkup_arec_ptr.0 */
+       /* class_tid: 3, wh_plus, table: parif_def_lkup_arec_ptr.0 */
        {
        .description = "act_rec_ptr",
        .field_bit_size = 32,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
        },
-       /* class_tid: 4, wh_plus, table: parif_def_arec_ptr.0 */
+       /* class_tid: 3, wh_plus, table: parif_def_arec_ptr.0 */
        {
        .description = "act_rec_ptr",
        .field_bit_size = 32,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
        },
-       /* class_tid: 4, wh_plus, table: parif_def_err_arec_ptr.0 */
+       /* class_tid: 3, wh_plus, table: parif_def_err_arec_ptr.0 */
        {
        .description = "act_rec_ptr",
        .field_bit_size = 32,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
        },
-       /* class_tid: 5, wh_plus, table: int_vtag_encap_record.egr0 */
+       /* class_tid: 4, wh_plus, table: int_vtag_encap_record.egr0 */
        {
        .description = "ecv_tun_type",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "ecv_l4_type",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "ecv_l3_type",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "ecv_l2_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "ecv_vtag_type",
        .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {
-               BNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               ULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
        },
        {
        .description = "ecv_custom_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "ecv_valid",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "vtag_tpid",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x81, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               0x81,
+               0x00}
        },
        {
        .description = "vtag_vid",
        .field_bit_size = 12,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+       .field_opr1 = {
                (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
-               BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}
        },
        {
        .description = "vtag_de",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "vtag_pcp",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "spare",
        .field_bit_size = 80,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
-       /* class_tid: 5, wh_plus, table: int_full_act_record.egr0 */
+       /* class_tid: 4, wh_plus, table: int_full_act_record.egr0 */
        {
        .description = "flow_cntr_ptr",
        .field_bit_size = 14,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "age_enable",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "agg_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "rate_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "flow_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_key",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_mir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_match",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "encap_ptr",
        .field_bit_size = 11,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}
        },
        {
        .description = "dst_ip_ptr",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcp_dst_port",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "src_ip_ptr",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcp_src_port",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "meter_id",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "l3_rdir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tl3_rdir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "l3_ttl_dec",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tl3_ttl_dec",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "decap_func",
        .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "vnic_or_vport",
        .field_bit_size = 12,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {
-               (BNXT_ULP_WH_PLUS_SYM_LOOPBACK_PORT >> 8) & 0xff,
-               BNXT_ULP_WH_PLUS_SYM_LOOPBACK_PORT & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               (ULP_WP_SYM_LOOPBACK_PORT >> 8) & 0xff,
+               ULP_WP_SYM_LOOPBACK_PORT & 0xff}
        },
        {
        .description = "pop_vlan",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "meter",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "mirror",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "drop",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "hit",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "type",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
-       /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */
+       /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */
        {
        .description = "act_record_ptr",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "reserved",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "l2_byp_lkup_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               1}
        },
        {
        .description = "parif",
        .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "allowed_pri",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "default_pri",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "allowed_tpid",
        .field_bit_size = 6,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "default_tpid",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "bd_act_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               1}
        },
        {
        .description = "sp_rec_ptr",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "byp_sp_lkup",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               1}
        },
        {
        .description = "pri_anti_spoof_ctl",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tpid_anti_spoof_ctl",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
-       /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */
+       /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */
        {
        .description = "rid",
        .field_bit_size = 32,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_RID & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_RID & 0xff}
        },
        {
        .description = "l2_cntxt_tcam_index",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
        },
        {
        .description = "l2_cntxt_id",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "src_property_ptr",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
-       /* class_tid: 5, wh_plus, table: int_full_act_record.ing0 */
+       /* class_tid: 4, wh_plus, table: int_full_act_record.ing0 */
        {
        .description = "flow_cntr_ptr",
        .field_bit_size = 14,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "age_enable",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "agg_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "rate_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "flow_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_key",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_mir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_match",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "encap_ptr",
        .field_bit_size = 11,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "dst_ip_ptr",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcp_dst_port",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "src_ip_ptr",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcp_src_port",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "meter_id",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "l3_rdir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tl3_rdir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "l3_ttl_dec",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tl3_ttl_dec",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "decap_func",
        .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "vnic_or_vport",
        .field_bit_size = 12,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+       .field_opr1 = {
                (BNXT_ULP_CF_IDX_VF_FUNC_VNIC >> 8) & 0xff,
-               BNXT_ULP_CF_IDX_VF_FUNC_VNIC & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_CF_IDX_VF_FUNC_VNIC & 0xff}
        },
        {
        .description = "pop_vlan",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               1}
        },
        {
        .description = "meter",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "mirror",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "drop",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "hit",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "type",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
-       /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.dtagged_ing0 */
+       /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.dtagged_ing0 */
        {
        .description = "act_record_ptr",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
        },
        {
        .description = "reserved",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "l2_byp_lkup_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               1}
        },
        {
        .description = "parif",
        .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "allowed_pri",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "default_pri",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "allowed_tpid",
        .field_bit_size = 6,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "default_tpid",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "bd_act_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "sp_rec_ptr",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "byp_sp_lkup",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               1}
        },
        {
        .description = "pri_anti_spoof_ctl",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tpid_anti_spoof_ctl",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
-       /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */
+       /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */
        {
        .description = "act_record_ptr",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
        },
        {
        .description = "reserved",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "l2_byp_lkup_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               1}
        },
        {
        .description = "parif",
        .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "allowed_pri",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "default_pri",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "allowed_tpid",
        .field_bit_size = 6,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "default_tpid",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "bd_act_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "sp_rec_ptr",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "byp_sp_lkup",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               1}
        },
        {
        .description = "pri_anti_spoof_ctl",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tpid_anti_spoof_ctl",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
-       /* class_tid: 6, wh_plus, table: l2_cntxt_tcam.egr */
+       /* class_tid: 5, wh_plus, table: l2_cntxt_tcam.egr */
        {
        .description = "l2_cntxt_id",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
        },
        {
        .description = "prof_func_id",
        .field_bit_size = 7,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+       .field_opr1 = {
                (BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,
-               BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}
        },
        {
        .description = "l2_byp_lkup_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "parif",
        .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+       .field_opr1 = {
                (BNXT_ULP_CF_IDX_VF_FUNC_PARIF >> 8) & 0xff,
-               BNXT_ULP_CF_IDX_VF_FUNC_PARIF & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_CF_IDX_VF_FUNC_PARIF & 0xff}
        },
        {
        .description = "allowed_pri",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "default_pri",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "allowed_tpid",
        .field_bit_size = 6,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "default_tpid",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "bd_act_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "sp_rec_ptr",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "byp_sp_lkup",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               1}
        },
        {
        .description = "pri_anti_spoof_ctl",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tpid_anti_spoof_ctl",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
-       /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */
+       /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */
        {
        .description = "rid",
        .field_bit_size = 32,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_RID >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_RID & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_RID & 0xff}
        },
        {
        .description = "l2_cntxt_tcam_index",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}
        },
        {
        .description = "l2_cntxt_id",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}
        },
        {
        .description = "src_property_ptr",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
-       /* class_tid: 6, wh_plus, table: parif_def_lkup_arec_ptr.egr */
+       /* class_tid: 5, wh_plus, table: parif_def_lkup_arec_ptr.egr */
        {
        .description = "act_rec_ptr",
        .field_bit_size = 32,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+       .field_opr1 = {
                (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
-               BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
        },
-       /* class_tid: 6, wh_plus, table: parif_def_arec_ptr.egr */
+       /* class_tid: 5, wh_plus, table: parif_def_arec_ptr.egr */
        {
        .description = "act_rec_ptr",
        .field_bit_size = 32,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+       .field_opr1 = {
                (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
-               BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
        },
-       /* class_tid: 6, wh_plus, table: parif_def_err_arec_ptr.egr */
+       /* class_tid: 5, wh_plus, table: parif_def_err_arec_ptr.egr */
        {
        .description = "act_rec_ptr",
        .field_bit_size = 32,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,
+       .field_opr1 = {
                (BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,
-               BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}
        },
-       /* class_tid: 6, wh_plus, table: int_full_act_record.ing */
+       /* class_tid: 5, wh_plus, table: int_full_act_record.ing */
        {
        .description = "flow_cntr_ptr",
        .field_bit_size = 14,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "age_enable",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "agg_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "rate_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "flow_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_key",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_mir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_match",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "encap_ptr",
        .field_bit_size = 11,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "dst_ip_ptr",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcp_dst_port",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "src_ip_ptr",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcp_src_port",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "meter_id",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "l3_rdir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tl3_rdir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "l3_ttl_dec",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tl3_ttl_dec",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "decap_func",
        .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "vnic_or_vport",
        .field_bit_size = 12,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CF,
+       .field_opr1 = {
                (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff,
-               BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff}
        },
        {
        .description = "pop_vlan",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "meter",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "mirror",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "drop",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "hit",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "type",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
-       /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_bypass.ing */
+       /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.ing */
        {
        .description = "act_record_ptr",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,
-       .field_operand = {
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_RF,
+       .field_opr1 = {
                (BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,
-               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+               BNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}
        },
        {
        .description = "reserved",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "l2_byp_lkup_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               1}
        },
        {
        .description = "parif",
        .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "allowed_pri",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "default_pri",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "allowed_tpid",
        .field_bit_size = 6,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "default_tpid",
        .field_bit_size = 3,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "bd_act_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "sp_rec_ptr",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "byp_sp_lkup",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               1}
        },
        {
        .description = "pri_anti_spoof_ctl",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tpid_anti_spoof_ctl",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
-       /* class_tid: 7, wh_plus, table: int_full_act_record.0 */
+       /* class_tid: 6, wh_plus, table: int_full_act_record.0 */
        {
        .description = "flow_cntr_ptr",
        .field_bit_size = 14,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "age_enable",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "agg_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "rate_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "flow_cntr_en",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_key",
        .field_bit_size = 8,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_mir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcpflags_match",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "encap_ptr",
        .field_bit_size = 11,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "dst_ip_ptr",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcp_dst_port",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "src_ip_ptr",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tcp_src_port",
        .field_bit_size = 16,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "meter_id",
        .field_bit_size = 10,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "l3_rdir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tl3_rdir",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "l3_ttl_dec",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "tl3_ttl_dec",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "decap_func",
        .field_bit_size = 4,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "vnic_or_vport",
        .field_bit_size = 12,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,
-       .field_operand = {
-               (BNXT_ULP_WH_PLUS_SYM_LOOPBACK_PORT >> 8) & 0xff,
-               BNXT_ULP_WH_PLUS_SYM_LOOPBACK_PORT & 0xff,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_CONST,
+       .field_opr1 = {
+               (ULP_WP_SYM_LOOPBACK_PORT >> 8) & 0xff,
+               ULP_WP_SYM_LOOPBACK_PORT & 0xff}
        },
        {
        .description = "pop_vlan",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "meter",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "mirror",
        .field_bit_size = 2,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "drop",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "hit",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        },
        {
        .description = "type",
        .field_bit_size = 1,
-       .field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO
+       .field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
+       .field_src1 = BNXT_ULP_FIELD_SRC_ZERO
        }
 };
 
 struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
+       /* class_tid: 1, wh_plus, table: l2_cntxt_tcam_cache.rd */
+       {
+       .description = "l2_cntxt_id",
+       .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
+       .ident_bit_size = 10,
+       .ident_bit_pos = 42
+       },
        /* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */
        {
        .description = "l2_cntxt_id",
@@ -7414,12 +6435,6 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
        },
        /* class_tid: 1, wh_plus, table: profile_tcam_cache.rd */
        {
-       .description = "flow_sig_id",
-       .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
-       .ident_bit_size = 8,
-       .ident_bit_pos = 58
-       },
-       {
        .description = "profile_tcam_index",
        .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
        .ident_bit_size = 10,
@@ -7431,44 +6446,13 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
        .ident_bit_size = 8,
        .ident_bit_pos = 42
        },
-       /* class_tid: 1, wh_plus, table: profile_tcam.0 */
-       {
-       .description = "em_profile_id",
-       .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
-       .ident_type = TF_IDENT_TYPE_EM_PROF,
-       .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
-       .ident_bit_size = 8,
-       .ident_bit_pos = 28
-       },
-       /* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */
-       {
-       .description = "l2_cntxt_id",
-       .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
-       .ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
-       .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
-       .ident_bit_size = 10,
-       .ident_bit_pos = 0
-       },
-       /* class_tid: 2, wh_plus, table: profile_tcam_cache.rd */
-       {
-       .description = "profile_tcam_index",
-       .regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,
-       .ident_bit_size = 10,
-       .ident_bit_pos = 32
-       },
        {
        .description = "flow_sig_id",
        .regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID,
        .ident_bit_size = 8,
        .ident_bit_pos = 58
        },
-       {
-       .description = "em_profile_id",
-       .regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,
-       .ident_bit_size = 8,
-       .ident_bit_pos = 42
-       },
-       /* class_tid: 2, wh_plus, table: profile_tcam.0 */
+       /* class_tid: 1, wh_plus, table: profile_tcam.0 */
        {
        .description = "em_profile_id",
        .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -7477,7 +6461,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
        .ident_bit_size = 8,
        .ident_bit_pos = 28
        },
-       /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */
+       /* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */
        {
        .description = "l2_cntxt_id",
        .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -7486,14 +6470,14 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
        .ident_bit_size = 10,
        .ident_bit_pos = 0
        },
-       /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd */
+       /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.rd */
        {
        .description = "l2_cntxt_id",
        .regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,
        .ident_bit_size = 10,
        .ident_bit_pos = 42
        },
-       /* class_tid: 4, wh_plus, table: l2_cntxt_tcam.0 */
+       /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */
        {
        .description = "l2_cntxt_id",
        .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
@@ -7502,7 +6486,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
        .ident_bit_size = 10,
        .ident_bit_pos = 0
        },
-       /* class_tid: 6, wh_plus, table: l2_cntxt_tcam.egr */
+       /* class_tid: 5, wh_plus, table: l2_cntxt_tcam.egr */
        {
        .description = "l2_cntxt_id",
        .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,

diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index adb2266..02dfb04 100644 (file)
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -160,6 +160,7 @@ struct bnxt_ulp_mapper_cond_list_info {
        enum bnxt_ulp_cond_list_opc cond_list_opcode;
        uint32_t cond_start_idx;
        uint32_t cond_nums;
+       uint32_t cond_goto;
 };
 
 struct bnxt_ulp_template_device_tbls {
@@ -252,12 +253,15 @@ struct bnxt_ulp_mapper_tbl_info {
 };
 
 struct bnxt_ulp_mapper_field_info {
-       uint8_t                 description[64];
-       enum bnxt_ulp_field_opc field_opcode;
-       uint16_t                field_bit_size;
-       uint8_t                 field_operand[16];
-       uint8_t                 field_operand_true[16];
-       uint8_t                 field_operand_false[16];
+       uint8_t                         description[64];
+       uint16_t                        field_bit_size;
+       enum bnxt_ulp_field_cond_src    field_cond_src;
+       uint8_t                         field_cond_opr[16];
+       enum bnxt_ulp_field_src         field_src1;
+       uint8_t                         field_opr1[16];
+       enum bnxt_ulp_field_src         field_src2;
+       uint8_t                         field_opr2[16];
+
 };
 
 struct bnxt_ulp_mapper_key_info {

diff --git a/drivers/net/bnxt/tf_ulp/ulp_tun.c b/drivers/net/bnxt/tf_ulp/ulp_tun.c
index 7661c45..6a65185 100644 (file)
--- a/drivers/net/bnxt/tf_ulp/ulp_tun.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_tun.c
@@ -25,7 +25,7 @@ ulp_install_outer_tun_flow(struct ulp_rte_parser_params *params,
        /* Reset the JUMP action bit in the action bitmap as we don't
         * offload this action.
         */
-       ULP_BITMAP_RESET(params->act_bitmap.bits, BNXT_ULP_ACTION_BIT_JUMP);
+       ULP_BITMAP_RESET(params->act_bitmap.bits, BNXT_ULP_ACT_BIT_JUMP);
 
        ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_F1);
 

diff --git a/drivers/net/bnxt/tf_ulp/ulp_tun.h b/drivers/net/bnxt/tf_ulp/ulp_tun.h
index 8d8fd52..f753038 100644 (file)
--- a/drivers/net/bnxt/tf_ulp/ulp_tun.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_tun.h
@@ -18,7 +18,7 @@
 #define        BNXT_OUTER_TUN_SIGNATURE(l3_tun, params)                \
        ((l3_tun) &&                                    \
         ULP_BITMAP_ISSET((params)->act_bitmap.bits,    \
-                         BNXT_ULP_ACTION_BIT_JUMP))
+                         BNXT_ULP_ACT_BIT_JUMP))
 #define        BNXT_INNER_TUN_SIGNATURE(l3_tun, l3_tun_decap, params)          \
        ((l3_tun) && (l3_tun_decap) &&                                  \
         !ULP_BITMAP_ISSET((params)->hdr_bitmap.bits,                   \