net/ice/base: add macros to parse flow director Rx desc

Add descriptor field offset and mask definition. It is used to parse
FDIR Rx descriptor field value.

Signed-off-by: Yahui Cao <yahui.cao@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>

diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h
index a0e284a..99edcc8 100644 (file)
--- a/drivers/net/ice/base/ice_lan_tx_rx.h
+++ b/drivers/net/ice/base/ice_lan_tx_rx.h
@@ -175,6 +175,50 @@ struct ice_fltr_desc {
                        (0xFFFFFFFFULL << ICE_FXD_FLTR_QW1_FDID_S)
 #define ICE_FXD_FLTR_QW1_FDID_ZERO     0x0ULL
 
+/* definition for FD filter programming status descriptor WB format */
+#define ICE_FXD_FLTR_WB_QW0_BUKT_LEN_S 28
+#define ICE_FXD_FLTR_WB_QW0_BUKT_LEN_M \
+                       (0xFULL << ICE_FXD_FLTR_WB_QW0_BUKT_LEN_S)
+
+#define ICE_FXD_FLTR_WB_QW0_FLTR_STAT_S        32
+#define ICE_FXD_FLTR_WB_QW0_FLTR_STAT_M        \
+                       (0xFFFFFFFFULL << ICE_FXD_FLTR_WB_QW0_FLTR_STAT_S)
+
+#define ICE_FXD_FLTR_WB_QW1_DD_S       0
+#define ICE_FXD_FLTR_WB_QW1_DD_M       (0x1ULL << ICE_FXD_FLTR_WB_QW1_DD_S)
+#define ICE_FXD_FLTR_WB_QW1_DD_YES     0x1ULL
+
+#define ICE_FXD_FLTR_WB_QW1_PROG_ID_S  1
+#define ICE_FXD_FLTR_WB_QW1_PROG_ID_M  \
+                               (0x3ULL << ICE_FXD_FLTR_WB_QW1_PROG_ID_S)
+#define ICE_FXD_FLTR_WB_QW1_PROG_ADD   0x0ULL
+#define ICE_FXD_FLTR_WB_QW1_PROG_DEL   0x1ULL
+
+#define ICE_FXD_FLTR_WB_QW1_FAIL_S     4
+#define ICE_FXD_FLTR_WB_QW1_FAIL_M     (0x1ULL << ICE_FXD_FLTR_WB_QW1_FAIL_S)
+#define ICE_FXD_FLTR_WB_QW1_FAIL_YES   0x1ULL
+
+#define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_S        5
+#define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_M        \
+                               (0x1ULL << ICE_FXD_FLTR_WB_QW1_FAIL_PROF_S)
+#define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_YES      0x1ULL
+
+#define ICE_FXD_FLTR_WB_QW1_FLT_ADDR_S 8
+#define ICE_FXD_FLTR_WB_QW1_FLT_ADDR_M \
+                               (0x3FFFULL << ICE_FXD_FLTR_WB_QW1_FLT_ADDR_S)
+
+#define ICE_FXD_FLTR_WB_QW1_PKT_PROF_S 28
+#define ICE_FXD_FLTR_WB_QW1_PKT_PROF_M \
+                               (0x7FULL << ICE_FXD_FLTR_WB_QW1_PKT_PROF_S)
+
+#define ICE_FXD_FLTR_WB_QW1_BUKT_HASH_S        38
+#define ICE_FXD_FLTR_WB_QW1_BUKT_HASH_M        \
+                               (0x3FFFFFF << ICE_FXD_FLTR_WB_QW1_BUKT_HASH_S)
+
+#define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_M        \
+                               (0x1ULL << ICE_FXD_FLTR_WB_QW1_FAIL_PROF_S)
+#define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_YES      0x1ULL
+
 enum ice_rx_desc_status_bits {
        /* Note: These are predefined bit offsets */
        ICE_RX_DESC_STATUS_DD_S                 = 0,