event/cnxk: fix SSO and TIM argument parsing
authorShijith Thotton <sthotton@marvell.com>
Mon, 30 Aug 2021 16:06:46 +0000 (21:36 +0530)
committerJerin Jacob <jerinj@marvell.com>
Thu, 21 Oct 2021 08:14:50 +0000 (10:14 +0200)
Type of kvargs value and handler function argument should match to avoid
spilling memory.

Fixes: 7ffa7379965e ("event/cnxk: add option to configure getwork mode")
Cc: stable@dpdk.org
Signed-off-by: Shijith Thotton <sthotton@marvell.com>
drivers/event/cnxk/cnxk_eventdev.c
drivers/event/cnxk/cnxk_tim_evdev.h

index 9a87239..9deab08 100644 (file)
@@ -665,11 +665,11 @@ cnxk_sso_parse_devargs(struct cnxk_sso_evdev *dev, struct rte_devargs *devargs)
                           &dev->xae_cnt);
        rte_kvargs_process(kvlist, CNXK_SSO_GGRP_QOS, &parse_sso_kvargs_dict,
                           dev);
-       rte_kvargs_process(kvlist, CNXK_SSO_FORCE_BP, &parse_kvargs_value,
+       rte_kvargs_process(kvlist, CNXK_SSO_FORCE_BP, &parse_kvargs_flag,
                           &dev->force_ena_bp);
-       rte_kvargs_process(kvlist, CN9K_SSO_SINGLE_WS, &parse_kvargs_value,
+       rte_kvargs_process(kvlist, CN9K_SSO_SINGLE_WS, &parse_kvargs_flag,
                           &single_ws);
-       rte_kvargs_process(kvlist, CN10K_SSO_GW_MODE, &parse_kvargs_value,
+       rte_kvargs_process(kvlist, CN10K_SSO_GW_MODE, &parse_kvargs_flag,
                           &dev->gw_mode);
        dev->dual_ws = !single_ws;
        rte_kvargs_free(kvlist);
index c369f6f..8e25cef 100644 (file)
@@ -90,8 +90,8 @@ struct cnxk_tim_evdev {
        uint32_t chunk_sz;
        /* Dev args */
        uint8_t disable_npa;
-       uint16_t chunk_slots;
-       uint16_t min_ring_cnt;
+       uint32_t chunk_slots;
+       uint32_t min_ring_cnt;
        uint8_t enable_stats;
        uint16_t ring_ctl_cnt;
        struct cnxk_tim_ctl *ring_ctl_data;