crypto/qat: add MD5 HMAC capability

Added posibility to compute MD5 HMAC digest with Intel QuickAssist
Technology driver.

Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Signed-off-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>

diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index cae1958..485abb4 100644 (file)
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -57,6 +57,7 @@ Hash algorithms:
 * ``RTE_CRYPTO_AUTH_SHA512_HMAC``
 * ``RTE_CRYPTO_AUTH_AES_XCBC_MAC``
 * ``RTE_CRYPTO_AUTH_SNOW3G_UIA2``
+* ``RTE_CRYPTO_AUTH_MD5_HMAC``
 
 
 Limitations

diff --git a/doc/guides/rel_notes/release_16_11.rst b/doc/guides/rel_notes/release_16_11.rst
index e7f3967..7ba66dc 100644 (file)
--- a/doc/guides/rel_notes/release_16_11.rst
+++ b/doc/guides/rel_notes/release_16_11.rst
@@ -64,6 +64,12 @@ New Features
   * increase mailbox version to ixgbe_mbox_api_13
   * add two MAC ops for Hyper-V support
 
+* **Updated the QAT PMD.**
+
+  The QAT PMD was updated with following support:
+
+  * MD5_HMAC algorithm
+
 
 Resolved Issues
 ---------------

diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
index c658f6e..6de695e 100644 (file)
--- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
+++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
@@ -58,6 +58,7 @@
 
 #include <openssl/sha.h>       /* Needed to calculate pre-compute values */
 #include <openssl/aes.h>       /* Needed to calculate pre-compute values */
+#include <openssl/md5.h>       /* Needed to calculate pre-compute values */
 
 
 /*
@@ -86,6 +87,9 @@ static int qat_hash_get_state1_size(enum icp_qat_hw_auth_algo qat_hash_alg)
        case ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2:
                return QAT_HW_ROUND_UP(ICP_QAT_HW_SNOW_3G_UIA2_STATE1_SZ,
                                                QAT_HW_DEFAULT_ALIGNMENT);
+       case ICP_QAT_HW_AUTH_ALGO_MD5:
+               return QAT_HW_ROUND_UP(ICP_QAT_HW_MD5_STATE1_SZ,
+                                               QAT_HW_DEFAULT_ALIGNMENT);
        case ICP_QAT_HW_AUTH_ALGO_DELIMITER:
                /* return maximum state1 size in this case */
                return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA512_STATE1_SZ,
@@ -107,6 +111,8 @@ static int qat_hash_get_digest_size(enum icp_qat_hw_auth_algo qat_hash_alg)
                return ICP_QAT_HW_SHA256_STATE1_SZ;
        case ICP_QAT_HW_AUTH_ALGO_SHA512:
                return ICP_QAT_HW_SHA512_STATE1_SZ;
+       case ICP_QAT_HW_AUTH_ALGO_MD5:
+               return ICP_QAT_HW_MD5_STATE1_SZ;
        case ICP_QAT_HW_AUTH_ALGO_DELIMITER:
                /* return maximum digest size in this case */
                return ICP_QAT_HW_SHA512_STATE1_SZ;
@@ -129,6 +135,8 @@ static int qat_hash_get_block_size(enum icp_qat_hw_auth_algo qat_hash_alg)
                return SHA512_CBLOCK;
        case ICP_QAT_HW_AUTH_ALGO_GALOIS_128:
                return 16;
+       case ICP_QAT_HW_AUTH_ALGO_MD5:
+               return MD5_CBLOCK;
        case ICP_QAT_HW_AUTH_ALGO_DELIMITER:
                /* return maximum block size in this case */
                return SHA512_CBLOCK;
@@ -172,6 +180,18 @@ static int partial_hash_sha512(uint8_t *data_in, uint8_t *data_out)
        return 0;
 }
 
+static int partial_hash_md5(uint8_t *data_in, uint8_t *data_out)
+{
+       MD5_CTX ctx;
+
+       if (!MD5_Init(&ctx))
+               return -EFAULT;
+       MD5_Transform(&ctx, data_in);
+       rte_memcpy(data_out, &ctx, MD5_DIGEST_LENGTH);
+
+       return 0;
+}
+
 static int partial_hash_compute(enum icp_qat_hw_auth_algo hash_alg,
                        uint8_t *data_in,
                        uint8_t *data_out)
@@ -213,6 +233,10 @@ static int partial_hash_compute(enum icp_qat_hw_auth_algo hash_alg,
                        *hash_state_out_be64 =
                                rte_bswap64(*(((uint64_t *)digest)+i));
                break;
+       case ICP_QAT_HW_AUTH_ALGO_MD5:
+               if (partial_hash_md5(data_in, data_out))
+                       return -EFAULT;
+               break;
        default:
                PMD_DRV_LOG(ERR, "invalid hash alg %u", hash_alg);
                return -EFAULT;
@@ -620,6 +644,15 @@ int qat_alg_aead_session_create_content_desc_auth(struct qat_session *cdesc,
                auth_param->hash_state_sz =
                                RTE_ALIGN_CEIL(add_auth_data_length, 16) >> 3;
                break;
+       case ICP_QAT_HW_AUTH_ALGO_MD5:
+               if (qat_alg_do_precomputes(ICP_QAT_HW_AUTH_ALGO_MD5,
+                       authkey, authkeylen, cdesc->cd_cur_ptr,
+                       &state1_size)) {
+                       PMD_DRV_LOG(ERR, "(MD5)precompute failed");
+                       return -EFAULT;
+               }
+               state2_size = ICP_QAT_HW_MD5_STATE2_SZ;
+               break;
        default:
                PMD_DRV_LOG(ERR, "Invalid HASH alg %u", cdesc->qat_hash_alg);
                return -EFAULT;

diff --git a/drivers/crypto/qat/qat_crypto.c b/drivers/crypto/qat/qat_crypto.c
index 362dc01..d428149 100644 (file)
--- a/drivers/crypto/qat/qat_crypto.c
+++ b/drivers/crypto/qat/qat_crypto.c
@@ -131,6 +131,27 @@ static const struct rte_cryptodev_capabilities qat_pmd_capabilities[] = {
                        }, }
                }, }
        },
+       {       /* MD5 HMAC */
+               .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+               {.sym = {
+                       .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+                       {.auth = {
+                               .algo = RTE_CRYPTO_AUTH_MD5_HMAC,
+                               .block_size = 64,
+                               .key_size = {
+                                       .min = 8,
+                                       .max = 64,
+                                       .increment = 8
+                               },
+                               .digest_size = {
+                                       .min = 16,
+                                       .max = 16,
+                                       .increment = 0
+                               },
+                               .aad_size = { 0 }
+                       }, }
+               }, }
+       },
        {       /* AES XCBC MAC */
                .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
                {.sym = {
@@ -526,6 +547,9 @@ qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
        case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
                session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2;
                break;
+       case RTE_CRYPTO_AUTH_MD5_HMAC:
+               session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_MD5;
+               break;
        case RTE_CRYPTO_AUTH_NULL:
        case RTE_CRYPTO_AUTH_SHA1:
        case RTE_CRYPTO_AUTH_SHA256:
@@ -535,7 +559,6 @@ qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
        case RTE_CRYPTO_AUTH_SHA384:
        case RTE_CRYPTO_AUTH_SHA384_HMAC:
        case RTE_CRYPTO_AUTH_MD5:
-       case RTE_CRYPTO_AUTH_MD5_HMAC:
        case RTE_CRYPTO_AUTH_AES_CCM:
        case RTE_CRYPTO_AUTH_AES_GMAC:
        case RTE_CRYPTO_AUTH_KASUMI_F9:
@@ -574,7 +597,8 @@ qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
        return session;
 
 error_out:
-       rte_mempool_put(internals->sess_mp, session);
+       if (internals->sess_mp != NULL)
+               rte_mempool_put(internals->sess_mp, session);
        return NULL;
 }