}
return -EINVAL;
}
+
+/*
+ * Api to get the phy port for a given port id.
+ *
+ * ulp_ctxt [in] Ptr to ulp context
+ * port_id [in] device port id
+ * phy_port [out] phy_port of the dpdk port_id
+ *
+ * Returns 0 on success or negative number on failure.
+ */
+int32_t
+ulp_port_db_phy_port_get(struct bnxt_ulp_context *ulp_ctxt,
+ uint32_t port_id, uint16_t *phy_port)
+{
+ struct ulp_func_if_info *info;
+
+ info = ulp_port_db_func_if_info_get(ulp_ctxt, port_id);
+ if (info) {
+ *phy_port = info->phy_port_id;
+ return 0;
+ }
+ return -EINVAL;
+}
ulp_port_db_parent_vnic_get(struct bnxt_ulp_context *ulp_ctxt,
uint32_t port_id, uint8_t **vnic);
+/*
+ * Api to get the phy port for a given port id.
+ *
+ * ulp_ctxt [in] Ptr to ulp context
+ * port_id [in] device port id
+ * phy_port [out] phy_port of the dpdk port_id
+ *
+ * Returns 0 on success or negative number on failure.
+ */
+int32_t
+ulp_port_db_phy_port_get(struct bnxt_ulp_context *ulp_ctxt,
+ uint32_t port_id, uint16_t *phy_port);
+
#endif /* _ULP_PORT_DB_H_ */
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_SVIF_FLAG,
rte_be_to_cpu_16(svif));
if (!mask) {
+ uint32_t port_id = 0;
+ uint16_t phy_port = 0;
+
+ /* Validate the control port */
+ port_id = ULP_COMP_FLD_IDX_RD(params,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID);
+ if (ulp_port_db_phy_port_get(params->ulp_ctx,
+ port_id, &phy_port) ||
+ (uint16_t)port_spec->index != phy_port) {
+ BNXT_TF_DBG(ERR, "Mismatch of control and phy_port\n");
+ return BNXT_TF_RC_PARSE_ERR;
+ }
ULP_BITMAP_SET(params->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_SVIF_IGNORE);
memset(hdr_field->mask, 0xFF, sizeof(mask));