u8 reserved_at_100[0x100];
};
+struct mlx5_ifc_fte_match_set_misc5_bits {
+ u8 macsec_tag_0[0x20];
+ u8 macsec_tag_1[0x20];
+ u8 macsec_tag_2[0x20];
+ u8 macsec_tag_3[0x20];
+ u8 tunnel_header_0[0x20];
+ u8 tunnel_header_1[0x20];
+ u8 tunnel_header_2[0x20];
+ u8 tunnel_header_3[0x20];
+ u8 reserved[0x100];
+};
+
/* Flow matcher. */
struct mlx5_ifc_fte_match_param_bits {
struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
+ struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5;
/*
* Add reserved bit to match the struct size with the size defined in PRM.
* This extension is not required in Linux.
*/
#ifndef HAVE_INFINIBAND_VERBS_H
- u8 reserved_0[0x400];
+ u8 reserved_0[0x200];
#endif
};
MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT,
MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT,
MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT,
+ MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT,
};
enum {
* Table 1872 - Flow Table Fields Supported 2 Format
*/
struct mlx5_ifc_ft_fields_support_2_bits {
- u8 reserved_at_0[0x14];
+ u8 reserved_at_0[0xf];
+ u8 tunnel_header_2_3[0x1];
+ u8 tunnel_header_0_1[0x1];
+ u8 macsec_syndrome[0x1];
+ u8 macsec_tag[0x1];
+ u8 outer_lrh_sl[0x1];
u8 inner_ipv4_ihl[0x1];
u8 outer_ipv4_ihl[0x1];
u8 psp_syndrome[0x1];
u8 inner_l4_checksum_ok[0x1];
u8 outer_ipv4_checksum_ok[0x1];
u8 outer_l4_checksum_ok[0x1];
+ u8 reserved_at_20[0x60];
};
struct mlx5_ifc_flow_table_nic_cap_bits {
u8 reserved_at_0[0x200];
struct mlx5_ifc_flow_table_prop_layout_bits
- flow_table_properties_nic_receive;
+ flow_table_properties_nic_receive;
+ struct mlx5_ifc_flow_table_prop_layout_bits
+ flow_table_properties_nic_receive_rdma;
+ struct mlx5_ifc_flow_table_prop_layout_bits
+ flow_table_properties_nic_receive_sniffer;
+ struct mlx5_ifc_flow_table_prop_layout_bits
+ flow_table_properties_nic_transmit;
+ struct mlx5_ifc_flow_table_prop_layout_bits
+ flow_table_properties_nic_transmit_rdma;
struct mlx5_ifc_flow_table_prop_layout_bits
- flow_table_properties_unused[5];
- u8 reserved_at_1C0[0x200];
- u8 header_modify_nic_receive[0x400];
+ flow_table_properties_nic_transmit_sniffer;
+ u8 reserved_at_e00[0x600];
struct mlx5_ifc_ft_fields_support_2_bits
- ft_field_support_2_nic_receive;
+ ft_field_support_2_nic_receive;
};
struct mlx5_ifc_cmd_hca_cap_2_bits {
return ret;
}
+/**
+ * Detect misc5 support or not
+ *
+ * @param[in] priv
+ * Device private data pointer
+ */
+#ifdef HAVE_MLX5DV_DR
+static void
+__mlx5_discovery_misc5_cap(struct mlx5_priv *priv)
+{
+#ifdef HAVE_IBV_FLOW_DV_SUPPORT
+ /* Dummy VxLAN matcher to detect rdma-core misc5 cap
+ * Case: IPv4--->UDP--->VxLAN--->vni
+ */
+ void *tbl;
+ struct mlx5_flow_dv_match_params matcher_mask;
+ void *match_m;
+ void *matcher;
+ void *headers_m;
+ void *misc5_m;
+ uint32_t *tunnel_header_m;
+ struct mlx5dv_flow_matcher_attr dv_attr;
+
+ memset(&matcher_mask, 0, sizeof(matcher_mask));
+ matcher_mask.size = sizeof(matcher_mask.buf);
+ match_m = matcher_mask.buf;
+ headers_m = MLX5_ADDR_OF(fte_match_param, match_m, outer_headers);
+ misc5_m = MLX5_ADDR_OF(fte_match_param,
+ match_m, misc_parameters_5);
+ tunnel_header_m = (uint32_t *)
+ MLX5_ADDR_OF(fte_match_set_misc5,
+ misc5_m, tunnel_header_1);
+ MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
+ MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 4);
+ MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
+ *tunnel_header_m = 0xffffff;
+
+ tbl = mlx5_glue->dr_create_flow_tbl(priv->sh->rx_domain, 1);
+ if (!tbl) {
+ DRV_LOG(INFO, "No SW steering support");
+ return;
+ }
+ dv_attr.type = IBV_FLOW_ATTR_NORMAL,
+ dv_attr.match_mask = (void *)&matcher_mask,
+ dv_attr.match_criteria_enable =
+ (1 << MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT) |
+ (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT);
+ dv_attr.priority = 3;
+#ifdef HAVE_MLX5DV_DR_ESWITCH
+ void *misc2_m;
+ if (priv->config.dv_esw_en) {
+ /* FDB enabled reg_c_0 */
+ dv_attr.match_criteria_enable |=
+ (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT);
+ misc2_m = MLX5_ADDR_OF(fte_match_param,
+ match_m, misc_parameters_2);
+ MLX5_SET(fte_match_set_misc2, misc2_m,
+ metadata_reg_c_0, 0xffff);
+ }
+#endif
+ matcher = mlx5_glue->dv_create_flow_matcher(priv->sh->ctx,
+ &dv_attr, tbl);
+ if (matcher) {
+ priv->sh->misc5_cap = 1;
+ mlx5_glue->dv_destroy_flow_matcher(matcher);
+ }
+ mlx5_glue->dr_destroy_flow_tbl(tbl);
+#else
+ RTE_SET_USED(priv);
+#endif
+}
+#endif
+
/**
* Verbs callback to free a memory.
*
if (sh->fdb_domain)
mlx5_glue->dr_allow_duplicate_rules(sh->fdb_domain, 0);
}
+
+ __mlx5_discovery_misc5_cap(priv);
#endif /* HAVE_MLX5DV_DR */
sh->default_miss_action =
mlx5_glue->dr_create_flow_action_default_miss();
goto error;
}
}
+ if (config->hca_attr.flow.tunnel_header_0_1)
+ sh->tunnel_header_0_1 = 1;
#endif
#ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
if (config->hca_attr.flow_hit_aso &&
last_item = MLX5_FLOW_LAYER_GRE_KEY;
break;
case RTE_FLOW_ITEM_TYPE_VXLAN:
- ret = mlx5_flow_validate_item_vxlan(items, item_flags,
+ ret = mlx5_flow_validate_item_vxlan(dev, items,
+ item_flags, attr,
error);
if (ret < 0)
return ret;
memset(dev_flow, 0, sizeof(*dev_flow));
dev_flow->handle = dev_handle;
dev_flow->handle_idx = handle_idx;
- /*
- * In some old rdma-core releases, before continuing, a check of the
- * length of matching parameter will be done at first. It needs to use
- * the length without misc4 param. If the flow has misc4 support, then
- * the length needs to be adjusted accordingly. Each param member is
- * aligned with a 64B boundary naturally.
- */
- dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
- MLX5_ST_SZ_BYTES(fte_match_set_misc4);
+ dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
dev_flow->ingress = attr->ingress;
dev_flow->dv.transfer = attr->transfer;
return dev_flow;
/**
* Add VXLAN item to matcher and to the value.
*
+ * @param[in] dev
+ * Pointer to the Ethernet device structure.
+ * @param[in] attr
+ * Flow rule attributes.
* @param[in, out] matcher
* Flow matcher.
* @param[in, out] key
* Item is inner pattern.
*/
static void
-flow_dv_translate_item_vxlan(void *matcher, void *key,
+flow_dv_translate_item_vxlan(struct rte_eth_dev *dev,
+ const struct rte_flow_attr *attr,
+ void *matcher, void *key,
const struct rte_flow_item *item,
int inner)
{
const struct rte_flow_item_vxlan *vxlan_v = item->spec;
void *headers_m;
void *headers_v;
- void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
- void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
- char *vni_m;
- char *vni_v;
+ void *misc5_m;
+ void *misc5_v;
+ uint32_t *tunnel_header_v;
+ uint32_t *tunnel_header_m;
uint16_t dport;
- int size;
- int i;
+ struct mlx5_priv *priv = dev->data->dev_private;
+ const struct rte_flow_item_vxlan nic_mask = {
+ .vni = "\xff\xff\xff",
+ .rsvd1 = 0xff,
+ };
if (inner) {
headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
}
if (!vxlan_v)
return;
- if (!vxlan_m)
- vxlan_m = &rte_flow_item_vxlan_mask;
- size = sizeof(vxlan_m->vni);
- vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
- vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
- memcpy(vni_m, vxlan_m->vni, size);
- for (i = 0; i < size; ++i)
- vni_v[i] = vni_m[i] & vxlan_v->vni[i];
+ if (!vxlan_m) {
+ if ((!attr->group && !priv->sh->tunnel_header_0_1) ||
+ (attr->group && !priv->sh->misc5_cap))
+ vxlan_m = &rte_flow_item_vxlan_mask;
+ else
+ vxlan_m = &nic_mask;
+ }
+ if ((!attr->group && !attr->transfer && !priv->sh->tunnel_header_0_1) ||
+ ((attr->group || attr->transfer) && !priv->sh->misc5_cap)) {
+ void *misc_m;
+ void *misc_v;
+ char *vni_m;
+ char *vni_v;
+ int size;
+ int i;
+ misc_m = MLX5_ADDR_OF(fte_match_param,
+ matcher, misc_parameters);
+ misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
+ size = sizeof(vxlan_m->vni);
+ vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
+ vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
+ memcpy(vni_m, vxlan_m->vni, size);
+ for (i = 0; i < size; ++i)
+ vni_v[i] = vni_m[i] & vxlan_v->vni[i];
+ return;
+ }
+ misc5_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_5);
+ misc5_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_5);
+ tunnel_header_v = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
+ misc5_v,
+ tunnel_header_1);
+ tunnel_header_m = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
+ misc5_m,
+ tunnel_header_1);
+ *tunnel_header_v = (vxlan_v->vni[0] & vxlan_m->vni[0]) |
+ (vxlan_v->vni[1] & vxlan_m->vni[1]) << 8 |
+ (vxlan_v->vni[2] & vxlan_m->vni[2]) << 16;
+ if (*tunnel_header_v)
+ *tunnel_header_m = vxlan_m->vni[0] |
+ vxlan_m->vni[1] << 8 |
+ vxlan_m->vni[2] << 16;
+ else
+ *tunnel_header_m = 0x0;
+ *tunnel_header_v |= (vxlan_v->rsvd1 & vxlan_m->rsvd1) << 24;
+ if (vxlan_v->rsvd1 & vxlan_m->rsvd1)
+ *tunnel_header_m |= vxlan_m->rsvd1 << 24;
}
/**
match_criteria_enable |=
(!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
+ match_criteria_enable |=
+ (!HEADER_IS_ZERO(match_criteria, misc_parameters_5)) <<
+ MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT;
return match_criteria_enable;
}
+static void
+__flow_dv_adjust_buf_size(size_t *size, uint8_t match_criteria)
+{
+ /*
+ * Check flow matching criteria first, subtract misc5/4 length if flow
+ * doesn't own misc5/4 parameters. In some old rdma-core releases,
+ * misc5/4 are not supported, and matcher creation failure is expected
+ * w/o subtration. If misc5 is provided, misc4 must be counted in since
+ * misc5 is right after misc4.
+ */
+ if (!(match_criteria & (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT))) {
+ *size = MLX5_ST_SZ_BYTES(fte_match_param) -
+ MLX5_ST_SZ_BYTES(fte_match_set_misc5);
+ if (!(match_criteria & (1 <<
+ MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT))) {
+ *size -= MLX5_ST_SZ_BYTES(fte_match_set_misc4);
+ }
+ }
+}
+
struct mlx5_hlist_entry *
flow_dv_tbl_create_cb(struct mlx5_hlist *list, uint64_t key64, void *cb_ctx)
{
*cache = *ref;
dv_attr.match_criteria_enable =
flow_dv_matcher_enable(cache->mask.buf);
+ __flow_dv_adjust_buf_size(&ref->mask.size,
+ dv_attr.match_criteria_enable);
dv_attr.priority = ref->priority;
if (tbl->is_egress)
dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
.error = error,
.data = ref,
};
-
/**
* tunnel offload API requires this registration for cases when
* tunnel match rule was inserted before tunnel set rule.
uint64_t action_flags = 0;
struct mlx5_flow_dv_matcher matcher = {
.mask = {
- .size = sizeof(matcher.mask.buf) -
- MLX5_ST_SZ_BYTES(fte_match_set_misc4),
+ .size = sizeof(matcher.mask.buf),
},
};
int actions_n = 0;
last_item = MLX5_FLOW_LAYER_GRE;
break;
case RTE_FLOW_ITEM_TYPE_VXLAN:
- flow_dv_translate_item_vxlan(match_mask, match_value,
+ flow_dv_translate_item_vxlan(dev, attr,
+ match_mask, match_value,
items, tunnel);
matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
last_item = MLX5_FLOW_LAYER_VXLAN;
NULL,
"cannot create eCPRI parser");
}
- /* Adjust the length matcher and device flow value. */
- matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
- dev_flow->dv.value.size =
- MLX5_ST_SZ_BYTES(fte_match_param);
flow_dv_translate_item_ecpri(dev, match_mask,
match_value, items);
/* No other protocol should follow eCPRI layer. */
int idx;
struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
+ uint8_t misc_mask;
MLX5_ASSERT(wks);
for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
}
dv->actions[n++] = priv->sh->default_miss_action;
}
+ misc_mask = flow_dv_matcher_enable(dv->value.buf);
+ __flow_dv_adjust_buf_size(&dv->value.size, misc_mask);
err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
(void *)&dv->value, n,
dv->actions, &dh->drv_flow);
{
int ret;
struct mlx5_flow_dv_match_params value = {
- .size = sizeof(value.buf) -
- MLX5_ST_SZ_BYTES(fte_match_set_misc4),
+ .size = sizeof(value.buf),
};
struct mlx5_flow_dv_match_params matcher = {
- .size = sizeof(matcher.buf) -
- MLX5_ST_SZ_BYTES(fte_match_set_misc4),
+ .size = sizeof(matcher.buf),
};
struct mlx5_priv *priv = dev->data->dev_private;
+ uint8_t misc_mask;
if (match_src_port && (priv->representor || priv->master)) {
if (flow_dv_translate_item_port_id(dev, matcher.buf,
(enum modify_reg)color_reg_c_idx,
rte_col_2_mlx5_col(color),
UINT32_MAX);
+ misc_mask = flow_dv_matcher_enable(value.buf);
+ __flow_dv_adjust_buf_size(&value.size, misc_mask);
ret = mlx5_flow_os_create_flow(matcher_object,
(void *)&value, actions_n, actions, rule);
if (ret) {
struct mlx5_flow_tbl_resource *tbl_rsc = sub_policy->tbl_rsc;
struct mlx5_flow_dv_matcher matcher = {
.mask = {
- .size = sizeof(matcher.mask.buf) -
- MLX5_ST_SZ_BYTES(fte_match_set_misc4),
+ .size = sizeof(matcher.mask.buf),
},
.tbl = tbl_rsc,
};
struct mlx5_flow_dv_match_params value = {
- .size = sizeof(value.buf) -
- MLX5_ST_SZ_BYTES(fte_match_set_misc4),
+ .size = sizeof(value.buf),
};
struct mlx5_flow_cb_ctx ctx = {
.error = error,
int domain, ret, i;
struct mlx5_flow_counter *cnt;
struct mlx5_flow_dv_match_params value = {
- .size = sizeof(value.buf) -
- MLX5_ST_SZ_BYTES(fte_match_set_misc4),
+ .size = sizeof(value.buf),
};
struct mlx5_flow_dv_match_params matcher_para = {
- .size = sizeof(matcher_para.buf) -
- MLX5_ST_SZ_BYTES(fte_match_set_misc4),
+ .size = sizeof(matcher_para.buf),
};
int mtr_id_reg_c = mlx5_flow_get_reg_id(dev, MLX5_MTR_ID,
0, &error);
struct mlx5_cache_entry *entry;
struct mlx5_flow_dv_matcher matcher = {
.mask = {
- .size = sizeof(matcher.mask.buf) -
- MLX5_ST_SZ_BYTES(fte_match_set_misc4),
+ .size = sizeof(matcher.mask.buf),
},
};
struct mlx5_flow_dv_matcher *drop_matcher;
.error = &error,
.data = &matcher,
};
+ uint8_t misc_mask;
if (!priv->mtr_en || mtr_id_reg_c < 0) {
rte_errno = ENOTSUP;
actions[i++] = priv->sh->dr_drop_action;
flow_dv_match_meta_reg(matcher_para.buf, value.buf,
(enum modify_reg)mtr_id_reg_c, 0, 0);
+ misc_mask = flow_dv_matcher_enable(value.buf);
+ __flow_dv_adjust_buf_size(&value.size, misc_mask);
ret = mlx5_flow_os_create_flow
(mtrmng->def_matcher[domain]->matcher_object,
(void *)&value, i, actions,
fm->drop_cnt, NULL);
actions[i++] = cnt->action;
actions[i++] = priv->sh->dr_drop_action;
+ misc_mask = flow_dv_matcher_enable(value.buf);
+ __flow_dv_adjust_buf_size(&value.size, misc_mask);
ret = mlx5_flow_os_create_flow(drop_matcher->matcher_object,
(void *)&value, i, actions,
&fm->drop_rule[domain]);
if (ret)
goto err;
dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
+ __flow_dv_adjust_buf_size(&mask.size, dv_attr.match_criteria_enable);
ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
&matcher);
if (ret)
goto err;
+ __flow_dv_adjust_buf_size(&value.size, dv_attr.match_criteria_enable);
ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 1,
actions, &flow);
err:
git.droids-corp.org / dpdk.git / commitdiff