common/mlx5: read software parsing capabilities from DevX
authorTal Shnaiderman <talshn@nvidia.com>
Tue, 12 Oct 2021 12:45:43 +0000 (15:45 +0300)
committerRaslan Darawsheh <rasland@nvidia.com>
Tue, 12 Oct 2021 13:29:33 +0000 (15:29 +0200)
mlx5 in Windows needs the software parsing hca capabilities
to query the NIC for TSO and Checksum offloading support.

Added the capability as part of the capabilities
queried by the PMD using DevX.

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Tested-by: Idan Hackmon <idanhac@nvidia.com>
drivers/common/mlx5/mlx5_devx_cmds.c
drivers/common/mlx5/mlx5_devx_cmds.h

index eefb869..ee2388c 100644 (file)
@@ -1000,6 +1000,12 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
                                        hcattr, tunnel_lro_gre);
        attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps,
                                          hcattr, tunnel_lro_vxlan);
+       attr->swp = MLX5_GET(per_protocol_networking_offload_caps,
+                                         hcattr, swp);
+       attr->swp_csum = MLX5_GET(per_protocol_networking_offload_caps,
+                                         hcattr, swp_csum);
+       attr->swp_lso = MLX5_GET(per_protocol_networking_offload_caps,
+                                         hcattr, swp_lso);
        attr->lro_max_msg_sz_mode = MLX5_GET
                                        (per_protocol_networking_offload_caps,
                                         hcattr, lro_max_msg_sz_mode);
index e149f8b..857a4e7 100644 (file)
@@ -116,6 +116,9 @@ struct mlx5_hca_attr {
        uint32_t lro_cap:1;
        uint32_t tunnel_lro_gre:1;
        uint32_t tunnel_lro_vxlan:1;
+       uint32_t swp:1;
+       uint32_t swp_csum:1;
+       uint32_t swp_lso:1;
        uint32_t lro_max_msg_sz_mode:2;
        uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];
        uint16_t lro_min_mss_size;