common/cnxk: support CNF95xx B0 variant

Add CNF95xx B0 variant to the list of supported models.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>

diff --git a/doc/guides/rel_notes/release_22_03.rst b/doc/guides/rel_notes/release_22_03.rst
index 31f73030505019a3b1dcb80547f79b981f6e7eb2..40045c3e8854635fdd46a30339f4ec387367496a 100644 (file)
--- a/doc/guides/rel_notes/release_22_03.rst
+++ b/doc/guides/rel_notes/release_22_03.rst
@@ -162,6 +162,7 @@ New Features
   * Added queue based priority flow control support for CN9K & CN10K.
   * Added support for IP reassembly for inline inbound IPsec packets.
   * Added support for packet marking in traffic manager.
+  * Added support for CNF95xx B0 variant SoC.
 
 * **Updated Mellanox mlx5 driver.**
 

diff --git a/drivers/common/cnxk/roc_model.c b/drivers/common/cnxk/roc_model.c
index 49617c02b77c3b0d89cd26d637c55f8b4ec0ccf5..4120029541fffb0206747e93f13c4f84cce7045a 100644 (file)
--- a/drivers/common/cnxk/roc_model.c
+++ b/drivers/common/cnxk/roc_model.c
@@ -56,6 +56,7 @@ static const struct model_db {
        {VENDOR_CAVIUM, PART_95xx, 1, 0, ROC_MODEL_CNF95xx_B0, "cnf95xx_b0"},
        {VENDOR_CAVIUM, PART_95xxN, 0, 0, ROC_MODEL_CNF95xxN_A0, "cnf95xxn_a0"},
        {VENDOR_CAVIUM, PART_95xxN, 0, 1, ROC_MODEL_CNF95xxN_A0, "cnf95xxn_a1"},
+       {VENDOR_CAVIUM, PART_95xxN, 1, 0, ROC_MODEL_CNF95xxN_B0, "cnf95xxn_b0"},
        {VENDOR_CAVIUM, PART_95O, 0, 0, ROC_MODEL_CNF95xxO_A0, "cnf95O_a0"},
        {VENDOR_CAVIUM, PART_95xxMM, 0, 0, ROC_MODEL_CNF95xxMM_A0,
         "cnf95xxmm_a0"}};

diff --git a/drivers/common/cnxk/roc_model.h b/drivers/common/cnxk/roc_model.h
index cee06779bc19114615c2bb68612808589511a792..4567566169a33cae8c2c94b145588ca9832245a7 100644 (file)
--- a/drivers/common/cnxk/roc_model.h
+++ b/drivers/common/cnxk/roc_model.h
@@ -19,6 +19,7 @@ struct roc_model {
 #define ROC_MODEL_CNF95xxN_A0  BIT_ULL(12)
 #define ROC_MODEL_CNF95xxO_A0  BIT_ULL(13)
 #define ROC_MODEL_CNF95xxN_A1  BIT_ULL(14)
+#define ROC_MODEL_CNF95xxN_B0  BIT_ULL(15)
 #define ROC_MODEL_CN98xx_A0    BIT_ULL(16)
 #define ROC_MODEL_CN106xx_A0   BIT_ULL(20)
 #define ROC_MODEL_CNF105xx_A0  BIT_ULL(21)
@@ -39,11 +40,12 @@ struct roc_model {
        (ROC_MODEL_CN96xx_Ax | ROC_MODEL_CN96xx_C0 | ROC_MODEL_CNF95xx_A0 |    \
         ROC_MODEL_CNF95xx_B0 | ROC_MODEL_CNF95xxMM_A0 |                       \
         ROC_MODEL_CNF95xxO_A0 | ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CN98xx_A0 | \
-        ROC_MODEL_CNF95xxN_A1)
+        ROC_MODEL_CNF95xxN_A1 | ROC_MODEL_CNF95xxN_B0)
 #define ROC_MODEL_CNF9K                                                        \
        (ROC_MODEL_CNF95xx_A0 | ROC_MODEL_CNF95xx_B0 |                         \
         ROC_MODEL_CNF95xxMM_A0 | ROC_MODEL_CNF95xxO_A0 |                      \
-        ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CNF95xxN_A1)
+        ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CNF95xxN_A1 |                       \
+        ROC_MODEL_CNF95xxN_B0)
 
 #define ROC_MODEL_CN106xx   (ROC_MODEL_CN106xx_A0)
 #define ROC_MODEL_CNF105xx  (ROC_MODEL_CNF105xx_A0)