F: doc/guides/nics/enetc.rst
F: doc/guides/nics/features/enetc.ini
+NXP pfe
+M: Gagandeep Singh <g.singh@nxp.com>
+M: Akhil Goyal <akhil.goyal@nxp.com>
+F: doc/guides/nics/pfe.rst
+F: drivers/net/pfe/
+F: doc/guides/nics/features/pfe.ini
+
QLogic bnx2x
M: Rasesh Mody <rmody@marvell.com>
M: Shahed Shaikh <shshaikh@marvell.com>
CONFIG_RTE_LIBRTE_AVP_PMD=n
CONFIG_RTE_LIBRTE_PMD_IOAT_RAWDEV=n
+#
+# NXP PFE PMD Driver
+#
+CONFIG_RTE_LIBRTE_PFE_PMD=y
+
CONFIG_RTE_SCHED_VECTOR=n
#
CONFIG_RTE_LIBRTE_CXGBE_PMD=y
+#
+# Compile burst-oriented NXP PFE PMD driver
+#
+CONFIG_RTE_LIBRTE_PFE_PMD=n
+
# NXP DPAA Bus
CONFIG_RTE_LIBRTE_DPAA_BUS=n
CONFIG_RTE_LIBRTE_DPAA_MEMPOOL=n
--- /dev/null
+;
+; Supported features of the 'pfe' network poll mode driver.
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+[Features]
+Linux VFIO = Y
+ARMv8 = Y
+Usage doc = Y
nfp
octeontx
octeontx2
+ pfe
qede
sfc_efx
softnic
--- /dev/null
+.. SPDX-License-Identifier: BSD-3-Clause
+ Copyright 2019 NXP
+
+PFE Poll Mode Driver
+======================
+
+The PFE NIC PMD (**librte_pmd_pfe**) provides poll mode driver
+support for the inbuilt NIC found in the **NXP LS1012** SoC.
+
+More information can be found at `NXP Official Website
+<https://nxp.com/ls1012a>`_.
+
+PFE
+---
+
+This section provides an overview of the NXP PFE
+and how it is integrated into the DPDK.
+
+Contents summary
+
+- PFE overview
+- PFE features
+- Supported PFE SoCs
+- Prerequisites
+- Driver compilation and testing
+- Limitations
+
+PFE Overview
+~~~~~~~~~~~~
+
+PFE is a hardware programmable packet forwarding engine to provide
+high performance Ethernet interfaces. The diagram below shows a
+system level overview of PFE:
+
+.. code-block:: console
+
+ ====================================================+===============
+ US +-----------------------------------------+ | Kernel Space
+ | | |
+ | PFE Ethernet Driver | |
+ +-----------------------------------------+ |
+ ^ | ^ | |
+ PFE RXQ| |TXQ RXQ| |TXQ |
+ PMD | | | | |
+ | v | v | +----------+
+ +---------+ +----------+ | | pfe.ko |
+ | net_pfe0| | net_pfe1 | | +----------+
+ +---------+ +----------+ |
+ ^ | ^ | |
+ TXQ| |RXQ TXQ| |RXQ |
+ | | | | |
+ | v | v |
+ +------------------------+ |
+ | | |
+ | PFE HIF driver | |
+ +------------------------+ |
+ ^ | |
+ RX | TX | |
+ RING| RING| |
+ | v |
+ +--------------+ |
+ | | |
+ ==================| HIF |==================+===============
+ +-----------+ +--------------+
+ | | | | HW
+ | PFE +--------------+ |
+ | +-----+ +-----+ |
+ | | MAC | | MAC | |
+ | | | | | |
+ +-------+-----+----------------+-----+----+
+ | PHY | | PHY |
+ +-----+ +-----+
+
+
+The HIF, PFE, MAC and PHY are the hardware blocks, the pfe.ko is a kernel
+module, the PFE HIF driver and the PFE ethernet driver combined represent
+as DPDK PFE poll mode driver are running in the userspace.
+
+The PFE hardware supports one HIF (host interface) RX ring and one TX ring
+to send and receive packets through packet forwarding engine. Both network
+interface traffic is multiplexed and send over HIF queue.
+
+net_pfe0 and net_pfe1 are logical ethernet interfaces, created by HIF client
+driver. HIF driver is responsible for send and receive packets between
+host interface and these logical interfaces. PFE ethernet driver is a
+hardware independent and register with the HIF client driver to transmit and
+receive packets from HIF via logical interfaces.
+
+pfe.ko is required for PHY initialisation and also responsible for creating
+the character device "pfe_us_cdev" which will be used for interacting with
+the kernel layer for link status.
+
+PFE Features
+~~~~~~~~~~~~
+
+- ARMv8
+
+Supported PFE SoCs
+~~~~~~~~~~~~~~~~~~
+
+- LS1012
+
+Prerequisites
+~~~~~~~~~~~~~
+
+Below are some pre-requisites for executing PFE PMD on a PFE
+compatible board:
+
+1. **ARM 64 Tool Chain**
+
+ For example, the `*aarch64* Linaro Toolchain <https://releases.linaro.org/components/toolchain/binaries/7.3-2018.05/aarch64-linux-gnu/gcc-linaro-7.3.1-2018.05-i686_aarch64-linux-gnu.tar.xz>`_.
+
+2. **Linux Kernel**
+
+ It can be obtained from `NXP's Github hosting <https://source.codeaurora.org/external/qoriq/qoriq-components/linux>`_.
+
+3. **Rootfile system**
+
+ Any *aarch64* supporting filesystem can be used. For example,
+ Ubuntu 16.04 LTS (Xenial) or 18.04 (Bionic) userland which can be obtained
+ from `here <http://cdimage.ubuntu.com/ubuntu-base/releases/18.04/release/ubuntu-base-18.04.1-base-arm64.tar.gz>`_.
+
+4. The ethernet device will be registered as virtual device, so pfe has dependency on
+ **rte_bus_vdev** library and it is mandatory to use `--vdev` with value `net_pfe` to
+ run DPDK application.
+
+The following dependencies are not part of DPDK and must be installed
+separately:
+
+- **NXP Linux LSDK**
+
+ NXP Layerscape software development kit (LSDK) includes support for family
+ of QorIQ® ARM-Architecture-based system on chip (SoC) processors
+ and corresponding boards.
+
+ It includes the Linux board support packages (BSPs) for NXP SoCs,
+ a fully operational tool chain, kernel and board specific modules.
+
+ LSDK and related information can be obtained from: `LSDK <https://www.nxp.com/support/developer-resources/run-time-software/linux-software-and-development-tools/layerscape-software-development-kit:LAYERSCAPE-SDK>`_
+
+- **pfe kernel module**
+
+ pfe kernel module can be obtained from NXP Layerscape software development kit at
+ location `/lib/modules/<kernel version>/kernel/drivers/staging/fsl_ppfe` in rootfs.
+ Module should be loaded using below command:
+
+ .. code-block:: console
+
+ insmod pfe.ko us=1
+
+
+Driver compilation and testing
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Follow instructions available in the document
+:ref:`compiling and testing a PMD for a NIC <pmd_build_and_test>`
+to launch **testpmd**
+
+Additionally, PFE driver needs `--vdev` as an input with value `net_pfe`
+to execute DPDK application. There is an optional parameter `intf` available
+to specify port ID. PFE driver supports only two interfaces, so valid values
+for `intf` are 0 and 1.
+see the command below:
+
+ .. code-block:: console
+
+ <dpdk app> <EAL args> --vdev="net_pfe0,intf=0" --vdev="net_pfe1,intf=1" -- ...
+
+
+Limitations
+~~~~~~~~~~~
+
+- Multi buffer pool cannot be supported.
Subsystem 3(HNS3) network engine found in the Hisilicon Kunpeng 920 SoC.
See the :doc:`../nics/hns3` guide for more details on this new driver.
+* **Added NXP PFE PMD.**
+
+ Added the new PFE driver for the NXP LS1012A platform. See the
+ :doc:`../nics/pfe` NIC driver guide for more details on this new driver.
+
* **Updated the Intel e1000 driver.**
Added support for the ``RTE_ETH_DEV_CLOSE_REMOVE`` flag.
DIRS-$(CONFIG_RTE_LIBRTE_OCTEONTX_PMD) += octeontx
DIRS-$(CONFIG_RTE_LIBRTE_OCTEONTX2_PMD) += octeontx2
DIRS-$(CONFIG_RTE_LIBRTE_PMD_PCAP) += pcap
+DIRS-$(CONFIG_RTE_LIBRTE_PFE_PMD) += pfe
DIRS-$(CONFIG_RTE_LIBRTE_QEDE_PMD) += qede
DIRS-$(CONFIG_RTE_LIBRTE_PMD_RING) += ring
DIRS-$(CONFIG_RTE_LIBRTE_SFC_EFX_PMD) += sfc
'octeontx',
'octeontx2',
'pcap',
+ 'pfe',
'qede',
'ring',
'sfc',
--- /dev/null
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright 2019 NXP
+#
+
+include $(RTE_SDK)/mk/rte.vars.mk
+
+#
+# library name
+#
+LIB = librte_pmd_pfe.a
+
+CFLAGS += -O3 $(WERROR_FLAGS)
+CFLAGS += -I$(RTE_SDK)/drivers/common/dpaax
+
+EXPORT_MAP := rte_pmd_pfe_version.map
+LIBABIVER := 1
+
+# Interfaces with DPDK
+SRCS-$(CONFIG_RTE_LIBRTE_PFE_PMD) += pfe_ethdev.c
+
+LDLIBS += -lrte_bus_vdev
+LDLIBS += -lrte_bus_dpaa
+LDLIBS += -lrte_common_dpaax
+LDLIBS += -lrte_eal
+LDLIBS += -lrte_ethdev -lrte_kvargs
+
+include $(RTE_SDK)/mk/rte.lib.mk
--- /dev/null
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright 2019 NXP
+
+if host_machine.system() != 'linux'
+ build = false
+endif
+deps += ['bus_dpaa']
+
+sources = files('pfe_ethdev.c')
--- /dev/null
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright 2019 NXP
+ */
+
+#ifndef _PFE_ETH_H_
+#define _PFE_ETH_H_
+
+#include <compat.h>
+#include <rte_ethdev.h>
+#include <rte_ethdev_vdev.h>
+
+#define ETH_ALEN 6
+#define GEMAC_NO_PHY BIT(0)
+
+#define PFE_SOC_ID_FILE "/sys/devices/soc0/soc_id"
+extern unsigned int pfe_svr;
+#define SVR_LS1012A_REV2 0x87040020
+#define SVR_LS1012A_REV1 0x87040010
+
+struct ls1012a_eth_platform_data {
+ /* device specific information */
+ u32 device_flags;
+ char name[16];
+
+ /* board specific information */
+ u32 mii_config;
+ u32 phy_flags;
+ u32 gem_id;
+ u32 bus_id;
+ u32 phy_id;
+ u32 mdio_muxval;
+ u8 mac_addr[ETH_ALEN];
+};
+
+struct ls1012a_mdio_platform_data {
+ int enabled;
+ int irq[32];
+ u32 phy_mask;
+ int mdc_div;
+};
+
+struct ls1012a_pfe_platform_data {
+ struct ls1012a_eth_platform_data ls1012a_eth_pdata[3];
+ struct ls1012a_mdio_platform_data ls1012a_mdio_pdata[3];
+};
+
+#define EMAC_TXQ_CNT 16
+#define EMAC_TXQ_DEPTH (HIF_TX_DESC_NT)
+
+#define JUMBO_FRAME_SIZE 10258
+#define EMAC_RXQ_CNT 1
+#define EMAC_RXQ_DEPTH HIF_RX_DESC_NT
+
+struct pfe_eth_priv_s {
+ struct pfe *pfe;
+ int low_tmu_q;
+ int high_tmu_q;
+ struct rte_eth_dev *ndev;
+ struct rte_eth_stats stats;
+ int id;
+ int promisc;
+ int link_fd;
+
+ spinlock_t lock; /* protect member variables */
+ void *EMAC_baseaddr;
+ /* This points to the EMAC base from where we access PHY */
+ void *PHY_baseaddr;
+ void *GPI_baseaddr;
+
+ struct ls1012a_eth_platform_data *einfo;
+};
+
+#endif /* _PFE_ETH_H_ */
--- /dev/null
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright 2019 NXP
+ */
+
+#include <rte_kvargs.h>
+#include <rte_ethdev_vdev.h>
+#include <rte_bus_vdev.h>
+#include <dpaa_of.h>
+
+#include "pfe_mod.h"
+
+#define PFE_MAX_MACS 1 /*we can support upto 4 MACs per IF*/
+#define PFE_VDEV_GEM_ID_ARG "intf"
+
+struct pfe_vdev_init_params {
+ int8_t gem_id;
+};
+static struct pfe *g_pfe;
+
+/* TODO: make pfe_svr a runtime option.
+ * Driver should be able to get the SVR
+ * information from HW.
+ */
+unsigned int pfe_svr = SVR_LS1012A_REV1;
+
+static void
+pfe_soc_version_get(void)
+{
+ FILE *svr_file = NULL;
+ unsigned int svr_ver = 0;
+
+ svr_file = fopen(PFE_SOC_ID_FILE, "r");
+ if (!svr_file)
+ return; /* Not supported on this infra */
+
+ if (fscanf(svr_file, "svr:%x", &svr_ver) > 0)
+ pfe_svr = svr_ver;
+ else
+ printf("Unable to read SoC device");
+
+ fclose(svr_file);
+}
+
+static int
+pfe_eth_open_cdev(struct pfe_eth_priv_s *priv)
+{
+ int pfe_cdev_fd;
+
+ if (priv == NULL)
+ return -1;
+
+ pfe_cdev_fd = open(PFE_CDEV_PATH, O_RDONLY);
+ if (pfe_cdev_fd < 0) {
+ priv->link_fd = PFE_CDEV_INVALID_FD;
+ return -1;
+ }
+
+ priv->link_fd = pfe_cdev_fd;
+
+ return 0;
+}
+
+static void
+pfe_eth_close_cdev(struct pfe_eth_priv_s *priv)
+{
+ if (priv == NULL)
+ return;
+
+ if (priv->link_fd != PFE_CDEV_INVALID_FD) {
+ close(priv->link_fd);
+ priv->link_fd = PFE_CDEV_INVALID_FD;
+ }
+}
+
+static void
+pfe_eth_exit(struct rte_eth_dev *dev, struct pfe *pfe)
+{
+ /* Close the device file for link status */
+ pfe_eth_close_cdev(dev->data->dev_private);
+
+ rte_free(dev->data->mac_addrs);
+ rte_eth_dev_release_port(dev);
+ pfe->nb_devs--;
+}
+
+static int
+pfe_eth_init(struct rte_vdev_device *vdev, struct pfe *pfe, int id)
+{
+ struct rte_eth_dev *eth_dev = NULL;
+ struct pfe_eth_priv_s *priv = NULL;
+ int err;
+
+ eth_dev = rte_eth_vdev_allocate(vdev, sizeof(*priv));
+ if (eth_dev == NULL)
+ return -ENOMEM;
+
+ priv = eth_dev->data->dev_private;
+ priv->ndev = eth_dev;
+ priv->pfe = pfe;
+
+ pfe->eth.eth_priv[id] = priv;
+
+#define HIF_GEMAC_TMUQ_BASE 6
+ priv->low_tmu_q = HIF_GEMAC_TMUQ_BASE + (id * 2);
+ priv->high_tmu_q = priv->low_tmu_q + 1;
+
+ rte_spinlock_init(&priv->lock);
+
+ /* Copy the station address into the dev structure, */
+ eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
+ ETHER_ADDR_LEN * PFE_MAX_MACS, 0);
+ if (eth_dev->data->mac_addrs == NULL) {
+ err = -ENOMEM;
+ goto err0;
+ }
+
+ eth_dev->data->mtu = 1500;
+
+ eth_dev->data->nb_rx_queues = 1;
+ eth_dev->data->nb_tx_queues = 1;
+
+ /* For link status, open the PFE CDEV; Error from this function
+ * is silently ignored; In case of error, the link status will not
+ * be available.
+ */
+ pfe_eth_open_cdev(priv);
+ rte_eth_dev_probing_finish(eth_dev);
+
+ return 0;
+err0:
+ rte_eth_dev_release_port(eth_dev);
+ return err;
+}
+
+/* Parse integer from integer argument */
+static int
+parse_integer_arg(const char *key __rte_unused,
+ const char *value, void *extra_args)
+{
+ int i;
+ char *end;
+ errno = 0;
+
+ i = strtol(value, &end, 10);
+ if (*end != 0 || errno != 0 || i < 0 || i > 1)
+ return -EINVAL;
+
+ *((uint32_t *)extra_args) = i;
+
+ return 0;
+}
+
+static int
+pfe_parse_vdev_init_params(struct pfe_vdev_init_params *params,
+ struct rte_vdev_device *dev)
+{
+ struct rte_kvargs *kvlist = NULL;
+ int ret = 0;
+
+ static const char * const pfe_vdev_valid_params[] = {
+ PFE_VDEV_GEM_ID_ARG,
+ NULL
+ };
+
+ const char *input_args = rte_vdev_device_args(dev);
+
+ if (!input_args)
+ return -1;
+
+ kvlist = rte_kvargs_parse(input_args, pfe_vdev_valid_params);
+ if (kvlist == NULL)
+ return -1;
+
+ ret = rte_kvargs_process(kvlist,
+ PFE_VDEV_GEM_ID_ARG,
+ &parse_integer_arg,
+ ¶ms->gem_id);
+ rte_kvargs_free(kvlist);
+ return ret;
+}
+
+static int
+pmd_pfe_probe(struct rte_vdev_device *vdev)
+{
+ const u32 *prop;
+ const struct device_node *np;
+ const char *name;
+ const uint32_t *addr;
+ uint64_t cbus_addr, ddr_size, cbus_size;
+ int rc = -1, fd = -1, gem_id;
+ unsigned int interface_count = 0;
+ size_t size = 0;
+ struct pfe_vdev_init_params init_params = {
+ .gem_id = -1
+ };
+
+ name = rte_vdev_device_name(vdev);
+ rc = pfe_parse_vdev_init_params(&init_params, vdev);
+ if (rc < 0)
+ return -EINVAL;
+
+ if (g_pfe) {
+ if (g_pfe->nb_devs >= g_pfe->max_intf)
+ return -EINVAL;
+
+ goto eth_init;
+ }
+
+ g_pfe = rte_zmalloc(NULL, sizeof(*g_pfe), RTE_CACHE_LINE_SIZE);
+ if (g_pfe == NULL)
+ return -EINVAL;
+
+ /* Load the device-tree driver */
+ rc = of_init();
+ if (rc)
+ goto err;
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,pfe");
+ if (!np) {
+ rc = -EINVAL;
+ goto err;
+ }
+
+ addr = of_get_address(np, 0, &cbus_size, NULL);
+ if (!addr)
+ goto err;
+
+ cbus_addr = of_translate_address(np, addr);
+ if (!cbus_addr)
+ goto err;
+
+
+ addr = of_get_address(np, 1, &ddr_size, NULL);
+ if (!addr)
+ goto err;
+
+ g_pfe->ddr_phys_baseaddr = of_translate_address(np, addr);
+ if (!g_pfe->ddr_phys_baseaddr)
+ goto err;
+
+ g_pfe->ddr_size = ddr_size;
+ g_pfe->cbus_size = cbus_size;
+
+ fd = open("/dev/mem", O_RDWR);
+ g_pfe->cbus_baseaddr = mmap(NULL, cbus_size, PROT_READ | PROT_WRITE,
+ MAP_SHARED, fd, cbus_addr);
+ close(fd);
+ if (g_pfe->cbus_baseaddr == MAP_FAILED) {
+ rc = -EINVAL;
+ goto err;
+ }
+
+ /* Read interface count */
+ prop = of_get_property(np, "fsl,pfe-num-interfaces", &size);
+ if (!prop) {
+ rc = -ENXIO;
+ goto err_prop;
+ }
+
+ interface_count = rte_be_to_cpu_32((unsigned int)*prop);
+ if (interface_count <= 0) {
+ rc = -ENXIO;
+ goto err_prop;
+ }
+ g_pfe->max_intf = interface_count;
+ pfe_soc_version_get();
+eth_init:
+ if (init_params.gem_id < 0)
+ gem_id = g_pfe->nb_devs;
+ else
+ gem_id = init_params.gem_id;
+
+ RTE_LOG(INFO, PMD, "Init pmd_pfe for %s gem-id %d(given =%d)\n",
+ name, gem_id, init_params.gem_id);
+
+ rc = pfe_eth_init(vdev, g_pfe, gem_id);
+ if (rc < 0)
+ goto err_eth;
+ else
+ g_pfe->nb_devs++;
+
+ return 0;
+
+err_eth:
+err_prop:
+ munmap(g_pfe->cbus_baseaddr, cbus_size);
+err:
+ rte_free(g_pfe);
+ return rc;
+}
+
+static int
+pmd_pfe_remove(struct rte_vdev_device *vdev)
+{
+ const char *name;
+ struct rte_eth_dev *eth_dev = NULL;
+
+ name = rte_vdev_device_name(vdev);
+ if (name == NULL)
+ return -EINVAL;
+
+ if (!g_pfe)
+ return 0;
+
+ eth_dev = rte_eth_dev_allocated(name);
+ if (eth_dev == NULL)
+ return -ENODEV;
+
+ pfe_eth_exit(eth_dev, g_pfe);
+ munmap(g_pfe->cbus_baseaddr, g_pfe->cbus_size);
+
+ return 0;
+}
+
+static
+struct rte_vdev_driver pmd_pfe_drv = {
+ .probe = pmd_pfe_probe,
+ .remove = pmd_pfe_remove,
+};
+
+RTE_PMD_REGISTER_VDEV(PFE_NAME_PMD, pmd_pfe_drv);
+RTE_PMD_REGISTER_PARAM_STRING(PFE_NAME_PMD, PFE_VDEV_GEM_ID_ARG "=<int> ");
--- /dev/null
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright 2019 NXP
+ */
+
+#ifndef _PFE_MOD_H_
+#define _PFE_MOD_H_
+
+struct pfe;
+
+#include "pfe_eth.h"
+
+#define PHYID_MAX_VAL 32
+
+/* PFE DPDK driver supports two interfaces.
+ */
+#define PFE_CDEV_ETH_COUNT 2
+
+/* PFE DPDK driver needs a kernel module named "pfe.ko", This module
+ * is required for PHY initialisation and creates a character device
+ * "pfe_us_cdev" for IOCTL support. PFE DPDK driver uses this character
+ * device for link status.
+ */
+#define PFE_CDEV_PATH "/dev/pfe_us_cdev"
+#define PFE_CDEV_INVALID_FD -1
+#define PFE_NAME_PMD net_pfe
+
+/* used when 'read' call is issued, returning PFE_CDEV_ETH_COUNT number of
+ * pfe_shared_info as array.
+ */
+struct pfe_shared_info {
+ uint32_t phy_id; /* Link phy ID */
+ uint8_t state; /* Has either 0 or 1 */
+};
+
+struct pfe_eth {
+ struct pfe_eth_priv_s *eth_priv[PFE_CDEV_ETH_COUNT];
+};
+
+struct pfe {
+ uint64_t ddr_phys_baseaddr;
+ void *ddr_baseaddr;
+ uint64_t ddr_size;
+ void *cbus_baseaddr;
+ uint64_t cbus_size;
+ struct pfe_eth eth;
+ int mdio_muxval[PHYID_MAX_VAL];
+ uint8_t nb_devs;
+ uint8_t max_intf;
+ int cdev_fd;
+};
+
+/* IOCTL Commands */
+#define PFE_CDEV_ETH0_STATE_GET _IOR('R', 0, int)
+#define PFE_CDEV_ETH1_STATE_GET _IOR('R', 1, int)
+#define PFE_CDEV_HIF_INTR_EN _IOWR('R', 2, int)
+#endif /* _PFE_MOD_H */
--- /dev/null
+DPDK_19.11 {
+
+ local: *;
+};
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_NULL) += -lrte_pmd_null
_LDLIBS-$(CONFIG_RTE_LIBRTE_OCTEONTX2_PMD) += -lrte_pmd_octeontx2 -lm
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_PCAP) += -lrte_pmd_pcap -lpcap
+_LDLIBS-$(CONFIG_RTE_LIBRTE_PFE_PMD) += -lrte_pmd_pfe
_LDLIBS-$(CONFIG_RTE_LIBRTE_QEDE_PMD) += -lrte_pmd_qede
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_RING) += -lrte_pmd_ring
ifeq ($(CONFIG_RTE_LIBRTE_SCHED),y)
git.droids-corp.org / dpdk.git / commitdiff