CFLAGS += -O3
CFLAGS += $(WERROR_FLAGS)
+CFLAGS += -DALLOW_EXPERIMENTAL_API
EXPORT_MAP := rte_pmd_atlantic_version.map
}
done:
atl_enable_intr(dev);
- rte_intr_enable(intr_handle);
+ rte_intr_ack(intr_handle);
return 0;
}
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2018 Aquantia Corporation
+allow_experimental_apis = true
+
sources = files(
'atl_rxtx.c',
'atl_ethdev.c',
CFLAGS += -O3
CFLAGS += $(WERROR_FLAGS) -I$(SRCDIR)
+CFLAGS += -DALLOW_EXPERIMENTAL_API
LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring
LDLIBS += -lrte_ethdev -lrte_net -lrte_kvargs
LDLIBS += -lrte_bus_pci
status);
/* re-enable UIO interrupt handling */
- ret = rte_intr_enable(&pci_dev->intr_handle);
+ ret = rte_intr_ack(&pci_dev->intr_handle);
if (ret < 0) {
PMD_DRV_LOG(ERR, "Failed to re-enable UIO interrupts, ret=%d\n",
ret);
build = false
reason = 'only supported on linux'
endif
+allow_experimental_apis = true
sources = files('avp_ethdev.c')
install_headers('rte_avp_common.h', 'rte_avp_fifo.h')
CFLAGS += -O3
CFLAGS += $(WERROR_FLAGS)
+CFLAGS += -DALLOW_EXPERIMENTAL_API
EXPORT_MAP := rte_pmd_axgbe_version.map
DMA_CH_SR, dma_ch_isr);
}
}
- /* Enable interrupts since disabled after generation*/
- rte_intr_enable(&pdata->pci_dev->intr_handle);
+ /* Unmask interrupts since disabled after generation */
+ rte_intr_ack(&pdata->pci_dev->intr_handle);
}
/*
reason = 'only supported on linux'
endif
+allow_experimental_apis = true
+
sources = files('axgbe_ethdev.c',
'axgbe_dev.c',
'axgbe_mdio.c',
CFLAGS += -O3
CFLAGS += $(WERROR_FLAGS)
CFLAGS += -DZLIB_CONST
+CFLAGS += -DALLOW_EXPERIMENTAL_API
LDLIBS += -lz
LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring
LDLIBS += -lrte_ethdev -lrte_net -lrte_kvargs
PMD_DEBUG_PERIODIC_LOG(INFO, sc, "Interrupt handled");
bnx2x_interrupt_action(dev, 1);
- rte_intr_enable(&sc->pci_dev->intr_handle);
+ rte_intr_ack(&sc->pci_dev->intr_handle);
}
static void bnx2x_periodic_start(void *param)
build = dep.found()
reason = 'missing dependency, "zlib"'
ext_deps += dep
+allow_experimental_apis = true
cflags += '-DZLIB_CONST'
sources = files('bnx2x.c',
'bnx2x_ethdev.c',
struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
em_rxq_intr_enable(hw);
- rte_intr_enable(intr_handle);
+ rte_intr_ack(intr_handle);
return 0;
}
return -1;
intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
- rte_intr_enable(intr_handle);
+ rte_intr_ack(intr_handle);
/* set get_link_status to check register later */
hw->mac.get_link_status = 1;
}
igb_intr_enable(dev);
- rte_intr_enable(intr_handle);
+ rte_intr_ack(intr_handle);
if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
}
igbvf_intr_enable(dev);
- rte_intr_enable(intr_handle);
+ rte_intr_ack(intr_handle);
return 0;
}
E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
E1000_WRITE_FLUSH(hw);
- rte_intr_enable(intr_handle);
+ rte_intr_ack(intr_handle);
return 0;
}
CFLAGS += -O3
CFLAGS += $(WERROR_FLAGS)
+CFLAGS += -DALLOW_EXPERIMENTAL_API
EXPORT_MAP := rte_pmd_fm10k_version.map
else
FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(pdev, queue_id)),
FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR);
- rte_intr_enable(&pdev->intr_handle);
+ rte_intr_ack(&pdev->intr_handle);
return 0;
}
FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_AUTOMASK |
FM10K_ITR_MASK_CLEAR);
/* Re-enable interrupt from host side */
- rte_intr_enable(dev->intr_handle);
+ rte_intr_ack(dev->intr_handle);
}
/**
FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_AUTOMASK |
FM10K_ITR_MASK_CLEAR);
/* Re-enable interrupt from host side */
- rte_intr_enable(dev->intr_handle);
+ rte_intr_ack(dev->intr_handle);
}
/* Mailbox message handler in VF */
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2017 Intel Corporation
+allow_experimental_apis = true
+
subdir('base')
objs = [base_objs]
I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
I40E_WRITE_FLUSH(hw);
- rte_intr_enable(&pci_dev->intr_handle);
+ rte_intr_ack(&pci_dev->intr_handle);
return 0;
}
IAVF_WRITE_FLUSH(hw);
- rte_intr_enable(&pci_dev->intr_handle);
+ rte_intr_ack(&pci_dev->intr_handle);
return 0;
}
CFLAGS += -O3
CFLAGS += $(WERROR_FLAGS)
+CFLAGS += -DALLOW_EXPERIMENTAL_API
LDLIBS += -lrte_eal -lrte_mbuf -lrte_ethdev -lrte_kvargs
LDLIBS += -lrte_bus_pci -lrte_mempool
done:
/* Enable interrupt */
ice_pf_enable_irq0(hw);
- rte_intr_enable(dev->intr_handle);
+ rte_intr_ack(dev->intr_handle);
}
/* Initialize SW parameters of PF */
val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
- rte_intr_enable(&pci_dev->intr_handle);
+ rte_intr_ack(&pci_dev->intr_handle);
return 0;
}
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2018 Intel Corporation
+allow_experimental_apis = true
+
subdir('base')
objs = [base_objs]
PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
ixgbe_enable_intr(dev);
- rte_intr_enable(intr_handle);
+ rte_intr_ack(intr_handle);
}
/**
RTE_SET_USED(queue_id);
IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
- rte_intr_enable(intr_handle);
+ rte_intr_ack(intr_handle);
return 0;
}
mask &= (1 << (queue_id - 32));
IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
}
- rte_intr_enable(intr_handle);
+ rte_intr_ack(intr_handle);
return 0;
}
if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
/* If MSI-X auto-masking is used, clear the entry */
rte_wmb();
- rte_intr_enable(&pci_dev->intr_handle);
+ rte_intr_ack(&pci_dev->intr_handle);
} else {
/* Make sure all updates are written before un-masking */
rte_wmb();
CFLAGS += -O3
CFLAGS += $(WERROR_FLAGS)
+CFLAGS += -DALLOW_EXPERIMENTAL_API
LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring
LDLIBS += -lrte_ethdev -lrte_net -lrte_kvargs
LDLIBS += -lrte_bus_pci
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2018 Luca Boccassi <bluca@debian.org>
+allow_experimental_apis = true
+
subdir('base')
objs = [base_objs]
if (status & 0x1) {
qede_interrupt_action(ECORE_LEADING_HWFN(edev));
- if (rte_intr_enable(eth_dev->intr_handle))
- DP_ERR(edev, "rte_intr_enable failed\n");
+ if (rte_intr_ack(eth_dev->intr_handle))
+ DP_ERR(edev, "rte_intr_ack failed\n");
}
}
struct ecore_dev *edev = &qdev->edev;
qede_interrupt_action(ECORE_LEADING_HWFN(edev));
- if (rte_intr_enable(eth_dev->intr_handle))
- DP_ERR(edev, "rte_intr_enable failed\n");
+ if (rte_intr_ack(eth_dev->intr_handle))
+ DP_ERR(edev, "rte_intr_ack failed\n");
}
static void
if (qmask & (1 << sa->mgmt_evq_index))
sfc_intr_handle_mgmt_evq(sa);
- if (rte_intr_enable(&pci_dev->intr_handle) != 0)
+ if (rte_intr_ack(&pci_dev->intr_handle) != 0)
sfc_err(sa, "cannot reenable interrupts");
sfc_log_init(sa, "done");
sfc_intr_handle_mgmt_evq(sa);
- if (rte_intr_enable(&pci_dev->intr_handle) != 0)
+ if (rte_intr_ack(&pci_dev->intr_handle) != 0)
sfc_err(sa, "cannot reenable interrupts");
sfc_log_init(sa, "done");
return virtio_send_command(hw->cvq, &ctrl, &len, 1);
}
+static int
+virtio_intr_unmask(struct rte_eth_dev *dev)
+{
+ struct virtio_hw *hw = dev->data->dev_private;
+
+ if (rte_intr_ack(dev->intr_handle) < 0)
+ return -1;
+
+ if (!hw->virtio_user_dev)
+ hw->use_msix = vtpci_msix_detect(RTE_ETH_DEV_TO_PCI(dev));
+
+ return 0;
+}
+
static int
virtio_intr_enable(struct rte_eth_dev *dev)
{
isr = vtpci_isr(hw);
PMD_DRV_LOG(INFO, "interrupt status = %#x", isr);
- if (virtio_intr_enable(dev) < 0)
+ if (virtio_intr_unmask(dev) < 0)
PMD_DRV_LOG(ERR, "interrupt enable failed");
if (isr & VIRTIO_PCI_ISR_CONFIG) {
vmxnet3_process_events(dev);
- if (rte_intr_enable(&pci_dev->intr_handle) < 0)
+ if (rte_intr_ack(&pci_dev->intr_handle) < 0)
PMD_DRV_LOG(ERR, "interrupt enable failed");
}