net/e1000/base: expose FEXTNVM registers and masks
authorGuinan Sun <guinanx.sun@intel.com>
Mon, 6 Jul 2020 08:12:16 +0000 (08:12 +0000)
committerFerruh Yigit <ferruh.yigit@intel.com>
Tue, 7 Jul 2020 21:38:27 +0000 (23:38 +0200)
Adding defines for FEXTNVM8 and FEXTNVM12 registers with new masks for
future use.

Signed-off-by: Nir Efrati <nir.efrati@intel.com>
Signed-off-by: Guinan Sun <guinanx.sun@intel.com>
Reviewed-by: Wei Zhao <wei.zhao1@intel.com>
drivers/net/e1000/base/e1000_ich8lan.h
drivers/net/e1000/base/e1000_regs.h

index bfee467..3be3ee2 100644 (file)
 #if !defined(EXTERNAL_RELEASE) || defined(ULP_SUPPORT)
 #define E1000_FEXTNVM7_DISABLE_SMB_PERST       0x00000020
 #endif /* !EXTERNAL_RELEASE || ULP_SUPPORT */
+#define E1000_FEXTNVM8_UNBIND_DPG_FROM_MPHY    0x00000400
 #define E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS      0x00000800
 #define E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS       0x00001000
 #define E1000_FEXTNVM11_DISABLE_PB_READ                0x00000200
 #define E1000_FEXTNVM11_DISABLE_MULR_FIX       0x00002000
-
+#define E1000_FEXTNVM12_DONT_WAK_DPG_CLKREQ    0x00001000
 /* bit24: RXDCTL thresholds granularity: 0 - cache lines, 1 - descriptors */
 #define E1000_RXDCTL_THRESH_UNIT_DESC  0x01000000
 
index 71c8d28..8ee1c76 100644 (file)
 #define E1000_FEXTNVM5 0x00014  /* Future Extended NVM 5 - RW */
 #define E1000_FEXTNVM6 0x00010  /* Future Extended NVM 6 - RW */
 #define E1000_FEXTNVM7 0x000E4  /* Future Extended NVM 7 - RW */
+#define E1000_FEXTNVM8 0x5BB0  /* Future Extended NVM 8 - RW */
 #define E1000_FEXTNVM9 0x5BB4  /* Future Extended NVM 9 - RW */
 #define E1000_FEXTNVM11        0x5BBC  /* Future Extended NVM 11 - RW */
+#define E1000_FEXTNVM12        0x5BC0  /* Future Extended NVM 12 - RW */
 #define E1000_PCIEANACFG       0x00F18 /* PCIE Analog Config */
 #define E1000_FCT      0x00030  /* Flow Control Type - RW */
 #define E1000_CONNSW   0x00034  /* Copper/Fiber switch control - RW */