--- /dev/null
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright 2019 NXP
+ */
+
+#ifndef _CBUS_H_
+#define _CBUS_H_
+
+#include <compat.h>
+
+#define EMAC1_BASE_ADDR (CBUS_BASE_ADDR + 0x200000)
+#define EGPI1_BASE_ADDR (CBUS_BASE_ADDR + 0x210000)
+#define EMAC2_BASE_ADDR (CBUS_BASE_ADDR + 0x220000)
+#define EGPI2_BASE_ADDR (CBUS_BASE_ADDR + 0x230000)
+#define BMU1_BASE_ADDR (CBUS_BASE_ADDR + 0x240000)
+#define BMU2_BASE_ADDR (CBUS_BASE_ADDR + 0x250000)
+#define ARB_BASE_ADDR (CBUS_BASE_ADDR + 0x260000)
+#define DDR_CONFIG_BASE_ADDR (CBUS_BASE_ADDR + 0x270000)
+#define HIF_BASE_ADDR (CBUS_BASE_ADDR + 0x280000)
+#define HGPI_BASE_ADDR (CBUS_BASE_ADDR + 0x290000)
+#define LMEM_BASE_ADDR (CBUS_BASE_ADDR + 0x300000)
+#define LMEM_SIZE 0x10000
+#define LMEM_END (LMEM_BASE_ADDR + LMEM_SIZE)
+#define TMU_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x310000)
+#define CLASS_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x320000)
+#define HIF_NOCPY_BASE_ADDR (CBUS_BASE_ADDR + 0x350000)
+#define UTIL_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x360000)
+#define CBUS_GPT_BASE_ADDR (CBUS_BASE_ADDR + 0x370000)
+
+/*
+ * defgroup XXX_MEM_ACCESS_ADDR PE memory access through CSR
+ * XXX_MEM_ACCESS_ADDR register bit definitions.
+ */
+#define PE_MEM_ACCESS_WRITE BIT(31) /* Internal Memory Write. */
+#define PE_MEM_ACCESS_IMEM BIT(15)
+#define PE_MEM_ACCESS_DMEM BIT(16)
+
+/* Byte Enables of the Internal memory access. These are interpred in BE */
+#define PE_MEM_ACCESS_BYTE_ENABLE(offset, size) \
+ ({ typeof(size) size_ = (size); \
+ (((BIT(size_) - 1) << (4 - (offset) - (size_))) & 0xf) << 24; })
+
+#include "cbus/emac_mtip.h"
+#include "cbus/gpi.h"
+#include "cbus/bmu.h"
+#include "cbus/hif.h"
+#include "cbus/tmu_csr.h"
+#include "cbus/class_csr.h"
+#include "cbus/hif_nocpy.h"
+#include "cbus/util_csr.h"
+
+/* PFE cores states */
+#define CORE_DISABLE 0x00000000
+#define CORE_ENABLE 0x00000001
+#define CORE_SW_RESET 0x00000002
+
+/* LMEM defines */
+#define LMEM_HDR_SIZE 0x0010
+#define LMEM_BUF_SIZE_LN2 0x7
+#define LMEM_BUF_SIZE BIT(LMEM_BUF_SIZE_LN2)
+
+/* DDR defines */
+#define DDR_HDR_SIZE 0x0100
+#define DDR_BUF_SIZE_LN2 0xb
+#define DDR_BUF_SIZE BIT(DDR_BUF_SIZE_LN2)
+
+#endif /* _CBUS_H_ */
--- /dev/null
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright 2019 NXP
+ */
+
+#ifndef _BMU_H_
+#define _BMU_H_
+
+#define BMU_VERSION 0x000
+#define BMU_CTRL 0x004
+#define BMU_UCAST_CONFIG 0x008
+#define BMU_UCAST_BASE_ADDR 0x00c
+#define BMU_BUF_SIZE 0x010
+#define BMU_BUF_CNT 0x014
+#define BMU_THRES 0x018
+#define BMU_INT_SRC 0x020
+#define BMU_INT_ENABLE 0x024
+#define BMU_ALLOC_CTRL 0x030
+#define BMU_FREE_CTRL 0x034
+#define BMU_FREE_ERR_ADDR 0x038
+#define BMU_CURR_BUF_CNT 0x03c
+#define BMU_MCAST_CNT 0x040
+#define BMU_MCAST_ALLOC_CTRL 0x044
+#define BMU_REM_BUF_CNT 0x048
+#define BMU_LOW_WATERMARK 0x050
+#define BMU_HIGH_WATERMARK 0x054
+#define BMU_INT_MEM_ACCESS 0x100
+
+struct BMU_CFG {
+ unsigned long baseaddr;
+ u32 count;
+ u32 size;
+ u32 low_watermark;
+ u32 high_watermark;
+};
+
+#define BMU1_BUF_SIZE LMEM_BUF_SIZE_LN2
+#define BMU2_BUF_SIZE DDR_BUF_SIZE_LN2
+
+#define BMU2_MCAST_ALLOC_CTRL (BMU2_BASE_ADDR + BMU_MCAST_ALLOC_CTRL)
+
+#endif /* _BMU_H_ */
--- /dev/null
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright 2019 NXP
+ */
+
+#ifndef _CLASS_CSR_H_
+#define _CLASS_CSR_H_
+
+#include <compat.h>
+
+/* @file class_csr.h.
+ * class_csr - block containing all the classifier control and status register.
+ * Mapped on CBUS and accessible from all PE's and ARM.
+ */
+#define CLASS_VERSION (CLASS_CSR_BASE_ADDR + 0x000)
+#define CLASS_TX_CTRL (CLASS_CSR_BASE_ADDR + 0x004)
+#define CLASS_INQ_PKTPTR (CLASS_CSR_BASE_ADDR + 0x010)
+
+/* (ddr_hdr_size[24:16], lmem_hdr_size[5:0]) */
+#define CLASS_HDR_SIZE (CLASS_CSR_BASE_ADDR + 0x014)
+
+/* LMEM header size for the Classifier block.\ Data in the LMEM
+ * is written from this offset.
+ */
+#define CLASS_HDR_SIZE_LMEM(off) ((off) & 0x3f)
+
+/* DDR header size for the Classifier block.\ Data in the DDR
+ * is written from this offset.
+ */
+#define CLASS_HDR_SIZE_DDR(off) (((off) & 0x1ff) << 16)
+
+#define CLASS_PE0_QB_DM_ADDR0 (CLASS_CSR_BASE_ADDR + 0x020)
+
+/* DMEM address of first [15:0] and second [31:16] buffers on QB side. */
+#define CLASS_PE0_QB_DM_ADDR1 (CLASS_CSR_BASE_ADDR + 0x024)
+
+/* DMEM address of third [15:0] and fourth [31:16] buffers on QB side. */
+#define CLASS_PE0_RO_DM_ADDR0 (CLASS_CSR_BASE_ADDR + 0x060)
+
+/* DMEM address of first [15:0] and second [31:16] buffers on RO side. */
+#define CLASS_PE0_RO_DM_ADDR1 (CLASS_CSR_BASE_ADDR + 0x064)
+
+/* DMEM address of third [15:0] and fourth [31:16] buffers on RO side. */
+
+/* @name Class PE memory access. Allows external PE's and HOST to
+ * read/write PMEM/DMEM memory ranges for each classifier PE.
+ */
+/* {sr_pe_mem_cmd[31], csr_pe_mem_wren[27:24], csr_pe_mem_addr[23:0]},
+ * See \ref XXX_MEM_ACCESS_ADDR for details.
+ */
+#define CLASS_MEM_ACCESS_ADDR (CLASS_CSR_BASE_ADDR + 0x100)
+
+/* Internal Memory Access Write Data [31:0] */
+#define CLASS_MEM_ACCESS_WDATA (CLASS_CSR_BASE_ADDR + 0x104)
+
+/* Internal Memory Access Read Data [31:0] */
+#define CLASS_MEM_ACCESS_RDATA (CLASS_CSR_BASE_ADDR + 0x108)
+#define CLASS_TM_INQ_ADDR (CLASS_CSR_BASE_ADDR + 0x114)
+#define CLASS_PE_STATUS (CLASS_CSR_BASE_ADDR + 0x118)
+
+#define CLASS_PHY1_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x11c)
+#define CLASS_PHY1_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x120)
+#define CLASS_PHY1_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x124)
+#define CLASS_PHY1_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x128)
+#define CLASS_PHY1_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x12c)
+#define CLASS_PHY1_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x130)
+#define CLASS_PHY1_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x134)
+#define CLASS_PHY1_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x138)
+#define CLASS_PHY1_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x13c)
+#define CLASS_PHY1_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x140)
+#define CLASS_PHY2_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x144)
+#define CLASS_PHY2_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x148)
+#define CLASS_PHY2_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x14c)
+#define CLASS_PHY2_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x150)
+#define CLASS_PHY2_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x154)
+#define CLASS_PHY2_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x158)
+#define CLASS_PHY2_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x15c)
+#define CLASS_PHY2_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x160)
+#define CLASS_PHY2_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x164)
+#define CLASS_PHY2_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x168)
+#define CLASS_PHY3_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x16c)
+#define CLASS_PHY3_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x170)
+#define CLASS_PHY3_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x174)
+#define CLASS_PHY3_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x178)
+#define CLASS_PHY3_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x17c)
+#define CLASS_PHY3_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x180)
+#define CLASS_PHY3_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x184)
+#define CLASS_PHY3_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x188)
+#define CLASS_PHY3_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x18c)
+#define CLASS_PHY3_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x190)
+#define CLASS_PHY1_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x194)
+#define CLASS_PHY1_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x198)
+#define CLASS_PHY1_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x19c)
+#define CLASS_PHY1_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1a0)
+#define CLASS_PHY2_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1a4)
+#define CLASS_PHY2_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1a8)
+#define CLASS_PHY2_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x1ac)
+#define CLASS_PHY2_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1b0)
+#define CLASS_PHY3_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1b4)
+#define CLASS_PHY3_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1b8)
+#define CLASS_PHY3_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x1bc)
+#define CLASS_PHY3_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1c0)
+#define CLASS_PHY4_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1c4)
+#define CLASS_PHY4_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1c8)
+#define CLASS_PHY4_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x1cc)
+#define CLASS_PHY4_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1d0)
+#define CLASS_PHY4_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x1d4)
+#define CLASS_PHY4_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x1d8)
+#define CLASS_PHY4_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x1dc)
+#define CLASS_PHY4_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x1e0)
+#define CLASS_PHY4_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x1e4)
+#define CLASS_PHY4_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x1e8)
+#define CLASS_PHY4_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x1ec)
+#define CLASS_PHY4_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x1f0)
+#define CLASS_PHY4_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x1f4)
+#define CLASS_PHY4_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x1f8)
+
+#define CLASS_PE_SYS_CLK_RATIO (CLASS_CSR_BASE_ADDR + 0x200)
+#define CLASS_AFULL_THRES (CLASS_CSR_BASE_ADDR + 0x204)
+#define CLASS_GAP_BETWEEN_READS (CLASS_CSR_BASE_ADDR + 0x208)
+#define CLASS_MAX_BUF_CNT (CLASS_CSR_BASE_ADDR + 0x20c)
+#define CLASS_TSQ_FIFO_THRES (CLASS_CSR_BASE_ADDR + 0x210)
+#define CLASS_TSQ_MAX_CNT (CLASS_CSR_BASE_ADDR + 0x214)
+#define CLASS_IRAM_DATA_0 (CLASS_CSR_BASE_ADDR + 0x218)
+#define CLASS_IRAM_DATA_1 (CLASS_CSR_BASE_ADDR + 0x21c)
+#define CLASS_IRAM_DATA_2 (CLASS_CSR_BASE_ADDR + 0x220)
+#define CLASS_IRAM_DATA_3 (CLASS_CSR_BASE_ADDR + 0x224)
+
+#define CLASS_BUS_ACCESS_ADDR (CLASS_CSR_BASE_ADDR + 0x228)
+
+#define CLASS_BUS_ACCESS_WDATA (CLASS_CSR_BASE_ADDR + 0x22c)
+#define CLASS_BUS_ACCESS_RDATA (CLASS_CSR_BASE_ADDR + 0x230)
+
+/* (route_entry_size[9:0], route_hash_size[23:16]
+ * (this is actually ln2(size)))
+ */
+#define CLASS_ROUTE_HASH_ENTRY_SIZE (CLASS_CSR_BASE_ADDR + 0x234)
+
+#define CLASS_ROUTE_ENTRY_SIZE(size) ((size) & 0x1ff)
+#define CLASS_ROUTE_HASH_SIZE(hash_bits) (((hash_bits) & 0xff) << 16)
+
+#define CLASS_ROUTE_TABLE_BASE (CLASS_CSR_BASE_ADDR + 0x238)
+
+#define CLASS_ROUTE_MULTI (CLASS_CSR_BASE_ADDR + 0x23c)
+#define CLASS_SMEM_OFFSET (CLASS_CSR_BASE_ADDR + 0x240)
+#define CLASS_LMEM_BUF_SIZE (CLASS_CSR_BASE_ADDR + 0x244)
+#define CLASS_VLAN_ID (CLASS_CSR_BASE_ADDR + 0x248)
+#define CLASS_BMU1_BUF_FREE (CLASS_CSR_BASE_ADDR + 0x24c)
+#define CLASS_USE_TMU_INQ (CLASS_CSR_BASE_ADDR + 0x250)
+#define CLASS_VLAN_ID1 (CLASS_CSR_BASE_ADDR + 0x254)
+
+#define CLASS_BUS_ACCESS_BASE (CLASS_CSR_BASE_ADDR + 0x258)
+#define CLASS_BUS_ACCESS_BASE_MASK (0xFF000000)
+/* bit 31:24 of PE peripheral address are stored in CLASS_BUS_ACCESS_BASE */
+
+#define CLASS_HIF_PARSE (CLASS_CSR_BASE_ADDR + 0x25c)
+
+#define CLASS_HOST_PE0_GP (CLASS_CSR_BASE_ADDR + 0x260)
+#define CLASS_PE0_GP (CLASS_CSR_BASE_ADDR + 0x264)
+#define CLASS_HOST_PE1_GP (CLASS_CSR_BASE_ADDR + 0x268)
+#define CLASS_PE1_GP (CLASS_CSR_BASE_ADDR + 0x26c)
+#define CLASS_HOST_PE2_GP (CLASS_CSR_BASE_ADDR + 0x270)
+#define CLASS_PE2_GP (CLASS_CSR_BASE_ADDR + 0x274)
+#define CLASS_HOST_PE3_GP (CLASS_CSR_BASE_ADDR + 0x278)
+#define CLASS_PE3_GP (CLASS_CSR_BASE_ADDR + 0x27c)
+#define CLASS_HOST_PE4_GP (CLASS_CSR_BASE_ADDR + 0x280)
+#define CLASS_PE4_GP (CLASS_CSR_BASE_ADDR + 0x284)
+#define CLASS_HOST_PE5_GP (CLASS_CSR_BASE_ADDR + 0x288)
+#define CLASS_PE5_GP (CLASS_CSR_BASE_ADDR + 0x28c)
+
+#define CLASS_PE_INT_SRC (CLASS_CSR_BASE_ADDR + 0x290)
+#define CLASS_PE_INT_ENABLE (CLASS_CSR_BASE_ADDR + 0x294)
+
+#define CLASS_TPID0_TPID1 (CLASS_CSR_BASE_ADDR + 0x298)
+#define CLASS_TPID2 (CLASS_CSR_BASE_ADDR + 0x29c)
+
+#define CLASS_L4_CHKSUM_ADDR (CLASS_CSR_BASE_ADDR + 0x2a0)
+
+#define CLASS_PE0_DEBUG (CLASS_CSR_BASE_ADDR + 0x2a4)
+#define CLASS_PE1_DEBUG (CLASS_CSR_BASE_ADDR + 0x2a8)
+#define CLASS_PE2_DEBUG (CLASS_CSR_BASE_ADDR + 0x2ac)
+#define CLASS_PE3_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b0)
+#define CLASS_PE4_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b4)
+#define CLASS_PE5_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b8)
+
+#define CLASS_STATE (CLASS_CSR_BASE_ADDR + 0x2bc)
+
+/* CLASS defines */
+#define CLASS_PBUF_SIZE 0x100 /* Fixed by hardware */
+#define CLASS_PBUF_HEADER_OFFSET 0x80 /* Can be configured */
+
+/* Can be configured */
+#define CLASS_PBUF0_BASE_ADDR 0x000
+/* Can be configured */
+#define CLASS_PBUF1_BASE_ADDR (CLASS_PBUF0_BASE_ADDR + CLASS_PBUF_SIZE)
+/* Can be configured */
+#define CLASS_PBUF2_BASE_ADDR (CLASS_PBUF1_BASE_ADDR + CLASS_PBUF_SIZE)
+/* Can be configured */
+#define CLASS_PBUF3_BASE_ADDR (CLASS_PBUF2_BASE_ADDR + CLASS_PBUF_SIZE)
+
+#define CLASS_PBUF0_HEADER_BASE_ADDR (CLASS_PBUF0_BASE_ADDR + \
+ CLASS_PBUF_HEADER_OFFSET)
+#define CLASS_PBUF1_HEADER_BASE_ADDR (CLASS_PBUF1_BASE_ADDR + \
+ CLASS_PBUF_HEADER_OFFSET)
+#define CLASS_PBUF2_HEADER_BASE_ADDR (CLASS_PBUF2_BASE_ADDR + \
+ CLASS_PBUF_HEADER_OFFSET)
+#define CLASS_PBUF3_HEADER_BASE_ADDR (CLASS_PBUF3_BASE_ADDR + \
+ CLASS_PBUF_HEADER_OFFSET)
+
+#define CLASS_PE0_RO_DM_ADDR0_VAL ((CLASS_PBUF1_BASE_ADDR << 16) | \
+ CLASS_PBUF0_BASE_ADDR)
+#define CLASS_PE0_RO_DM_ADDR1_VAL ((CLASS_PBUF3_BASE_ADDR << 16) | \
+ CLASS_PBUF2_BASE_ADDR)
+
+#define CLASS_PE0_QB_DM_ADDR0_VAL ((CLASS_PBUF1_HEADER_BASE_ADDR << 16) |\
+ CLASS_PBUF0_HEADER_BASE_ADDR)
+#define CLASS_PE0_QB_DM_ADDR1_VAL ((CLASS_PBUF3_HEADER_BASE_ADDR << 16) |\
+ CLASS_PBUF2_HEADER_BASE_ADDR)
+
+#define CLASS_ROUTE_SIZE 128
+#define CLASS_MAX_ROUTE_SIZE 256
+#define CLASS_ROUTE_HASH_BITS 20
+#define CLASS_ROUTE_HASH_MASK (BIT(CLASS_ROUTE_HASH_BITS) - 1)
+
+/* Can be configured */
+#define CLASS_ROUTE0_BASE_ADDR 0x400
+/* Can be configured */
+#define CLASS_ROUTE1_BASE_ADDR (CLASS_ROUTE0_BASE_ADDR + CLASS_ROUTE_SIZE)
+/* Can be configured */
+#define CLASS_ROUTE2_BASE_ADDR (CLASS_ROUTE1_BASE_ADDR + CLASS_ROUTE_SIZE)
+/* Can be configured */
+#define CLASS_ROUTE3_BASE_ADDR (CLASS_ROUTE2_BASE_ADDR + CLASS_ROUTE_SIZE)
+
+#define CLASS_SA_SIZE 128
+#define CLASS_IPSEC_SA0_BASE_ADDR 0x600
+/* not used */
+#define CLASS_IPSEC_SA1_BASE_ADDR (CLASS_IPSEC_SA0_BASE_ADDR + CLASS_SA_SIZE)
+/* not used */
+#define CLASS_IPSEC_SA2_BASE_ADDR (CLASS_IPSEC_SA1_BASE_ADDR + CLASS_SA_SIZE)
+/* not used */
+#define CLASS_IPSEC_SA3_BASE_ADDR (CLASS_IPSEC_SA2_BASE_ADDR + CLASS_SA_SIZE)
+
+/* generic purpose free dmem buffer, last portion of 2K dmem pbuf */
+#define CLASS_GP_DMEM_BUF_SIZE (2048 - (CLASS_PBUF_SIZE * 4) - \
+ (CLASS_ROUTE_SIZE * 4) - (CLASS_SA_SIZE))
+#define CLASS_GP_DMEM_BUF ((void *)(CLASS_IPSEC_SA0_BASE_ADDR + \
+ CLASS_SA_SIZE))
+
+#define TWO_LEVEL_ROUTE BIT(0)
+#define PHYNO_IN_HASH BIT(1)
+#define HW_ROUTE_FETCH BIT(3)
+#define HW_BRIDGE_FETCH BIT(5)
+#define IP_ALIGNED BIT(6)
+#define ARC_HIT_CHECK_EN BIT(7)
+#define CLASS_TOE BIT(11)
+#define HASH_NORMAL (0 << 12)
+#define HASH_CRC_PORT BIT(12)
+#define HASH_CRC_IP (2 << 12)
+#define HASH_CRC_PORT_IP (3 << 12)
+#define QB2BUS_LE BIT(15)
+
+#define TCP_CHKSUM_DROP BIT(0)
+#define UDP_CHKSUM_DROP BIT(1)
+#define IPV4_CHKSUM_DROP BIT(9)
+
+/*CLASS_HIF_PARSE bits*/
+#define HIF_PKT_CLASS_EN BIT(0)
+#define HIF_PKT_OFFSET(ofst) (((ofst) & 0xF) << 1)
+
+struct class_cfg {
+ u32 toe_mode;
+ unsigned long route_table_baseaddr;
+ u32 route_table_hash_bits;
+ u32 pe_sys_clk_ratio;
+ u32 resume;
+};
+
+#endif /* _CLASS_CSR_H_ */
--- /dev/null
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright 2019 NXP
+ */
+
+#ifndef _EMAC_H_
+#define _EMAC_H_
+
+/* This file is for Ethernet MAC registers and offsets
+ */
+
+#include <linux/ethtool.h>
+
+#define EMAC_IEVENT_REG 0x004
+#define EMAC_IMASK_REG 0x008
+#define EMAC_R_DES_ACTIVE_REG 0x010
+#define EMAC_X_DES_ACTIVE_REG 0x014
+#define EMAC_ECNTRL_REG 0x024
+#define EMAC_MII_DATA_REG 0x040
+#define EMAC_MII_CTRL_REG 0x044
+#define EMAC_MIB_CTRL_STS_REG 0x064
+#define EMAC_RCNTRL_REG 0x084
+#define EMAC_TCNTRL_REG 0x0C4
+#define EMAC_PHY_ADDR_LOW 0x0E4
+#define EMAC_PHY_ADDR_HIGH 0x0E8
+#define EMAC_GAUR 0x120
+#define EMAC_GALR 0x124
+#define EMAC_TFWR_STR_FWD 0x144
+#define EMAC_RX_SECTION_FULL 0x190
+#define EMAC_RX_SECTION_EMPTY 0x194
+#define EMAC_TX_SECTION_EMPTY 0x1A0
+#define EMAC_TRUNC_FL 0x1B0
+
+#define RMON_T_DROP 0x200 /* Count of frames not cntd correctly */
+#define RMON_T_PACKETS 0x204 /* RMON TX packet count */
+#define RMON_T_BC_PKT 0x208 /* RMON TX broadcast pkts */
+#define RMON_T_MC_PKT 0x20c /* RMON TX multicast pkts */
+#define RMON_T_CRC_ALIGN 0x210 /* RMON TX pkts with CRC align err */
+#define RMON_T_UNDERSIZE 0x214 /* RMON TX pkts < 64 bytes, good CRC */
+#define RMON_T_OVERSIZE 0x218 /* RMON TX pkts > MAX_FL bytes good CRC */
+#define RMON_T_FRAG 0x21c /* RMON TX pkts < 64 bytes, bad CRC */
+#define RMON_T_JAB 0x220 /* RMON TX pkts > MAX_FL bytes, bad CRC */
+#define RMON_T_COL 0x224 /* RMON TX collision count */
+#define RMON_T_P64 0x228 /* RMON TX 64 byte pkts */
+#define RMON_T_P65TO127 0x22c /* RMON TX 65 to 127 byte pkts */
+#define RMON_T_P128TO255 0x230 /* RMON TX 128 to 255 byte pkts */
+#define RMON_T_P256TO511 0x234 /* RMON TX 256 to 511 byte pkts */
+#define RMON_T_P512TO1023 0x238 /* RMON TX 512 to 1023 byte pkts */
+#define RMON_T_P1024TO2047 0x23c /* RMON TX 1024 to 2047 byte pkts */
+#define RMON_T_P_GTE2048 0x240 /* RMON TX pkts > 2048 bytes */
+#define RMON_T_OCTETS 0x244 /* RMON TX octets */
+#define IEEE_T_DROP 0x248 /* Count of frames not counted crtly */
+#define IEEE_T_FRAME_OK 0x24c /* Frames tx'd OK */
+#define IEEE_T_1COL 0x250 /* Frames tx'd with single collision */
+#define IEEE_T_MCOL 0x254 /* Frames tx'd with multiple collision */
+#define IEEE_T_DEF 0x258 /* Frames tx'd after deferral delay */
+#define IEEE_T_LCOL 0x25c /* Frames tx'd with late collision */
+#define IEEE_T_EXCOL 0x260 /* Frames tx'd with excesv collisions */
+#define IEEE_T_MACERR 0x264 /* Frames tx'd with TX FIFO underrun */
+#define IEEE_T_CSERR 0x268 /* Frames tx'd with carrier sense err */
+#define IEEE_T_SQE 0x26c /* Frames tx'd with SQE err */
+#define IEEE_T_FDXFC 0x270 /* Flow control pause frames tx'd */
+#define IEEE_T_OCTETS_OK 0x274 /* Octet count for frames tx'd w/o err */
+#define RMON_R_PACKETS 0x284 /* RMON RX packet count */
+#define RMON_R_BC_PKT 0x288 /* RMON RX broadcast pkts */
+#define RMON_R_MC_PKT 0x28c /* RMON RX multicast pkts */
+#define RMON_R_CRC_ALIGN 0x290 /* RMON RX pkts with CRC alignment err */
+#define RMON_R_UNDERSIZE 0x294 /* RMON RX pkts < 64 bytes, good CRC */
+#define RMON_R_OVERSIZE 0x298 /* RMON RX pkts > MAX_FL bytes good CRC */
+#define RMON_R_FRAG 0x29c /* RMON RX pkts < 64 bytes, bad CRC */
+#define RMON_R_JAB 0x2a0 /* RMON RX pkts > MAX_FL bytes, bad CRC */
+#define RMON_R_RESVD_O 0x2a4 /* Reserved */
+#define RMON_R_P64 0x2a8 /* RMON RX 64 byte pkts */
+#define RMON_R_P65TO127 0x2ac /* RMON RX 65 to 127 byte pkts */
+#define RMON_R_P128TO255 0x2b0 /* RMON RX 128 to 255 byte pkts */
+#define RMON_R_P256TO511 0x2b4 /* RMON RX 256 to 511 byte pkts */
+#define RMON_R_P512TO1023 0x2b8 /* RMON RX 512 to 1023 byte pkts */
+#define RMON_R_P1024TO2047 0x2bc /* RMON RX 1024 to 2047 byte pkts */
+#define RMON_R_P_GTE2048 0x2c0 /* RMON RX pkts > 2048 bytes */
+#define RMON_R_OCTETS 0x2c4 /* RMON RX octets */
+#define IEEE_R_DROP 0x2c8 /* Count frames not counted correctly */
+#define IEEE_R_FRAME_OK 0x2cc /* Frames rx'd OK */
+#define IEEE_R_CRC 0x2d0 /* Frames rx'd with CRC err */
+#define IEEE_R_ALIGN 0x2d4 /* Frames rx'd with alignment err */
+#define IEEE_R_MACERR 0x2d8 /* Receive FIFO overflow count */
+#define IEEE_R_FDXFC 0x2dc /* Flow control pause frames rx'd */
+#define IEEE_R_OCTETS_OK 0x2e0 /* Octet cnt for frames rx'd w/o err */
+
+#define EMAC_SMAC_0_0 0x500 /*Supplemental MAC Address 0 (RW).*/
+#define EMAC_SMAC_0_1 0x504 /*Supplemental MAC Address 0 (RW).*/
+
+/* GEMAC definitions and settings */
+
+#define EMAC_PORT_0 0
+#define EMAC_PORT_1 1
+
+/* GEMAC Bit definitions */
+#define EMAC_IEVENT_HBERR 0x80000000
+#define EMAC_IEVENT_BABR 0x40000000
+#define EMAC_IEVENT_BABT 0x20000000
+#define EMAC_IEVENT_GRA 0x10000000
+#define EMAC_IEVENT_TXF 0x08000000
+#define EMAC_IEVENT_TXB 0x04000000
+#define EMAC_IEVENT_RXF 0x02000000
+#define EMAC_IEVENT_RXB 0x01000000
+#define EMAC_IEVENT_MII 0x00800000
+#define EMAC_IEVENT_EBERR 0x00400000
+#define EMAC_IEVENT_LC 0x00200000
+#define EMAC_IEVENT_RL 0x00100000
+#define EMAC_IEVENT_UN 0x00080000
+
+#define EMAC_IMASK_HBERR 0x80000000
+#define EMAC_IMASK_BABR 0x40000000
+#define EMAC_IMASKT_BABT 0x20000000
+#define EMAC_IMASK_GRA 0x10000000
+#define EMAC_IMASKT_TXF 0x08000000
+#define EMAC_IMASK_TXB 0x04000000
+#define EMAC_IMASKT_RXF 0x02000000
+#define EMAC_IMASK_RXB 0x01000000
+#define EMAC_IMASK_MII 0x00800000
+#define EMAC_IMASK_EBERR 0x00400000
+#define EMAC_IMASK_LC 0x00200000
+#define EMAC_IMASKT_RL 0x00100000
+#define EMAC_IMASK_UN 0x00080000
+
+#define EMAC_RCNTRL_MAX_FL_SHIFT 16
+#define EMAC_RCNTRL_LOOP 0x00000001
+#define EMAC_RCNTRL_DRT 0x00000002
+#define EMAC_RCNTRL_MII_MODE 0x00000004
+#define EMAC_RCNTRL_PROM 0x00000008
+#define EMAC_RCNTRL_BC_REJ 0x00000010
+#define EMAC_RCNTRL_FCE 0x00000020
+#define EMAC_RCNTRL_RGMII 0x00000040
+#define EMAC_RCNTRL_SGMII 0x00000080
+#define EMAC_RCNTRL_RMII 0x00000100
+#define EMAC_RCNTRL_RMII_10T 0x00000200
+#define EMAC_RCNTRL_CRC_FWD 0x00004000
+
+#define EMAC_TCNTRL_GTS 0x00000001
+#define EMAC_TCNTRL_HBC 0x00000002
+#define EMAC_TCNTRL_FDEN 0x00000004
+#define EMAC_TCNTRL_TFC_PAUSE 0x00000008
+#define EMAC_TCNTRL_RFC_PAUSE 0x00000010
+
+#define EMAC_ECNTRL_RESET 0x00000001 /* reset the EMAC */
+#define EMAC_ECNTRL_ETHER_EN 0x00000002 /* enable the EMAC */
+#define EMAC_ECNTRL_MAGIC_ENA 0x00000004
+#define EMAC_ECNTRL_SLEEP 0x00000008
+#define EMAC_ECNTRL_SPEED 0x00000020
+#define EMAC_ECNTRL_DBSWAP 0x00000100
+
+#define EMAC_X_WMRK_STRFWD 0x00000100
+
+#define EMAC_X_DES_ACTIVE_TDAR 0x01000000
+#define EMAC_R_DES_ACTIVE_RDAR 0x01000000
+
+#define EMAC_RX_SECTION_EMPTY_V 0x00010006
+/*
+ * The possible operating speeds of the MAC, currently supporting 10, 100 and
+ * 1000Mb modes.
+ */
+enum mac_speed {SPEED_10M, SPEED_100M, SPEED_1000M, SPEED_1000M_PCS};
+
+/* MII-related definitios */
+#define EMAC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */
+#define EMAC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */
+#define EMAC_MII_DATA_OP_CL45_RD 0x30000000 /* Perform a read operation */
+#define EMAC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */
+#define EMAC_MII_DATA_OP_CL45_WR 0x10000000 /* Perform a write operation */
+#define EMAC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */
+#define EMAC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */
+#define EMAC_MII_DATA_TA 0x00020000 /* Turnaround */
+#define EMAC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */
+
+#define EMAC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */
+#define EMAC_MII_DATA_RA_MASK 0x1F /* MII Register address mask */
+#define EMAC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */
+#define EMAC_MII_DATA_PA_MASK 0x1F /* MII PHY address mask */
+
+#define EMAC_MII_DATA_RA(v) (((v) & EMAC_MII_DATA_RA_MASK) << \
+ EMAC_MII_DATA_RA_SHIFT)
+#define EMAC_MII_DATA_PA(v) (((v) & EMAC_MII_DATA_RA_MASK) << \
+ EMAC_MII_DATA_PA_SHIFT)
+#define EMAC_MII_DATA(v) ((v) & 0xffff)
+
+#define EMAC_MII_SPEED_SHIFT 1
+#define EMAC_HOLDTIME_SHIFT 8
+#define EMAC_HOLDTIME_MASK 0x7
+#define EMAC_HOLDTIME(v) (((v) & EMAC_HOLDTIME_MASK) << \
+ EMAC_HOLDTIME_SHIFT)
+
+/*
+ * The Address organisation for the MAC device. All addresses are split into
+ * two 32-bit register fields. The first one (bottom) is the lower 32-bits of
+ * the address and the other field are the high order bits - this may be 16-bits
+ * in the case of MAC addresses, or 32-bits for the hash address.
+ * In terms of memory storage, the first item (bottom) is assumed to be at a
+ * lower address location than 'top'. i.e. top should be at address location of
+ * 'bottom' + 4 bytes.
+ */
+struct pfe_mac_addr {
+ u32 bottom; /* Lower 32-bits of address. */
+ u32 top; /* Upper 32-bits of address. */
+};
+
+/*
+ * The following is the organisation of the address filters section of the MAC
+ * registers. The Cadence MAC contains four possible specific address match
+ * addresses, if an incoming frame corresponds to any one of these four
+ * addresses then the frame will be copied to memory.
+ * It is not necessary for all four of the address match registers to be
+ * programmed, this is application dependent.
+ */
+struct spec_addr {
+ struct pfe_mac_addr one; /* Specific address register 1. */
+ struct pfe_mac_addr two; /* Specific address register 2. */
+ struct pfe_mac_addr three; /* Specific address register 3. */
+ struct pfe_mac_addr four; /* Specific address register 4. */
+};
+
+struct gemac_cfg {
+ u32 mode;
+ u32 speed;
+ u32 duplex;
+};
+
+/* EMAC Hash size */
+#define EMAC_HASH_REG_BITS 64
+
+#define EMAC_SPEC_ADDR_MAX 4
+
+#endif /* _EMAC_H_ */
--- /dev/null
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright 2019 NXP
+ */
+
+#ifndef _GPI_H_
+#define _GPI_H_
+
+/* Generic Packet Interface:The generic packet interface block interfaces
+ * to block like ethernet, Host interfac and covert data into WSP internal
+ * structures
+ */
+
+#define GPI_VERSION 0x00
+#define GPI_CTRL 0x04
+#define GPI_RX_CONFIG 0x08
+#define GPI_HDR_SIZE 0x0c
+#define GPI_BUF_SIZE 0x10
+#define GPI_LMEM_ALLOC_ADDR 0x14
+#define GPI_LMEM_FREE_ADDR 0x18
+#define GPI_DDR_ALLOC_ADDR 0x1c
+#define GPI_DDR_FREE_ADDR 0x20
+#define GPI_CLASS_ADDR 0x24
+#define GPI_DRX_FIFO 0x28
+#define GPI_TRX_FIFO 0x2c
+#define GPI_INQ_PKTPTR 0x30
+#define GPI_DDR_DATA_OFFSET 0x34
+#define GPI_LMEM_DATA_OFFSET 0x38
+#define GPI_TMLF_TX 0x4c
+#define GPI_DTX_ASEQ 0x50
+#define GPI_FIFO_STATUS 0x54
+#define GPI_FIFO_DEBUG 0x58
+#define GPI_TX_PAUSE_TIME 0x5c
+#define GPI_LMEM_SEC_BUF_DATA_OFFSET 0x60
+#define GPI_DDR_SEC_BUF_DATA_OFFSET 0x64
+#define GPI_TOE_CHKSUM_EN 0x68
+#define GPI_OVERRUN_DROPCNT 0x6c
+#define GPI_CSR_MTIP_PAUSE_REG 0x74
+#define GPI_CSR_MTIP_PAUSE_QUANTUM 0x78
+#define GPI_CSR_RX_CNT 0x7c
+#define GPI_CSR_TX_CNT 0x80
+#define GPI_CSR_DEBUG1 0x84
+#define GPI_CSR_DEBUG2 0x88
+
+struct gpi_cfg {
+ u32 lmem_rtry_cnt;
+ u32 tmlf_txthres;
+ u32 aseq_len;
+ u32 mtip_pause_reg;
+};
+
+/* GPI commons defines */
+#define GPI_LMEM_BUF_EN 0x1
+#define GPI_DDR_BUF_EN 0x1
+
+/* EGPI 1 defines */
+#define EGPI1_LMEM_RTRY_CNT 0x40
+#define EGPI1_TMLF_TXTHRES 0xBC
+#define EGPI1_ASEQ_LEN 0x50
+
+/* EGPI 2 defines */
+#define EGPI2_LMEM_RTRY_CNT 0x40
+#define EGPI2_TMLF_TXTHRES 0xBC
+#define EGPI2_ASEQ_LEN 0x40
+
+/* EGPI 3 defines */
+#define EGPI3_LMEM_RTRY_CNT 0x40
+#define EGPI3_TMLF_TXTHRES 0xBC
+#define EGPI3_ASEQ_LEN 0x40
+
+/* HGPI defines */
+#define HGPI_LMEM_RTRY_CNT 0x40
+#define HGPI_TMLF_TXTHRES 0xBC
+#define HGPI_ASEQ_LEN 0x40
+
+#define EGPI_PAUSE_TIME 0x000007D0
+#define EGPI_PAUSE_ENABLE 0x40000000
+#endif /* _GPI_H_ */
--- /dev/null
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright 2019 NXP
+ */
+
+#ifndef _HIF_H_
+#define _HIF_H_
+
+/* @file hif.h.
+ * hif - PFE hif block control and status register.
+ * Mapped on CBUS and accessible from all PE's and ARM.
+ */
+#define HIF_VERSION (HIF_BASE_ADDR + 0x00)
+#define HIF_TX_CTRL (HIF_BASE_ADDR + 0x04)
+#define HIF_TX_CURR_BD_ADDR (HIF_BASE_ADDR + 0x08)
+#define HIF_TX_ALLOC (HIF_BASE_ADDR + 0x0c)
+#define HIF_TX_BDP_ADDR (HIF_BASE_ADDR + 0x10)
+#define HIF_TX_STATUS (HIF_BASE_ADDR + 0x14)
+#define HIF_RX_CTRL (HIF_BASE_ADDR + 0x20)
+#define HIF_RX_BDP_ADDR (HIF_BASE_ADDR + 0x24)
+#define HIF_RX_STATUS (HIF_BASE_ADDR + 0x30)
+#define HIF_INT_SRC (HIF_BASE_ADDR + 0x34)
+#define HIF_INT_ENABLE (HIF_BASE_ADDR + 0x38)
+#define HIF_POLL_CTRL (HIF_BASE_ADDR + 0x3c)
+#define HIF_RX_CURR_BD_ADDR (HIF_BASE_ADDR + 0x40)
+#define HIF_RX_ALLOC (HIF_BASE_ADDR + 0x44)
+#define HIF_TX_DMA_STATUS (HIF_BASE_ADDR + 0x48)
+#define HIF_RX_DMA_STATUS (HIF_BASE_ADDR + 0x4c)
+#define HIF_INT_COAL (HIF_BASE_ADDR + 0x50)
+
+/* HIF_INT_SRC/ HIF_INT_ENABLE control bits */
+#define HIF_INT BIT(0)
+#define HIF_RXBD_INT BIT(1)
+#define HIF_RXPKT_INT BIT(2)
+#define HIF_TXBD_INT BIT(3)
+#define HIF_TXPKT_INT BIT(4)
+
+/* HIF_TX_CTRL bits */
+#define HIF_CTRL_DMA_EN BIT(0)
+#define HIF_CTRL_BDP_POLL_CTRL_EN BIT(1)
+#define HIF_CTRL_BDP_CH_START_WSTB BIT(2)
+
+/* HIF_RX_STATUS bits */
+#define BDP_CSR_RX_DMA_ACTV BIT(16)
+
+/* HIF_INT_ENABLE bits */
+#define HIF_INT_EN BIT(0)
+#define HIF_RXBD_INT_EN BIT(1)
+#define HIF_RXPKT_INT_EN BIT(2)
+#define HIF_TXBD_INT_EN BIT(3)
+#define HIF_TXPKT_INT_EN BIT(4)
+
+/* HIF_POLL_CTRL bits*/
+#define HIF_RX_POLL_CTRL_CYCLE 0x0400
+#define HIF_TX_POLL_CTRL_CYCLE 0x0400
+
+/* HIF_INT_COAL bits*/
+#define HIF_INT_COAL_ENABLE BIT(31)
+
+/* Buffer descriptor control bits */
+#define BD_CTRL_BUFLEN_MASK 0x3fff
+#define BD_BUF_LEN(x) ((x) & BD_CTRL_BUFLEN_MASK)
+#define BD_CTRL_CBD_INT_EN BIT(16)
+#define BD_CTRL_PKT_INT_EN BIT(17)
+#define BD_CTRL_LIFM BIT(18)
+#define BD_CTRL_LAST_BD BIT(19)
+#define BD_CTRL_DIR BIT(20)
+#define BD_CTRL_LMEM_CPY BIT(21) /* Valid only for HIF_NOCPY */
+#define BD_CTRL_PKT_XFER BIT(24)
+#define BD_CTRL_DESC_EN BIT(31)
+#define BD_CTRL_PARSE_DISABLE BIT(25)
+#define BD_CTRL_BRFETCH_DISABLE BIT(26)
+#define BD_CTRL_RTFETCH_DISABLE BIT(27)
+
+/* Buffer descriptor status bits*/
+#define BD_STATUS_CONN_ID(x) ((x) & 0xffff)
+#define BD_STATUS_DIR_PROC_ID BIT(16)
+#define BD_STATUS_CONN_ID_EN BIT(17)
+#define BD_STATUS_PE2PROC_ID(x) (((x) & 7) << 18)
+#define BD_STATUS_LE_DATA BIT(21)
+#define BD_STATUS_CHKSUM_EN BIT(22)
+
+/* HIF Buffer descriptor status bits */
+#define DIR_PROC_ID BIT(16)
+#define PROC_ID(id) ((id) << 18)
+
+#endif /* _HIF_H_ */
--- /dev/null
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright 2019 NXP
+ */
+
+#ifndef _HIF_NOCPY_H_
+#define _HIF_NOCPY_H_
+
+#define HIF_NOCPY_VERSION (HIF_NOCPY_BASE_ADDR + 0x00)
+#define HIF_NOCPY_TX_CTRL (HIF_NOCPY_BASE_ADDR + 0x04)
+#define HIF_NOCPY_TX_CURR_BD_ADDR (HIF_NOCPY_BASE_ADDR + 0x08)
+#define HIF_NOCPY_TX_ALLOC (HIF_NOCPY_BASE_ADDR + 0x0c)
+#define HIF_NOCPY_TX_BDP_ADDR (HIF_NOCPY_BASE_ADDR + 0x10)
+#define HIF_NOCPY_TX_STATUS (HIF_NOCPY_BASE_ADDR + 0x14)
+#define HIF_NOCPY_RX_CTRL (HIF_NOCPY_BASE_ADDR + 0x20)
+#define HIF_NOCPY_RX_BDP_ADDR (HIF_NOCPY_BASE_ADDR + 0x24)
+#define HIF_NOCPY_RX_STATUS (HIF_NOCPY_BASE_ADDR + 0x30)
+#define HIF_NOCPY_INT_SRC (HIF_NOCPY_BASE_ADDR + 0x34)
+#define HIF_NOCPY_INT_ENABLE (HIF_NOCPY_BASE_ADDR + 0x38)
+#define HIF_NOCPY_POLL_CTRL (HIF_NOCPY_BASE_ADDR + 0x3c)
+#define HIF_NOCPY_RX_CURR_BD_ADDR (HIF_NOCPY_BASE_ADDR + 0x40)
+#define HIF_NOCPY_RX_ALLOC (HIF_NOCPY_BASE_ADDR + 0x44)
+#define HIF_NOCPY_TX_DMA_STATUS (HIF_NOCPY_BASE_ADDR + 0x48)
+#define HIF_NOCPY_RX_DMA_STATUS (HIF_NOCPY_BASE_ADDR + 0x4c)
+#define HIF_NOCPY_RX_INQ0_PKTPTR (HIF_NOCPY_BASE_ADDR + 0x50)
+#define HIF_NOCPY_RX_INQ1_PKTPTR (HIF_NOCPY_BASE_ADDR + 0x54)
+#define HIF_NOCPY_TX_PORT_NO (HIF_NOCPY_BASE_ADDR + 0x60)
+#define HIF_NOCPY_LMEM_ALLOC_ADDR (HIF_NOCPY_BASE_ADDR + 0x64)
+#define HIF_NOCPY_CLASS_ADDR (HIF_NOCPY_BASE_ADDR + 0x68)
+#define HIF_NOCPY_TMU_PORT0_ADDR (HIF_NOCPY_BASE_ADDR + 0x70)
+#define HIF_NOCPY_TMU_PORT1_ADDR (HIF_NOCPY_BASE_ADDR + 0x74)
+#define HIF_NOCPY_TMU_PORT2_ADDR (HIF_NOCPY_BASE_ADDR + 0x7c)
+#define HIF_NOCPY_TMU_PORT3_ADDR (HIF_NOCPY_BASE_ADDR + 0x80)
+#define HIF_NOCPY_TMU_PORT4_ADDR (HIF_NOCPY_BASE_ADDR + 0x84)
+#define HIF_NOCPY_INT_COAL (HIF_NOCPY_BASE_ADDR + 0x90)
+
+#endif /* _HIF_NOCPY_H_ */
--- /dev/null
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright 2019 NXP
+ */
+
+#ifndef _TMU_CSR_H_
+#define _TMU_CSR_H_
+
+#define TMU_VERSION (TMU_CSR_BASE_ADDR + 0x000)
+#define TMU_INQ_WATERMARK (TMU_CSR_BASE_ADDR + 0x004)
+#define TMU_PHY_INQ_PKTPTR (TMU_CSR_BASE_ADDR + 0x008)
+#define TMU_PHY_INQ_PKTINFO (TMU_CSR_BASE_ADDR + 0x00c)
+#define TMU_PHY_INQ_FIFO_CNT (TMU_CSR_BASE_ADDR + 0x010)
+#define TMU_SYS_GENERIC_CONTROL (TMU_CSR_BASE_ADDR + 0x014)
+#define TMU_SYS_GENERIC_STATUS (TMU_CSR_BASE_ADDR + 0x018)
+#define TMU_SYS_GEN_CON0 (TMU_CSR_BASE_ADDR + 0x01c)
+#define TMU_SYS_GEN_CON1 (TMU_CSR_BASE_ADDR + 0x020)
+#define TMU_SYS_GEN_CON2 (TMU_CSR_BASE_ADDR + 0x024)
+#define TMU_SYS_GEN_CON3 (TMU_CSR_BASE_ADDR + 0x028)
+#define TMU_SYS_GEN_CON4 (TMU_CSR_BASE_ADDR + 0x02c)
+#define TMU_TEQ_DISABLE_DROPCHK (TMU_CSR_BASE_ADDR + 0x030)
+#define TMU_TEQ_CTRL (TMU_CSR_BASE_ADDR + 0x034)
+#define TMU_TEQ_QCFG (TMU_CSR_BASE_ADDR + 0x038)
+#define TMU_TEQ_DROP_STAT (TMU_CSR_BASE_ADDR + 0x03c)
+#define TMU_TEQ_QAVG (TMU_CSR_BASE_ADDR + 0x040)
+#define TMU_TEQ_WREG_PROB (TMU_CSR_BASE_ADDR + 0x044)
+#define TMU_TEQ_TRANS_STAT (TMU_CSR_BASE_ADDR + 0x048)
+#define TMU_TEQ_HW_PROB_CFG0 (TMU_CSR_BASE_ADDR + 0x04c)
+#define TMU_TEQ_HW_PROB_CFG1 (TMU_CSR_BASE_ADDR + 0x050)
+#define TMU_TEQ_HW_PROB_CFG2 (TMU_CSR_BASE_ADDR + 0x054)
+#define TMU_TEQ_HW_PROB_CFG3 (TMU_CSR_BASE_ADDR + 0x058)
+#define TMU_TEQ_HW_PROB_CFG4 (TMU_CSR_BASE_ADDR + 0x05c)
+#define TMU_TEQ_HW_PROB_CFG5 (TMU_CSR_BASE_ADDR + 0x060)
+#define TMU_TEQ_HW_PROB_CFG6 (TMU_CSR_BASE_ADDR + 0x064)
+#define TMU_TEQ_HW_PROB_CFG7 (TMU_CSR_BASE_ADDR + 0x068)
+#define TMU_TEQ_HW_PROB_CFG8 (TMU_CSR_BASE_ADDR + 0x06c)
+#define TMU_TEQ_HW_PROB_CFG9 (TMU_CSR_BASE_ADDR + 0x070)
+#define TMU_TEQ_HW_PROB_CFG10 (TMU_CSR_BASE_ADDR + 0x074)
+#define TMU_TEQ_HW_PROB_CFG11 (TMU_CSR_BASE_ADDR + 0x078)
+#define TMU_TEQ_HW_PROB_CFG12 (TMU_CSR_BASE_ADDR + 0x07c)
+#define TMU_TEQ_HW_PROB_CFG13 (TMU_CSR_BASE_ADDR + 0x080)
+#define TMU_TEQ_HW_PROB_CFG14 (TMU_CSR_BASE_ADDR + 0x084)
+#define TMU_TEQ_HW_PROB_CFG15 (TMU_CSR_BASE_ADDR + 0x088)
+#define TMU_TEQ_HW_PROB_CFG16 (TMU_CSR_BASE_ADDR + 0x08c)
+#define TMU_TEQ_HW_PROB_CFG17 (TMU_CSR_BASE_ADDR + 0x090)
+#define TMU_TEQ_HW_PROB_CFG18 (TMU_CSR_BASE_ADDR + 0x094)
+#define TMU_TEQ_HW_PROB_CFG19 (TMU_CSR_BASE_ADDR + 0x098)
+#define TMU_TEQ_HW_PROB_CFG20 (TMU_CSR_BASE_ADDR + 0x09c)
+#define TMU_TEQ_HW_PROB_CFG21 (TMU_CSR_BASE_ADDR + 0x0a0)
+#define TMU_TEQ_HW_PROB_CFG22 (TMU_CSR_BASE_ADDR + 0x0a4)
+#define TMU_TEQ_HW_PROB_CFG23 (TMU_CSR_BASE_ADDR + 0x0a8)
+#define TMU_TEQ_HW_PROB_CFG24 (TMU_CSR_BASE_ADDR + 0x0ac)
+#define TMU_TEQ_HW_PROB_CFG25 (TMU_CSR_BASE_ADDR + 0x0b0)
+#define TMU_TDQ_IIFG_CFG (TMU_CSR_BASE_ADDR + 0x0b4)
+/* [9:0] Scheduler Enable for each of the scheduler in the TDQ.
+ * This is a global Enable for all schedulers in PHY0
+ */
+#define TMU_TDQ0_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x0b8)
+
+#define TMU_LLM_CTRL (TMU_CSR_BASE_ADDR + 0x0bc)
+#define TMU_LLM_BASE_ADDR (TMU_CSR_BASE_ADDR + 0x0c0)
+#define TMU_LLM_QUE_LEN (TMU_CSR_BASE_ADDR + 0x0c4)
+#define TMU_LLM_QUE_HEADPTR (TMU_CSR_BASE_ADDR + 0x0c8)
+#define TMU_LLM_QUE_TAILPTR (TMU_CSR_BASE_ADDR + 0x0cc)
+#define TMU_LLM_QUE_DROPCNT (TMU_CSR_BASE_ADDR + 0x0d0)
+#define TMU_INT_EN (TMU_CSR_BASE_ADDR + 0x0d4)
+#define TMU_INT_SRC (TMU_CSR_BASE_ADDR + 0x0d8)
+#define TMU_INQ_STAT (TMU_CSR_BASE_ADDR + 0x0dc)
+#define TMU_CTRL (TMU_CSR_BASE_ADDR + 0x0e0)
+
+/* [31] Mem Access Command. 0 = Internal Memory Read, 1 = Internal memory
+ * Write [27:24] Byte Enables of the Internal memory access [23:0] Address of
+ * the internal memory. This address is used to access both the PM and DM of
+ * all the PE's
+ */
+#define TMU_MEM_ACCESS_ADDR (TMU_CSR_BASE_ADDR + 0x0e4)
+
+/* Internal Memory Access Write Data */
+#define TMU_MEM_ACCESS_WDATA (TMU_CSR_BASE_ADDR + 0x0e8)
+/* Internal Memory Access Read Data. The commands are blocked
+ * at the mem_access only
+ */
+#define TMU_MEM_ACCESS_RDATA (TMU_CSR_BASE_ADDR + 0x0ec)
+
+/* [31:0] PHY0 in queue address (must be initialized with one of the
+ * xxx_INQ_PKTPTR cbus addresses)
+ */
+#define TMU_PHY0_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0f0)
+/* [31:0] PHY1 in queue address (must be initialized with one of the
+ * xxx_INQ_PKTPTR cbus addresses)
+ */
+#define TMU_PHY1_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0f4)
+/* [31:0] PHY2 in queue address (must be initialized with one of the
+ * xxx_INQ_PKTPTR cbus addresses)
+ */
+#define TMU_PHY2_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0f8)
+/* [31:0] PHY3 in queue address (must be initialized with one of the
+ * xxx_INQ_PKTPTR cbus addresses)
+ */
+#define TMU_PHY3_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0fc)
+#define TMU_BMU_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x100)
+#define TMU_TX_CTRL (TMU_CSR_BASE_ADDR + 0x104)
+
+#define TMU_BUS_ACCESS_WDATA (TMU_CSR_BASE_ADDR + 0x108)
+#define TMU_BUS_ACCESS (TMU_CSR_BASE_ADDR + 0x10c)
+#define TMU_BUS_ACCESS_RDATA (TMU_CSR_BASE_ADDR + 0x110)
+
+#define TMU_PE_SYS_CLK_RATIO (TMU_CSR_BASE_ADDR + 0x114)
+#define TMU_PE_STATUS (TMU_CSR_BASE_ADDR + 0x118)
+#define TMU_TEQ_MAX_THRESHOLD (TMU_CSR_BASE_ADDR + 0x11c)
+/* [31:0] PHY4 in queue address (must be initialized with one of the
+ * xxx_INQ_PKTPTR cbus addresses)
+ */
+#define TMU_PHY4_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x134)
+/* [9:0] Scheduler Enable for each of the scheduler in the TDQ.
+ * This is a global Enable for all schedulers in PHY1
+ */
+#define TMU_TDQ1_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x138)
+/* [9:0] Scheduler Enable for each of the scheduler in the TDQ.
+ * This is a global Enable for all schedulers in PHY2
+ */
+#define TMU_TDQ2_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x13c)
+/* [9:0] Scheduler Enable for each of the scheduler in the TDQ.
+ * This is a global Enable for all schedulers in PHY3
+ */
+#define TMU_TDQ3_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x140)
+#define TMU_BMU_BUF_SIZE (TMU_CSR_BASE_ADDR + 0x144)
+/* [31:0] PHY5 in queue address (must be initialized with one of the
+ * xxx_INQ_PKTPTR cbus addresses)
+ */
+#define TMU_PHY5_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x148)
+
+#define SW_RESET BIT(0) /* Global software reset */
+#define INQ_RESET BIT(2)
+#define TEQ_RESET BIT(3)
+#define TDQ_RESET BIT(4)
+#define PE_RESET BIT(5)
+#define MEM_INIT BIT(6)
+#define MEM_INIT_DONE BIT(7)
+#define LLM_INIT BIT(8)
+#define LLM_INIT_DONE BIT(9)
+#define ECC_MEM_INIT_DONE BIT(10)
+
+struct tmu_cfg {
+ u32 pe_sys_clk_ratio;
+ unsigned long llm_base_addr;
+ u32 llm_queue_len;
+};
+
+/* Not HW related for pfe_ctrl / pfe common defines */
+#define DEFAULT_MAX_QDEPTH 80
+#define DEFAULT_Q0_QDEPTH 511 /*We keep one large queue for host tx qos */
+#define DEFAULT_TMU3_QDEPTH 127
+
+#endif /* _TMU_CSR_H_ */
--- /dev/null
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright 2019 NXP
+ */
+
+#ifndef _UTIL_CSR_H_
+#define _UTIL_CSR_H_
+
+#define UTIL_VERSION (UTIL_CSR_BASE_ADDR + 0x000)
+#define UTIL_TX_CTRL (UTIL_CSR_BASE_ADDR + 0x004)
+#define UTIL_INQ_PKTPTR (UTIL_CSR_BASE_ADDR + 0x010)
+
+#define UTIL_HDR_SIZE (UTIL_CSR_BASE_ADDR + 0x014)
+
+#define UTIL_PE0_QB_DM_ADDR0 (UTIL_CSR_BASE_ADDR + 0x020)
+#define UTIL_PE0_QB_DM_ADDR1 (UTIL_CSR_BASE_ADDR + 0x024)
+#define UTIL_PE0_RO_DM_ADDR0 (UTIL_CSR_BASE_ADDR + 0x060)
+#define UTIL_PE0_RO_DM_ADDR1 (UTIL_CSR_BASE_ADDR + 0x064)
+
+#define UTIL_MEM_ACCESS_ADDR (UTIL_CSR_BASE_ADDR + 0x100)
+#define UTIL_MEM_ACCESS_WDATA (UTIL_CSR_BASE_ADDR + 0x104)
+#define UTIL_MEM_ACCESS_RDATA (UTIL_CSR_BASE_ADDR + 0x108)
+
+#define UTIL_TM_INQ_ADDR (UTIL_CSR_BASE_ADDR + 0x114)
+#define UTIL_PE_STATUS (UTIL_CSR_BASE_ADDR + 0x118)
+
+#define UTIL_PE_SYS_CLK_RATIO (UTIL_CSR_BASE_ADDR + 0x200)
+#define UTIL_AFULL_THRES (UTIL_CSR_BASE_ADDR + 0x204)
+#define UTIL_GAP_BETWEEN_READS (UTIL_CSR_BASE_ADDR + 0x208)
+#define UTIL_MAX_BUF_CNT (UTIL_CSR_BASE_ADDR + 0x20c)
+#define UTIL_TSQ_FIFO_THRES (UTIL_CSR_BASE_ADDR + 0x210)
+#define UTIL_TSQ_MAX_CNT (UTIL_CSR_BASE_ADDR + 0x214)
+#define UTIL_IRAM_DATA_0 (UTIL_CSR_BASE_ADDR + 0x218)
+#define UTIL_IRAM_DATA_1 (UTIL_CSR_BASE_ADDR + 0x21c)
+#define UTIL_IRAM_DATA_2 (UTIL_CSR_BASE_ADDR + 0x220)
+#define UTIL_IRAM_DATA_3 (UTIL_CSR_BASE_ADDR + 0x224)
+
+#define UTIL_BUS_ACCESS_ADDR (UTIL_CSR_BASE_ADDR + 0x228)
+#define UTIL_BUS_ACCESS_WDATA (UTIL_CSR_BASE_ADDR + 0x22c)
+#define UTIL_BUS_ACCESS_RDATA (UTIL_CSR_BASE_ADDR + 0x230)
+
+#define UTIL_INQ_AFULL_THRES (UTIL_CSR_BASE_ADDR + 0x234)
+
+struct util_cfg {
+ u32 pe_sys_clk_ratio;
+};
+
+#endif /* _UTIL_CSR_H_ */
--- /dev/null
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright 2019 NXP
+ */
+
+#ifndef _PFE_H_
+#define _PFE_H_
+
+#include "cbus.h"
+
+/*
+ * WARNING: non atomic version.
+ */
+static inline void
+set_bit(unsigned long nr, void *addr)
+{
+ int *m = ((int *)addr) + (nr >> 5);
+ *m |= 1 << (nr & 31);
+}
+
+static inline int
+test_bit(int nr, const void *addr)
+{
+ return (1UL & (((const int *)addr)[nr >> 5] >> (nr & 31))) != 0UL;
+}
+
+/*
+ * WARNING: non atomic version.
+ */
+static inline void
+clear_bit(unsigned long nr, void *addr)
+{
+ int *m = ((int *)addr) + (nr >> 5);
+ *m &= ~(1 << (nr & 31));
+}
+
+/*
+ * WARNING: non atomic version.
+ */
+static inline int
+test_and_clear_bit(unsigned long nr, void *addr)
+{
+ unsigned long mask = 1 << (nr & 0x1f);
+ int *m = ((int *)addr) + (nr >> 5);
+ int old = *m;
+
+ *m = old & ~mask;
+ return (old & mask) != 0;
+}
+
+/*
+ * WARNING: non atomic version.
+ */
+static inline int
+test_and_set_bit(unsigned long nr, void *addr)
+{
+ unsigned long mask = 1 << (nr & 0x1f);
+ int *m = ((int *)addr) + (nr >> 5);
+ int old = *m;
+
+ *m = old | mask;
+ return (old & mask) != 0;
+}
+
+#ifndef BIT
+#define BIT(nr) (1UL << (nr))
+#endif
+#define CLASS_DMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20))
+/*
+ * Only valid for mem access register interface
+ */
+#define CLASS_IMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20))
+#define CLASS_DMEM_SIZE 0x00002000
+#define CLASS_IMEM_SIZE 0x00008000
+
+#define TMU_DMEM_BASE_ADDR(i) (0x00000000 + ((i) << 20))
+/*
+ * Only valid for mem access register interface
+ */
+#define TMU_IMEM_BASE_ADDR(i) (0x00000000 + ((i) << 20))
+#define TMU_DMEM_SIZE 0x00000800
+#define TMU_IMEM_SIZE 0x00002000
+
+#define UTIL_DMEM_BASE_ADDR 0x00000000
+#define UTIL_DMEM_SIZE 0x00002000
+
+#define PE_LMEM_BASE_ADDR 0xc3010000
+#define PE_LMEM_SIZE 0x8000
+#define PE_LMEM_END (PE_LMEM_BASE_ADDR + PE_LMEM_SIZE)
+
+#define DMEM_BASE_ADDR 0x00000000
+#define DMEM_SIZE 0x2000 /* TMU has less... */
+#define DMEM_END (DMEM_BASE_ADDR + DMEM_SIZE)
+
+#define PMEM_BASE_ADDR 0x00010000
+#define PMEM_SIZE 0x8000 /* TMU has less... */
+#define PMEM_END (PMEM_BASE_ADDR + PMEM_SIZE)
+
+#define writel(v, p) ({*(volatile unsigned int *)(p) = (v); })
+#define readl(p) (*(const volatile unsigned int *)(p))
+
+/* These check memory ranges from PE point of view/memory map */
+#define IS_DMEM(addr, len) \
+ ({ typeof(addr) addr_ = (addr); \
+ ((unsigned long)(addr_) >= DMEM_BASE_ADDR) && \
+ (((unsigned long)(addr_) + (len)) <= DMEM_END); })
+
+#define IS_PMEM(addr, len) \
+ ({ typeof(addr) addr_ = (addr); \
+ ((unsigned long)(addr_) >= PMEM_BASE_ADDR) && \
+ (((unsigned long)(addr_) + (len)) <= PMEM_END); })
+
+#define IS_PE_LMEM(addr, len) \
+ ({ typeof(addr) addr_ = (addr); \
+ ((unsigned long)(addr_) >= \
+ PE_LMEM_BASE_ADDR) && \
+ (((unsigned long)(addr_) + \
+ (len)) <= PE_LMEM_END); })
+
+#define IS_PFE_LMEM(addr, len) \
+ ({ typeof(addr) addr_ = (addr); \
+ ((unsigned long)(addr_) >= \
+ CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR)) && \
+ (((unsigned long)(addr_) + (len)) <= \
+ CBUS_VIRT_TO_PFE(LMEM_END)); })
+
+#define __IS_PHYS_DDR(addr, len) \
+ ({ typeof(addr) addr_ = (addr); \
+ ((unsigned long)(addr_) >= \
+ DDR_PHYS_BASE_ADDR) && \
+ (((unsigned long)(addr_) + (len)) <= \
+ DDR_PHYS_END); })
+
+#define IS_PHYS_DDR(addr, len) __IS_PHYS_DDR(DDR_PFE_TO_PHYS(addr), len)
+
+/*
+ * If using a run-time virtual address for the cbus base address use this code
+ */
+extern void *cbus_base_addr;
+extern void *ddr_base_addr;
+extern unsigned long ddr_phys_base_addr;
+extern unsigned int ddr_size;
+
+#define CBUS_BASE_ADDR cbus_base_addr
+#define DDR_PHYS_BASE_ADDR ddr_phys_base_addr
+#define DDR_BASE_ADDR ddr_base_addr
+#define DDR_SIZE ddr_size
+
+#define DDR_PHYS_END (DDR_PHYS_BASE_ADDR + DDR_SIZE)
+
+#define LS1012A_PFE_RESET_WA /*
+ * PFE doesn't have global reset and re-init
+ * should takecare few things to make PFE
+ * functional after reset
+ */
+#define PFE_CBUS_PHYS_BASE_ADDR 0xc0000000 /* CBUS physical base address
+ * as seen by PE's.
+ */
+/* CBUS physical base address as seen by PE's. */
+#define PFE_CBUS_PHYS_BASE_ADDR_FROM_PFE 0xc0000000
+
+#define DDR_PHYS_TO_PFE(p) (((unsigned long)(p)) & 0x7FFFFFFF)
+#define DDR_PFE_TO_PHYS(p) (((unsigned long)(p)) | 0x80000000)
+#define CBUS_PHYS_TO_PFE(p) (((p) - PFE_CBUS_PHYS_BASE_ADDR) + \
+ PFE_CBUS_PHYS_BASE_ADDR_FROM_PFE)
+/* Translates to PFE address map */
+
+#define DDR_PHYS_TO_VIRT(p) (((p) - DDR_PHYS_BASE_ADDR) + DDR_BASE_ADDR)
+#define DDR_VIRT_TO_PHYS(v) (((v) - DDR_BASE_ADDR) + DDR_PHYS_BASE_ADDR)
+#define DDR_VIRT_TO_PFE(p) (DDR_PHYS_TO_PFE(DDR_VIRT_TO_PHYS(p)))
+
+#define CBUS_VIRT_TO_PFE(v) (((v) - CBUS_BASE_ADDR) + \
+ PFE_CBUS_PHYS_BASE_ADDR)
+#define CBUS_PFE_TO_VIRT(p) (((unsigned long)(p) - \
+ PFE_CBUS_PHYS_BASE_ADDR) + CBUS_BASE_ADDR)
+
+/* The below part of the code is used in QOS control driver from host */
+#define TMU_APB_BASE_ADDR 0xc1000000 /* TMU base address seen by
+ * pe's
+ */
+
+enum {
+ CLASS0_ID = 0,
+ CLASS1_ID,
+ CLASS2_ID,
+ CLASS3_ID,
+ CLASS4_ID,
+ CLASS5_ID,
+ TMU0_ID,
+ TMU1_ID,
+ TMU2_ID,
+ TMU3_ID,
+#if !defined(CONFIG_FSL_PFE_UTIL_DISABLED)
+ UTIL_ID,
+#endif
+ MAX_PE
+};
+
+#define CLASS_MASK (BIT(CLASS0_ID) | BIT(CLASS1_ID) |\
+ BIT(CLASS2_ID) | BIT(CLASS3_ID) |\
+ BIT(CLASS4_ID) | BIT(CLASS5_ID))
+#define CLASS_MAX_ID CLASS5_ID
+
+#define TMU_MASK (BIT(TMU0_ID) | BIT(TMU1_ID) |\
+ BIT(TMU3_ID))
+
+#define TMU_MAX_ID TMU3_ID
+
+#if !defined(CONFIG_FSL_PFE_UTIL_DISABLED)
+#define UTIL_MASK BIT(UTIL_ID)
+#endif
+
+struct pe_status {
+ u32 cpu_state;
+ u32 activity_counter;
+ u32 rx;
+ union {
+ u32 tx;
+ u32 tmu_qstatus;
+ };
+ u32 drop;
+#if defined(CFG_PE_DEBUG)
+ u32 debug_indicator;
+ u32 debug[16];
+#endif
+} __rte_aligned(16);
+
+struct pe_sync_mailbox {
+ u32 stop;
+ u32 stopped;
+};
+
+/* Drop counter definitions */
+
+#define CLASS_NUM_DROP_COUNTERS 13
+#define UTIL_NUM_DROP_COUNTERS 8
+
+/* PE information.
+ * Structure containing PE's specific information. It is used to create
+ * generic C functions common to all PE's.
+ * Before using the library functions this structure needs to be initialized
+ * with the different registers virtual addresses
+ * (according to the ARM MMU mmaping). The default initialization supports a
+ * virtual == physical mapping.
+ */
+struct pe_info {
+ u32 dmem_base_addr; /* PE's dmem base address */
+ u32 pmem_base_addr; /* PE's pmem base address */
+ u32 pmem_size; /* PE's pmem size */
+
+ void *mem_access_wdata; /* PE's _MEM_ACCESS_WDATA register
+ * address
+ */
+ void *mem_access_addr; /* PE's _MEM_ACCESS_ADDR register
+ * address
+ */
+ void *mem_access_rdata; /* PE's _MEM_ACCESS_RDATA register
+ * address
+ */
+};
+
+void pe_lmem_read(u32 *dst, u32 len, u32 offset);
+void pe_lmem_write(u32 *src, u32 len, u32 offset);
+
+void pe_dmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len);
+void pe_pmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len);
+
+u32 pe_pmem_read(int id, u32 addr, u8 size);
+
+void pe_dmem_write(int id, u32 val, u32 addr, u8 size);
+u32 pe_dmem_read(int id, u32 addr, u8 size);
+void class_pe_lmem_memcpy_to32(u32 dst, const void *src, unsigned int len);
+void class_pe_lmem_memset(u32 dst, int val, unsigned int len);
+void class_bus_write(u32 val, u32 addr, u8 size);
+u32 class_bus_read(u32 addr, u8 size);
+
+#define class_bus_readl(addr) class_bus_read(addr, 4)
+#define class_bus_readw(addr) class_bus_read(addr, 2)
+#define class_bus_readb(addr) class_bus_read(addr, 1)
+
+#define class_bus_writel(val, addr) class_bus_write(val, addr, 4)
+#define class_bus_writew(val, addr) class_bus_write(val, addr, 2)
+#define class_bus_writeb(val, addr) class_bus_write(val, addr, 1)
+
+#define pe_dmem_readl(id, addr) pe_dmem_read(id, addr, 4)
+#define pe_dmem_readw(id, addr) pe_dmem_read(id, addr, 2)
+#define pe_dmem_readb(id, addr) pe_dmem_read(id, addr, 1)
+
+#define pe_dmem_writel(id, val, addr) pe_dmem_write(id, val, addr, 4)
+#define pe_dmem_writew(id, val, addr) pe_dmem_write(id, val, addr, 2)
+#define pe_dmem_writeb(id, val, addr) pe_dmem_write(id, val, addr, 1)
+
+/*int pe_load_elf_section(int id, const void *data, elf32_shdr *shdr); */
+//int pe_load_elf_section(int id, const void *data, struct elf32_shdr *shdr,
+// struct device *dev);
+
+void pfe_lib_init(void *cbus_base, void *ddr_base, unsigned long ddr_phys_base,
+ unsigned int ddr_size);
+void bmu_init(void *base, struct BMU_CFG *cfg);
+void bmu_reset(void *base);
+void bmu_enable(void *base);
+void bmu_disable(void *base);
+void bmu_set_config(void *base, struct BMU_CFG *cfg);
+
+/*
+ * An enumerated type for loopback values. This can be one of three values, no
+ * loopback -normal operation, local loopback with internal loopback module of
+ * MAC or PHY loopback which is through the external PHY.
+ */
+#ifndef __MAC_LOOP_ENUM__
+#define __MAC_LOOP_ENUM__
+enum mac_loop {LB_NONE, LB_EXT, LB_LOCAL};
+#endif
+
+/* Get Chip Revision level
+ *
+ */
+static inline unsigned int CHIP_REVISION(void)
+{
+ /*For LS1012A return always 1 */
+ return 1;
+}
+
+/* Start HIF rx DMA
+ *
+ */
+static inline void hif_rx_dma_start(void)
+{
+ writel(HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB, HIF_RX_CTRL);
+}
+
+/* Start HIF tx DMA
+ *
+ */
+static inline void hif_tx_dma_start(void)
+{
+ writel(HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB, HIF_TX_CTRL);
+}
+
+#endif /* _PFE_H_ */
git.droids-corp.org / dpdk.git / commitdiff