#
CONFIG_RTE_NEXT_ABI=y
+#
+# Machine's cache line size
+#
+CONFIG_RTE_CACHE_LINE_SIZE=64
+
#
# Compile Environment Abstraction Layer
#
#
CONFIG_RTE_NEXT_ABI=y
+#
+# Machine's cache line size
+#
+CONFIG_RTE_CACHE_LINE_SIZE=64
+
#
# Compile Environment Abstraction Layer
#
CONFIG_RTE_EAL_IGB_UIO=y
CONFIG_RTE_EAL_VFIO=y
CONFIG_RTE_MALLOC_DEBUG=n
-
# Default driver path (or "" to disable)
CONFIG_RTE_EAL_PMD_PATH=""
CONFIG_RTE_TOOLCHAIN="gcc"
CONFIG_RTE_TOOLCHAIN_GCC=y
-CONFIG_RTE_CACHE_LINE_SIZE=64
-
CONFIG_RTE_IXGBE_INC_VECTOR=n
CONFIG_RTE_LIBRTE_VIRTIO_PMD=n
CONFIG_RTE_LIBRTE_IVSHMEM=n
CONFIG_RTE_ARCH_PPC_64=y
CONFIG_RTE_ARCH_64=y
+CONFIG_RTE_CACHE_LINE_SIZE=128
+
CONFIG_RTE_TOOLCHAIN="gcc"
CONFIG_RTE_TOOLCHAIN_GCC=y
};
#define SOCKET_ID_ANY -1 /**< Any NUMA socket. */
-#ifndef RTE_CACHE_LINE_SIZE
-#define RTE_CACHE_LINE_SIZE 64 /**< Cache line size. */
-#endif
#define RTE_CACHE_LINE_MASK (RTE_CACHE_LINE_SIZE-1) /**< Cache line mask. */
#define RTE_CACHE_LINE_ROUNDUP(size) \
*/
#define RTE_KNI_NAMESIZE 32
-#ifndef RTE_CACHE_LINE_SIZE
-#define RTE_CACHE_LINE_SIZE 64 /**< Cache line size. */
-#endif
-
/*
* Request id.
*/
ARCH ?= arm
CROSS ?=
-CPU_CFLAGS ?= -marm -DRTE_CACHE_LINE_SIZE=64 -munaligned-access
+CPU_CFLAGS ?= -marm -munaligned-access
CPU_LDFLAGS ?=
CPU_ASFLAGS ?= -felf
ARCH ?= powerpc
CROSS ?=
-CPU_CFLAGS ?= -m64 -DRTE_CACHE_LINE_SIZE=128
+CPU_CFLAGS ?= -m64
CPU_LDFLAGS ?=
CPU_ASFLAGS ?= -felf64
# CPU_LDFLAGS =
# CPU_ASFLAGS =
-MACHINE_CFLAGS += -march=armv8-a+crc -DRTE_CACHE_LINE_SIZE=64
+MACHINE_CFLAGS += -march=armv8-a+crc
# CPU_LDFLAGS =
# CPU_ASFLAGS =
-MACHINE_CFLAGS += -march=armv8-a+crc -mcpu=thunderx -DRTE_CACHE_LINE_SIZE=128
+MACHINE_CFLAGS += -march=armv8-a+crc -mcpu=thunderx
# CPU_LDFLAGS =
# CPU_ASFLAGS =
-MACHINE_CFLAGS += -march=armv8-a -DRTE_CACHE_LINE_SIZE=64
+MACHINE_CFLAGS += -march=armv8-a