net/ice/base: enable I2C read/write commands

Enable I2C read/write AQ commands. They are now required for
controlling the external physical connectors via external I2C
port expander on E810-T adapters.

Signed-off-by: Maciej Machnikowski <maciej.machnikowski@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>

diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h
index 4b78da9..f9a741e 100644 (file)
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -1665,6 +1665,31 @@ struct ice_aqc_get_link_topo {
        u8 rsvd[9];
 };
 
+/* Read/Write I2C (direct, 0x06E2/0x06E3) */
+struct ice_aqc_i2c {
+       struct ice_aqc_link_topo_addr topo_addr;
+       __le16 i2c_addr;
+       u8 i2c_params;
+#define ICE_AQC_I2C_DATA_SIZE_S                0
+#define ICE_AQC_I2C_DATA_SIZE_M                (0xF << ICE_AQC_I2C_DATA_SIZE_S)
+#define ICE_AQC_I2C_ADDR_TYPE_M                BIT(4)
+#define ICE_AQC_I2C_ADDR_TYPE_7BIT     0
+#define ICE_AQC_I2C_ADDR_TYPE_10BIT    ICE_AQC_I2C_ADDR_TYPE_M
+#define ICE_AQC_I2C_DATA_OFFSET_S      5
+#define ICE_AQC_I2C_DATA_OFFSET_M      (0x3 << ICE_AQC_I2C_DATA_OFFSET_S)
+#define ICE_AQC_I2C_USE_REPEATED_START BIT(7)
+       u8 rsvd;
+       __le16 i2c_bus_addr;
+#define ICE_AQC_I2C_ADDR_7BIT_MASK     0x7F
+#define ICE_AQC_I2C_ADDR_10BIT_MASK    0x3FF
+       u8 i2c_data[4]; /* Used only by write command, reserved in read. */
+};
+
+/* Read I2C Response (direct, 0x06E2) */
+struct ice_aqc_read_i2c_resp {
+       u8 i2c_data[16];
+};
+
 /* Set Port Identification LED (direct, 0x06E9) */
 struct ice_aqc_set_port_id_led {
        u8 lport_num;
@@ -2838,6 +2863,8 @@ struct ice_aq_desc {
                struct ice_aqc_get_phy_caps get_phy;
                struct ice_aqc_set_phy_cfg set_phy;
                struct ice_aqc_restart_an restart_an;
+               struct ice_aqc_i2c read_write_i2c;
+               struct ice_aqc_read_i2c_resp read_i2c_resp;
                struct ice_aqc_sff_eeprom read_write_sff_param;
                struct ice_aqc_set_port_id_led set_port_id_led;
                struct ice_aqc_get_sw_cfg get_sw_conf;
@@ -3074,6 +3101,8 @@ enum ice_adminq_opc {
        ice_aqc_opc_set_event_mask                      = 0x0613,
        ice_aqc_opc_set_mac_lb                          = 0x0620,
        ice_aqc_opc_get_link_topo                       = 0x06E0,
+       ice_aqc_opc_read_i2c                            = 0x06E2,
+       ice_aqc_opc_write_i2c                           = 0x06E3,
        ice_aqc_opc_set_port_id_led                     = 0x06E9,
        ice_aqc_opc_get_port_options                    = 0x06EA,
        ice_aqc_opc_set_port_option                     = 0x06EB,

diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index 356a8b4..befaa83 100644 (file)
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -4766,6 +4766,100 @@ enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw)
                return ICE_FW_MODE_NORMAL;
 }
 
+/**
+ * ice_aq_read_i2c
+ * @hw: pointer to the hw struct
+ * @topo_addr: topology address for a device to communicate with
+ * @bus_addr: 7-bit I2C bus address
+ * @addr: I2C memory address (I2C offset) with up to 16 bits
+ * @params: I2C parameters: bit [7] - Repeated start, bits [6:5] data offset size,
+ *                         bit [4] - I2C address type, bits [3:0] - data size to read (0-16 bytes)
+ * @data: pointer to data (0 to 16 bytes) to be read from the I2C device
+ * @cd: pointer to command details structure or NULL
+ *
+ * Read I2C (0x06E2)
+ */
+enum ice_status
+ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,
+               u16 bus_addr, __le16 addr, u8 params, u8 *data,
+               struct ice_sq_cd *cd)
+{
+       struct ice_aq_desc desc = { 0 };
+       struct ice_aqc_i2c *cmd;
+       enum ice_status status;
+       u8 data_size;
+
+       ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_i2c);
+       cmd = &desc.params.read_write_i2c;
+
+       if (!data)
+               return ICE_ERR_PARAM;
+
+       data_size = (params & ICE_AQC_I2C_DATA_SIZE_M) >> ICE_AQC_I2C_DATA_SIZE_S;
+
+       cmd->i2c_bus_addr = CPU_TO_LE16(bus_addr);
+       cmd->topo_addr = topo_addr;
+       cmd->i2c_params = params;
+       cmd->i2c_addr = addr;
+
+       status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
+       if (!status) {
+               struct ice_aqc_read_i2c_resp *resp;
+               u8 i;
+
+               resp = &desc.params.read_i2c_resp;
+               for (i = 0; i < data_size; i++) {
+                       *data = resp->i2c_data[i];
+                       data++;
+               }
+       }
+
+       return status;
+}
+
+/**
+ * ice_aq_write_i2c
+ * @hw: pointer to the hw struct
+ * @topo_addr: topology address for a device to communicate with
+ * @bus_addr: 7-bit I2C bus address
+ * @addr: I2C memory address (I2C offset) with up to 16 bits
+ * @params: I2C parameters: bit [4] - I2C address type, bits [3:0] - data size to write (0-7 bytes)
+ * @data: pointer to data (0 to 4 bytes) to be written to the I2C device
+ * @cd: pointer to command details structure or NULL
+ *
+ * Write I2C (0x06E3)
+ */
+enum ice_status
+ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,
+                u16 bus_addr, __le16 addr, u8 params, u8 *data,
+                struct ice_sq_cd *cd)
+{
+       struct ice_aq_desc desc = { 0 };
+       struct ice_aqc_i2c *cmd;
+       u8 i, data_size;
+
+       ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_write_i2c);
+       cmd = &desc.params.read_write_i2c;
+
+       data_size = (params & ICE_AQC_I2C_DATA_SIZE_M) >> ICE_AQC_I2C_DATA_SIZE_S;
+
+       /* data_size limited to 4 */
+       if (data_size > 4)
+               return ICE_ERR_PARAM;
+
+       cmd->i2c_bus_addr = CPU_TO_LE16(bus_addr);
+       cmd->topo_addr = topo_addr;
+       cmd->i2c_params = params;
+       cmd->i2c_addr = addr;
+
+       for (i = 0; i < data_size; i++) {
+               cmd->i2c_data[i] = *data;
+               data++;
+       }
+
+       return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
+}
+
 /**
  * ice_fw_supports_link_override
  * @hw: pointer to the hardware structure

diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h
index 5b720c3..f9e3ed1 100644 (file)
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -225,5 +225,13 @@ ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size,
 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw);
 enum ice_status
 ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add);
+enum ice_status
+ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,
+               u16 bus_addr, __le16 addr, u8 params, u8 *data,
+               struct ice_sq_cd *cd);
+enum ice_status
+ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,
+                u16 bus_addr, __le16 addr, u8 params, u8 *data,
+                struct ice_sq_cd *cd);
 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw);
 #endif /* _ICE_COMMON_H_ */