e1000/base: fix K1 configuration
authorWenzhuo Lu <wenzhuo.lu@intel.com>
Fri, 16 Oct 2015 02:51:09 +0000 (10:51 +0800)
committerThomas Monjalon <thomas.monjalon@6wind.com>
Tue, 27 Oct 2015 15:12:56 +0000 (16:12 +0100)
This patch is for the following updates to the K1 configurations:
Tx idle period for entering K1 should be 128 ns.
Minimum Tx idle period in K1 should be 256 ns.

Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
drivers/net/e1000/base/e1000_ich8lan.c
drivers/net/e1000/base/e1000_ich8lan.h
drivers/net/e1000/base/e1000_phy.h
drivers/net/e1000/base/e1000_regs.h

index 37f6195..56a5e33 100644 (file)
@@ -1503,10 +1503,14 @@ STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
                if (ret_val)
                        return ret_val;
        }
-
        /* Clear link partner's EEE ability */
        hw->dev_spec.ich8lan.eee_lp_ability = 0;
 
+       /* Configure K0s minimum time */
+       if (hw->mac.type == e1000_pch_lpt) {
+               e1000_configure_k0s_lpt(hw, K1_ENTRY_LATENCY, K1_MIN_TIME);
+       }
+
        if (!link)
                return E1000_SUCCESS; /* No link detected */
 
@@ -5309,3 +5313,44 @@ release:
        }
 }
 
+/**
+ *  e1000_configure_k0s_lpt - Configure K0s power state
+ *  @hw: pointer to the HW structure
+ *  @entry_latency: Tx idle period for entering K0s - valid values are 0 to 3.
+ *     0 corresponds to 128ns, each value over 0 doubles the duration.
+ *  @min_time: Minimum Tx idle period allowed  - valid values are 0 to 4.
+ *     0 corresponds to 128ns, each value over 0 doubles the duration.
+ *
+ *  Configure the K1 power state based on the provided parameter.
+ *  Assumes semaphore already acquired.
+ *
+ *  Success returns 0, Failure returns:
+ *     -E1000_ERR_PHY (-2) in case of access error
+ *     -E1000_ERR_PARAM (-4) in case of parameters error
+ **/
+s32 e1000_configure_k0s_lpt(struct e1000_hw *hw, u8 entry_latency, u8 min_time)
+{
+       s32 ret_val;
+       u16 kmrn_reg = 0;
+
+       DEBUGFUNC("e1000_configure_k0s_lpt");
+
+       if (entry_latency > 3 || min_time > 4)
+               return -E1000_ERR_PARAM;
+
+       ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
+                                            &kmrn_reg);
+       if (ret_val)
+               return ret_val;
+
+       /* for now don't touch the latency */
+       kmrn_reg &= ~(E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_MASK);
+       kmrn_reg |= ((min_time << E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT));
+
+       ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
+                                             kmrn_reg);
+       if (ret_val)
+               return ret_val;
+
+       return E1000_SUCCESS;
+}
index f5d8ab1..09a9258 100644 (file)
@@ -114,7 +114,7 @@ POSSIBILITY OF SUCH DAMAGE.
 
 #define E1000_FEXTNVM6_REQ_PLL_CLK     0x00000100
 #define E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION       0x00000200
-
+#define E1000_FEXTNVM6_K1_OFF_ENABLE   0x80000000
 #if !defined(EXTERNAL_RELEASE) || defined(ULP_SUPPORT)
 #define E1000_FEXTNVM7_DISABLE_SMB_PERST       0x00000020
 #endif /* !EXTERNAL_RELEASE || ULP_SUPPORT */
@@ -179,6 +179,8 @@ POSSIBILITY OF SUCH DAMAGE.
 
 #define E1000_NVM_K1_CONFIG    0x1B /* NVM K1 Config Word */
 #define E1000_NVM_K1_ENABLE    0x1  /* NVM Enable K1 bit */
+#define K1_ENTRY_LATENCY       0
+#define K1_MIN_TIME            1
 
 /* SMBus Control Phy Register */
 #define CV_SMB_CTRL            PHY_REG(769, 23)
@@ -301,6 +303,7 @@ void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw);
 u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw);
 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
+s32 e1000_configure_k0s_lpt(struct e1000_hw *hw, u8 entry_latency, u8 min_time);
 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw);
 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);
 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data);
index 2b78af0..3e45a9e 100644 (file)
@@ -274,6 +274,13 @@ bool e1000_is_mphy_ready(struct e1000_hw *hw);
 #define E1000_KMRNCTRLSTA_K1_CONFIG    0x7
 #define E1000_KMRNCTRLSTA_K1_ENABLE    0x0002 /* enable K1 */
 #define E1000_KMRNCTRLSTA_HD_CTRL      0x10   /* Kumeran HD Control */
+#define E1000_KMRNCTRLSTA_K0S_CTRL     0x1E    /* Kumeran K0s Control */
+#define E1000_KMRNCTRLSTA_K0S_CTRL_ENTRY_LTNCY_SHIFT   0
+#define E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT      4
+#define E1000_KMRNCTRLSTA_K0S_CTRL_ENTRY_LTNCY_MASK    \
+       (3 << E1000_KMRNCTRLSTA_K0S_CTRL_ENTRY_LTNCY_SHIFT)
+#define E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_MASK \
+       (7 << E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT)
 #define E1000_KMRNCTRLSTA_OP_MODES     0x1F   /* Kumeran Modes of Operation */
 #define E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC     0x0002 /* change LSC to CSC */
 
index c4dd6f0..52ffa51 100644 (file)
@@ -66,6 +66,7 @@ POSSIBILITY OF SUCH DAMAGE.
 #define E1000_FEXTNVM4 0x00024  /* Future Extended NVM 4 - RW */
 #define E1000_FEXTNVM6 0x00010  /* Future Extended NVM 6 - RW */
 #define E1000_FEXTNVM7 0x000E4  /* Future Extended NVM 7 - RW */
+#define E1000_PCIEANACFG       0x00F18 /* PCIE Analog Config */
 #define E1000_FCT      0x00030  /* Flow Control Type - RW */
 #define E1000_CONNSW   0x00034  /* Copper/Fiber switch control - RW */
 #define E1000_VET      0x00038  /* VLAN Ether Type - RW */