net/e1000/base: add workaround for possible stalled packet

This works around a possible stalled packet issue, which may occur due to
clock recovery from the PCH being too slow, when the LAN is transitioning
from K1 at 1G link speed.

Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>

diff --git a/drivers/net/e1000/base/e1000_ich8lan.c b/drivers/net/e1000/base/e1000_ich8lan.c
index 7ab0f7c..89265d2 100644 (file)
--- a/drivers/net/e1000/base/e1000_ich8lan.c
+++ b/drivers/net/e1000/base/e1000_ich8lan.c
@@ -1584,6 +1584,16 @@ STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
                        hw->phy.ops.write_reg_locked(hw,
                                                     I217_PLL_CLOCK_GATE_REG,
                                                     phy_reg);
+
+                       if (speed == SPEED_1000) {
+                               hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,
+                                                           &phy_reg);
+
+                               phy_reg |= HV_PM_CTRL_K1_CLK_REQ;
+
+                               hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,
+                                                            phy_reg);
+                               }
                 }
                hw->phy.ops.release(hw);
 

diff --git a/drivers/net/e1000/base/e1000_ich8lan.h b/drivers/net/e1000/base/e1000_ich8lan.h
index 50e0e79..bc4ed1d 100644 (file)
--- a/drivers/net/e1000/base/e1000_ich8lan.h
+++ b/drivers/net/e1000/base/e1000_ich8lan.h
@@ -250,7 +250,7 @@ POSSIBILITY OF SUCH DAMAGE.
 
 /* PHY Power Management Control */
 #define HV_PM_CTRL             PHY_REG(770, 17)
-#define HV_PM_CTRL_PLL_STOP_IN_K1_GIGA 0x100
+#define HV_PM_CTRL_K1_CLK_REQ          0x200
 #define HV_PM_CTRL_K1_ENABLE           0x4000
 
 #define I217_PLL_CLOCK_GATE_REG        PHY_REG(772, 28)