net/sfc/base: support Medford2 event timer semantics

The event timer interface has changed for Medford2 - for
details see bug66418 comment 9. Update the common code to
use the new timer semantics for Medford2.

Signed-off-by: Andy Moreton <amoreton@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>

diff --git a/drivers/net/sfc/base/ef10_ev.c b/drivers/net/sfc/base/ef10_ev.c
index 256156b..6e00099 100644 (file)
--- a/drivers/net/sfc/base/ef10_ev.c
+++ b/drivers/net/sfc/base/ef10_ev.c
@@ -705,9 +705,15 @@ ef10_ev_qmoderate(
                        EFX_BAR_VI_WRITED(enp, ER_DD_EVQ_INDIRECT,
                            eep->ee_index, &dword, 0);
                } else {
-                       EFX_POPULATE_DWORD_2(dword,
+                       /*
+                        * NOTE: The TMR_REL field introduced in Medford2 is
+                        * ignored on earlier EF10 controllers. See bug66418
+                        * comment 9 for details.
+                        */
+                       EFX_POPULATE_DWORD_3(dword,
                            ERF_DZ_TC_TIMER_MODE, mode,
-                           ERF_DZ_TC_TIMER_VAL, ticks);
+                           ERF_DZ_TC_TIMER_VAL, ticks,
+                           ERF_FZ_TC_TMR_REL_VAL, ticks);
                        EFX_BAR_VI_WRITED(enp, ER_DZ_EVQ_TMR_REG,
                            eep->ee_index, &dword, 0);
                }

diff --git a/drivers/net/sfc/base/efx_regs_ef10.h b/drivers/net/sfc/base/efx_regs_ef10.h
index a832ce7..2cb96e8 100644 (file)
--- a/drivers/net/sfc/base/efx_regs_ef10.h
+++ b/drivers/net/sfc/base/efx_regs_ef10.h
@@ -156,6 +156,8 @@ extern "C" {
 #define        ER_FZ_EVQ_TMR_REG_64K_RESET 0x0
 
 
+#define        ERF_FZ_TC_TMR_REL_VAL_LBN 16
+#define        ERF_FZ_TC_TMR_REL_VAL_WIDTH 14
 #define        ERF_FZ_TC_TIMER_MODE_LBN 14
 #define        ERF_FZ_TC_TIMER_MODE_WIDTH 2
 #define        ERF_FZ_TC_TIMER_VAL_LBN 0
@@ -174,6 +176,8 @@ extern "C" {
 #define        ER_FZ_EVQ_TMR_REG_16K_RESET 0x0
 
 
+/* defined as ERF_FZ_TC_TMR_REL_VAL_LBN 16; */
+/* defined as ERF_FZ_TC_TMR_REL_VAL_WIDTH 14 */
 /* defined as ERF_FZ_TC_TIMER_MODE_LBN 14; */
 /* defined as ERF_FZ_TC_TIMER_MODE_WIDTH 2 */
 /* defined as ERF_FZ_TC_TIMER_VAL_LBN 0; */
@@ -192,6 +196,8 @@ extern "C" {
 #define        ER_DZ_EVQ_TMR_REG_RESET 0x0
 
 
+/* defined as ERF_FZ_TC_TMR_REL_VAL_LBN 16; */
+/* defined as ERF_FZ_TC_TMR_REL_VAL_WIDTH 14 */
 #define        ERF_DZ_TC_TIMER_MODE_LBN 14
 #define        ERF_DZ_TC_TIMER_MODE_WIDTH 2
 #define        ERF_DZ_TC_TIMER_VAL_LBN 0