crypto/nitrox: fix CSR register address generation

If the NPS_PKT ring/port is greater than 8191 the NPS_PKT*() macros will
evaluate to incorrect values due to unintended sign extension from int
to unsigned long. To fix this, add UL suffix to the constants in these
macros. The same problem is with AQMQ_QSZX() macro also.

Coverity issue: 349899, 349905, 349911, 349921, 349923
Fixes: 32e4930d5a3b ("crypto/nitrox: add hardware queue management")
Fixes: 0a8fc2423bff ("crypto/nitrox: introduce Nitrox driver")
Cc: stable@dpdk.org
Signed-off-by: Nagadheeraj Rottela <rnagadheeraj@marvell.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>

diff --git a/drivers/crypto/nitrox/nitrox_csr.h b/drivers/crypto/nitrox/nitrox_csr.h
index 8cd92e3..de7a3c6 100644 (file)
--- a/drivers/crypto/nitrox/nitrox_csr.h
+++ b/drivers/crypto/nitrox/nitrox_csr.h
@@ -12,18 +12,18 @@
 #define NITROX_CSR_ADDR(bar_addr, offset) (bar_addr + (offset))
 
 /* NPS packet registers */
-#define NPS_PKT_IN_INSTR_CTLX(_i)      (0x10060 + ((_i) * 0x40000))
-#define NPS_PKT_IN_INSTR_BADDRX(_i)    (0x10068 + ((_i) * 0x40000))
-#define NPS_PKT_IN_INSTR_RSIZEX(_i)    (0x10070 + ((_i) * 0x40000))
-#define NPS_PKT_IN_DONE_CNTSX(_i)      (0x10080 + ((_i) * 0x40000))
-#define NPS_PKT_IN_INSTR_BAOFF_DBELLX(_i)      (0x10078 + ((_i) * 0x40000))
-#define NPS_PKT_IN_INT_LEVELSX(_i)             (0x10088 + ((_i) * 0x40000))
-#define NPS_PKT_SLC_CTLX(_i)           (0x10000 + ((_i) * 0x40000))
-#define NPS_PKT_SLC_CNTSX(_i)          (0x10008 + ((_i) * 0x40000))
-#define NPS_PKT_SLC_INT_LEVELSX(_i)    (0x10010 + ((_i) * 0x40000))
+#define NPS_PKT_IN_INSTR_CTLX(_i)      (0x10060UL + ((_i) * 0x40000UL))
+#define NPS_PKT_IN_INSTR_BADDRX(_i)    (0x10068UL + ((_i) * 0x40000UL))
+#define NPS_PKT_IN_INSTR_RSIZEX(_i)    (0x10070UL + ((_i) * 0x40000UL))
+#define NPS_PKT_IN_DONE_CNTSX(_i)      (0x10080UL + ((_i) * 0x40000UL))
+#define NPS_PKT_IN_INSTR_BAOFF_DBELLX(_i)      (0x10078UL + ((_i) * 0x40000UL))
+#define NPS_PKT_IN_INT_LEVELSX(_i)             (0x10088UL + ((_i) * 0x40000UL))
+#define NPS_PKT_SLC_CTLX(_i)           (0x10000UL + ((_i) * 0x40000UL))
+#define NPS_PKT_SLC_CNTSX(_i)          (0x10008UL + ((_i) * 0x40000UL))
+#define NPS_PKT_SLC_INT_LEVELSX(_i)    (0x10010UL + ((_i) * 0x40000UL))
 
 /* AQM Virtual Function Registers */
-#define AQMQ_QSZX(_i)                  (0x20008 + ((_i)*0x40000))
+#define AQMQ_QSZX(_i)                  (0x20008UL + ((_i) * 0x40000UL))
 
 static inline uint64_t
 nitrox_read_csr(uint8_t *bar_addr, uint64_t offset)