net/sfc/base: move PHY/link config to ef10 NIC board cfg

Signed-off-by: Andy Moreton <amoreton@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>

diff --git a/drivers/net/sfc/base/ef10_nic.c b/drivers/net/sfc/base/ef10_nic.c
index 5f4357b..8e9d7a1 100644 (file)
--- a/drivers/net/sfc/base/ef10_nic.c
+++ b/drivers/net/sfc/base/ef10_nic.c
@@ -1548,6 +1548,8 @@ ef10_nic_board_cfg(
        const efx_nic_ops_t *enop = enp->en_enop;
        efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
        efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
+       ef10_link_state_t els;
+       efx_port_t *epp = &(enp->en_port);
        uint32_t board_type = 0;
        uint32_t port;
        uint32_t pf;
@@ -1619,13 +1621,27 @@ ef10_nic_board_cfg(
        encp->enc_board_type = board_type;
        encp->enc_clk_mult = 1; /* not used for EF10 */
 
+       /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
+       if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
+               goto fail6;
+
+       /* Obtain the default PHY advertised capabilities */
+       if ((rc = ef10_phy_get_link(enp, &els)) != 0)
+               goto fail7;
+       epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
+       epp->ep_adv_cap_mask = els.els_adv_cap_mask;
+
        /* Get remaining controller-specific board config */
        if ((rc = enop->eno_board_cfg(enp)) != 0)
                if (rc != EACCES)
-                       goto fail6;
+                       goto fail8;
 
        return (0);
 
+fail8:
+       EFSYS_PROBE(fail8);
+fail7:
+       EFSYS_PROBE(fail7);
 fail6:
        EFSYS_PROBE(fail6);
 fail5:

diff --git a/drivers/net/sfc/base/hunt_nic.c b/drivers/net/sfc/base/hunt_nic.c
index 58c2d13..d33d2db 100644 (file)
--- a/drivers/net/sfc/base/hunt_nic.c
+++ b/drivers/net/sfc/base/hunt_nic.c
@@ -77,7 +77,6 @@ hunt_board_cfg(
        __in            efx_nic_t *enp)
 {
        efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
-       ef10_link_state_t els;
        efx_port_t *epp = &(enp->en_port);
        uint32_t mask;
        uint32_t flags;
@@ -96,16 +95,6 @@ hunt_board_cfg(
        EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K  == 8192);
        encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
 
-       /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
-       if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
-               goto fail1;
-
-       /* Obtain the default PHY advertised capabilities */
-       if ((rc = ef10_phy_get_link(enp, &els)) != 0)
-               goto fail2;
-       epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
-       epp->ep_adv_cap_mask = els.els_adv_cap_mask;
-
        /*
         * Enable firmware workarounds for hardware errata.
         * Expected responses are:
@@ -133,7 +122,7 @@ hunt_board_cfg(
        else if ((rc == ENOTSUP) || (rc == ENOENT))
                encp->enc_bug35388_workaround = B_FALSE;
        else
-               goto fail3;
+               goto fail1;
 
        /*
         * If the bug41750 workaround is enabled, then do not test interrupts,
@@ -152,7 +141,7 @@ hunt_board_cfg(
        } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
                encp->enc_bug41750_workaround = B_FALSE;
        } else {
-               goto fail4;
+               goto fail2;
        }
        if (EFX_PCI_FUNCTION_IS_VF(encp)) {
                /* Interrupt testing does not work for VFs. See bug50084. */
@@ -190,12 +179,12 @@ hunt_board_cfg(
        } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
                encp->enc_bug26807_workaround = B_FALSE;
        } else {
-               goto fail5;
+               goto fail3;
        }
 
        /* Get clock frequencies (in MHz). */
        if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
-               goto fail6;
+               goto fail4;
 
        /*
         * The Huntington timer quantum is 1536 sysclk cycles, documented for
@@ -214,7 +203,7 @@ hunt_board_cfg(
 
        /* Check capabilities of running datapath firmware */
        if ((rc = ef10_get_datapath_caps(enp)) != 0)
-               goto fail7;
+               goto fail5;
 
        /* Alignment for receive packet DMA buffers */
        encp->enc_rx_buf_align_start = 1;
@@ -264,13 +253,13 @@ hunt_board_cfg(
         * can result in time-of-check/time-of-use bugs.
         */
        if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
-               goto fail8;
+               goto fail6;
        encp->enc_privilege_mask = mask;
 
        /* Get interrupt vector limits */
        if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
                if (EFX_PCI_FUNCTION_IS_PF(encp))
-                       goto fail9;
+                       goto fail7;
 
                /* Ignore error (cannot query vector limits from a VF). */
                base = 0;
@@ -286,7 +275,7 @@ hunt_board_cfg(
        encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
 
        if ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0)
-               goto fail10;
+               goto fail8;
        encp->enc_required_pcie_bandwidth_mbps = bandwidth;
 
        /* All Huntington devices have a PCIe Gen3, 8 lane connector */
@@ -294,10 +283,6 @@ hunt_board_cfg(
 
        return (0);
 
-fail10:
-       EFSYS_PROBE(fail10);
-fail9:
-       EFSYS_PROBE(fail9);
 fail8:
        EFSYS_PROBE(fail8);
 fail7:

diff --git a/drivers/net/sfc/base/medford2_nic.c b/drivers/net/sfc/base/medford2_nic.c
index 2bd3d83..afaafb9 100644 (file)
--- a/drivers/net/sfc/base/medford2_nic.c
+++ b/drivers/net/sfc/base/medford2_nic.c
@@ -49,8 +49,6 @@ medford2_board_cfg(
        __in            efx_nic_t *enp)
 {
        efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
-       ef10_link_state_t els;
-       efx_port_t *epp = &(enp->en_port);
        uint32_t mask;
        uint32_t sysclk, dpcpu_clk;
        uint32_t base, nvec;
@@ -72,16 +70,6 @@ medford2_board_cfg(
        encp->enc_vi_window_shift = vi_window_shift;
 
 
-       /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
-       if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
-               goto fail2;
-
-       /* Obtain the default PHY advertised capabilities */
-       if ((rc = ef10_phy_get_link(enp, &els)) != 0)
-               goto fail3;
-       epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
-       epp->ep_adv_cap_mask = els.els_adv_cap_mask;
-
        /*
         * Enable firmware workarounds for hardware errata.
         * Expected responses are:
@@ -122,11 +110,11 @@ medford2_board_cfg(
        else if ((rc == ENOTSUP) || (rc == ENOENT))
                encp->enc_bug61265_workaround = B_FALSE;
        else
-               goto fail4;
+               goto fail2;
 
        /* Get clock frequencies (in MHz). */
        if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
-               goto fail5;
+               goto fail3;
 
        /*
         * The Medford2 timer quantum is 1536 dpcpu_clk cycles, documented for
@@ -138,7 +126,7 @@ medford2_board_cfg(
 
        /* Check capabilities of running datapath firmware */
        if ((rc = ef10_get_datapath_caps(enp)) != 0)
-               goto fail6;
+               goto fail4;
 
        /* Alignment for receive packet DMA buffers */
        encp->enc_rx_buf_align_start = 1;
@@ -146,7 +134,7 @@ medford2_board_cfg(
        /* Get the RX DMA end padding alignment configuration */
        if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
                if (rc != EACCES)
-                       goto fail7;
+                       goto fail5;
 
                /* Assume largest tail padding size supported by hardware */
                end_padding = 256;
@@ -198,13 +186,13 @@ medford2_board_cfg(
         * can result in time-of-check/time-of-use bugs.
         */
        if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
-               goto fail8;
+               goto fail6;
        encp->enc_privilege_mask = mask;
 
        /* Get interrupt vector limits */
        if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
                if (EFX_PCI_FUNCTION_IS_PF(encp))
-                       goto fail9;
+                       goto fail7;
 
                /* Ignore error (cannot query vector limits from a VF). */
                base = 0;
@@ -227,16 +215,12 @@ medford2_board_cfg(
 
        rc = medford2_nic_get_required_pcie_bandwidth(enp, &bandwidth);
        if (rc != 0)
-               goto fail10;
+               goto fail8;
        encp->enc_required_pcie_bandwidth_mbps = bandwidth;
        encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
 
        return (0);
 
-fail10:
-       EFSYS_PROBE(fail10);
-fail9:
-       EFSYS_PROBE(fail9);
 fail8:
        EFSYS_PROBE(fail8);
 fail7:

diff --git a/drivers/net/sfc/base/medford_nic.c b/drivers/net/sfc/base/medford_nic.c
index 7840c33..afa6493 100644 (file)
--- a/drivers/net/sfc/base/medford_nic.c
+++ b/drivers/net/sfc/base/medford_nic.c
@@ -47,8 +47,6 @@ medford_board_cfg(
        __in            efx_nic_t *enp)
 {
        efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
-       ef10_link_state_t els;
-       efx_port_t *epp = &(enp->en_port);
        uint32_t mask;
        uint32_t sysclk, dpcpu_clk;
        uint32_t base, nvec;
@@ -71,16 +69,6 @@ medford_board_cfg(
        EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K  == 8192);
        encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
 
-       /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
-       if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
-               goto fail1;
-
-       /* Obtain the default PHY advertised capabilities */
-       if ((rc = ef10_phy_get_link(enp, &els)) != 0)
-               goto fail2;
-       epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
-       epp->ep_adv_cap_mask = els.els_adv_cap_mask;
-
        /*
         * Enable firmware workarounds for hardware errata.
         * Expected responses are:
@@ -121,11 +109,11 @@ medford_board_cfg(
        else if ((rc == ENOTSUP) || (rc == ENOENT))
                encp->enc_bug61265_workaround = B_FALSE;
        else
-               goto fail3;
+               goto fail1;
 
        /* Get clock frequencies (in MHz). */
        if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
-               goto fail4;
+               goto fail2;
 
        /*
         * The Medford timer quantum is 1536 dpcpu_clk cycles, documented for
@@ -137,7 +125,7 @@ medford_board_cfg(
 
        /* Check capabilities of running datapath firmware */
        if ((rc = ef10_get_datapath_caps(enp)) != 0)
-               goto fail5;
+               goto fail3;
 
        /* Alignment for receive packet DMA buffers */
        encp->enc_rx_buf_align_start = 1;
@@ -145,7 +133,7 @@ medford_board_cfg(
        /* Get the RX DMA end padding alignment configuration */
        if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
                if (rc != EACCES)
-                       goto fail6;
+                       goto fail4;
 
                /* Assume largest tail padding size supported by hardware */
                end_padding = 256;
@@ -197,13 +185,13 @@ medford_board_cfg(
         * can result in time-of-check/time-of-use bugs.
         */
        if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
-               goto fail7;
+               goto fail5;
        encp->enc_privilege_mask = mask;
 
        /* Get interrupt vector limits */
        if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
                if (EFX_PCI_FUNCTION_IS_PF(encp))
-                       goto fail8;
+                       goto fail6;
 
                /* Ignore error (cannot query vector limits from a VF). */
                base = 0;
@@ -226,16 +214,12 @@ medford_board_cfg(
 
        rc = medford_nic_get_required_pcie_bandwidth(enp, &bandwidth);
        if (rc != 0)
-               goto fail9;
+               goto fail7;
        encp->enc_required_pcie_bandwidth_mbps = bandwidth;
        encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
 
        return (0);
 
-fail9:
-       EFSYS_PROBE(fail9);
-fail8:
-       EFSYS_PROBE(fail8);
 fail7:
        EFSYS_PROBE(fail7);
 fail6: