net/ice: support RSS RETA configuration in DCF mode

RSS RETA should be updated and queried by application,
Add related ops ('.reta_update', '.reta_query') for DCF.

Signed-off-by: Steve Yang <stevex.yang@intel.com>
Signed-off-by: Kevin Liu <kevinx.liu@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>

diff --git a/doc/guides/nics/features/ice_dcf.ini b/doc/guides/nics/features/ice_dcf.ini
index 54073f0b889f4ca3710a25ddc0eae6015278eae7..5221c99a9c4172da3f54a25116bb6b9491213c17 100644 (file)
--- a/doc/guides/nics/features/ice_dcf.ini
+++ b/doc/guides/nics/features/ice_dcf.ini
@@ -15,6 +15,7 @@ L3 checksum offload  = P
 L4 checksum offload  = P
 Inner L3 checksum    = P
 Inner L4 checksum    = P
+RSS reta update      = Y
 Basic stats          = Y
 Linux                = Y
 x86-32               = Y

diff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst
index 36906dc322fed813981035c9c4128ac173f13f76..fe4c5a86a2059ec15b30f1e70dee337ce54d4991 100644 (file)
--- a/doc/guides/rel_notes/release_22_07.rst
+++ b/doc/guides/rel_notes/release_22_07.rst
@@ -66,6 +66,10 @@ New Features
   * Added quanta size configuration support.
   * Added ``DEV_RX_OFFLOAD_TIMESTAMP`` support.
 
+* **Updated Intel ice driver.**
+
+ * Added support for RSS RETA configure in DCF mode.
+
 * **Updated Mellanox mlx5 driver.**
 
   * Added support for promiscuous mode on Windows.

diff --git a/drivers/net/ice/ice_dcf.c b/drivers/net/ice/ice_dcf.c
index 7f0c074b011b05398a03f6fe3e8aad9bf9957450..070d1b71ac55ffd125c2562ae4754f9a0deee541 100644 (file)
--- a/drivers/net/ice/ice_dcf.c
+++ b/drivers/net/ice/ice_dcf.c
@@ -790,7 +790,7 @@ ice_dcf_configure_rss_key(struct ice_dcf_hw *hw)
        return err;
 }
 
-static int
+int
 ice_dcf_configure_rss_lut(struct ice_dcf_hw *hw)
 {
        struct virtchnl_rss_lut *rss_lut;

diff --git a/drivers/net/ice/ice_dcf.h b/drivers/net/ice/ice_dcf.h
index 6ec766ebda0452f37cacb8e8a0fdf4baf5607a1f..b2c6aa2684a213505de8102788b9cf461fbe8cc0 100644 (file)
--- a/drivers/net/ice/ice_dcf.h
+++ b/drivers/net/ice/ice_dcf.h
@@ -122,6 +122,7 @@ int ice_dcf_send_aq_cmd(void *dcf_hw, struct ice_aq_desc *desc,
 int ice_dcf_handle_vsi_update_event(struct ice_dcf_hw *hw);
 int ice_dcf_init_hw(struct rte_eth_dev *eth_dev, struct ice_dcf_hw *hw);
 void ice_dcf_uninit_hw(struct rte_eth_dev *eth_dev, struct ice_dcf_hw *hw);
+int ice_dcf_configure_rss_lut(struct ice_dcf_hw *hw);
 int ice_dcf_init_rss(struct ice_dcf_hw *hw);
 int ice_dcf_configure_queues(struct ice_dcf_hw *hw);
 int ice_dcf_config_irq_map(struct ice_dcf_hw *hw);

diff --git a/drivers/net/ice/ice_dcf_ethdev.c b/drivers/net/ice/ice_dcf_ethdev.c
index 59610e058f099188ec841de5d9a47cbe963f8989..1ac66ed99048a81c9fb06090890b618c565e8a58 100644 (file)
--- a/drivers/net/ice/ice_dcf_ethdev.c
+++ b/drivers/net/ice/ice_dcf_ethdev.c
@@ -761,6 +761,81 @@ ice_dcf_dev_flow_ops_get(struct rte_eth_dev *dev,
        return 0;
 }
 
+static int
+ice_dcf_dev_rss_reta_update(struct rte_eth_dev *dev,
+                       struct rte_eth_rss_reta_entry64 *reta_conf,
+                       uint16_t reta_size)
+{
+       struct ice_dcf_adapter *adapter = dev->data->dev_private;
+       struct ice_dcf_hw *hw = &adapter->real_hw;
+       uint8_t *lut;
+       uint16_t i, idx, shift;
+       int ret;
+
+       if (!(hw->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RSS_PF))
+               return -ENOTSUP;
+
+       if (reta_size != hw->vf_res->rss_lut_size) {
+               PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
+                       "(%d) doesn't match the number of hardware can "
+                       "support (%d)", reta_size, hw->vf_res->rss_lut_size);
+               return -EINVAL;
+       }
+
+       lut = rte_zmalloc("rss_lut", reta_size, 0);
+       if (!lut) {
+               PMD_DRV_LOG(ERR, "No memory can be allocated");
+               return -ENOMEM;
+       }
+       /* store the old lut table temporarily */
+       rte_memcpy(lut, hw->rss_lut, reta_size);
+
+       for (i = 0; i < reta_size; i++) {
+               idx = i / RTE_ETH_RETA_GROUP_SIZE;
+               shift = i % RTE_ETH_RETA_GROUP_SIZE;
+               if (reta_conf[idx].mask & (1ULL << shift))
+                       lut[i] = reta_conf[idx].reta[shift];
+       }
+
+       rte_memcpy(hw->rss_lut, lut, reta_size);
+       /* send virtchnnl ops to configure rss*/
+       ret = ice_dcf_configure_rss_lut(hw);
+       if (ret) /* revert back */
+               rte_memcpy(hw->rss_lut, lut, reta_size);
+       rte_free(lut);
+
+       return ret;
+}
+
+static int
+ice_dcf_dev_rss_reta_query(struct rte_eth_dev *dev,
+                      struct rte_eth_rss_reta_entry64 *reta_conf,
+                      uint16_t reta_size)
+{
+       struct ice_dcf_adapter *adapter = dev->data->dev_private;
+       struct ice_dcf_hw *hw = &adapter->real_hw;
+       uint16_t i, idx, shift;
+
+       if (!(hw->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RSS_PF))
+               return -ENOTSUP;
+
+       if (reta_size != hw->vf_res->rss_lut_size) {
+               PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
+                       "(%d) doesn't match the number of hardware can "
+                       "support (%d)", reta_size, hw->vf_res->rss_lut_size);
+               return -EINVAL;
+       }
+
+       for (i = 0; i < reta_size; i++) {
+               idx = i / RTE_ETH_RETA_GROUP_SIZE;
+               shift = i % RTE_ETH_RETA_GROUP_SIZE;
+               if (reta_conf[idx].mask & (1ULL << shift))
+                       reta_conf[idx].reta[shift] = hw->rss_lut[i];
+       }
+
+       return 0;
+}
+
 #define ICE_DCF_32_BIT_WIDTH (CHAR_BIT * 4)
 #define ICE_DCF_48_BIT_WIDTH (CHAR_BIT * 6)
 #define ICE_DCF_48_BIT_MASK  RTE_LEN2MASK(ICE_DCF_48_BIT_WIDTH, uint64_t)
@@ -1107,6 +1182,8 @@ static const struct eth_dev_ops ice_dcf_eth_dev_ops = {
        .udp_tunnel_port_add     = ice_dcf_dev_udp_tunnel_port_add,
        .udp_tunnel_port_del     = ice_dcf_dev_udp_tunnel_port_del,
        .tm_ops_get              = ice_dcf_tm_ops_get,
+       .reta_update             = ice_dcf_dev_rss_reta_update,
+       .reta_query              = ice_dcf_dev_rss_reta_query,
 };
 
 static int