The previous version relied on the fact that DMA sync for device and
PIO write barrier in pair. Now each does its job.
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
/* BARRIERS */
#define EFSYS_MEM_READ_BARRIER() rte_rmb()
-#define EFSYS_PIO_WRITE_BARRIER() rte_wmb()
+#define EFSYS_PIO_WRITE_BARRIER() rte_io_wmb()
/* DMA SYNC */
*/
#define EFSYS_DMA_SYNC_FOR_KERNEL(_esmp, _offset, _size) ((void)0)
-#define EFSYS_DMA_SYNC_FOR_DEVICE(_esmp, _offset, _size) ((void)0)
+
+/* Just avoid store and compiler (impliciltly) reordering */
+#define EFSYS_DMA_SYNC_FOR_DEVICE(_esmp, _offset, _size) rte_wmb()
/* TIMESTAMP */