common/qat: support GEN2 device 200xx

This adds pci detection and documentation for Intel GEN2
QuickAssist device 200xx (PF Did 0x18ee, VF Did 0x18ef).

Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>

diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index 7ede427..e5d2cf4 100644 (file)
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -22,6 +22,7 @@ poll mode crypto driver support for the following hardware accelerator devices:
 * ``Intel QuickAssist Technology DH895xCC``
 * ``Intel QuickAssist Technology C62x``
 * ``Intel QuickAssist Technology C3xxx``
+* ``Intel QuickAssist Technology 200xx``
 * ``Intel QuickAssist Technology D15xx``
 * ``Intel QuickAssist Technology C4xxx``
 
@@ -393,6 +394,8 @@ to see the full table)
    +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
    | Yes | Yes | Yes | "   | "        | 01.org/4.2.0+ | "             | "          | "      | "    | "      | "      |
    +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
+   | Yes | No  | No  | 2   | 200xx    | p             | qat_200xx     | 200xx      | 18ee   | 1    | 18ef   | 16     |
+   +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
    | Yes | No  | No  | 2   | D15xx    | 01.org/4.2.0+ | qat_d15xx     | d15xx      | 6f54   | 1    | 6f55   | 16     |
    +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
    | Yes | No  | No  | 3   | C4xxx    | p             | qat_c4xxx     | c4xxx      | 18a0   | 1    | 18a1   | 128    |
@@ -619,8 +622,8 @@ adjust the unbind command below::
         done; \
     done
 
-For Intel(R) QuickAssist Technology C3xxx or D15xx device
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+For Intel(R) QuickAssist Technology C3xxx or 200xx or D15xx device
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 The unbind command below assumes ``BDFs`` of ``01:01.00-01:02.07``, if your
 VFs are different adjust the unbind command below::

diff --git a/doc/guides/rel_notes/release_20_08.rst b/doc/guides/rel_notes/release_20_08.rst
index 01880b8..580af2d 100644 (file)
--- a/doc/guides/rel_notes/release_20_08.rst
+++ b/doc/guides/rel_notes/release_20_08.rst
@@ -201,6 +201,8 @@ New Features
     ``rte_security`` API.
   * Added Chacha20-Poly1305 AEAD algorithm.
   * Improved handling of multi process in QAT crypto and compression PMDs.
+  * Added support for Intel GEN2 QuickAssist device 200xx
+    (PF Did 0x18ee, VF Did 0x18ef).
 
 * **Updated the OCTEON TX2 crypto PMD.**
 

diff --git a/drivers/common/qat/qat_device.c b/drivers/common/qat/qat_device.c
index a6ab29f..b050ce2 100644 (file)
--- a/drivers/common/qat/qat_device.c
+++ b/drivers/common/qat/qat_device.c
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2018 Intel Corporation
+ * Copyright(c) 2018-2020 Intel Corporation
  */
 
 #include <rte_string_fns.h>
@@ -53,6 +53,9 @@ static const struct rte_pci_id pci_id_qat_map[] = {
                {
                        RTE_PCI_DEVICE(0x8086, 0x6f55),
                },
+               {
+                       RTE_PCI_DEVICE(0x8086, 0x18ef),
+               },
                {
                        RTE_PCI_DEVICE(0x8086, 0x18a1),
                },
@@ -223,6 +226,7 @@ qat_pci_device_allocate(struct rte_pci_device *pci_dev,
        case 0x37c9:
        case 0x19e3:
        case 0x6f55:
+       case 0x18ef:
                qat_dev->qat_dev_gen = QAT_GEN2;
                break;
        case 0x18a1: