common/mlx5: check send on time capability

The patch provides check for send scheduling on time hardware capability.
With this capability enabled hardware is able to handle Wait WQEs
with directly specified timestamp values. No Clock Queue is needed
anymore to handle send scheduling.

Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c
index 70a430f1340e34d2ae917c3dd3f8e983c8876ab0..9f1419ded8e8499698e5577bc71b7aa63574cd41 100644 (file)
--- a/drivers/common/mlx5/mlx5_devx_cmds.c
+++ b/drivers/common/mlx5/mlx5_devx_cmds.c
@@ -962,6 +962,7 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
                MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled);
        attr->umr_modify_entity_size_disabled =
                MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled);
+       attr->wait_on_time = MLX5_GET(cmd_hca_cap, hcattr, wait_on_time);
        attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto);
        if (attr->crypto)
                attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts);

diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h
index 4373761c29826e8e3265cd73521f71fdcdfafd11..1bac18c59dfdcb7ee9ac75b58944e816b5ecea11 100644 (file)
--- a/drivers/common/mlx5/mlx5_devx_cmds.h
+++ b/drivers/common/mlx5/mlx5_devx_cmds.h
@@ -201,6 +201,7 @@ struct mlx5_hca_attr {
        uint32_t scatter_fcs_w_decap_disable:1;
        uint32_t flow_hit_aso:1; /* General obj type FLOW_HIT_ASO supported. */
        uint32_t roce:1;
+       uint32_t wait_on_time:1;
        uint32_t rq_ts_format:2;
        uint32_t sq_ts_format:2;
        uint32_t steering_format_version:4;

diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index b9e39aa717da31a24e239de4aae98a5d0d269681..ce3e47059fd8980c54b8cf070eb6a7441baea443 100644 (file)
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -133,6 +133,19 @@
 #define MLX5_OPCODE_WAIT 0x0fu
 #endif
 
+#define MLX5_OPC_MOD_WAIT_CQ_PI 0u
+#define MLX5_OPC_MOD_WAIT_DATA 1u
+#define MLX5_OPC_MOD_WAIT_TIME 2u
+
+
+#define MLX5_WAIT_COND_INVERT 0x10u
+#define MLX5_WAIT_COND_ALWAYS_TRUE 0u
+#define MLX5_WAIT_COND_EQUAL 1u
+#define MLX5_WAIT_COND_BIGGER 2u
+#define MLX5_WAIT_COND_SMALLER 3u
+#define MLX5_WAIT_COND_CYCLIC_BIGGER 4u
+#define MLX5_WAIT_COND_CYCLIC_SMALLER 5u
+
 #ifndef HAVE_MLX5_OPCODE_ACCESS_ASO
 #define MLX5_OPCODE_ACCESS_ASO 0x2du
 #endif
@@ -348,6 +361,15 @@ struct mlx5_wqe_qseg {
        uint32_t qpn_cqn;
 } __rte_packed;
 
+struct mlx5_wqe_wseg {
+       uint32_t operation;
+       uint32_t lkey;
+       uint32_t va_high;
+       uint32_t va_low;
+       uint64_t value;
+       uint64_t mask;
+} __rte_packed;
+
 /* The title WQEBB, header of WQE. */
 struct mlx5_wqe {
        union {
@@ -1660,7 +1682,10 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8 num_vhca_ports[0x8];
        u8 reserved_at_618[0x6];
        u8 sw_owner_id[0x1];
-       u8 reserved_at_61f[0x129];
+       u8 reserved_at_61f[0x6C];
+       u8 wait_on_data[0x1];
+       u8 wait_on_time[0x1];
+       u8 reserved_at_68d[0xBB];
        u8 dma_mmo_qp[0x1];
        u8 regexp_mmo_qp[0x1];
        u8 compress_mmo_qp[0x1];