net/mlx5: fix Tx descriptor with VLAN insertions

If VLAN tag insertion transmit offload is engaged
(DEV_TX_OFFLOAD_VLAN_INSERT in tx queue configuration is set)
the transmit descriptor may be built with wrong format, due to
packet length is not adjusted. Also, the ring buffer wrap up
is not handled correctly.

Fixes: 18a1c20044c0 ("net/mlx5: implement Tx burst template")
Cc: stable@dpdk.org
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>

diff --git a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c
index 8ec90c3..f540977 100644 (file)
--- a/drivers/net/mlx5/mlx5_rxtx.c
+++ b/drivers/net/mlx5/mlx5_rxtx.c
@@ -2861,13 +2861,14 @@ mlx5_tx_dseg_vlan(struct mlx5_txq_data *restrict txq,
        memcpy(pdst, buf, MLX5_DSEG_MIN_INLINE_SIZE);
        buf += MLX5_DSEG_MIN_INLINE_SIZE;
        pdst += MLX5_DSEG_MIN_INLINE_SIZE;
+       len -= MLX5_DSEG_MIN_INLINE_SIZE;
        /* Insert VLAN ethertype + VLAN tag. Pointer is aligned. */
        assert(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));
+       if (unlikely(pdst >= (uint8_t *)txq->wqes_end))
+               pdst = (uint8_t *)txq->wqes;
        *(uint32_t *)pdst = rte_cpu_to_be_32((RTE_ETHER_TYPE_VLAN << 16) |
                                              loc->mbuf->vlan_tci);
        pdst += sizeof(struct rte_vlan_hdr);
-       if (unlikely(pdst >= (uint8_t *)txq->wqes_end))
-               pdst = (uint8_t *)txq->wqes;
        /*
         * The WQEBB space availability is checked by caller.
         * Here we should be aware of WQE ring buffer wraparound only.