]> git.droids-corp.org - dpdk.git/commitdiff
net/ice/base: support queue BW allocation configuration
authorWenjun Wu <wenjun1.wu@intel.com>
Tue, 17 May 2022 05:09:27 +0000 (13:09 +0800)
committerQi Zhang <qi.z.zhang@intel.com>
Wed, 18 May 2022 04:22:43 +0000 (06:22 +0200)
This patch adds BW allocation support of queue scheduling node
to support WFQ in queue level.

Signed-off-by: Wenjun Wu <wenjun1.wu@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
drivers/net/ice/base/ice_sched.c
drivers/net/ice/base/ice_sched.h

index e697c579be218d2d6d012c19bdafa401a4567f63..4ca15bf8f8b83af02905461ff5b7a736bc596799 100644 (file)
@@ -3613,6 +3613,70 @@ ice_cfg_vsi_q_priority(struct ice_port_info *pi, u16 num_qs, u32 *q_ids,
        return status;
 }
 
+/**
+ * ice_sched_save_q_bw_alloc - save queue node's BW allocation information
+ * @q_ctx: queue context structure
+ * @rl_type: rate limit type min, max, or shared
+ * @bw_alloc: BW weight/allocation
+ *
+ * Save BW information of queue type node for post replay use.
+ */
+static enum ice_status
+ice_sched_save_q_bw_alloc(struct ice_q_ctx *q_ctx, enum ice_rl_type rl_type,
+                         u32 bw_alloc)
+{
+       switch (rl_type) {
+       case ICE_MIN_BW:
+               ice_set_clear_cir_bw_alloc(&q_ctx->bw_t_info, bw_alloc);
+               break;
+       case ICE_MAX_BW:
+               ice_set_clear_eir_bw_alloc(&q_ctx->bw_t_info, bw_alloc);
+               break;
+       default:
+               return ICE_ERR_PARAM;
+       }
+       return ICE_SUCCESS;
+}
+
+/**
+ * ice_cfg_q_bw_alloc - configure queue BW weight/alloc params
+ * @pi: port information structure
+ * @vsi_handle: sw VSI handle
+ * @tc: traffic class
+ * @q_handle: software queue handle
+ * @rl_type: min, max, or shared
+ * @bw_alloc: BW weight/allocation
+ *
+ * This function configures BW allocation of queue scheduling node.
+ */
+enum ice_status
+ice_cfg_q_bw_alloc(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
+                  u16 q_handle, enum ice_rl_type rl_type, u32 bw_alloc)
+{
+       enum ice_status status = ICE_ERR_PARAM;
+       struct ice_sched_node *node;
+       struct ice_q_ctx *q_ctx;
+
+       ice_acquire_lock(&pi->sched_lock);
+       q_ctx = ice_get_lan_q_ctx(pi->hw, vsi_handle, tc, q_handle);
+       if (!q_ctx)
+               goto exit_q_bw_alloc;
+
+       node = ice_sched_find_node_by_teid(pi->root, q_ctx->q_teid);
+       if (!node) {
+               ice_debug(pi->hw, ICE_DBG_SCHED, "Wrong q_teid\n");
+               goto exit_q_bw_alloc;
+       }
+
+       status = ice_sched_cfg_node_bw_alloc(pi->hw, node, rl_type, bw_alloc);
+       if (!status)
+               status = ice_sched_save_q_bw_alloc(q_ctx, rl_type, bw_alloc);
+
+exit_q_bw_alloc:
+       ice_release_lock(&pi->sched_lock);
+       return status;
+}
+
 /**
  * ice_cfg_agg_vsi_priority_per_tc - config aggregator's VSI priority per TC
  * @pi: port information structure
index 1441b5f19111f0e53b9663b2088ae82d47608ab0..184ad09e6af42f5cca8ed9a07f55c32bbfd918de 100644 (file)
@@ -172,6 +172,9 @@ enum ice_status
 ice_cfg_vsi_q_priority(struct ice_port_info *pi, u16 num_qs, u32 *q_ids,
                       u8 *q_prio);
 enum ice_status
+ice_cfg_q_bw_alloc(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
+                  u16 q_handle, enum ice_rl_type rl_type, u32 bw_alloc);
+enum ice_status
 ice_cfg_vsi_bw_alloc(struct ice_port_info *pi, u16 vsi_handle, u8 ena_tcmap,
                     enum ice_rl_type rl_type, u8 *bw_alloc);
 enum ice_status