/* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1,
- wptr, pushed & erp->er_mask);
+ EF10_RXQ_DESC_SIZE, wptr, pushed & erp->er_mask);
EFSYS_PIO_WRITE_BARRIER();
EFX_BAR_VI_WRITED(enp, ER_DZ_RX_DESC_UPD_REG,
erp->er_index, &dword, B_FALSE);
/* Ensure ordering of memory (descriptors) and PIO (doorbell) */
EFX_DMA_SYNC_QUEUE_FOR_DEVICE(etp->et_esmp, etp->et_mask + 1,
- wptr, id);
+ EF10_TXQ_DESC_SIZE, wptr, id);
EFSYS_PIO_WRITE_BARRIER();
EFX_BAR_VI_DOORBELL_WRITEO(enp, ER_DZ_TX_DESC_UPD_REG,
etp->et_index, &oword);
/* Ensure ordering of memory (descriptors) and PIO (doorbell) */
EFX_DMA_SYNC_QUEUE_FOR_DEVICE(etp->et_esmp, etp->et_mask + 1,
- wptr, id);
+ EF10_TXQ_DESC_SIZE, wptr, id);
EFSYS_PIO_WRITE_BARRIER();
EFX_BAR_VI_WRITED2(enp, ER_DZ_TX_DESC_UPD_REG,
etp->et_index, &dword, B_FALSE);
_NOTE(CONSTANTCONDITION) \
} while (B_FALSE)
-#define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \
+#define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _desc_size, \
+ _wptr, _owptr) \
do { \
unsigned int _new = (_wptr); \
unsigned int _old = (_owptr); \
\
if ((_new) >= (_old)) \
EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
- (_old) * sizeof (efx_desc_t), \
- ((_new) - (_old)) * sizeof (efx_desc_t)); \
+ (_old) * (_desc_size), \
+ ((_new) - (_old)) * (_desc_size)); \
else \
/* \
* It is cheaper to sync entire map than sync \
*/ \
EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
0, \
- (_entries) * sizeof (efx_desc_t)); \
+ (_entries) * (_desc_size)); \
_NOTE(CONSTANTCONDITION) \
} while (B_FALSE)
/* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1,
- wptr, pushed & erp->er_mask);
+ SIENA_RXQ_DESC_SIZE, wptr, pushed & erp->er_mask);
EFSYS_PIO_WRITE_BARRIER();
EFX_BAR_TBL_WRITED3(enp, FR_BZ_RX_DESC_UPD_REGP0,
erp->er_index, &dword, B_FALSE);
/* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
EFX_DMA_SYNC_QUEUE_FOR_DEVICE(etp->et_esmp, etp->et_mask + 1,
- wptr, pushed & etp->et_mask);
+ SIENA_TXQ_DESC_SIZE, wptr, pushed & etp->et_mask);
EFSYS_PIO_WRITE_BARRIER();
EFX_BAR_TBL_WRITED3(enp, FR_BZ_TX_DESC_UPD_REGP0,
etp->et_index, &dword, B_FALSE);