common/mlx5: modify advanced Rx object via DevX

Implement TIR modification (see mlx5_devx_cmd_modify_tir()) using DevX
API. TIR is the object containing the hashed table of Rx queue. The
functionality to configure/modify this HW-related object is prerequisite
to implement rete_flow_shared_action_update() for shared RSS action in
mlx5 PMD. HW-related structures for TIR modification add in mlx5_prm.h.

Signed-off-by: Andrey Vesnovaty <andreyv@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c
index d3e90b5..8aee12d 100644 (file)
--- a/drivers/common/mlx5/mlx5_devx_cmds.c
+++ b/drivers/common/mlx5/mlx5_devx_cmds.c
@@ -1109,6 +1109,90 @@ mlx5_devx_cmd_create_tir(void *ctx,
        return tir;
 }
 
+/**
+ * Modify TIR using DevX API.
+ *
+ * @param[in] tir
+ *   Pointer to TIR DevX object structure.
+ * @param [in] modify_tir_attr
+ *   Pointer to TIR modification attributes structure.
+ *
+ * @return
+ *   0 on success, a negative errno value otherwise and rte_errno is set.
+ */
+int
+mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir,
+                        struct mlx5_devx_modify_tir_attr *modify_tir_attr)
+{
+       struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir;
+       uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0};
+       uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0};
+       void *tir_ctx;
+       int ret;
+
+       MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR);
+       MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn);
+       MLX5_SET64(modify_tir_in, in, modify_bitmask,
+                  modify_tir_attr->modify_bitmask);
+       tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
+       if (modify_tir_attr->modify_bitmask &
+                       MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) {
+               MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
+                        tir_attr->lro_timeout_period_usecs);
+               MLX5_SET(tirc, tir_ctx, lro_enable_mask,
+                        tir_attr->lro_enable_mask);
+               MLX5_SET(tirc, tir_ctx, lro_max_msg_sz,
+                        tir_attr->lro_max_msg_sz);
+       }
+       if (modify_tir_attr->modify_bitmask &
+                       MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE)
+               MLX5_SET(tirc, tir_ctx, indirect_table,
+                        tir_attr->indirect_table);
+       if (modify_tir_attr->modify_bitmask &
+                       MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) {
+               int i;
+               void *outer, *inner;
+
+               MLX5_SET(tirc, tir_ctx, rx_hash_symmetric,
+                        tir_attr->rx_hash_symmetric);
+               MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
+               for (i = 0; i < 10; i++) {
+                       MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i],
+                                tir_attr->rx_hash_toeplitz_key[i]);
+               }
+               outer = MLX5_ADDR_OF(tirc, tir_ctx,
+                                    rx_hash_field_selector_outer);
+               MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
+                        tir_attr->rx_hash_field_selector_outer.l3_prot_type);
+               MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
+                        tir_attr->rx_hash_field_selector_outer.l4_prot_type);
+               MLX5_SET
+               (rx_hash_field_select, outer, selected_fields,
+                tir_attr->rx_hash_field_selector_outer.selected_fields);
+               inner = MLX5_ADDR_OF(tirc, tir_ctx,
+                                    rx_hash_field_selector_inner);
+               MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
+                        tir_attr->rx_hash_field_selector_inner.l3_prot_type);
+               MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
+                        tir_attr->rx_hash_field_selector_inner.l4_prot_type);
+               MLX5_SET
+               (rx_hash_field_select, inner, selected_fields,
+                tir_attr->rx_hash_field_selector_inner.selected_fields);
+       }
+       if (modify_tir_attr->modify_bitmask &
+           MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) {
+               MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
+       }
+       ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in),
+                                        out, sizeof(out));
+       if (ret) {
+               DRV_LOG(ERR, "Failed to modify TIR using DevX");
+               rte_errno = errno;
+               return -errno;
+       }
+       return ret;
+}
+
 /**
  * Create RQT using DevX API.
  *

diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h
index c2d089c..abbea67 100644 (file)
--- a/drivers/common/mlx5/mlx5_devx_cmds.h
+++ b/drivers/common/mlx5/mlx5_devx_cmds.h
@@ -192,6 +192,13 @@ struct mlx5_devx_tir_attr {
        struct mlx5_rx_hash_field_select rx_hash_field_selector_inner;
 };
 
+/* TIR attributes structure, used by TIR modify. */
+struct mlx5_devx_modify_tir_attr {
+       uint32_t tirn:24;
+       uint64_t modify_bitmask;
+       struct mlx5_devx_tir_attr tir;
+};
+
 /* RQT attributes structure, used by RQT operations. */
 struct mlx5_devx_rqt_attr {
        uint8_t rq_type;
@@ -436,6 +443,9 @@ __rte_internal
 int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
                             struct mlx5_devx_rqt_attr *rqt_attr);
 __rte_internal
+int mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir,
+                            struct mlx5_devx_modify_tir_attr *tir_attr);
+__rte_internal
 int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,
                                      uint32_t ids[], uint32_t num);
 

diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index b8b656a..d342263 100644 (file)
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -830,6 +830,7 @@ enum {
        MLX5_CMD_OP_ACCESS_REGISTER = 0x805,
        MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
        MLX5_CMD_OP_CREATE_TIR = 0x900,
+       MLX5_CMD_OP_MODIFY_TIR = 0x901,
        MLX5_CMD_OP_CREATE_SQ = 0X904,
        MLX5_CMD_OP_MODIFY_SQ = 0X905,
        MLX5_CMD_OP_CREATE_RQ = 0x908,
@@ -1919,6 +1920,34 @@ struct mlx5_ifc_create_tir_in_bits {
        struct mlx5_ifc_tirc_bits ctx;
 };
 
+enum {
+       MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO = 1ULL << 0,
+       MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE = 1ULL << 1,
+       MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH = 1ULL << 2,
+       /* bit 3 - tunneled_offload_en modify not supported. */
+       MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN = 1ULL << 4,
+};
+
+struct mlx5_ifc_modify_tir_out_bits {
+       u8 status[0x8];
+       u8 reserved_at_8[0x18];
+       u8 syndrome[0x20];
+       u8 reserved_at_40[0x40];
+};
+
+struct mlx5_ifc_modify_tir_in_bits {
+       u8 opcode[0x10];
+       u8 uid[0x10];
+       u8 reserved_at_20[0x10];
+       u8 op_mod[0x10];
+       u8 reserved_at_40[0x8];
+       u8 tirn[0x18];
+       u8 reserved_at_60[0x20];
+       u8 modify_bitmask[0x40];
+       u8 reserved_at_c0[0x40];
+       struct mlx5_ifc_tirc_bits ctx;
+};
+
 enum {
        MLX5_INLINE_Q_TYPE_RQ = 0x0,
        MLX5_INLINE_Q_TYPE_VIRTQ = 0x1,

diff --git a/drivers/common/mlx5/version.map b/drivers/common/mlx5/version.map
index c4d57c0..884001c 100644 (file)
--- a/drivers/common/mlx5/version.map
+++ b/drivers/common/mlx5/version.map
@@ -30,6 +30,7 @@ INTERNAL {
        mlx5_devx_cmd_modify_rq;
        mlx5_devx_cmd_modify_rqt;
        mlx5_devx_cmd_modify_sq;
+       mlx5_devx_cmd_modify_tir;
        mlx5_devx_cmd_modify_virtq;
        mlx5_devx_cmd_qp_query_tis_td;
        mlx5_devx_cmd_query_hca_attr;