crypto/aesni_mb: support AVX512
authorDeclan Doherty <declan.doherty@intel.com>
Wed, 21 Dec 2016 22:05:00 +0000 (22:05 +0000)
committerPablo de Lara <pablo.de.lara.guarch@intel.com>
Wed, 18 Jan 2017 20:48:56 +0000 (21:48 +0100)
Release v0.44 of Intel(R) Multi-Buffer Crypto for IPsec library adds
support for AVX512 instructions. This patch enables the new AVX512
accelerated functions from the aesni_mb_pmd crypto poll mode driver.

This patch set requires that the aesni_mb_pmd is linked against the
version 0.44 or greater of the Multi-Buffer Crypto for IPsec library.

Signed-off-by: Declan Doherty <declan.doherty@intel.com>
Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
doc/guides/cryptodevs/overview.rst
drivers/crypto/aesni_mb/aesni_mb_ops.h
drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c
lib/librte_cryptodev/rte_cryptodev.h

index 2352b6a..6a4a32a 100644 (file)
@@ -42,6 +42,7 @@ Supported Feature Flags
    "RTE_CRYPTODEV_FF_CPU_SSE",,,x,x,x,x
    "RTE_CRYPTODEV_FF_CPU_AVX",,,x,x,x,x
    "RTE_CRYPTODEV_FF_CPU_AVX2",,,x,x,,
+   "RTE_CRYPTODEV_FF_CPU_AVX512",,,x,,,
    "RTE_CRYPTODEV_FF_CPU_AESNI",,,x,x,,
    "RTE_CRYPTODEV_FF_HW_ACCELERATED",x,,,,,
 
index 0c119bf..2d41d73 100644 (file)
@@ -44,7 +44,8 @@ enum aesni_mb_vector_mode {
        RTE_AESNI_MB_NOT_SUPPORTED = 0,
        RTE_AESNI_MB_SSE,
        RTE_AESNI_MB_AVX,
-       RTE_AESNI_MB_AVX2
+       RTE_AESNI_MB_AVX2,
+       RTE_AESNI_MB_AVX512
 };
 
 typedef void (*md5_one_block_t)(void *data, void *digest);
@@ -203,6 +204,31 @@ static const struct aesni_mb_ops job_ops[] = {
                                        aes_xcbc_expand_key_avx2
                                }
                        }
+               },
+               [RTE_AESNI_MB_AVX512] = {
+                       .job = {
+                               init_mb_mgr_avx512,
+                               get_next_job_avx512,
+                               submit_job_avx512,
+                               get_completed_job_avx512,
+                               flush_job_avx512
+                       },
+                       .aux = {
+                               .one_block = {
+                                       md5_one_block_avx512,
+                                       sha1_one_block_avx512,
+                                       sha224_one_block_avx512,
+                                       sha256_one_block_avx512,
+                                       sha384_one_block_avx512,
+                                       sha512_one_block_avx512
+                               },
+                               .keyexp = {
+                                       aes_keyexp_128_avx512,
+                                       aes_keyexp_192_avx512,
+                                       aes_keyexp_256_avx512,
+                                       aes_xcbc_expand_key_avx512
+                               }
+                       }
                }
 };
 
index bafd4d7..6d27d75 100644 (file)
@@ -655,7 +655,9 @@ cryptodev_aesni_mb_create(const char *name,
        }
 
        /* Check CPU for supported vector instruction set */
-       if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2))
+       if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F))
+               vector_mode = RTE_AESNI_MB_AVX512;
+       else if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2))
                vector_mode = RTE_AESNI_MB_AVX2;
        else if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX))
                vector_mode = RTE_AESNI_MB_AVX;
@@ -702,6 +704,9 @@ cryptodev_aesni_mb_create(const char *name,
        case RTE_AESNI_MB_AVX2:
                dev->feature_flags |= RTE_CRYPTODEV_FF_CPU_AVX2;
                break;
+       case RTE_AESNI_MB_AVX512:
+               dev->feature_flags |= RTE_CRYPTODEV_FF_CPU_AVX512;
+               break;
        default:
                break;
        }
index 8f63e8f..29d8eec 100644 (file)
@@ -225,6 +225,8 @@ struct rte_cryptodev_capabilities {
 /**< Utilises CPU AES-NI instructions */
 #define        RTE_CRYPTODEV_FF_HW_ACCELERATED         (1ULL << 7)
 /**< Operations are off-loaded to an external hardware accelerator */
+#define        RTE_CRYPTODEV_FF_CPU_AVX512             (1ULL << 8)
+/**< Utilises CPU SIMD AVX512 instructions */
 
 
 /**